mirror of
https://github.com/garrettsworkshop/Warp-LC.git
synced 2024-06-02 00:41:43 +00:00
483 lines
22 KiB
Plaintext
483 lines
22 KiB
Plaintext
Release 14.7 - xst P.20131013 (nt)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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--> Parameter TMPDIR set to xst/projnav.tmp
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.08 secs
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--> Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.08 secs
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--> Reading design: WarpLC.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Parsing
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3) HDL Elaboration
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4) HDL Synthesis
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4.1) HDL Synthesis Report
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5) Advanced HDL Synthesis
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5.1) Advanced HDL Synthesis Report
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6) Low Level Synthesis
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7) Partition Report
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8) Design Summary
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8.1) Primitive and Black Box Usage
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8.2) Device utilization summary
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8.3) Partition Resource Summary
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8.4) Timing Report
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8.4.1) Clock Information
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8.4.2) Asynchronous Control Signals Information
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8.4.3) Timing Summary
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8.4.4) Timing Details
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8.4.5) Cross Clock Domains Report
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "WarpLC.prj"
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "WarpLC"
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Output Format : NGC
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Target Device : xc6slx9-2-ftg256
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---- Source Options
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Top Module Name : WarpLC
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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Safe Implementation : No
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FSM Style : LUT
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RAM Extraction : Yes
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RAM Style : Auto
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ROM Extraction : Yes
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Shift Register Extraction : YES
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ROM Style : Auto
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Resource Sharing : YES
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Asynchronous To Synchronous : NO
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Shift Register Minimum Size : 2
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Use DSP Block : Auto
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Automatic Register Balancing : No
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---- Target Options
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LUT Combining : Auto
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Reduce Control Sets : Auto
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Add IO Buffers : YES
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Global Maximum Fanout : 100000
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Add Generic Clock Buffer(BUFG) : 16
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Register Duplication : YES
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Optimize Instantiated Primitives : NO
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Use Clock Enable : Auto
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Use Synchronous Set : Auto
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Use Synchronous Reset : Auto
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Pack IO Registers into IOBs : Auto
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Power Reduction : NO
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Keep Hierarchy : No
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Netlist Hierarchy : As_Optimized
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RTL Output : Yes
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Global Optimization : AllClockNets
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Read Cores : YES
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Write Timing Constraints : NO
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Cross Clock Analysis : NO
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : Maintain
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Slice Utilization Ratio : 100
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BRAM Utilization Ratio : 100
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DSP48 Utilization Ratio : 100
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Auto BRAM Packing : NO
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Slice Utilization Ratio Delta : 5
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---- Other Options
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Cores Search Directories : {"ipcore_dir" }
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=========================================================================
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=========================================================================
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* HDL Parsing *
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=========================================================================
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Analyzing Verilog file "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" into library work
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Parsing module <CLK>.
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Analyzing Verilog file "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\CLKGEN.v" into library work
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Parsing module <CLKGEN>.
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Analyzing Verilog file "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v" into library work
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Parsing module <WarpLC>.
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=========================================================================
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* HDL Elaboration *
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=========================================================================
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Elaborating module <WarpLC>.
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Elaborating module <CLKGEN>.
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Elaborating module <CLK>.
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Elaborating module <IBUFG>.
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Elaborating module <BUFIO2FB(DIVIDE_BYPASS="TRUE")>.
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Elaborating module <PLL_BASE(BANDWIDTH="OPTIMIZED",CLK_FEEDBACK="CLKFBOUT",COMPENSATION="EXTERNAL",DIVCLK_DIVIDE=1,CLKFBOUT_MULT=12,CLKFBOUT_PHASE=0.0,CLKOUT0_DIVIDE=6,CLKOUT0_PHASE=0.0,CLKOUT0_DUTY_CYCLE=0.5,CLKIN_PERIOD=30.0,REF_JITTER=0.008)>.
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WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 128: Assignment to clkout1_unused ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 129: Assignment to clkout2_unused ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 130: Assignment to clkout3_unused ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 131: Assignment to clkout4_unused ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 132: Assignment to clkout5_unused ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 133: Assignment to locked_unused ignored, since the identifier is never used
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Elaborating module <BUFG>.
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Elaborating module <ODDR2>.
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Elaborating module <ODDR2(DDR_ALIGNMENT="C0",INIT=1'b0,SRTYPE="ASYNC")>.
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WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 84: Assignment to CPUCLKr ignored, since the identifier is never used
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Synthesizing Unit <WarpLC>.
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Related source file is "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v".
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Set property "IOSTANDARD = LVCMOS33" for signal <FSB_A>.
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Set property "IOBDELAY = NONE" for signal <FSB_A>.
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Set property "IOSTANDARD = LVCMOS33" for signal <CPU_nAS>.
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Set property "IOBDELAY = NONE" for signal <CPU_nAS>.
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Set property "IOSTANDARD = LVCMOS33" for signal <INt>.
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Set property "IOBDELAY = NONE" for signal <INt>.
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Set property "IOB = FALSE" for signal <OUTt>.
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Set property "IOSTANDARD = LVCMOS33" for signal <OUTt>.
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Set property "DRIVE = 24" for signal <OUTt>.
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Set property "SLEW = FAST" for signal <OUTt>.
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Set property "IOSTANDARD = LVCMOS33" for signal <CPUCLK>.
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Set property "DRIVE = 24" for signal <CPUCLK>.
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Set property "SLEW = FAST" for signal <CPUCLK>.
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Set property "IOSTANDARD = LVCMOS33" for signal <FPUCLK>.
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Set property "DRIVE = 24" for signal <FPUCLK>.
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Set property "SLEW = FAST" for signal <FPUCLK>.
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Set property "IOSTANDARD = LVCMOS33" for signal <RAMCLK0>.
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Set property "DRIVE = 24" for signal <RAMCLK0>.
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Set property "SLEW = FAST" for signal <RAMCLK0>.
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Set property "IOSTANDARD = LVCMOS33" for signal <RAMCLK1>.
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Set property "DRIVE = 24" for signal <RAMCLK1>.
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Set property "SLEW = FAST" for signal <RAMCLK1>.
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Set property "IOSTANDARD = LVCMOS33" for signal <CPUCLKi>.
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Set property "IOBDELAY = NONE" for signal <CPUCLKi>.
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Set property "IOSTANDARD = LVCMOS33" for signal <CLKIN>.
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Set property "IOBDELAY = NONE" for signal <CLKIN>.
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Set property "IOSTANDARD = LVCMOS33" for signal <CLKFB_IN>.
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Set property "IOBDELAY = NONE" for signal <CLKFB_IN>.
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Set property "IOSTANDARD = LVCMOS33" for signal <CLKFB_OUT>.
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Set property "DRIVE = 24" for signal <CLKFB_OUT>.
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Set property "SLEW = FAST" for signal <CLKFB_OUT>.
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INFO:Xst:3210 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 79: Output port <CPUCLKr> of the instance <CLKGEN_inst> is unconnected or connected to loadless signal.
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Found 32-bit register for signal <AR>.
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Found 1-bit register for signal <OUTt>.
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Found 32-bit comparator equal for signal <FSB_A[31]_AR[31]_equal_2_o> created at line 92
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Summary:
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inferred 33 D-type flip-flop(s).
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inferred 1 Comparator(s).
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Unit <WarpLC> synthesized.
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Synthesizing Unit <CLKGEN>.
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Related source file is "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\CLKGEN.v".
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Found 1-bit register for signal <CPUCLKr>.
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Summary:
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inferred 1 D-type flip-flop(s).
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Unit <CLKGEN> synthesized.
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Synthesizing Unit <CLK>.
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Related source file is "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v".
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Summary:
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no macro.
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Unit <CLK> synthesized.
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=========================================================================
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HDL Synthesis Report
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Macro Statistics
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# Registers : 3
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1-bit register : 2
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32-bit register : 1
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# Comparators : 1
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32-bit comparator equal : 1
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=========================================================================
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=========================================================================
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* Advanced HDL Synthesis *
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=========================================================================
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=========================================================================
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Advanced HDL Synthesis Report
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Macro Statistics
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# Registers : 34
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Flip-Flops : 34
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# Comparators : 1
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32-bit comparator equal : 1
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=========================================================================
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=========================================================================
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* Low Level Synthesis *
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=========================================================================
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INFO:Xst:1901 - Instance pll_base_inst in unit pll_base_inst of type PLL_BASE has been replaced by PLL_ADV
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Optimizing unit <WarpLC> ...
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Optimizing unit <CLK> ...
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Mapping all equations...
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Building and optimizing final netlist ...
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Found area constraint ratio of 100 (+ 5) on block WarpLC, actual ratio is 1.
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Final Macro Processing ...
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=========================================================================
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Final Register Report
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Macro Statistics
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# Registers : 34
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Flip-Flops : 34
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=========================================================================
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=========================================================================
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* Partition Report *
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=========================================================================
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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=========================================================================
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* Design Summary *
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=========================================================================
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Top Level Output File Name : WarpLC.ngc
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Primitive and Black Box Usage:
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------------------------------
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# BELS : 29
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# GND : 1
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# INV : 3
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# LUT3 : 1
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# LUT4 : 1
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# LUT6 : 10
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# MUXCY : 12
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# VCC : 1
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# FlipFlops/Latches : 39
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# FD : 34
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# ODDR2 : 5
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# Clock Buffers : 2
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# BUFG : 2
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# IO Buffers : 43
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# IBUF : 35
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# IBUFG : 2
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# OBUF : 6
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# Others : 2
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# BUFIO2FB : 1
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# PLL_ADV : 1
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Device utilization summary:
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---------------------------
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Selected Device : 6slx9ftg256-2
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Slice Logic Utilization:
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Number of Slice Registers: 39 out of 11440 0%
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Number of Slice LUTs: 15 out of 5720 0%
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Number used as Logic: 15 out of 5720 0%
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Slice Logic Distribution:
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Number of LUT Flip Flop pairs used: 52
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Number with an unused Flip Flop: 13 out of 52 25%
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Number with an unused LUT: 37 out of 52 71%
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Number of fully used LUT-FF pairs: 2 out of 52 3%
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Number of unique control sets: 1
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IO Utilization:
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Number of IOs: 43
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Number of bonded IOBs: 43 out of 186 23%
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Specific Feature Utilization:
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Number of BUFG/BUFGCTRLs: 2 out of 16 12%
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Number of PLL_ADVs: 1 out of 2 50%
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---------------------------
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Partition Resource Summary:
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---------------------------
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No Partitions were found in this design.
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---------------------------
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=========================================================================
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Timing Report
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NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
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FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
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GENERATED AFTER PLACE-and-ROUTE.
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Clock Information:
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------------------
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------------------------------------------------+------------------------+-------+
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Clock Signal | Clock buffer(FF name) | Load |
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------------------------------------------------+------------------------+-------+
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CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0 | BUFG | 42 |
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CLKGEN_inst/instance_name/pll_base_inst/CLKFBOUT| BUFG | 2 |
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------------------------------------------------+------------------------+-------+
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Asynchronous Control Signals Information:
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----------------------------------------
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No asynchronous control signals found in this design
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Timing Summary:
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---------------
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Speed Grade: -2
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Minimum period: 2.580ns (Maximum Frequency: 387.597MHz)
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Minimum input arrival time before clock: 3.547ns
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Maximum output required time after clock: 4.118ns
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Maximum combinational path delay: 1.328ns
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Timing Details:
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---------------
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All values displayed in nanoseconds (ns)
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=========================================================================
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Timing constraint: Default period analysis for Clock 'CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0'
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Clock period: 2.580ns (frequency: 387.597MHz)
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Total number of paths / destination ports: 35 / 4
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-------------------------------------------------------------------------
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Delay: 1.290ns (Levels of Logic = 0)
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Source: CLKGEN_inst/CPUCLKr (FF)
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Destination: CLKGEN_inst/FPUCLK_inst (FF)
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Source Clock: CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0 rising
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Destination Clock: CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0 falling
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Data Path: CLKGEN_inst/CPUCLKr to CLKGEN_inst/FPUCLK_inst
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
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FD:C->Q 3 0.525 0.765 CLKGEN_inst/CPUCLKr (CLKGEN_inst/CPUCLKr)
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ODDR2:D1 0.000 CLKGEN_inst/FPUCLK_inst
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----------------------------------------
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Total 1.290ns (0.525ns logic, 0.765ns route)
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(40.7% logic, 59.3% route)
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=========================================================================
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Timing constraint: Default OFFSET IN BEFORE for Clock 'CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0'
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Total number of paths / destination ports: 67 / 33
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-------------------------------------------------------------------------
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Offset: 3.547ns (Levels of Logic = 14)
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Source: FSB_A<2> (PAD)
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Destination: OUTt (FF)
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Destination Clock: CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0 rising
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Data Path: FSB_A<2> to OUTt
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
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IBUF:I->O 2 1.328 1.181 FSB_A_2_IBUF (FSB_A_2_IBUF)
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LUT6:I0->O 1 0.254 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<0> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<0>)
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MUXCY:S->O 1 0.215 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<0> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<0>)
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MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<1> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<1>)
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MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<2> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<2>)
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MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>)
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MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<4> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<4>)
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MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<5> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<5>)
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MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<6> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<6>)
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MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>)
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MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<8> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<8>)
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MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<9> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<9>)
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MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<10> (FSB_A[31]_AR[31]_equal_2_o)
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MUXCY:CI->O 1 0.262 0.000 CPU_nAS_FSB_A[31]_AND_3_o1_cy (CPU_nAS_FSB_A[31]_AND_3_o)
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FD:D 0.074 OUTt
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----------------------------------------
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Total 3.547ns (2.366ns logic, 1.181ns route)
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(66.7% logic, 33.3% route)
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=========================================================================
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Timing constraint: Default OFFSET OUT AFTER for Clock 'CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0'
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Total number of paths / destination ports: 1 / 1
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-------------------------------------------------------------------------
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Offset: 4.118ns (Levels of Logic = 1)
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Source: OUTt (FF)
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Destination: OUTt (PAD)
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Source Clock: CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0 rising
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Data Path: OUTt to OUTt
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
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FD:C->Q 1 0.525 0.681 OUTt (OUTt_OBUF)
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OBUF:I->O 2.912 OUTt_OBUF (OUTt)
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----------------------------------------
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Total 4.118ns (3.437ns logic, 0.681ns route)
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(83.5% logic, 16.5% route)
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=========================================================================
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Timing constraint: Default path analysis
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Total number of paths / destination ports: 1 / 1
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-------------------------------------------------------------------------
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Delay: 1.328ns (Levels of Logic = 1)
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Source: CLKFB_IN (PAD)
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Destination: CLKGEN_inst/instance_name/clkfb_bufio2fb:I (PAD)
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Data Path: CLKFB_IN to CLKGEN_inst/instance_name/clkfb_bufio2fb:I
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Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
IBUFG:I->O 0 1.328 0.000 CLKGEN_inst/instance_name/clkfb_ibufg (CLKGEN_inst/instance_name/clkfb_ibuf2bufio2fb)
|
|
BUFIO2FB:I 0.000 CLKGEN_inst/instance_name/clkfb_bufio2fb
|
|
----------------------------------------
|
|
Total 1.328ns (1.328ns logic, 0.000ns route)
|
|
(100.0% logic, 0.0% route)
|
|
|
|
=========================================================================
|
|
|
|
Cross Clock Domains Report:
|
|
--------------------------
|
|
|
|
Clock to Setup on destination clock CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0
|
|
-----------------------------------------------+---------+---------+---------+---------+
|
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
|
-----------------------------------------------+---------+---------+---------+---------+
|
|
CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0| 2.454| | 1.290| |
|
|
-----------------------------------------------+---------+---------+---------+---------+
|
|
|
|
=========================================================================
|
|
|
|
|
|
Total REAL time to Xst completion: 2.00 secs
|
|
Total CPU time to Xst completion: 2.72 secs
|
|
|
|
-->
|
|
|
|
Total memory usage is 225148 kilobytes
|
|
|
|
Number of errors : 0 ( 0 filtered)
|
|
Number of warnings : 7 ( 0 filtered)
|
|
Number of infos : 2 ( 0 filtered)
|
|
|