mirror of
https://github.com/garrettsworkshop/Warp-LC.git
synced 2024-06-02 16:41:28 +00:00
97 lines
1.8 KiB
Verilog
97 lines
1.8 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 06:27:24 10/29/2021
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// Design Name:
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// Module Name: WarpLC
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module WarpLC(
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(* IOSTANDARD = "LVCMOS33" *)
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(* IOBDELAY = "NONE" *)
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input CPU_nAS,
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(* IOSTANDARD = "LVCMOS33" *)
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(* IOBDELAY = "NONE" *)
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input [31:0] FSB_A,
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(* IOSTANDARD = "LVCMOS33" *)
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(* IOBDELAY = "NONE" *)
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input INt,
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(* IOB = "FALSE" *)
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(* IOSTANDARD = "LVCMOS33" *)
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(* DRIVE = "24" *)
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(* SLEW = "FAST" *)
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output reg OUTt,
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(* IOSTANDARD = "LVCMOS33" *)
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(* DRIVE = "24" *)
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(* SLEW = "FAST" *)
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output CPUCLK,
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(* IOSTANDARD = "LVCMOS33" *)
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(* DRIVE = "24" *)
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(* SLEW = "FAST" *)
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output FPUCLK,
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(* IOSTANDARD = "LVCMOS33" *)
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(* DRIVE = "24" *)
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(* SLEW = "FAST" *)
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output RAMCLK0,
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(* IOSTANDARD = "LVCMOS33" *)
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(* DRIVE = "24" *)
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(* SLEW = "FAST" *)
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output RAMCLK1,
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(* IOSTANDARD = "LVCMOS33" *)
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(* IOBDELAY = "NONE" *)
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input CPUCLKi,
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(* IOSTANDARD = "LVCMOS33" *)
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(* IOBDELAY = "NONE" *)
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input CLKIN,
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(* IOSTANDARD = "LVCMOS33" *)
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(* IOBDELAY = "NONE" *)
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input CLKFB_IN,
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(* IOSTANDARD = "LVCMOS33" *)
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(* DRIVE = "24" *)
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(* SLEW = "FAST" *)
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output CLKFB_OUT);
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wire FSBCLK;
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wire CPUCLKr;
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CLKGEN CLKGEN_inst(
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.CLKIN(CLKIN),
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.CLKFB_IN(CLKFB_IN),
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.CLKFB_OUT(CLKFB_OUT),
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.FSBCLK(FSBCLK),
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.CPUCLKr(CPUCLKr),
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.CPUCLK(CPUCLK),
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.FPUCLK(FPUCLK),
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.RAMCLK0(RAMCLK0),
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.RAMCLK1(RAMCLK1));
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reg [31:0] AR;
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always @(posedge FSBCLK) begin
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OUTt <= ~CPU_nAS && INt && CPUCLKi && FSB_A[31:0]==AR[31:0];
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AR[31:0] <= FSB_A[31:0];
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end
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endmodule
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