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https://github.com/garrettsworkshop/Warp-LC.git
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628 lines
36 KiB
Plaintext
628 lines
36 KiB
Plaintext
--------------------------------------------------------------------------------
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Release 14.7 Trace (nt)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n
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3 -fastpaths -xml WarpLC_preroute.twx WarpLC_map.ncd -o WarpLC_preroute.twr
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WarpLC.pcf -ucf PLL.ucf
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Design file: WarpLC_map.ncd
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Physical constraint file: WarpLC.pcf
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Device,package,speed: xc6slx9,ftg256,C,-2 (PRODUCTION 1.23 2013-10-13)
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Report level: verbose report
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Environment Variable Effect
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-------------------- ------
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NONE No environment variables were set
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--------------------------------------------------------------------------------
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INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
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INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
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option. All paths that are not constrained will be reported in the
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unconstrained paths section(s) of the report.
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INFO:Timing:3284 - This timing report was generated using estimated delay
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information. For accurate numbers, please refer to the post Place and Route
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timing report.
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INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
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a 50 Ohm transmission line loading model. For the details of this model,
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and for more information on accounting for different loading conditions,
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please see the device datasheet.
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================================================================================
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Timing constraint: NET "FSBCLK" PERIOD = 10 ns HIGH 50%;
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For more information, see Period Analysis in the Timing Closure User Guide (UG612).
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0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
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0 timing errors detected. (0 component switching limit errors)
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Minimum period is 1.866ns.
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--------------------------------------------------------------------------------
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Component Switching Limit Checks: NET "FSBCLK" PERIOD = 10 ns HIGH 50%;
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--------------------------------------------------------------------------------
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Slack: 8.134ns (period - min period limit)
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Period: 10.000ns
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Min period limit: 1.866ns (535.906MHz) (Tickper)
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Physical resource: OUTt_OBUF/CLK0
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Logical resource: OUTt/CLK0
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Location pin: ILOGIC_X0Y5.CLK0
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Clock network: FSBCLK
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--------------------------------------------------------------------------------
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================================================================================
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Timing constraint: NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;
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For more information, see Period Analysis in the Timing Closure User Guide (UG612).
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0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
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0 timing errors detected. (0 component switching limit errors)
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Minimum period is 5.000ns.
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--------------------------------------------------------------------------------
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Component Switching Limit Checks: NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;
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--------------------------------------------------------------------------------
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Slack: 15.000ns (period - (min low pulse limit / (low pulse / period)))
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Period: 20.000ns
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Low pulse: 10.000ns
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Low pulse limit: 2.500ns (Tdcmpw_CLKIN_50_100)
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Physical resource: instance_name/pll_base_inst/PLL_ADV/CLKIN1
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Logical resource: instance_name/pll_base_inst/PLL_ADV/CLKIN1
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Location pin: PLL_ADV_X0Y1.CLKIN1
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Clock network: instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
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--------------------------------------------------------------------------------
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Slack: 15.000ns (period - (min high pulse limit / (high pulse / period)))
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Period: 20.000ns
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High pulse: 10.000ns
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High pulse limit: 2.500ns (Tdcmpw_CLKIN_50_100)
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Physical resource: instance_name/pll_base_inst/PLL_ADV/CLKIN1
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Logical resource: instance_name/pll_base_inst/PLL_ADV/CLKIN1
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Location pin: PLL_ADV_X0Y1.CLKIN1
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Clock network: instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
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--------------------------------------------------------------------------------
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Slack: 17.780ns (period - min period limit)
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Period: 20.000ns
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Min period limit: 2.220ns (450.450MHz) (Tpllper_CLKIN(Finmax))
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Physical resource: instance_name/pll_base_inst/PLL_ADV/CLKIN1
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Logical resource: instance_name/pll_base_inst/PLL_ADV/CLKIN1
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Location pin: PLL_ADV_X0Y1.CLKIN1
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Clock network: instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
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--------------------------------------------------------------------------------
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================================================================================
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Timing constraint: PERIOD analysis for net "instance_name/clkfbout" derived
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from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; duty cycle corrected
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to 20 nS HIGH 10 nS
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For more information, see Period Analysis in the Timing Closure User Guide (UG612).
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0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
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0 timing errors detected. (0 component switching limit errors)
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Minimum period is 2.666ns.
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--------------------------------------------------------------------------------
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Component Switching Limit Checks: PERIOD analysis for net "instance_name/clkfbout" derived from
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NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;
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duty cycle corrected to 20 nS HIGH 10 nS
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--------------------------------------------------------------------------------
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Slack: 17.334ns (period - min period limit)
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Period: 20.000ns
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Min period limit: 2.666ns (375.094MHz) (Tbcper_I)
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Physical resource: instance_name/clkfbout_bufg/I0
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Logical resource: instance_name/clkfbout_bufg/I0
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Location pin: BUFGMUX_X2Y3.I0
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Clock network: instance_name/clkfbout
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--------------------------------------------------------------------------------
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Slack: 17.751ns (period - min period limit)
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Period: 20.000ns
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Min period limit: 2.249ns (444.642MHz) (Tockper)
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Physical resource: CLKFB_OUT_OBUF/CLK0
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Logical resource: instance_name/clkfbout_oddr/CK0
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Location pin: OLOGIC_X0Y7.CLK0
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Clock network: instance_name/clkfb_bufg_out
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--------------------------------------------------------------------------------
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Slack: 17.780ns (period - min period limit)
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Period: 20.000ns
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Min period limit: 2.220ns (450.450MHz) (Tpllper_CLKFB)
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Physical resource: instance_name/pll_base_inst/PLL_ADV/CLKFBOUT
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Logical resource: instance_name/pll_base_inst/PLL_ADV/CLKFBOUT
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Location pin: PLL_ADV_X0Y1.CLKFBOUT
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Clock network: instance_name/clkfbout
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--------------------------------------------------------------------------------
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================================================================================
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Timing constraint: PERIOD analysis for net "instance_name/clkout0" derived from
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NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; divided by 2.00 to 10 nS
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For more information, see Period Analysis in the Timing Closure User Guide (UG612).
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0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
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0 timing errors detected. (0 component switching limit errors)
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Minimum period is 2.666ns.
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--------------------------------------------------------------------------------
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Component Switching Limit Checks: PERIOD analysis for net "instance_name/clkout0" derived from
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NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;
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divided by 2.00 to 10 nS
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--------------------------------------------------------------------------------
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Slack: 7.334ns (period - min period limit)
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Period: 10.000ns
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Min period limit: 2.666ns (375.094MHz) (Tbcper_I)
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Physical resource: instance_name/clkout1_buf/I0
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Logical resource: instance_name/clkout1_buf/I0
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Location pin: BUFGMUX_X3Y13.I0
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Clock network: instance_name/clkout0
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--------------------------------------------------------------------------------
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Slack: 8.948ns (period - min period limit)
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Period: 10.000ns
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Min period limit: 1.052ns (950.570MHz) (Tpllper_CLKOUT(Foutmax))
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Physical resource: instance_name/pll_base_inst/PLL_ADV/CLKOUT0
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Logical resource: instance_name/pll_base_inst/PLL_ADV/CLKOUT0
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Location pin: PLL_ADV_X0Y1.CLKOUT0
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Clock network: instance_name/clkout0
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--------------------------------------------------------------------------------
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Slack: 310.000ns (max period limit - period)
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Period: 10.000ns
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Max period limit: 320.000ns (3.125MHz) (Tpllper_CLKOUT(Foutmin))
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Physical resource: instance_name/pll_base_inst/PLL_ADV/CLKOUT0
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Logical resource: instance_name/pll_base_inst/PLL_ADV/CLKOUT0
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Location pin: PLL_ADV_X0Y1.CLKOUT0
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Clock network: instance_name/clkout0
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--------------------------------------------------------------------------------
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================================================================================
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Timing constraint: COMP "CPU_nAS" OFFSET = IN 10 ns VALID 11 ns BEFORE COMP
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"CLKIN";
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For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).
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1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
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0 timing errors detected. (0 setup errors, 0 hold errors)
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Minimum allowable offset is 9.880ns.
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--------------------------------------------------------------------------------
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Paths for end point OUTt (ILOGIC_X0Y5.SR), 1 path
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--------------------------------------------------------------------------------
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Slack (setup path): 0.120ns (requirement - (data path - clock path - clock arrival + uncertainty))
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Source: CPU_nAS (PAD)
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Destination: OUTt (FF)
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Destination Clock: FSBCLK rising at 0.000ns
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Requirement: 10.000ns
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Data Path Delay: 4.575ns (Levels of Logic = 1)
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Clock Path Delay: -4.891ns (Levels of Logic = 4)
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Clock Uncertainty: 0.414ns
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Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.050ns
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Discrete Jitter (DJ): 0.287ns
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Phase Error (PE): 0.267ns
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Maximum Data Path at Slow Process Corner: CPU_nAS to OUTt
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Location Delay type Delay(ns) Physical Resource
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Logical Resource(s)
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------------------------------------------------- -------------------
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N4.I Tiopi 1.557 CPU_nAS
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CPU_nAS
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CPU_nAS_IBUF
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ProtoComp0.IMUX.1
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ILOGIC_X0Y5.SR net (fanout=1) e 2.043 CPU_nAS_IBUF
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ILOGIC_X0Y5.CLK0 Tisrck 0.975 OUTt_OBUF
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OUTt
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------------------------------------------------- ---------------------------
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Total 4.575ns (2.532ns logic, 2.043ns route)
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(55.3% logic, 44.7% route)
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Minimum Clock Path at Slow Process Corner: CLKIN to OUTt
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Location Delay type Delay(ns) Physical Resource
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Logical Resource(s)
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------------------------------------------------- -------------------
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J4.I Tiopi 0.902 CLKIN
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CLKIN
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instance_name/clkin1_buf
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ProtoComp0.IMUX.3
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BUFIO2_X0Y23.I net (fanout=1) e 0.000 instance_name/clkin1
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BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
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SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
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PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
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PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -8.248 instance_name/pll_base_inst/PLL_ADV
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instance_name/pll_base_inst/PLL_ADV
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BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 instance_name/clkout0
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BUFGMUX_X3Y13.O Tgi0o 0.197 instance_name/clkout1_buf
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instance_name/clkout1_buf
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ILOGIC_X0Y5.CLK0 net (fanout=1) e 1.574 FSBCLK
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------------------------------------------------- ---------------------------
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Total -4.891ns (-6.970ns logic, 2.079ns route)
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--------------------------------------------------------------------------------
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Hold Paths: COMP "CPU_nAS" OFFSET = IN 10 ns VALID 11 ns BEFORE COMP "CLKIN";
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--------------------------------------------------------------------------------
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Paths for end point OUTt (ILOGIC_X0Y5.SR), 1 path
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--------------------------------------------------------------------------------
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Slack (hold path): 6.650ns (requirement - (clock path + clock arrival + uncertainty - data path))
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Source: CPU_nAS (PAD)
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Destination: OUTt (FF)
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Destination Clock: FSBCLK rising at 0.000ns
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Requirement: 1.000ns
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Data Path Delay: 2.965ns (Levels of Logic = 1)
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Clock Path Delay: -3.099ns (Levels of Logic = 4)
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Clock Uncertainty: 0.414ns
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Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.050ns
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Discrete Jitter (DJ): 0.287ns
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Phase Error (PE): 0.267ns
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Minimum Data Path at Fast Process Corner: CPU_nAS to OUTt
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Location Delay type Delay(ns) Physical Resource
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Logical Resource(s)
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------------------------------------------------- -------------------
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N4.I Tiopi 0.763 CPU_nAS
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CPU_nAS
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CPU_nAS_IBUF
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ProtoComp0.IMUX.1
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ILOGIC_X0Y5.SR net (fanout=1) e 2.043 CPU_nAS_IBUF
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ILOGIC_X0Y5.CLK0 Ticksr (-Th) -0.159 OUTt_OBUF
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OUTt
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------------------------------------------------- ---------------------------
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Total 2.965ns (0.922ns logic, 2.043ns route)
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(31.1% logic, 68.9% route)
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Maximum Clock Path at Fast Process Corner: CLKIN to OUTt
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Location Delay type Delay(ns) Physical Resource
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Logical Resource(s)
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------------------------------------------------- -------------------
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J4.I Tiopi 0.367 CLKIN
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CLKIN
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instance_name/clkin1_buf
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ProtoComp0.IMUX.3
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BUFIO2_X0Y23.I net (fanout=1) e 0.000 instance_name/clkin1
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BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
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SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
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PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
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PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -5.738 instance_name/pll_base_inst/PLL_ADV
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instance_name/pll_base_inst/PLL_ADV
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BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 instance_name/clkout0
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BUFGMUX_X3Y13.O Tgi0o 0.063 instance_name/clkout1_buf
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instance_name/clkout1_buf
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ILOGIC_X0Y5.CLK0 net (fanout=1) e 1.574 FSBCLK
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------------------------------------------------- ---------------------------
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Total -3.099ns (-5.178ns logic, 2.079ns route)
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--------------------------------------------------------------------------------
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================================================================================
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Timing constraint: COMP "INt" OFFSET = IN 10 ns VALID 11 ns BEFORE COMP
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"CLKIN";
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For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).
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1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
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0 timing errors detected. (0 setup errors, 0 hold errors)
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Minimum allowable offset is 8.814ns.
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--------------------------------------------------------------------------------
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Paths for end point OUTt (ILOGIC_X0Y5.D), 1 path
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--------------------------------------------------------------------------------
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Slack (setup path): 1.186ns (requirement - (data path - clock path - clock arrival + uncertainty))
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Source: INt (PAD)
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Destination: OUTt (FF)
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Destination Clock: FSBCLK rising at 0.000ns
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Requirement: 10.000ns
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Data Path Delay: 3.509ns (Levels of Logic = 2)
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Clock Path Delay: -4.891ns (Levels of Logic = 4)
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Clock Uncertainty: 0.414ns
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Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.050ns
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Discrete Jitter (DJ): 0.287ns
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Phase Error (PE): 0.267ns
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Maximum Data Path at Slow Process Corner: INt to OUTt
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Location Delay type Delay(ns) Physical Resource
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Logical Resource(s)
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------------------------------------------------- -------------------
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M4.I Tiopi 1.557 INt
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INt
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INt_IBUF
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ProtoComp0.IMUX.2
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ILOGIC_X0Y5.D net (fanout=1) e 0.229 CPU_nAS_INt_AND_1_o_norst
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ILOGIC_X0Y5.CLK0 Tidock 1.723 OUTt_OBUF
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ProtoComp3.D2OFFBYP_SRC
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OUTt
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------------------------------------------------- ---------------------------
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Total 3.509ns (3.280ns logic, 0.229ns route)
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(93.5% logic, 6.5% route)
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Minimum Clock Path at Slow Process Corner: CLKIN to OUTt
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Location Delay type Delay(ns) Physical Resource
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Logical Resource(s)
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------------------------------------------------- -------------------
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J4.I Tiopi 0.902 CLKIN
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CLKIN
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instance_name/clkin1_buf
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ProtoComp0.IMUX.3
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BUFIO2_X0Y23.I net (fanout=1) e 0.000 instance_name/clkin1
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BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
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SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
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PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
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PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -8.248 instance_name/pll_base_inst/PLL_ADV
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instance_name/pll_base_inst/PLL_ADV
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BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 instance_name/clkout0
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BUFGMUX_X3Y13.O Tgi0o 0.197 instance_name/clkout1_buf
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instance_name/clkout1_buf
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ILOGIC_X0Y5.CLK0 net (fanout=1) e 1.574 FSBCLK
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------------------------------------------------- ---------------------------
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Total -4.891ns (-6.970ns logic, 2.079ns route)
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--------------------------------------------------------------------------------
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Hold Paths: COMP "INt" OFFSET = IN 10 ns VALID 11 ns BEFORE COMP "CLKIN";
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--------------------------------------------------------------------------------
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Paths for end point OUTt (ILOGIC_X0Y5.D), 1 path
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--------------------------------------------------------------------------------
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Slack (hold path): 5.307ns (requirement - (clock path + clock arrival + uncertainty - data path))
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Source: INt (PAD)
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Destination: OUTt (FF)
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Destination Clock: FSBCLK rising at 0.000ns
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Requirement: 1.000ns
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Data Path Delay: 1.622ns (Levels of Logic = 2)
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Clock Path Delay: -3.099ns (Levels of Logic = 4)
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Clock Uncertainty: 0.414ns
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Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.050ns
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Discrete Jitter (DJ): 0.287ns
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Phase Error (PE): 0.267ns
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Minimum Data Path at Fast Process Corner: INt to OUTt
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Location Delay type Delay(ns) Physical Resource
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Logical Resource(s)
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------------------------------------------------- -------------------
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M4.I Tiopi 0.763 INt
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INt
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INt_IBUF
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ProtoComp0.IMUX.2
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ILOGIC_X0Y5.D net (fanout=1) e 0.229 CPU_nAS_INt_AND_1_o_norst
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ILOGIC_X0Y5.CLK0 Tiockd (-Th) -0.630 OUTt_OBUF
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ProtoComp3.D2OFFBYP_SRC
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OUTt
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------------------------------------------------- ---------------------------
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Total 1.622ns (1.393ns logic, 0.229ns route)
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(85.9% logic, 14.1% route)
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Maximum Clock Path at Fast Process Corner: CLKIN to OUTt
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Location Delay type Delay(ns) Physical Resource
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Logical Resource(s)
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------------------------------------------------- -------------------
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J4.I Tiopi 0.367 CLKIN
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CLKIN
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instance_name/clkin1_buf
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ProtoComp0.IMUX.3
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BUFIO2_X0Y23.I net (fanout=1) e 0.000 instance_name/clkin1
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BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
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SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
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PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
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PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -5.738 instance_name/pll_base_inst/PLL_ADV
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instance_name/pll_base_inst/PLL_ADV
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BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 instance_name/clkout0
|
|
BUFGMUX_X3Y13.O Tgi0o 0.063 instance_name/clkout1_buf
|
|
instance_name/clkout1_buf
|
|
ILOGIC_X0Y5.CLK0 net (fanout=1) e 1.574 FSBCLK
|
|
------------------------------------------------- ---------------------------
|
|
Total -3.099ns (-5.178ns logic, 2.079ns route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
|
|
================================================================================
|
|
Timing constraint: COMP "OUTt" OFFSET = OUT 4 ns AFTER COMP "CLKIN";
|
|
For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612).
|
|
|
|
1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
|
|
0 timing errors detected.
|
|
Minimum allowable offset is 1.412ns.
|
|
--------------------------------------------------------------------------------
|
|
|
|
Paths for end point OUTt (M3.PAD), 1 path
|
|
--------------------------------------------------------------------------------
|
|
Slack (slowest paths): 2.588ns (requirement - (clock arrival + clock path + data path + uncertainty))
|
|
Source: OUTt (FF)
|
|
Destination: OUTt (PAD)
|
|
Source Clock: FSBCLK rising at 0.000ns
|
|
Requirement: 4.000ns
|
|
Data Path Delay: 6.068ns (Levels of Logic = 1)
|
|
Clock Path Delay: -5.070ns (Levels of Logic = 4)
|
|
Clock Uncertainty: 0.414ns
|
|
|
|
Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.287ns
|
|
Phase Error (PE): 0.267ns
|
|
|
|
Maximum Clock Path at Slow Process Corner: CLKIN to OUTt
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
J4.I Tiopi 1.037 CLKIN
|
|
CLKIN
|
|
instance_name/clkin1_buf
|
|
ProtoComp0.IMUX.3
|
|
BUFIO2_X0Y23.I net (fanout=1) e 0.000 instance_name/clkin1
|
|
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
|
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
|
PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
|
|
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -8.585 instance_name/pll_base_inst/PLL_ADV
|
|
instance_name/pll_base_inst/PLL_ADV
|
|
BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 instance_name/clkout0
|
|
BUFGMUX_X3Y13.O Tgi0o 0.209 instance_name/clkout1_buf
|
|
instance_name/clkout1_buf
|
|
ILOGIC_X0Y5.CLK0 net (fanout=1) e 1.574 FSBCLK
|
|
------------------------------------------------- ---------------------------
|
|
Total -5.070ns (-7.149ns logic, 2.079ns route)
|
|
|
|
Maximum Data Path at Slow Process Corner: OUTt to OUTt
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
ILOGIC_X0Y5.Q4 Tickq 1.778 OUTt_OBUF
|
|
OUTt
|
|
M3.O net (fanout=1) e 2.308 OUTt_OBUF
|
|
M3.PAD Tioop 1.982 OUTt
|
|
OUTt_OBUF
|
|
OUTt
|
|
------------------------------------------------- ---------------------------
|
|
Total 6.068ns (3.760ns logic, 2.308ns route)
|
|
(62.0% logic, 38.0% route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
|
|
Fastest Paths: COMP "OUTt" OFFSET = OUT 4 ns AFTER COMP "CLKIN";
|
|
--------------------------------------------------------------------------------
|
|
|
|
Paths for end point OUTt (M3.PAD), 1 path
|
|
--------------------------------------------------------------------------------
|
|
Delay (fastest paths): 0.213ns (clock arrival + clock path + data path - uncertainty)
|
|
Source: OUTt (FF)
|
|
Destination: OUTt (PAD)
|
|
Source Clock: FSBCLK rising at 0.000ns
|
|
Data Path Delay: 3.663ns (Levels of Logic = 1)
|
|
Clock Path Delay: -3.036ns (Levels of Logic = 4)
|
|
Clock Uncertainty: 0.414ns
|
|
|
|
Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.287ns
|
|
Phase Error (PE): 0.267ns
|
|
|
|
Minimum Clock Path at Fast Process Corner: CLKIN to OUTt
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
J4.I Tiopi 0.321 CLKIN
|
|
CLKIN
|
|
instance_name/clkin1_buf
|
|
ProtoComp0.IMUX.3
|
|
BUFIO2_X0Y23.I net (fanout=1) e 0.000 instance_name/clkin1
|
|
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
|
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
|
PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
|
|
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -5.617 instance_name/pll_base_inst/PLL_ADV
|
|
instance_name/pll_base_inst/PLL_ADV
|
|
BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 instance_name/clkout0
|
|
BUFGMUX_X3Y13.O Tgi0o 0.059 instance_name/clkout1_buf
|
|
instance_name/clkout1_buf
|
|
ILOGIC_X0Y5.CLK0 net (fanout=1) e 1.574 FSBCLK
|
|
------------------------------------------------- ---------------------------
|
|
Total -3.036ns (-5.115ns logic, 2.079ns route)
|
|
|
|
Minimum Data Path at Fast Process Corner: OUTt to OUTt
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
ILOGIC_X0Y5.Q4 Tickq 0.656 OUTt_OBUF
|
|
OUTt
|
|
M3.O net (fanout=1) e 2.308 OUTt_OBUF
|
|
M3.PAD Tioop 0.699 OUTt
|
|
OUTt_OBUF
|
|
OUTt
|
|
------------------------------------------------- ---------------------------
|
|
Total 3.663ns (1.355ns logic, 2.308ns route)
|
|
(37.0% logic, 63.0% route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Derived Constraint Report
|
|
Derived Constraints for instance_name/clkin1
|
|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
|
| | Period | Actual Period | Timing Errors | Paths Analyzed |
|
|
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|
|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
|
|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
|
|instance_name/clkin1 | 20.000ns| 5.000ns| 5.332ns| 0| 0| 0| 0|
|
|
| instance_name/clkfbout | 20.000ns| 2.666ns| N/A| 0| 0| 0| 0|
|
|
| instance_name/clkout0 | 10.000ns| 2.666ns| N/A| 0| 0| 0| 0|
|
|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
|
|
|
All constraints were met.
|
|
|
|
|
|
Data Sheet report:
|
|
-----------------
|
|
All values displayed in nanoseconds (ns)
|
|
|
|
Setup/Hold to clock CLKIN
|
|
------------+------------+------------+------------+------------+------------------+--------+
|
|
|Max Setup to| Process |Max Hold to | Process | | Clock |
|
|
Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase |
|
|
------------+------------+------------+------------+------------+------------------+--------+
|
|
CPU_nAS | 9.880(R)| SLOW | -5.650(R)| FAST |FSBCLK | 0.000|
|
|
INt | 8.814(R)| SLOW | -4.307(R)| FAST |FSBCLK | 0.000|
|
|
------------+------------+------------+------------+------------+------------------+--------+
|
|
|
|
Clock CLKIN to Pad
|
|
------------+-----------------+------------+-----------------+------------+------------------+--------+
|
|
|Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
|
|
Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
|
|
------------+-----------------+------------+-----------------+------------+------------------+--------+
|
|
OUTt | 1.412(R)| SLOW | 0.213(R)| FAST |FSBCLK | 0.000|
|
|
------------+-----------------+------------+-----------------+------------+------------------+--------+
|
|
|
|
COMP "CPU_nAS" OFFSET = IN 10 ns VALID 11 ns BEFORE COMP "CLKIN";
|
|
Worst Case Data Window 4.230; Ideal Clock Offset To Actual Clock 3.265;
|
|
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
|
| | Process | | Process | Setup | Hold |Source Offset|
|
|
Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center |
|
|
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
|
CPU_nAS | 9.880(R)| SLOW | -5.650(R)| FAST | 0.120| 6.650| -3.265|
|
|
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
|
Worst Case Summary| 9.880| - | -5.650| - | 0.120| 6.650| |
|
|
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
|
|
|
COMP "INt" OFFSET = IN 10 ns VALID 11 ns BEFORE COMP "CLKIN";
|
|
Worst Case Data Window 4.507; Ideal Clock Offset To Actual Clock 2.061;
|
|
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
|
| | Process | | Process | Setup | Hold |Source Offset|
|
|
Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center |
|
|
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
|
INt | 8.814(R)| SLOW | -4.307(R)| FAST | 1.186| 5.307| -2.061|
|
|
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
|
Worst Case Summary| 8.814| - | -4.307| - | 1.186| 5.307| |
|
|
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
|
|
|
COMP "OUTt" OFFSET = OUT 4 ns AFTER COMP "CLKIN";
|
|
Bus Skew: 0.000 ns;
|
|
-----------------------------------------------+-------------+------------+-------------+------------+--------------+
|
|
|Max (slowest)| Process |Min (fastest)| Process | |
|
|
PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)|
|
|
-----------------------------------------------+-------------+------------+-------------+------------+--------------+
|
|
OUTt | 1.412| SLOW | 0.213| FAST | 0.000|
|
|
-----------------------------------------------+-------------+------------+-------------+------------+--------------+
|
|
|
|
|
|
Timing summary:
|
|
---------------
|
|
|
|
Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
|
|
|
|
Constraints cover 3 paths, 0 nets, and 12 connections
|
|
|
|
Design statistics:
|
|
Minimum period: 5.000ns{1} (Maximum frequency: 200.000MHz)
|
|
Minimum input required time before clock: 9.880ns
|
|
Minimum output required time after clock: 1.412ns
|
|
|
|
|
|
------------------------------------Footnotes-----------------------------------
|
|
1) The minimum period statistic assumes all single cycle delays.
|
|
|
|
Analysis completed Fri Oct 29 10:25:28 2021
|
|
--------------------------------------------------------------------------------
|
|
|
|
Trace Settings:
|
|
-------------------------
|
|
Trace Settings
|
|
|
|
Peak Memory Usage: 167 MB
|
|
|
|
|
|
|