171 lines
8.4 KiB
HTML
171 lines
8.4 KiB
HTML
<html><head><link type='text/css' href='style.css' rel='stylesheet'></head><body class='pgBgnd'>
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<h3 align='center'>Equations</h3>
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<table width='90%' align='center' border='1' cellpadding='0' cellspacing='0'>
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<tr><td>
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</td></tr><tr><td>
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********** Mapped Logic **********
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$OpTx$BIN_STEP$409 <= ((EXP9_.EXP)
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<br/> OR (A(5) AND NOT NC(3) AND NOT STERM)
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<br/> OR (NOT A(5) AND NC(3) AND NOT STERM)
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<br/> OR (A(9) AND NOT NC(7) AND NOT STERM)
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<br/> OR (NOT A(9) AND NC(7) AND NOT STERM)
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<br/> OR (A(19) AND NOT NR(8) AND NOT STERM)
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<br/> OR (EXP12_.EXP)
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<br/> OR (NOT A(24) AND NB(0) AND NOT STERM)
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<br/> OR (A(4) AND NOT NC(2) AND NOT STERM)
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<br/> OR (NOT A(4) AND NC(2) AND NOT STERM)
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<br/> OR (A(8) AND NOT NC(6) AND NOT STERM)
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<br/> OR (NOT A(8) AND NC(6) AND NOT STERM)
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<br/> OR (NOT FC(2) AND NOT STERM)
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<br/> OR (A(31) AND NOT STERM)
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<br/> OR (A(15) AND NOT NR(4) AND NOT STERM)
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<br/> OR (NOT A(15) AND NR(4) AND NOT STERM)
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<br/> OR (NOT A(19) AND NR(8) AND NOT STERM));
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FDCPE_NA: FDCPE port map (NA,NA_D,CLK,'0','0');
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<br/> NA_D <= ((CMD(0) AND NOT CMD(1))
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<br/> OR (NOT CMD(1) AND NA));
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</td></tr><tr><td>
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FDCPE_NB0: FDCPE port map (NB(0),A(24),CLK,'0','0',NB_CE(0));
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<br/> NB_CE(0) <= (CMD(0) AND NOT CMD(1));
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</td></tr><tr><td>
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FDCPE_NB1: FDCPE port map (NB(1),A(25),CLK,'0','0',NB_CE(1));
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<br/> NB_CE(1) <= (CMD(0) AND NOT CMD(1));
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</td></tr><tr><td>
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FDCPE_NC0: FDCPE port map (NC(0),NOT A(2),CLK,'0','0',NC_CE(0));
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<br/> NC_CE(0) <= (CMD(0) AND NOT CMD(1));
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</td></tr><tr><td>
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FDCPE_NC1: FDCPE port map (NC(1),NC_D(1),CLK,'0','0',NC_CE(1));
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<br/> NC_D(1) <= A(2)
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<br/> XOR
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<br/> NC_D(1) <= A(3);
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<br/> NC_CE(1) <= (CMD(0) AND NOT CMD(1));
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</td></tr><tr><td>
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FDCPE_NC2: FDCPE port map (NC(2),NC_D(2),CLK,'0','0',NC_CE(2));
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<br/> NC_D(2) <= A(4)
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<br/> XOR
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<br/> NC_D(2) <= (A(2) AND A(3));
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<br/> NC_CE(2) <= (CMD(0) AND NOT CMD(1));
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</td></tr><tr><td>
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FDCPE_NC3: FDCPE port map (NC(3),NC_D(3),CLK,'0','0',NC_CE(3));
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<br/> NC_D(3) <= A(5)
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<br/> XOR
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<br/> NC_D(3) <= (A(2) AND A(3) AND A(4));
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<br/> NC_CE(3) <= (CMD(0) AND NOT CMD(1));
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</td></tr><tr><td>
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FDCPE_NC4: FDCPE port map (NC(4),NC_D(4),CLK,'0','0',NC_CE(4));
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<br/> NC_D(4) <= A(6)
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<br/> XOR
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<br/> NC_D(4) <= (A(2) AND A(3) AND A(4) AND A(5));
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<br/> NC_CE(4) <= (CMD(0) AND NOT CMD(1));
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</td></tr><tr><td>
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FDCPE_NC5: FDCPE port map (NC(5),NC_D(5),CLK,'0','0',NC_CE(5));
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<br/> NC_D(5) <= A(7)
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<br/> XOR
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<br/> NC_D(5) <= (A(2) AND A(3) AND A(4) AND A(5) AND A(6));
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<br/> NC_CE(5) <= (CMD(0) AND NOT CMD(1));
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</td></tr><tr><td>
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FDCPE_NC6: FDCPE port map (NC(6),NC_D(6),CLK,'0','0',NC_CE(6));
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<br/> NC_D(6) <= A(8)
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<br/> XOR
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<br/> NC_D(6) <= (A(2) AND A(3) AND A(4) AND A(5) AND A(6) AND A(7));
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<br/> NC_CE(6) <= (CMD(0) AND NOT CMD(1));
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</td></tr><tr><td>
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FDCPE_NC7: FDCPE port map (NC(7),NC_D(7),CLK,'0','0',NC_CE(7));
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<br/> NC_D(7) <= A(9)
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<br/> XOR
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<br/> NC_D(7) <= (A(2) AND A(3) AND A(4) AND A(5) AND A(6) AND A(7) AND
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<br/> A(8));
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<br/> NC_CE(7) <= (CMD(0) AND NOT CMD(1));
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</td></tr><tr><td>
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FDCPE_NC8: FDCPE port map (NC(8),NC_D(8),CLK,'0','0',NC_CE(8));
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<br/> NC_D(8) <= A(10)
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<br/> XOR
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<br/> NC_D(8) <= (A(2) AND A(3) AND A(4) AND A(5) AND A(6) AND A(7) AND
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<br/> A(8) AND A(9));
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<br/> NC_CE(8) <= (CMD(0) AND NOT CMD(1));
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</td></tr><tr><td>
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FDCPE_NR0: FDCPE port map (NR(0),A(11),CLK,'0','0',NR_CE(0));
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<br/> NR_CE(0) <= (CMD(0) AND NOT CMD(1));
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</td></tr><tr><td>
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FDCPE_NR1: FDCPE port map (NR(1),A(12),CLK,'0','0',NR_CE(1));
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<br/> NR_CE(1) <= (CMD(0) AND NOT CMD(1));
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</td></tr><tr><td>
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FDCPE_NR2: FDCPE port map (NR(2),A(13),CLK,'0','0',NR_CE(2));
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<br/> NR_CE(2) <= (CMD(0) AND NOT CMD(1));
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</td></tr><tr><td>
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FDCPE_NR3: FDCPE port map (NR(3),A(14),CLK,'0','0',NR_CE(3));
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<br/> NR_CE(3) <= (CMD(0) AND NOT CMD(1));
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</td></tr><tr><td>
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FDCPE_NR4: FDCPE port map (NR(4),A(15),CLK,'0','0',NR_CE(4));
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<br/> NR_CE(4) <= (CMD(0) AND NOT CMD(1));
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</td></tr><tr><td>
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FDCPE_NR5: FDCPE port map (NR(5),A(16),CLK,'0','0',NR_CE(5));
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<br/> NR_CE(5) <= (CMD(0) AND NOT CMD(1));
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</td></tr><tr><td>
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FDCPE_NR6: FDCPE port map (NR(6),A(17),CLK,'0','0',NR_CE(6));
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<br/> NR_CE(6) <= (CMD(0) AND NOT CMD(1));
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</td></tr><tr><td>
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FDCPE_NR7: FDCPE port map (NR(7),A(18),CLK,'0','0',NR_CE(7));
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<br/> NR_CE(7) <= (CMD(0) AND NOT CMD(1));
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</td></tr><tr><td>
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FDCPE_NR8: FDCPE port map (NR(8),A(19),CLK,'0','0',NR_CE(8));
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<br/> NR_CE(8) <= (CMD(0) AND NOT CMD(1));
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</td></tr><tr><td>
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FDCPE_NR9: FDCPE port map (NR(9),A(20),CLK,'0','0',NR_CE(9));
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<br/> NR_CE(9) <= (CMD(0) AND NOT CMD(1));
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</td></tr><tr><td>
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FDCPE_NR10: FDCPE port map (NR(10),A(21),CLK,'0','0',NR_CE(10));
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<br/> NR_CE(10) <= (CMD(0) AND NOT CMD(1));
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</td></tr><tr><td>
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FDCPE_NR11: FDCPE port map (NR(11),A(22),CLK,'0','0',NR_CE(11));
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<br/> NR_CE(11) <= (CMD(0) AND NOT CMD(1));
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</td></tr><tr><td>
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FDCPE_NR12: FDCPE port map (NR(12),A(23),CLK,'0','0',NR_CE(12));
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<br/> NR_CE(12) <= (CMD(0) AND NOT CMD(1));
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</td></tr><tr><td>
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</td></tr><tr><td>
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nFPUCS <= NOT (((FC(1) AND FC(0) AND A(17) AND A(13) AND NOT A(14) AND NOT A(15) AND
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<br/> NOT A(16) AND NOT A(18) AND NOT A(19) AND FC(2) AND NOT nAS)
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<br/> OR (FC(1) AND FC(0) AND A(17) AND A(13) AND NOT A(14) AND NOT A(15) AND
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<br/> NOT A(16) AND NOT A(18) AND NOT A(19) AND FC(2) AND NOT CLKdat)));
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</td></tr><tr><td>
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</td></tr><tr><td>
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nSTERM <= NOT (((STERM AND NOT $OpTx$BIN_STEP$409)
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<br/> OR (NOT FC(0) AND NA AND NOT $OpTx$BIN_STEP$409)));
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</td></tr><tr><td>
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Register Legend:
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<br/> FDCPE (Q,D,C,CLR,PRE,CE);
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<br/> FTCPE (Q,D,C,CLR,PRE,CE);
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<br/> LDCP (Q,D,G,CLR,PRE);
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</td></tr><tr><td>
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</td></tr>
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</table>
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