125 lines
7.5 KiB
XML
125 lines
7.5 KiB
XML
<?xml version='1.0' encoding='utf-8'?>
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<!--This is an ISE project configuration file.-->
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<!--It holds project specific layout data for the projectmgr plugin.-->
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<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
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<Project version="2" owner="projectmgr" name="WarpLC" >
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<!--This is an ISE project configuration file.-->
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<ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
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<ClosedNodes>
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<SelectedItem>cs - CS (C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/CS.v)</SelectedItem>
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<ClosedNodes>
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<ClosedNodesVersion>1</ClosedNodesVersion>
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<ClosedNode>Configure Target Device</ClosedNode>
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<ClosedNode>Design Utilities</ClosedNode>
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<ClosedNode>Implement Design</ClosedNode>
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<ClosedNode>Synthesize - XST</ClosedNode>
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<ClosedNode>User Constraints</ClosedNode>
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<CurrentItem>work</CurrentItem>
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</ItemView>
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<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
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<ClosedNodes>
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<ClosedNodesVersion>1</ClosedNodesVersion>
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<ClosedNode>Configure Target Device</ClosedNode>
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<ClosedNode>Design Utilities</ClosedNode>
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<ClosedNode>Implement Design</ClosedNode>
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<ClosedNode>Synthesize - XST</ClosedNode>
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<ClosedNode>User Constraints</ClosedNode>
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</ClosedNodes>
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<SelectedItem/>
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<ClosedNodesVersion>1</ClosedNodesVersion>
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<ClosedNode>Implement Design/Place & Route/Back-annotate Pin Locations</ClosedNode>
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<ClosedNode>Implement Design/Place & Route/Generate IBIS Model</ClosedNode>
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<ClosedNode>Synthesize - XST</ClosedNode>
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<CurrentItem></CurrentItem>
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<CurrentItem>CORE Generator</CurrentItem>
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<CurrentItem/>
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</ItemView>
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<SourceProcessView>000000ff00000000000000020000012e0000011301000000050100000002</SourceProcessView>
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<CurrentView>Implementation</CurrentView>
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</Project>
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