                               Performance Summary Report
                               --------------------------

    Design:     WarpSE
    Device:     XC95144XL-10-TQ100
    Speed File: Version 3.0
    Program:    Timing Report Generator:  version P.20131013
    Date:       Mon Apr 10 20:34:36 2023

    Performance Summary:

    Pad to Pad (tPD)                          :         11.0ns (1 macrocell levels)
    Pad 'A_FSB<23>' to Pad 'nRAS'

    Clock net 'FCLK' path delays:

    Clock Pad to Output Pad (tCO)             :         14.5ns (2 macrocell levels)
    Clock Pad 'FCLK' to Output Pad 'nRES'                                     (GCK)

    Clock to Setup (tCYC)                     :         20.1ns (2 macrocell levels)
    Clock to Q, net 'cnt/IS_FSM_FFd1.Q' to DFF Setup(D) at 'cnt/LTimer<0>.D'        (GCK)
    Target FF drives output net 'cnt/LTimer<0>'

    Setup to Clock at the Pad (tSU)           :         16.6ns (1 macrocell levels)
    Data signal 'A_FSB<23>' to DFF D input Pin at 'cnt/LTimer<0>.D'
    Clock pad 'FCLK'                                                          (GCK)

                              Minimum Clock Period: 20.1ns
                         Maximum Internal Clock Speed: 49.7Mhz
                                (Limited by Cycle Time)

    Clock net 'C16M' path delays:

    Clock Pad to Output Pad (tCO)             :         13.5ns (2 macrocell levels)
    Clock Pad 'C16M' to Output Pad 'nADoutLE0'                                (GCK)

    Clock to Setup (tCYC)                     :         11.0ns (1 macrocell levels)
    Clock to Q, net 'iobm/IOS_FSM_FFd7.Q' to DFF Setup(D) at 'nLDS_IOB.D'        (GCK)
    Target FF drives output net 'nLDS_IOB'

    Setup to Clock at the Pad (tSU)           :          6.5ns (0 macrocell levels)
    Data signal 'C8M' to DFF D input Pin at 'iobm/C8Mr.D'
    Clock pad 'C16M'                                                          (GCK)

                              Minimum Clock Period: 11.0ns
                         Maximum Internal Clock Speed: 90.9Mhz
                                (Limited by Cycle Time)

    Clock net 'C8M' path delays:

    Clock Pad to Output Pad (tCO)             :          5.8ns (1 macrocell levels)
    Clock Pad 'C8M' to Output Pad 'nVMA_IOB'                                  (GCK)

    Clock to Setup (tCYC)                     :         10.0ns (1 macrocell levels)
    Clock to Q, net 'nVMA_IOB.Q' to TFF Setup(D) at 'nVMA_IOB.D'              (GCK)
    Target FF drives output net 'nVMA_IOB'

    Setup to Clock at the Pad (tSU)           :          6.5ns (0 macrocell levels)
    Data signal 'nBERR_IOB' to DFF D input Pin at 'IOBERR.D'
    Clock pad 'C8M'                                                           (GCK)

                              Minimum Clock Period: 10.0ns
                         Maximum Internal Clock Speed: 100.0Mhz
                                (Limited by Cycle Time)

    --------------------------------------------------------------------------------
                                Pad to Pad (tPD) (nsec)

    \ From        A     A     A     A     A     A     A     A     A     A     A
     \            _     _     _     _     _     _     _     _     _     _     _
      \           F     F     F     F     F     F     F     F     F     F     F
       \          S     S     S     S     S     S     S     S     S     S     S
        \         B     B     B     B     B     B     B     B     B     B     B
         \        <     <     <     <     <     <     <     <     <     <     <
          \       1     1     1     1     1     1     1     1     1     1     1
           \      0     1     2     3     4     5     6     7     8     9     >
            \     >     >     >     >     >     >     >     >     >     >
      To     \------------------------------------------------------------------

    RA<0>                                                                  10.0
    RA<10>                                               10.0
    RA<11>                                                           11.0
    RA<1>      10.0
    RA<2>                                          10.0
    RA<3>                                                            10.0
    RA<4>            10.0
    RA<5>                  10.0
    RA<6>                        10.0
    RA<7>                              10.0
    RA<8>                                                      10.0
    RA<9>                                    10.0
    nDinOE
    nRAMLWE
    nRAMUWE
    nRAS
    nROMCS
    nROMWE

    --------------------------------------------------------------------------------
                                Pad to Pad (tPD) (nsec)

    \ From        A     A     A     A     A     A     A     A     A     A     A
     \            _     _     _     _     _     _     _     _     _     _     _
      \           F     F     F     F     F     F     F     F     F     F     F
       \          S     S     S     S     S     S     S     S     S     S     S
        \         B     B     B     B     B     B     B     B     B     B     B
         \        <     <     <     <     <     <     <     <     <     <     <
          \       2     2     2     2     2     3     4     5     6     7     8
           \      0     1     2     3     >     >     >     >     >     >     >
            \     >     >     >     >
      To     \------------------------------------------------------------------

    RA<0>
    RA<10>                                                           10.0
    RA<11>     11.0
    RA<1>                              10.0
    RA<2>                                                            10.0
    RA<3>      10.0
    RA<4>                                    10.0
    RA<5>                                          10.0
    RA<6>                                                10.0
    RA<7>                                                      10.0
    RA<8>            10.0
    RA<9>                                                                  10.0
    nDinOE     10.0  10.0  10.0  10.0
    nRAMLWE
    nRAMUWE
    nRAS                   11.0  11.0
    nROMCS     10.0  10.0  10.0  10.0
    nROMWE

    --------------------------------------------------------------------------------
                                Pad to Pad (tPD) (nsec)

    \ From        A     n     n     n     n
     \            _     A     L     U     W
      \           F     S     D     D     E
       \          S     _     S     S     _
        \         B     F     _     _     F
         \        <     S     F     F     S
          \       9     B     S     S     B
           \      >           B     B
            \
      To     \------------------------------

    RA<0>      10.0
    RA<10>
    RA<11>
    RA<1>
    RA<2>
    RA<3>
    RA<4>
    RA<5>
    RA<6>
    RA<7>
    RA<8>
    RA<9>
    nDinOE           10.0              10.0
    nRAMLWE                10.0        10.0
    nRAMUWE                      11.0  11.0
    nRAS             11.0
    nROMCS
    nROMWE           10.0              10.0

    --------------------------------------------------------------------------------
                          Clock Pad to Output Pad (tCO) (nsec)

    \ From         C     C     F
     \             1     8     C
      \            6     M     L
       \           M           K
        \
         \
          \
           \
            \
             \
      To      \------------------

    RA<0>                   13.5
    RA<10>                  13.5
    RA<11>                  14.5
    RA<1>                   13.5
    RA<2>                   13.5
    RA<3>                   13.5
    RA<4>                   13.5
    RA<5>                   13.5
    RA<6>                   13.5
    RA<7>                   13.5
    RA<8>                   13.5
    RA<9>                   13.5
    nADoutLE0   13.5        13.5
    nADoutLE1                5.8
    nAS_IOB      5.8        14.5
    nAoutOE                  5.8
    nBERR_FSB                5.8
    nBR_IOB                  5.8
    nCAS                     5.8
    nDTACK_FSB               5.8
    nDinLE       5.8
    nDoutOE     13.5        13.5
    nLDS_IOB     5.8        14.5
    nOE                      5.8
    nRAMLWE                 13.5
    nRAMUWE                 14.5
    nRAS                    14.5
    nRES                    14.5
    nROMCS                  13.5
    nUDS_IOB     5.8        14.5
    nVMA_IOB           5.8  14.5
    nVPA_FSB                 5.8

    --------------------------------------------------------------------------------
                       Setup to Clock at Pad (tSU or tSUF) (nsec)

    \ From         C     C     F
     \             1     8     C
      \            6     M     L
       \           M           K
        \
         \
          \
           \
            \
             \
      To      \------------------

    A_FSB<10>               16.6
    A_FSB<11>               16.6
    A_FSB<12>               16.6
    A_FSB<13>               16.6
    A_FSB<14>               16.6
    A_FSB<15>               16.6
    A_FSB<16>               16.6
    A_FSB<17>               16.6
    A_FSB<18>               16.6
    A_FSB<19>               16.6
    A_FSB<20>               16.6
    A_FSB<21>               16.6
    A_FSB<22>               16.6
    A_FSB<23>               16.6
    A_FSB<8>                16.6
    A_FSB<9>                16.6
    C8M          6.5
    E                  6.5   6.5
    nAS_FSB                 16.6
    nBERR_IOB          6.5
    nDTACK_IOB         6.5
    nIPL2                    6.5
    nLDS_FSB                 6.5
    nRES               6.5   6.5
    nUDS_FSB                 6.5
    nVPA_IOB           6.5
    nWE_FSB                 16.6

    --------------------------------------------------------------------------------
                              Clock to Setup (tCYC) (nsec)
                                     (Clock: FCLK)

    \ From                 I     I     I     I     I     Q     R     R     R     c
     \                     O     O     O     O     O     o     A     e     e     n
      \                    L     N     R     U     W     S     M     f     f     t
       \                   0     P     D     0     R     R     R     R     U     /
        \                  .     R     R     .     R     e     e     e     r     E
         \                 Q     e     E     Q     E     a     a     q     g     r
          \                      a     Q           Q     d     d     .     .     <
           \                     d     .           .     y     y     Q     Q     0
            \                    y     Q           Q     .     .                 >
             \                   .                       Q     Q                 .
              \                  Q                                               Q
               \
                \
                 \
                  \
                   \
                    \
                     \
      To              \------------------------------------------------------------

    ALE0S.D
    IOL0.D              11.0
    IONPReady.D               11.0
    IORDREQ.D                       10.0
    IOU0.D                                11.0
    IOWRREQ.D                                   10.0
    QoSReady.D                                        10.0
    RAMReady.D                                                    11.0  11.0
    RefReq.CE                                                                 10.0
    RefReq.D
    RefUrg.CE                                                                 10.0
    RefUrg.D
    cnt/Er<1>.D                                                               10.0
    cnt/IS_FSM_FFd1.D                                                         10.0
    cnt/IS_FSM_FFd2.D                                                         10.0
    cnt/LTimer<0>.D                                                           19.1
    cnt/LTimer<10>.D                                                          10.0
    cnt/LTimer<11>.D                                                          10.0
    cnt/LTimer<1>.D                                                           19.1
    cnt/LTimer<2>.D                                                           10.0
    cnt/LTimer<3>.D                                                           10.0
    cnt/LTimer<4>.D                                                           10.0
    cnt/LTimer<5>.D                                                           10.0
    cnt/LTimer<6>.D                                                           10.0
    cnt/LTimer<7>.D                                                           10.0
    cnt/LTimer<8>.D                                                           10.0
    cnt/LTimer<9>.D                                                           11.0
    cnt/LTimerTC.D
    cnt/Timer<0>.CE                                                           10.0
    cnt/Timer<0>.D                                                            10.0
    cnt/Timer<1>.CE                                                           10.0
    cnt/Timer<1>.D                                                            10.0
    cnt/Timer<2>.CE                                                           10.0
    cnt/Timer<2>.D                                                            10.0
    cnt/Timer<3>.CE                                                           10.0
    cnt/Timer<3>.D                                                            10.0
    cnt/TimerTC.CE                                                            10.0
    cnt/TimerTC.D
    cnt/WS<0>.D
    cnt/WS<1>.D
    cnt/WS<2>.D
    cnt/WS<3>.D
    cs/nOverlay.D
    iobs/Clear1.D
    iobs/IOL1.CE
    iobs/IORW1.D
    iobs/IOU1.CE
    iobs/Load1.D
    iobs/Sent.D
    iobs/TS_FSM_FFd1.D
    iobs/TS_FSM_FFd2.D
    nADoutLE1.D
    nAoutOE.D
    nBERR_FSB.D
    nBR_IOB.D
    nCAS.D                                                        11.0  11.0
    nDTACK_FSB.D              11.0                    10.0  11.0
    nOE.D
    nRESout.D
    nVPA_FSB.D                10.0
    ram/BACTr.D
    ram/DTACKr.D
    ram/RASEL.D
    ram/RASEN.D                                                   11.0  11.0
    ram/RASrf.D
    ram/RASrr.D                                                         10.0
    ram/RS_FSM_FFd1.D
    ram/RS_FSM_FFd2.D
    ram/RS_FSM_FFd3.D
    ram/RS_FSM_FFd4.D
    ram/RS_FSM_FFd5.D
    ram/RS_FSM_FFd6.D
    ram/RS_FSM_FFd7.D                                             11.0  10.0
    ram/RS_FSM_FFd8.D                                             11.0  11.0
    ram/RefDone.D                                                 10.0  10.0

    --------------------------------------------------------------------------------
                              Clock to Setup (tCYC) (nsec)
                                     (Clock: FCLK)

    \ From                 c     c     c     c     c     c     c     c     c     c
     \                     n     n     n     n     n     n     n     n     n     n
      \                    t     t     t     t     t     t     t     t     t     t
       \                   /     /     /     /     /     /     /     /     /     /
        \                  E     I     I     L     L     L     L     L     L     L
         \                 r     S     S     T     T     T     T     T     T     T
          \                <     _     _     i     i     i     i     i     i     i
           \               1     F     F     m     m     m     m     m     m     m
            \              >     S     S     e     e     e     e     e     e     e
             \             .     M     M     r     r     r     r     r     r     r
              \            Q     _     _     <     <     <     <     <     <     <
               \                 F     F     0     1     1     1     2     3     4
                \                F     F     >     0     1     >     >     >     >
                 \               d     d     .     >     >     .     .     .     .
                  \              1     2     Q     .     .     Q     Q     Q     Q
                   \             .     .           Q     Q
                    \            Q     Q
                     \
      To              \------------------------------------------------------------

    ALE0S.D
    IOL0.D
    IONPReady.D
    IORDREQ.D
    IOU0.D
    IOWRREQ.D
    QoSReady.D                            10.0              10.0
    RAMReady.D
    RefReq.CE           10.0
    RefReq.D
    RefUrg.CE           10.0
    RefUrg.D
    cnt/Er<1>.D
    cnt/IS_FSM_FFd1.D   10.0  10.0  10.0
    cnt/IS_FSM_FFd2.D   10.0  10.0  10.0
    cnt/LTimer<0>.D     19.1  20.1  20.1  19.1  19.1  19.1  19.1  19.1  19.1  19.1
    cnt/LTimer<10>.D    10.0  10.0  10.0  10.0  10.0        10.0  10.0  10.0  10.0
    cnt/LTimer<11>.D    10.0  10.0  10.0  10.0  10.0  10.0  10.0  10.0  10.0  10.0
    cnt/LTimer<1>.D     19.1  20.1  20.1  19.1  19.1  19.1  19.1  19.1  19.1  19.1
    cnt/LTimer<2>.D     10.0  10.0  10.0  10.0              10.0  10.0
    cnt/LTimer<3>.D     10.0  10.0  10.0  10.0              10.0  10.0  10.0
    cnt/LTimer<4>.D     10.0  10.0  10.0  10.0              10.0  10.0  10.0  10.0
    cnt/LTimer<5>.D     10.0  10.0  10.0  10.0              10.0  10.0  10.0  10.0
    cnt/LTimer<6>.D     10.0  10.0  10.0  10.0              10.0  10.0  10.0  10.0
    cnt/LTimer<7>.D     10.0  10.0  10.0  10.0              10.0  10.0  10.0  10.0
    cnt/LTimer<8>.D     10.0  10.0  10.0  10.0              10.0  10.0  10.0  10.0
    cnt/LTimer<9>.D     11.0  10.0  11.0  11.0              11.0  11.0  11.0  11.0
    cnt/LTimerTC.D                        10.0  10.0  10.0  10.0  10.0  10.0  10.0
    cnt/Timer<0>.CE     10.0
    cnt/Timer<0>.D      10.0
    cnt/Timer<1>.CE     10.0
    cnt/Timer<1>.D      10.0
    cnt/Timer<2>.CE     10.0
    cnt/Timer<2>.D      10.0
    cnt/Timer<3>.CE     10.0
    cnt/Timer<3>.D      10.0
    cnt/TimerTC.CE      10.0
    cnt/TimerTC.D
    cnt/WS<0>.D
    cnt/WS<1>.D
    cnt/WS<2>.D
    cnt/WS<3>.D
    cs/nOverlay.D
    iobs/Clear1.D
    iobs/IOL1.CE
    iobs/IORW1.D
    iobs/IOU1.CE
    iobs/Load1.D
    iobs/Sent.D
    iobs/TS_FSM_FFd1.D
    iobs/TS_FSM_FFd2.D
    nADoutLE1.D
    nAoutOE.D                 11.0  11.0
    nBERR_FSB.D
    nBR_IOB.D                 10.0  10.0
    nCAS.D
    nDTACK_FSB.D
    nOE.D
    nRESout.D                 10.0  10.0
    nVPA_FSB.D
    ram/BACTr.D
    ram/DTACKr.D
    ram/RASEL.D
    ram/RASEN.D
    ram/RASrf.D
    ram/RASrr.D
    ram/RS_FSM_FFd1.D
    ram/RS_FSM_FFd2.D
    ram/RS_FSM_FFd3.D
    ram/RS_FSM_FFd4.D
    ram/RS_FSM_FFd5.D
    ram/RS_FSM_FFd6.D
    ram/RS_FSM_FFd7.D
    ram/RS_FSM_FFd8.D
    ram/RefDone.D

    --------------------------------------------------------------------------------
                              Clock to Setup (tCYC) (nsec)
                                     (Clock: FCLK)

    \ From                 c     c     c     c     c     c     c     c     c     c
     \                     n     n     n     n     n     n     n     n     n     n
      \                    t     t     t     t     t     t     t     t     t     t
       \                   /     /     /     /     /     /     /     /     /     /
        \                  L     L     L     L     L     L     T     T     T     T
         \                 T     T     T     T     T     T     i     i     i     i
          \                i     i     i     i     i     i     m     m     m     m
           \               m     m     m     m     m     m     e     e     e     e
            \              e     e     e     e     e     e     r     r     r     r
             \             r     r     r     r     r     r     <     <     <     <
              \            <     <     <     <     <     T     0     1     2     3
               \           5     6     7     8     9     C     >     >     >     >
                \          >     >     >     >     >     .     .     .     .     .
                 \         .     .     .     .     .     Q     Q     Q     Q     Q
                  \        Q     Q     Q     Q     Q
                   \
                    \
                     \
      To              \------------------------------------------------------------

    ALE0S.D
    IOL0.D
    IONPReady.D
    IORDREQ.D
    IOU0.D
    IOWRREQ.D
    QoSReady.D
    RAMReady.D
    RefReq.CE
    RefReq.D                                                10.0  10.0  10.0  10.0
    RefUrg.CE
    RefUrg.D                                                      10.0  10.0  10.0
    cnt/Er<1>.D
    cnt/IS_FSM_FFd1.D                                 10.0
    cnt/IS_FSM_FFd2.D                                 10.0
    cnt/LTimer<0>.D     19.1  19.1  19.1  19.1  19.1
    cnt/LTimer<10>.D    10.0  10.0  10.0  10.0  10.0
    cnt/LTimer<11>.D    10.0  10.0  10.0  10.0  10.0
    cnt/LTimer<1>.D     19.1  19.1  19.1  19.1  19.1
    cnt/LTimer<2>.D
    cnt/LTimer<3>.D
    cnt/LTimer<4>.D
    cnt/LTimer<5>.D     10.0
    cnt/LTimer<6>.D     10.0  10.0
    cnt/LTimer<7>.D     10.0  10.0  10.0
    cnt/LTimer<8>.D     10.0  10.0  10.0  10.0
    cnt/LTimer<9>.D     11.0  11.0  11.0  11.0  10.0
    cnt/LTimerTC.D      10.0  10.0  10.0  10.0  10.0
    cnt/Timer<0>.CE
    cnt/Timer<0>.D                                          10.0
    cnt/Timer<1>.CE
    cnt/Timer<1>.D                                          10.0  10.0
    cnt/Timer<2>.CE
    cnt/Timer<2>.D                                          10.0  10.0  10.0
    cnt/Timer<3>.CE
    cnt/Timer<3>.D                                          10.0  10.0  10.0  10.0
    cnt/TimerTC.CE
    cnt/TimerTC.D                                           10.0  10.0  10.0  10.0
    cnt/WS<0>.D
    cnt/WS<1>.D
    cnt/WS<2>.D
    cnt/WS<3>.D
    cs/nOverlay.D
    iobs/Clear1.D
    iobs/IOL1.CE
    iobs/IORW1.D
    iobs/IOU1.CE
    iobs/Load1.D
    iobs/Sent.D
    iobs/TS_FSM_FFd1.D
    iobs/TS_FSM_FFd2.D
    nADoutLE1.D
    nAoutOE.D
    nBERR_FSB.D
    nBR_IOB.D
    nCAS.D
    nDTACK_FSB.D
    nOE.D
    nRESout.D
    nVPA_FSB.D
    ram/BACTr.D
    ram/DTACKr.D
    ram/RASEL.D
    ram/RASEN.D
    ram/RASrf.D
    ram/RASrr.D
    ram/RS_FSM_FFd1.D
    ram/RS_FSM_FFd2.D
    ram/RS_FSM_FFd3.D
    ram/RS_FSM_FFd4.D
    ram/RS_FSM_FFd5.D
    ram/RS_FSM_FFd6.D
    ram/RS_FSM_FFd7.D
    ram/RS_FSM_FFd8.D
    ram/RefDone.D

    --------------------------------------------------------------------------------
                              Clock to Setup (tCYC) (nsec)
                                     (Clock: FCLK)

    \ From                 c     c     c     c     c     c     c     f     i     i
     \                     n     n     n     n     n     n     s     s     o     o
      \                    t     t     t     t     t     t     /     b     b     b
       \                   /     /     /     /     /     /     n     /     s     s
        \                  T     W     W     W     W     n     O     A     /     /
         \                 i     S     S     S     S     I     v     S     C     I
          \                m     <     <     <     <     P     e     r     l     O
           \               e     0     1     2     3     L     r     f     e     A
            \              r     >     >     >     >     2     l     .     a     C
             \             T     .     .     .     .     r     a     Q     r     T
              \            C     Q     Q     Q     Q     .     y           1     r
               \           .                             Q     .           .     .
                \          Q                                   Q           Q     Q
                 \
                  \
                   \
                    \
                     \
      To              \------------------------------------------------------------

    ALE0S.D
    IOL0.D                                                  11.0  11.0
    IONPReady.D                                                   11.0
    IORDREQ.D                                               11.0  11.0        10.0
    IOU0.D                                                  11.4  11.0
    IOWRREQ.D                                               11.0  11.0        10.0
    QoSReady.D                11.4  11.4  11.4  11.4              19.1
    RAMReady.D                                                    11.0
    RefReq.CE
    RefReq.D
    RefUrg.CE
    RefUrg.D
    cnt/Er<1>.D
    cnt/IS_FSM_FFd1.D   10.0                          10.0
    cnt/IS_FSM_FFd2.D   10.0
    cnt/LTimer<0>.D     19.1                                      20.1
    cnt/LTimer<10>.D    10.0
    cnt/LTimer<11>.D    10.0
    cnt/LTimer<1>.D     19.1                                      20.1
    cnt/LTimer<2>.D     10.0
    cnt/LTimer<3>.D     10.0
    cnt/LTimer<4>.D     10.0
    cnt/LTimer<5>.D     10.0
    cnt/LTimer<6>.D     10.0
    cnt/LTimer<7>.D     10.0
    cnt/LTimer<8>.D     10.0
    cnt/LTimer<9>.D     11.0
    cnt/LTimerTC.D
    cnt/Timer<0>.CE
    cnt/Timer<0>.D      10.0
    cnt/Timer<1>.CE
    cnt/Timer<1>.D      10.0
    cnt/Timer<2>.CE
    cnt/Timer<2>.D      10.0
    cnt/Timer<3>.CE
    cnt/Timer<3>.D      10.0
    cnt/TimerTC.CE
    cnt/TimerTC.D
    cnt/WS<0>.D               10.0                                10.0
    cnt/WS<1>.D               10.0  10.0                          11.0
    cnt/WS<2>.D               10.0  10.0  10.0                    10.0
    cnt/WS<3>.D               10.0  10.0  10.0  10.0              10.0
    cs/nOverlay.D                                           10.0  10.0
    iobs/Clear1.D
    iobs/IOL1.CE
    iobs/IORW1.D                                                  11.0
    iobs/IOU1.CE
    iobs/Load1.D                                                  11.0
    iobs/Sent.D                                             11.4  11.4
    iobs/TS_FSM_FFd1.D                                                        10.0
    iobs/TS_FSM_FFd2.D                                      11.0  10.0        10.0
    nADoutLE1.D                                                         10.0
    nAoutOE.D
    nBERR_FSB.D                                                   10.0
    nBR_IOB.D                                         10.0
    nCAS.D                                                        11.0
    nDTACK_FSB.D                                                  10.0
    nOE.D                                                         11.0
    nRESout.D
    nVPA_FSB.D                                                    10.0
    ram/BACTr.D                                                   10.0
    ram/DTACKr.D
    ram/RASEL.D                                             10.0  10.0
    ram/RASEN.D                                                   11.0
    ram/RASrf.D
    ram/RASrr.D                                             10.0  10.0
    ram/RS_FSM_FFd1.D
    ram/RS_FSM_FFd2.D
    ram/RS_FSM_FFd3.D
    ram/RS_FSM_FFd4.D
    ram/RS_FSM_FFd5.D
    ram/RS_FSM_FFd6.D                                       10.0  10.0
    ram/RS_FSM_FFd7.D                                             11.0
    ram/RS_FSM_FFd8.D                                       11.0  11.0
    ram/RefDone.D

    --------------------------------------------------------------------------------
                              Clock to Setup (tCYC) (nsec)
                                     (Clock: FCLK)

    \ From                 i     i     i     i     i     i     i     i     n     n
     \                     o     o     o     o     o     o     o     o     A     A
      \                    b     b     b     b     b     b     b     b     D     o
       \                   s     s     s     s     s     s     s     s     o     u
        \                  /     /     /     /     /     /     /     /     u     t
         \                 I     I     I     I     L     S     T     T     t     O
          \                O     O     O     O     o     e     S     S     L     E
           \               D     L     R     U     a     n     _     _     E     .
            \              O     1     W     1     d     t     F     F     1     Q
             \             N     .     1     .     1     .     S     S     .
              \            E     Q     .     Q     .     Q     M     M     Q
               \           r           Q           Q           _     _
                \          .                                   F     F
                 \         Q                                   F     F
                  \                                            d     d
                   \                                           1     2
                    \                                          .     .
                     \                                         Q     Q
      To              \------------------------------------------------------------

    ALE0S.D                                                       10.0
    IOL0.D                    11.0                    10.0  10.0  11.4  11.4
    IONPReady.D         11.0                          11.0
    IORDREQ.D                       11.0              10.0  10.0  11.0  11.0
    IOU0.D                                11.0        10.0  10.0  11.4  11.4
    IOWRREQ.D                       10.0              11.0  11.0  11.0  11.0
    QoSReady.D
    RAMReady.D
    RefReq.CE
    RefReq.D
    RefUrg.CE
    RefUrg.D
    cnt/Er<1>.D
    cnt/IS_FSM_FFd1.D
    cnt/IS_FSM_FFd2.D
    cnt/LTimer<0>.D
    cnt/LTimer<10>.D
    cnt/LTimer<11>.D
    cnt/LTimer<1>.D
    cnt/LTimer<2>.D
    cnt/LTimer<3>.D
    cnt/LTimer<4>.D
    cnt/LTimer<5>.D
    cnt/LTimer<6>.D
    cnt/LTimer<7>.D
    cnt/LTimer<8>.D
    cnt/LTimer<9>.D
    cnt/LTimerTC.D
    cnt/Timer<0>.CE
    cnt/Timer<0>.D
    cnt/Timer<1>.CE
    cnt/Timer<1>.D
    cnt/Timer<2>.CE
    cnt/Timer<2>.D
    cnt/Timer<3>.CE
    cnt/Timer<3>.D
    cnt/TimerTC.CE
    cnt/TimerTC.D
    cnt/WS<0>.D
    cnt/WS<1>.D
    cnt/WS<2>.D
    cnt/WS<3>.D
    cs/nOverlay.D
    iobs/Clear1.D                                           10.0  10.0
    iobs/IOL1.CE                                10.0
    iobs/IORW1.D                    11.0              11.0  11.0  11.0  11.0
    iobs/IOU1.CE                                10.0
    iobs/Load1.D                                      11.0  11.0  11.0  11.0
    iobs/Sent.D                                       11.4  11.4  11.4  11.4
    iobs/TS_FSM_FFd1.D                                      10.0  10.0
    iobs/TS_FSM_FFd2.D                                10.0  10.0  11.0  11.0
    nADoutLE1.D                                 10.0                    10.0
    nAoutOE.D                                                                 11.0
    nBERR_FSB.D                                       10.0
    nBR_IOB.D
    nCAS.D
    nDTACK_FSB.D                                                        11.0
    nOE.D
    nRESout.D
    nVPA_FSB.D
    ram/BACTr.D
    ram/DTACKr.D
    ram/RASEL.D
    ram/RASEN.D
    ram/RASrf.D
    ram/RASrr.D
    ram/RS_FSM_FFd1.D
    ram/RS_FSM_FFd2.D
    ram/RS_FSM_FFd3.D
    ram/RS_FSM_FFd4.D
    ram/RS_FSM_FFd5.D
    ram/RS_FSM_FFd6.D
    ram/RS_FSM_FFd7.D
    ram/RS_FSM_FFd8.D
    ram/RefDone.D

    --------------------------------------------------------------------------------
                              Clock to Setup (tCYC) (nsec)
                                     (Clock: FCLK)

    \ From                 n     n     n     r     r     r     r     r     r     r
     \                     B     B     D     a     a     a     a     a     a     a
      \                    E     R     T     m     m     m     m     m     m     m
       \                   R     _     A     /     /     /     /     /     /     /
        \                  R     I     C     B     D     R     R     R     R     R
         \                 _     O     K     A     T     A     A     S     S     S
          \                F     B     _     C     A     S     S     _     _     _
           \               S     .     F     T     C     E     r     F     F     F
            \              B     Q     S     r     K     N     r     S     S     S
             \             .           B     .     r     .     .     M     M     M
              \            Q           .     Q     .     Q     Q     _     _     _
               \                       Q           Q                 F     F     F
                \                                                    F     F     F
                 \                                                   d     d     d
                  \                                                  1     2     3
                   \                                                 .     .     .
                    \                                                Q     Q     Q
                     \
      To              \------------------------------------------------------------

    ALE0S.D
    IOL0.D
    IONPReady.D
    IORDREQ.D
    IOU0.D
    IOWRREQ.D
    QoSReady.D
    RAMReady.D                            11.0        10.0        11.0
    RefReq.CE
    RefReq.D
    RefUrg.CE
    RefUrg.D
    cnt/Er<1>.D
    cnt/IS_FSM_FFd1.D
    cnt/IS_FSM_FFd2.D
    cnt/LTimer<0>.D
    cnt/LTimer<10>.D
    cnt/LTimer<11>.D
    cnt/LTimer<1>.D
    cnt/LTimer<2>.D
    cnt/LTimer<3>.D
    cnt/LTimer<4>.D
    cnt/LTimer<5>.D
    cnt/LTimer<6>.D
    cnt/LTimer<7>.D
    cnt/LTimer<8>.D
    cnt/LTimer<9>.D
    cnt/LTimerTC.D
    cnt/Timer<0>.CE
    cnt/Timer<0>.D
    cnt/Timer<1>.CE
    cnt/Timer<1>.D
    cnt/Timer<2>.CE
    cnt/Timer<2>.D
    cnt/Timer<3>.CE
    cnt/Timer<3>.D
    cnt/TimerTC.CE
    cnt/TimerTC.D
    cnt/WS<0>.D
    cnt/WS<1>.D
    cnt/WS<2>.D
    cnt/WS<3>.D
    cs/nOverlay.D
    iobs/Clear1.D
    iobs/IOL1.CE
    iobs/IORW1.D
    iobs/IOU1.CE
    iobs/Load1.D
    iobs/Sent.D
    iobs/TS_FSM_FFd1.D
    iobs/TS_FSM_FFd2.D
    nADoutLE1.D
    nAoutOE.D                 11.0
    nBERR_FSB.D         11.0
    nBR_IOB.D                 10.0
    nCAS.D                                11.0  10.0  11.0        10.0  10.0  10.0
    nDTACK_FSB.D
    nOE.D                                 11.0  11.0
    nRESout.D
    nVPA_FSB.D
    ram/BACTr.D
    ram/DTACKr.D                    10.0
    ram/RASEL.D                                 10.0  10.0
    ram/RASEN.D                           11.0        10.0        11.0
    ram/RASrf.D
    ram/RASrr.D                                       10.0                    10.0
    ram/RS_FSM_FFd1.D                                       10.0        10.0
    ram/RS_FSM_FFd2.D                                       10.0        10.0  10.0
    ram/RS_FSM_FFd3.D
    ram/RS_FSM_FFd4.D                           10.0
    ram/RS_FSM_FFd5.D                           10.0
    ram/RS_FSM_FFd6.D                                 10.0
    ram/RS_FSM_FFd7.D                     11.0        10.0
    ram/RS_FSM_FFd8.D                     11.0        11.0        11.0
    ram/RefDone.D                                                 10.0  10.0  10.0

    --------------------------------------------------------------------------------
                              Clock to Setup (tCYC) (nsec)
                                     (Clock: FCLK)

    \ From                 r     r     r     r     r     r
     \                     a     a     a     a     a     a
      \                    m     m     m     m     m     m
       \                   /     /     /     /     /     /
        \                  R     R     R     R     R     R
         \                 S     S     S     S     S     e
          \                _     _     _     _     _     f
           \               F     F     F     F     F     D
            \              S     S     S     S     S     o
             \             M     M     M     M     M     n
              \            _     _     _     _     _     e
               \           F     F     F     F     F     .
                \          F     F     F     F     F     Q
                 \         d     d     d     d     d
                  \        4     5     6     7     8
                   \       .     .     .     .     .
                    \      Q     Q     Q     Q     Q
                     \
      To              \------------------------------------

    ALE0S.D
    IOL0.D
    IONPReady.D
    IORDREQ.D
    IOU0.D
    IOWRREQ.D
    QoSReady.D
    RAMReady.D          11.0  11.0  11.0        10.0  11.0
    RefReq.CE
    RefReq.D
    RefUrg.CE
    RefUrg.D
    cnt/Er<1>.D
    cnt/IS_FSM_FFd1.D
    cnt/IS_FSM_FFd2.D
    cnt/LTimer<0>.D
    cnt/LTimer<10>.D
    cnt/LTimer<11>.D
    cnt/LTimer<1>.D
    cnt/LTimer<2>.D
    cnt/LTimer<3>.D
    cnt/LTimer<4>.D
    cnt/LTimer<5>.D
    cnt/LTimer<6>.D
    cnt/LTimer<7>.D
    cnt/LTimer<8>.D
    cnt/LTimer<9>.D
    cnt/LTimerTC.D
    cnt/Timer<0>.CE
    cnt/Timer<0>.D
    cnt/Timer<1>.CE
    cnt/Timer<1>.D
    cnt/Timer<2>.CE
    cnt/Timer<2>.D
    cnt/Timer<3>.CE
    cnt/Timer<3>.D
    cnt/TimerTC.CE
    cnt/TimerTC.D
    cnt/WS<0>.D
    cnt/WS<1>.D
    cnt/WS<2>.D
    cnt/WS<3>.D
    cs/nOverlay.D
    iobs/Clear1.D
    iobs/IOL1.CE
    iobs/IORW1.D
    iobs/IOU1.CE
    iobs/Load1.D
    iobs/Sent.D
    iobs/TS_FSM_FFd1.D
    iobs/TS_FSM_FFd2.D
    nADoutLE1.D
    nAoutOE.D
    nBERR_FSB.D
    nBR_IOB.D
    nCAS.D              11.0  10.0        11.0  11.0  11.0
    nDTACK_FSB.D
    nOE.D
    nRESout.D
    nVPA_FSB.D
    ram/BACTr.D
    ram/DTACKr.D
    ram/RASEL.D               10.0  10.0        10.0
    ram/RASEN.D         11.0                    10.0  11.0
    ram/RASrf.D                     10.0
    ram/RASrr.D         10.0              10.0  10.0  10.0
    ram/RS_FSM_FFd1.D
    ram/RS_FSM_FFd2.D
    ram/RS_FSM_FFd3.D                     10.0
    ram/RS_FSM_FFd4.D         10.0
    ram/RS_FSM_FFd5.D         10.0  10.0
    ram/RS_FSM_FFd6.D                           10.0
    ram/RS_FSM_FFd7.D   10.0                    11.0  11.0
    ram/RS_FSM_FFd8.D   11.0                    11.0  11.0
    ram/RefDone.D                         10.0        10.0

    --------------------------------------------------------------------------------
                              Clock to Setup (tCYC) (nsec)
                                     (Clock: C16M)

    \ From                  A     I     i     i     i     i     i     i     i     i
     \                      L     O     o     o     o     o     o     o     o     o
      \                     E     A     b     b     b     b     b     b     b     b
       \                    0     C     m     m     m     m     m     m     m     m
        \                   M     T     /     /     /     /     /     /     /     /
         \                  .     .     C     D     I     I     I     I     I     I
          \                 Q     Q     8     o     O     O     O     O     O     O
           \                            M     u     R     S     S     S     S     S
            \                           r     t     D     0     _     _     _     _
             \                          .     O     R     .     F     F     F     F
              \                         Q     E     E     Q     S     S     S     S
               \                              .     Q           M     M     M     M
                \                             Q     r           _     _     _     _
                 \                                  .           F     F     F     F
                  \                                 Q           F     F     F     F
                   \                                            d     d     d     d
                    \                                           1     2     3     4
                     \                                          .     .     .     .
                      \                                         Q     Q     Q     Q
      To               \------------------------------------------------------------

    ALE0M.D              10.0                    10.0        10.0  10.0  10.0  10.0
    IOACT.D                    11.0  10.0        10.0        11.0  11.0  11.0  10.0
    iobm/DoutOE.D                    10.0  10.0                          10.0  10.0
    iobm/IOS0.D                      10.0        10.0  10.0  10.0  10.0  10.0  10.0
    iobm/IOS_FSM_FFd1.D                                            10.0
    iobm/IOS_FSM_FFd2.D              10.0                                10.0
    iobm/IOS_FSM_FFd3.D              10.0                                10.0  10.0
    iobm/IOS_FSM_FFd4.D
    iobm/IOS_FSM_FFd5.D
    iobm/IOS_FSM_FFd6.D              10.0        10.0
    iobm/IOS_FSM_FFd7.D              10.0        10.0        10.0
    nAS_IOB.D                        10.0        10.0                    10.0  10.0
    nDinLE.D                                                             10.0  10.0
    nLDS_IOB.D                       11.0        11.0                    10.0  10.0
    nUDS_IOB.D                       11.0        11.0                    10.0  10.0

    --------------------------------------------------------------------------------
                              Clock to Setup (tCYC) (nsec)
                                     (Clock: C16M)

    \ From                  i     i     i     i     n     n
     \                      o     o     o     o     L     U
      \                     b     b     b     b     D     D
       \                    m     m     m     m     S     S
        \                   /     /     /     /     _     _
         \                  I     I     I     I     I     I
          \                 O     O     O     O     O     O
           \                S     S     S     W     B     B
            \               _     _     _     R     .     .
             \              F     F     F     R     Q     Q
              \             S     S     S     E
               \            M     M     M     Q
                \           _     _     _     r
                 \          F     F     F     .
                  \         F     F     F     Q
                   \        d     d     d
                    \       5     6     7
                     \      .     .     .
                      \     Q     Q     Q
      To               \------------------------------------

    ALE0M.D              10.0  10.0  10.0  10.0
    IOACT.D              10.0  10.0  11.0  11.0
    iobm/DoutOE.D        10.0  10.0  10.0  10.0
    iobm/IOS0.D          10.0  10.0  10.0  10.0
    iobm/IOS_FSM_FFd1.D
    iobm/IOS_FSM_FFd2.D
    iobm/IOS_FSM_FFd3.D
    iobm/IOS_FSM_FFd4.D  10.0
    iobm/IOS_FSM_FFd5.D        10.0
    iobm/IOS_FSM_FFd6.D              10.0  10.0
    iobm/IOS_FSM_FFd7.D              10.0  10.0
    nAS_IOB.D            10.0  10.0  10.0  10.0
    nDinLE.D
    nLDS_IOB.D           10.0  10.0  11.0        10.0
    nUDS_IOB.D           10.0  10.0  11.0              10.0

    --------------------------------------------------------------------------------
                              Clock to Setup (tCYC) (nsec)
                                      (Clock: C8M)

    \ From           i     i     i     i     i     i     n
     \               o     o     o     o     o     o     V
      \              b     b     b     b     b     b     M
       \             m     m     m     m     m     m     A
        \            /     /     /     /     /     /     _
         \           E     E     E     E     E     V     I
          \          S     S     S     S     r     P     O
           \         <     <     <     <     .     A     B
            \        0     1     2     3     Q     r     .
             \       >     >     >     >           .     Q
              \      .     .     .     .           Q
               \     Q     Q     Q     Q
      To        \------------------------------------------

    IODONE.D      10.0  10.0  10.0  10.0              10.0
    iobm/ES<0>.D  10.0  10.0  10.0  10.0  10.0
    iobm/ES<1>.D  10.0  10.0  10.0  10.0  10.0
    iobm/ES<2>.D  10.0  10.0  10.0        10.0
    iobm/ES<3>.D  10.0  10.0  10.0  10.0  10.0
    nVMA_IOB.D    10.0  10.0  10.0  10.0        10.0  10.0

    Path Type Definition:

    Pad to Pad (tPD) -                        Reports pad to pad paths that start
                                              at input pads and end at output pads.
                                              Paths are not traced through
                                              registers.

    Clock Pad to Output Pad (tCO) -           Reports paths that start at input
                                              pads trace through clock inputs of
                                              registers and end at output pads.
                                              Paths are not traced through PRE/CLR
                                              inputs of registers.

    Setup to Clock at Pad (tSU or tSUF) -     Reports external setup time of data
                                              to clock at pad. Data path starts at
                                              an input pad and ends at register
                                              (Fast Input Register for tSUF) D/T
                                              input. Clock path starts at input pad
                                              and ends at the register clock input.
                                              Paths are not traced through
                                              registers. Pin-to-pin setup
                                              requirement is not reported or
                                              guaranteed for product-term clocks
                                              derived from macrocell feedback
                                              signals.

    Clock to Setup (tCYC) -                   Register to register cycle time.
                                              Include source register tCO and
                                              destination register tSU. Note that
                                              when the computed Maximum Clock Speed
                                              is limited by tCYC it is computed
                                              assuming that all registers are
                                              rising-edge sensitive.