# Compiler Options

The Compiler Options page provides all the fitter options settings for the device family the fitter has selected.

# Fitter Options

Basic Tab

XPLA3 Advanced Options

CoolRunner-II Advanced Options

XC9500/XL/XV Advanced Options

## Basic Tab

The CPLD devices have the following fitter Implementation Options available in the Basic tab:

- #### Use Multi-Level Logic Optimization

This option simplifies the total number of logic expressions in a design, and then collapses the logic in order to meet user objectives such as density, speed and timing constraints. This optimization targets CPLD architecture, making it possible to collapse to the macrocell limits, reduce levels of logic, and minimize the total number of p-terms.

Multi-level Logic Optimization optimizes all combinatorial logic arcs spanning from an input pad or register output to an output pad or register input.

Multi-level Logic Optimization operates on combinatorial logic according to the following rules.

If timing constraints are set, the program optimizes for speed to meet timing constraints.

If timing constraints are not set, the program optimizes either for speed or density, depending on the user setting for the Use Timing Optimization option.

- If Use Timing Optimization is turned on, the combinatorial logic will be mapped for speed.

- If Use Timing Optimization is turned off, the combinatorial logic will be mapped for density. The goal of optimization will then be to reduce the total number of p-terms.

Logic marked with the NOREDUCE property will not be extracted or optimized.

By default, this option is on.

- Use Timing Constraints -- This option instructs the fitter use Timing Constraints when fitting the design. If this box is not checked, the fitter will ignore timing constraints, if necessary.

- Enable WYSIWYG Mode -- (CoolRunner only) The goal of the WYSIWYG options is to have a netlist reflect the user's specifications, as much as possible. All the nodes declared in the HDL design are preserved. By default, this property is set to Off (Checkbox is not checked) When this property is On (checkbox is checked), XST:

- Preserves all the user internal signals (nodes)

- Creates source_node constraints in NGC file for all these nodes.

- Skips the design optimization (collapse, factorization). Only the Boolean equation minimization is performed.

- Optimization Style-- The Optimization Method allows you to select from one of two basic optimization strategies: Density or Speed. Density focuses on solely on density, and Speed focuses solely on speed.

- Location Constraints -- The Try selection will attempt to fit the design with the pin assignments specified in the design source. If the design cannot be fit with these pin assignments, the fitter will remove the location constraints and attempt to fit the design with no location constraints. A warning message will tell the user if the location constraints have been removed.

- The Try selection will attempt to fit the design with the pin assignments specified in the design source. If the design cannot be fit with these pin assignments, the fitter will ignore the pin assignments.

- The On selection will attempt to fit the design with the pin assignments specified in the design source. If the design cannot be fit with these pin assignments, the fitter will notify the user that the device could not fit. It will not unlock the pins under this option.

- The Off selection will attempt to fit the design and will ignore the pin assignments specified in the design source. If the design can be fit with no pre-assigned pins, the fitter will assign pins, which can be viewed in the fitter report (filename.fit). The user should take these pin assignments and incorporate them back into the design source file. The user will be notified whether the fitting operation was successful.

- Output Slew Rate -- Use this option to control the default output slew rate. You can control the transition time of device output pins by setting the slew rate to Slow or Fast. Limiting the slew rate (Slow) reduces output switching surges in the device. The default is Fast.

Note: Any explicit slew rate control properties in the design or constraints file take precedence over this Output Slew Rate setting.

- FF Initial State -- Sets the initial state for all Flip-Flops. The options are Low, High and FPGA.

- Collapsing P-Term Limit -- This option controls the degree to which the fitter flattens a design netlist. A logic gate can collapse forward into a subsequent gate only if the number of product terms in the resulting logic function does not exceed the p-term limit. If the path delay of a logic function is not acceptable, increase the p-term limit to allow the larger functions to be further flattened. Choose a number from 3 to 48.

- Collapsing Input Limit -- This is a secondary option for controlling the degree to which the fitter flattens a design netlist. A logic gate can collapse forward into a subsequent gate only if the number of inputs in the resulting logic function does not exceed the input limit. If the design fails to fit the target device because flattening uses up too many of the function block inputs, decrease the input limit to prevent flattening of certain high fan-in functions.

## XPLA Advanced Options

The following options are available under XPLA Implementation Options, Advanced tab.

- Enable Fast Input Registers -- Enables the use of the Fast Input path in XPLA3 devices.

- Enable Use of Foldback NANDs -- When selected, the software will use foldback NANDs. This increases the capability to fit a design, sometimes at the expense of speed.

- Reserve JTAG Pins for ISP -- Checking this box will instruct the fitter to reserve JTAG pins.

## CoolRunner-II Advanced Options

The following options are found under the Advanced tab for CoolRunner-II devices.

- #### Use Global Clock(s) -- Select this option to allow the fitter to assign input pins used as clocks to dedicated global clock (GCK) pins of the device. If this option is disabled, only pins identified with the BUFG=CLK property in the design (or UCF file) will be assigned to GCK device pins. By default, this option is on.

- Use Global Output Enable(s) -- Select this option to allow the fitter to assign input pins used as output enable control to dedicated global OE (GTS) pins of the device. If this option is disabled, only pins identified with the BUFG=OE property in the design (or UCF file) will be assigned to GTS device pins. By default, this option is on.

- Use Global Set/Reset -- Select this option to allow the fitter to assign input pins used as register asynchronous reset or preset control to the dedicated global set/reset (GSR) pin of the device. If this option is disabled, only a pin identified with the BUFG=SR property in the design (or UCF file) will be assigned to the GSR device pin. By default, this option is on.

- Enable Fast Input Registers -- Enables fast input registers.

- Ignore DATA_GATE Attributes -- Data Gate is a power saving property that can be used in CoolRunner-II designs. This option allows you to turn Data Gate off in case you want the fitter to ignore data gate.

- Tristate Outputs Termination Node -- The Tristate Output Termination Mode globally sets all tristate outputs to the specified termination mode. By default, this field is set to Pullup.. The options are Pullup, Keeper and Float.

- Create Programmable Ground Pins on Unused I/O -- The Create Programmable GND Pins on Unused I/O property controls the option to indicate that you want all unused I/O pads to be configured as ground pins. This can reduce ground bounce. By default, this option is set to ground. The options are Ground, Pullup, Keeper and Float.

- Default Output Voltage Standard -- set a default voltage standard for CoolRunner-II device pins.

  IOSTANDARD names supported by CoolRunner-II are:

  I/O Standard | VCCIO | Input VREF | Board Termination Voltage (VTT)
  LVTTL | 3.3V | N/A | N/A
  LVCMOS33 | 3.3V | N/A | N/A
  LVCMOS25 | 2.5V | N/A | N/A
  LVCMOS18 | 1.8V | N/A | N/A
  LVCMOS15 | 1.5V | N/A | N/A
  HSTL_I | 1.5V | 0.75V | 0.75V
  SSTL2_I | 2.5V | 1.25V | 1.25V
  SSTL3_I | 3.3V | 1.5V | 1.5V

  The software automatically groups outputs with similar IOSTANDARD settings into the same bank when no location constraints are specified.

## XC9500/XL/XV Advanced Options

The following options are found under the Advanced tab for XC9500/XL/XV. Note that additional options for XC9500 only are also described below.

- #### Use Global Clock(s) -- Select this option to allow the fitter to assign input pins used as clocks to dedicated global clock (GCK) pins of the device. If this option is disabled, only pins identified with the BUFG=CLK property in the design (or UCF file) will be assigned to GCK device pins. By default, this option is on.

- Use Global Output Enable(s) -- Select this option to allow the fitter to assign input pins used as output enable control to dedicated global OE (GTS) pins of the device. If this option is disabled, only pins identified with the BUFG=OE property in the design (or UCF file) will be assigned to GTS device pins. By default, this option is on.

- Use Global Set/Reset -- Select this option to allow the fitter to assign input pins used as register asynchronous reset or preset control to the dedicated global set/reset (GSR) pin of the device. If this option is disabled, only a pin identified with the BUFG=SR property in the design (or UCF file) will be assigned to the GSR device pin. By default, this option is on.

- Create Programmable Ground Pins on Unused I/O -- Select this option to indicate that you want all unused I/O pads to be configured as ground pins. This can reduce ground bounce. By default, this option is off.

- Macrocell Power Setting -- Use this option to control device power consumption. Select Low or Standard to set the default power mode for the macrocells used to implement the design. Select Timing Driven to automatically reduce power on paths covered by timing specifications that can meet speed requirements while operating in low power. The default is Standard, which results in highest speed.

Note: Any explicit power control (PWR_MODE) properties in the design or constraints file take precedence over this Macrocell Power Setting.

- Enable FASTConnect/UIM Optimization (XC9500 only) -- Enables optimization of the FASTConnect/UIM for XC9500 devices.

- #### Use Local Feedback (XC9500 only)

Select this option to enable the software to use local macrocell feedback whenever possible. The local feedback path, running from each macrocell output to an input of the same function block, has shorter propagation delay than the global feedback path. The fitter always tries to use local macrocell feedback (if possible) to satisfy timing constraints. This option allows the fitter to use local feedback to generally improve timing on remaining paths. Using local feedback can speed up your design but could also make it difficult to maintain the same timing after a design change. By default, this option is on.

Note: To force the fitter to use local feedback, manually map both the source and load functions into the same function block using the property LOC=FBnn, then apply a timespec across the path.

Note: The XC9536 device does not have local feedback.

- #### Use Pin Feedback (XC9500 only)

Select this option to enable the software to use I/O pin feedback whenever possible. The pin feedback path has slightly shorter propagation delay than the global feedback path. If this option is enabled, the software uses the pin feedback path instead of the global feedback path for macrocell signals that do not drive 3-state outputs or slew-rate-limited outputs, and where the associated I/O pin is not used as input-only. By default, this option is on.