System Settings

Environment Settings
Environment Variable | xst | ngdbuild
PATHEXT | .COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH; .MSC | .COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH; .MSC

Path

C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;
C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;
C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;
C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;
C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;
C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;
C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;
C:\Xilinx\14.7\ISE_DS\common\bin\nt64;
C:\Xilinx\14.7\ISE_DS\common\lib\nt64;
C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\altera\13.0sp1\modelsim_ase\win32aloem;
C:\intelFPGA_lite\19.1\modelsim_ase\win32aloem

C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;
C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;
C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;
C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;
C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;
C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;
C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;
C:\Xilinx\14.7\ISE_DS\common\bin\nt64;
C:\Xilinx\14.7\ISE_DS\common\lib\nt64;
C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\altera\13.0sp1\modelsim_ase\win32aloem;
C:\intelFPGA_lite\19.1\modelsim_ase\win32aloem

XILINX | C:\Xilinx\14.7\ISE_DS\ISE\ | C:\Xilinx\14.7\ISE_DS\ISE\
XILINX_DSP | C:\Xilinx\14.7\ISE_DS\ISE | C:\Xilinx\14.7\ISE_DS\ISE
XILINX_EDK | C:\Xilinx\14.7\ISE_DS\EDK | C:\Xilinx\14.7\ISE_DS\EDK
XILINX_PLANAHEAD | C:\Xilinx\14.7\ISE_DS\PlanAhead | C:\Xilinx\14.7\ISE_DS\PlanAhead

Synthesis Property Settings
Switch Name | Property Name | Value | Default Value
-ifn |  | WarpSE.prj |
-ifmt |  | mixed | MIXED
-ofn |  | WarpSE |
-ofmt |  | NGC | NGC
-p |  | xc9500xl |
-top |  | WarpSE |
-opt_mode | Optimization Goal | Speed | SPEED
-opt_level | Optimization Effort | 1 | 1
-iuc | Use synthesis Constraints File | NO | NO
-keep_hierarchy | Keep Hierarchy | Yes | YES
-netlist_hierarchy | Netlist Hierarchy | As_Optimized | as_optimized
-rtlview | Generate RTL Schematic | Yes | NO
-bus_delimiter | Bus Delimiter | <> | <>
-verilog2001 | Verilog 2001 | YES | YES
-fsm_extract |  | YES | YES
-fsm_encoding |  | Auto | AUTO
-safe_implementation |  | No | NO
-resource_sharing |  | YES | YES
-iobuf |  | YES | YES
-equivalent_register_removal |  | YES | YES

Translation Property Settings
Switch Name | Property Name | Value | Default Value
-intstyle |  | ise | None
-dd |  | _ngo | None
-p |  | xc95144xl-TQ100-10 | None
-uc |  | C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/WarpSE-XC95144XL.ucf | None

Operating System Information
Operating System Information | xst | ngdbuild
CPU Architecture/Speed | AMD FX(tm)-8320 Eight-Core Processor /3511 MHz | AMD FX(tm)-8320 Eight-Core Processor /3511 MHz
Host | LabWin7 | LabWin7
OS Name | Microsoft Windows 7 , 64-bit | Microsoft Windows 7 , 64-bit
OS Release | Service Pack 1 (build 7601) | Service Pack 1 (build 7601)