# Xilinx Design Summary

MXSE Project Status (03/28/2022 - 09:28:10)
Project File: | WarpSE.xise | Parser Errors: | No Errors
Module Name: | CNT | Implementation State: | Fitted

Target Device:

xc95144xl-10TQ100

- Errors:

Product Version:

ISE 14.7

- Warnings:

Design Goal:</dif>

Balanced

- Routing Results:

Design Strategy:</dif>

Xilinx Default (unlocked)

- Timing Constraints:

Environment:</dif>

- Final Timing Score:

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report |  |  |  |  |
Translation Report |  |  |  |  |
Map Report |  |  |  |  |
Place and Route Report |  |  |  |  |
CPLD Fitter Report (Text) |  |  |  |  |
Power Report |  |  |  |  |
Post-PAR Static Timing Report |  |  |  |  |
Bitgen Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated
Post-Fit Simulation Model Report |  |

Date Generated: 03/28/2022 - 09:28:10