2022-03-28 03:45:53 +00:00
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<?xml version="1.0" encoding="UTF-8" ?>
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<document>
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<!--The data in this file is primarily intended for consumption by Xilinx tools.
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The structure and the elements are likely to change over the next few releases.
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This means code written to parse this file will need to be revisited each subsequent release.-->
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2022-09-04 01:32:05 +00:00
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<application name="pn" timeStamp="Sat Sep 03 16:22:17 2022">
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2022-03-28 03:45:53 +00:00
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<section name="Project Information" visible="false">
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2022-03-29 08:23:54 +00:00
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<property name="ProjectID" value="8B3C87EB1A1F4FD6BCA39339C89EC1EE" type="project"/>
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2022-03-28 03:45:53 +00:00
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<property name="ProjectIteration" value="0" type="project"/>
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2022-03-29 08:23:54 +00:00
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<property name="ProjectFile" value="Z:/Warp-SE/cpld/XC95144XL/WarpSE.xise" type="project"/>
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<property name="ProjectCreationTimestamp" value="2022-03-28T09:14:07" type="project"/>
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2022-03-28 03:45:53 +00:00
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</section>
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<section name="Project Statistics" visible="true">
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<property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
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<property name="PROP_FitterReportFormat" value="HTML" type="process"/>
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<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
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<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
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<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
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<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
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<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
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2022-03-29 08:23:54 +00:00
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<property name="PROP_SynthOptEffort" value="High" type="process"/>
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2022-03-28 03:45:53 +00:00
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<property name="PROP_SynthTopFile" value="changed" type="process"/>
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<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
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<property name="PROP_UseSmartGuide" value="false" type="design"/>
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<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
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2022-03-29 08:23:54 +00:00
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<property name="PROP_cpldfitHDLeqStyle" value="Verilog" type="process"/>
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<property name="PROP_intProjectCreationTimestamp" value="2022-03-28T09:14:07" type="design"/>
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<property name="PROP_intWbtProjectID" value="8B3C87EB1A1F4FD6BCA39339C89EC1EE" type="design"/>
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2022-03-28 03:45:53 +00:00
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<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
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<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
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2022-03-29 08:23:54 +00:00
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<property name="PROP_xcpldFitTemplate" value="Optimize Speed" type="process"/>
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<property name="PROP_xcpldFittimRptOption" value="Detail" type="process"/>
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<property name="PROP_xilxSynthKeepHierarchy_CPLD" value="No" type="process"/>
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2022-03-28 03:45:53 +00:00
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<property name="PROP_xilxSynthMaxFanout" value="100000" type="process"/>
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<property name="PROP_AutoTop" value="true" type="design"/>
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<property name="PROP_DevFamily" value="XC9500XL CPLDs" type="design"/>
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<property name="PROP_DevDevice" value="xc95144xl" type="design"/>
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<property name="PROP_DevFamilyPMName" value="xc9500xl" type="design"/>
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<property name="PROP_DevPackage" value="TQ100" type="design"/>
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<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
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<property name="PROP_DevSpeed" value="-10" type="design"/>
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<property name="PROP_PreferredLanguage" value="Verilog" type="design"/>
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<property name="FILE_UCF" value="1" type="source"/>
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<property name="FILE_VERILOG" value="7" type="source"/>
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</section>
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</application>
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</document>
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