mirror of
https://github.com/garrettsworkshop/Warp-SE.git
synced 2024-09-30 10:54:36 +00:00
Merge branch 'dev' of https://github.com/garrettsworkshop/Warp-SE into dev
This commit is contained in:
parent
acfd21a30f
commit
3a5c243ff3
42
cpld/CNT.v
42
cpld/CNT.v
@ -1,8 +1,8 @@
|
|||||||
module CNT(
|
module CNT(
|
||||||
/* C8M clock input */
|
/* C8M clock input */
|
||||||
input C8M, input E,
|
input C8M, input E, input Er,
|
||||||
/* Refresh request */
|
/* Refresh request */
|
||||||
output reg RefReq, output reg RefUrgent,
|
output reg RefReq, output RefUrgent,
|
||||||
/* Reset, switch, button */
|
/* Reset, switch, button */
|
||||||
input [3:1] SW, output reg nRESout, input nIPL2,
|
input [3:1] SW, output reg nRESout, input nIPL2,
|
||||||
/* Mac PDS bus master control outputs */
|
/* Mac PDS bus master control outputs */
|
||||||
@ -10,7 +10,7 @@ module CNT(
|
|||||||
/* Configuration outputs */
|
/* Configuration outputs */
|
||||||
output C20MEN, output C25MEN, output FastROMEN);
|
output C20MEN, output C25MEN, output FastROMEN);
|
||||||
|
|
||||||
/* Timer counts from 0 to 1001 (9) -- 10 states == 12.766 us
|
/* Timer counts from 0 to 1010 (10) -- 11 states == 14.042 us
|
||||||
* Refresh timer sequence
|
* Refresh timer sequence
|
||||||
* | Timer | RefReq | RefUrgent |
|
* | Timer | RefReq | RefUrgent |
|
||||||
* |------------------------------|
|
* |------------------------------|
|
||||||
@ -21,58 +21,60 @@ module CNT(
|
|||||||
* | 4 0100 | 1 | 0 |
|
* | 4 0100 | 1 | 0 |
|
||||||
* | 5 0101 | 1 | 0 |
|
* | 5 0101 | 1 | 0 |
|
||||||
* | 6 0110 | 1 | 0 |
|
* | 6 0110 | 1 | 0 |
|
||||||
* | 7 0111 | 1 | 1 |
|
* | 7 0111 | 1 | 0 |
|
||||||
* | 8 1000 | 1 | 1 |
|
* | 8 1000 | 1 | 1 |
|
||||||
* | 9 1001 | 1 | 1 |
|
* | 9 1001 | 1 | 1 |
|
||||||
|
* | 10 1010 | 1 | 1 |
|
||||||
* back to timer==0
|
* back to timer==0
|
||||||
*/
|
*/
|
||||||
reg [3:0] Timer = 0;
|
reg [3:0] Timer = 0;
|
||||||
reg TimerTC;
|
reg TimerTC;
|
||||||
always @(posedge E) begin
|
assign RefUrgent = Timer[3];
|
||||||
|
always @(negedge C8M) begin
|
||||||
|
if (Er && !E) begin
|
||||||
TimerTC <= Timer[3:0]==4'h8;
|
TimerTC <= Timer[3:0]==4'h8;
|
||||||
if (TimerTC) Timer <= 0;
|
if (TimerTC) Timer <= 0;
|
||||||
else Timer <= Timer+1;
|
else Timer <= Timer+1;
|
||||||
RefReq <= Timer[3:0]==4'h2 ||
|
RefReq <= Timer[3:0]==4'h2 ||
|
||||||
Timer[3:0]==4'h3 || Timer[3:0]==4'h4 || Timer[3:0]==4'h5 ||
|
Timer[3:0]==4'h3 || Timer[3:0]==4'h4 || Timer[3:0]==4'h5 ||
|
||||||
Timer[3:0]==4'h6 || Timer[3:0]==4'h7 || Timer[3:0]==4'h8;
|
Timer[3:0]==4'h6 || Timer[3:0]==4'h7 || Timer[3:0]==4'h8;
|
||||||
RefUrgent <= Timer[3:0]==4'h6 || Timer[3:0]==4'h7 || Timer[3:0]==4'h8;
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
/* Long timer counts from 0 to 8192 -- 8193 states == 104.588 ms */
|
/* Long timer counts from 0 to 8192 -- 8193 states == 115.046 ms */
|
||||||
reg [13:0] LTimer;
|
reg [13:0] LTimer;
|
||||||
wire LTimerTC = LTimer[13];
|
wire LTimerTC = LTimer[13];
|
||||||
always @(negedge C8M) begin
|
always @(negedge C8M) begin
|
||||||
if (TimerTC) begin
|
if (Er && !E) && TimerTC begin
|
||||||
if (LTimerTC) LTimer <= 0;
|
if (LTimerTC) LTimer <= 0;
|
||||||
else LTimer <= LTimer+1;
|
else LTimer <= LTimer+1;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
/* IPL2 synchronizer */
|
|
||||||
reg IPL2r; always @(negedge C8M) IPL2r <= !nIPL2;
|
|
||||||
|
|
||||||
/* Startup sequence control */
|
/* Startup sequence control */
|
||||||
reg [1:0] PORS = 0;
|
reg [1:0] INITS = 0;
|
||||||
|
assign nAoutOE = !AoutOE;
|
||||||
always @(negedge C8M) begin
|
always @(negedge C8M) begin
|
||||||
case (PORS)
|
case (INITS)
|
||||||
0: begin
|
0: begin
|
||||||
AoutOE <= 0; // Tristate PDS address and control
|
AoutOE <= 0; // Tristate PDS address and control
|
||||||
nRESout <= 0; // Hold reset low
|
nRESout <= 0; // Hold reset low
|
||||||
nBR_IOB <= 0; // Default to request bus
|
nBR_IOB <= 0; // Default to request bus
|
||||||
if (LTimerTC) PORS <= 1;
|
if (LTimerTC) INITS <= 1;
|
||||||
|
else INITS <= 0;
|
||||||
end 1: begin
|
end 1: begin
|
||||||
AoutOE <= 0; // Tristate PDS address and control
|
AoutOE <= 0; // Tristate PDS address and control
|
||||||
nRESout <= 0; // Hold reset low
|
nRESout <= 0; // Hold reset low
|
||||||
nBR_IOB <= nBR_IOB | IPL2r; // Disable bus request if NMI pressed
|
nBR_IOB <= nBR_IOB | !nIPL2; // Disable bus request if NMI pressed
|
||||||
if (LTimerTC && !IPL2r) PORS <= 2;
|
if (LTimerTC && !IPL2r) INITS <= 2;
|
||||||
end 2: begin
|
end 2: begin
|
||||||
AoutOE <= 0; // Tristate PDS address and control
|
AoutOE <= 0; // Tristate PDS address and control
|
||||||
nRESout <= 0; // Hold reset low
|
nRESout <= 0; // Hold reset low
|
||||||
if (LTimerTC) PORS <= 3;
|
if (LTimerTC) INITS <= 3;
|
||||||
end 3: begin
|
end 3: begin
|
||||||
AoutOE <= !nBR_IOB;
|
AoutOE <= !nBR_IOB; // Get on PDS bus if bus was requested
|
||||||
if (LTimerTC) nRESout <= 1; // Wait until LTimerTC to release reset
|
nRESout <= 1; // Release reset
|
||||||
PORS <= 3;
|
INITS <= 3;
|
||||||
end
|
end
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
|
Loading…
Reference in New Issue
Block a user