mirror of
https://github.com/garrettsworkshop/Warp-SE.git
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idk
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parent
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commit
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@ -1,5 +1,6 @@
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{
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"board": {
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"3dviewports": [],
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"design_settings": {
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"defaults": {
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"board_outline_line_width": 0.09999999999999999,
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@ -153,7 +154,8 @@
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"zones_allow_external_fillets": false,
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"zones_use_no_outline": true
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},
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"layer_presets": []
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"layer_presets": [],
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"viewports": []
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},
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"boards": [],
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"cvpcb": {
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@ -337,18 +339,23 @@
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"rule_severities": {
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"bus_definition_conflict": "error",
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"bus_entry_needed": "error",
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"bus_label_syntax": "error",
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"bus_to_bus_conflict": "error",
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"bus_to_net_conflict": "error",
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"conflicting_netclasses": "error",
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"different_unit_footprint": "error",
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"different_unit_net": "error",
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"duplicate_reference": "error",
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"duplicate_sheet_names": "error",
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"endpoint_off_grid": "warning",
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"extra_units": "error",
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"global_label_dangling": "warning",
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"hier_label_mismatch": "error",
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"label_dangling": "error",
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"lib_symbol_issues": "warning",
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"missing_bidi_pin": "warning",
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"missing_input_pin": "warning",
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"missing_power_pin": "error",
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"missing_unit": "warning",
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"multiple_net_names": "warning",
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"net_not_bus_member": "warning",
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"no_connect_connected": "warning",
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@ -358,6 +365,7 @@
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"pin_to_pin": "warning",
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"power_pin_not_driven": "error",
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"similar_labels": "warning",
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"simulation_model_issue": "error",
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"unannotated": "error",
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"unit_value_mismatch": "error",
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"unresolved_variable": "error",
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@ -375,7 +383,7 @@
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"net_settings": {
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"classes": [
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{
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"bus_width": 12.0,
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"bus_width": 12,
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"clearance": 0.2,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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@ -389,13 +397,15 @@
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"track_width": 0.2,
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"via_diameter": 0.6,
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"via_drill": 0.3,
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"wire_width": 6.0
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"wire_width": 6
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}
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],
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"meta": {
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"version": 2
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"version": 3
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},
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"net_colors": null
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"net_colors": null,
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"netclass_assignments": null,
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"netclass_patterns": []
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},
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"pcbnew": {
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"last_paths": {
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@ -411,6 +421,8 @@
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"schematic": {
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"annotate_start_num": 0,
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"drawing": {
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"dashed_lines_dash_length_ratio": 12.0,
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"dashed_lines_gap_length_ratio": 3.0,
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"default_line_thickness": 6.0,
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"default_text_size": 50.0,
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"field_names": [],
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@ -442,7 +454,11 @@
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"page_layout_descr_file": "",
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"plot_directory": "",
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"spice_adjust_passive_values": false,
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"spice_current_sheet_as_root": false,
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"spice_external_command": "spice \"%I\"",
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"spice_model_current_sheet_as_root": true,
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"spice_save_all_currents": false,
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"spice_save_all_voltages": false,
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"subpart_first_id": 65,
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"subpart_id_separator": 0
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},
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File diff suppressed because it is too large
Load Diff
4
PowerAdapter/sym-lib-table
Normal file
4
PowerAdapter/sym-lib-table
Normal file
@ -0,0 +1,4 @@
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(sym_lib_table
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(version 7)
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(lib (name "GW_Logic")(type "KiCad")(uri "${KIPRJMOD}/../../GW_Parts/GW_Logic.kicad_sym")(options "")(descr ""))
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)
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@ -1,5 +1,6 @@
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{
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"board": {
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"3dviewports": [],
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"design_settings": {
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"defaults": {
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"board_outline_line_width": 0.049999999999999996,
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@ -179,7 +180,8 @@
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"zones_allow_external_fillets": false,
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"zones_use_no_outline": true
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},
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"layer_presets": []
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"layer_presets": [],
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"viewports": []
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},
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"boards": [],
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"cvpcb": {
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@ -401,7 +403,7 @@
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"net_settings": {
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"classes": [
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{
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"bus_width": 12.0,
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"bus_width": 12,
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"clearance": 0.15,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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@ -415,13 +417,15 @@
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"track_width": 0.15,
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"via_diameter": 0.5,
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"via_drill": 0.2,
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"wire_width": 6.0
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"wire_width": 6
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}
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],
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"meta": {
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"version": 2
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"version": 3
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},
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"net_colors": null
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"net_colors": null,
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"netclass_assignments": null,
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"netclass_patterns": []
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},
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"pcbnew": {
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"last_paths": {
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37
cpld/CS.v
37
cpld/CS.v
@ -16,15 +16,13 @@ module CS(
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always @(posedge CLK, negedge nRES) begin
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if (~nRES) nOverlay0 <= 0;
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else if (BACT && ODCS) nOverlay0 <= 1;
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end
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always @(posedge CLK) begin
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if (~BACT) nOverlay1 <= nOverlay0;
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end
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/* Select signals - FSB domain */
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wire RAMCS_OverlayOff = A[23:22]==2'b00;
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wire RAMCS_OverlayOn = A[23:21]==3'b011;
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assign RAMCS = (RAMCS_OverlayOff && ~Overlay) || // 000000-3FFFFF when overlay disabled
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assign RAMCS = (RAMCS_OverlayOff && !Overlay) || // 000000-3FFFFF when overlay disabled
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(RAMCS_OverlayOn && Overlay); // 600000-7FFFFF when overlay enabled
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wire VidRAMCSWR64k = RAMCS && A[21:20]==2'h3 && A[19:16]==4'hF && ~nWE; // 3F0000-3FFFFF / 7F0000-7FFFFF
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wire VidRAMCSWR = VidRAMCSWR64k && (
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@ -44,23 +42,26 @@ module CS(
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(A[15:12]==4'hF && (A[11:8]==4'hD || A[11:8]==4'hE || A[11:8]==4'hF)) ||
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(A[15:12]==4'hA && (A[11:8]==4'h1 || A[11:8]==4'h2 || A[11:8]==4'h3)));
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assign ROMCS = (A[23:20]==4'h4 && FastROMEN) ||
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(A[23:20]==4'h8 && !FastROMEN) ||
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(A[23:20]==4'h0 && Overlay);
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assign ROMCS = (A[23:20]==4'h0 && FastROMEN && Overlay) ||
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(A[23:20]==4'h4 && FastROMEN) ||
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(A[23:20]==4'hC && !FastROMEN);
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/* Select signals - IOB domain */
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assign IACS = A[23:08]==16'hFFFF; // IACK
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assign IOCS = (A[23:20]==4'h4 && !FastROMEN) || // Motherboard ROM
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A[23:20]==4'h5 || // SCSI
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A[23:20]==4'h8 || // empty
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A[23:20]==4'h9 || // SCC read/reset
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A[23:20]==4'hA || // empty
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A[23:20]==4'hB || // SCC write
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A[23:20]==4'hC || // empty
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A[23:20]==4'hD || // IWM
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A[23:20]==4'hE || // VIA
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A[23:20]==4'hF || // IACK
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VidRAMCSWR;
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assign IACS = A[23:08]==16'hFFFF; // IACK
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assign IOCS = (A[23:20]==4'h0 && !FastROMEN && !Overlay) ||
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(A[23:20]==4'h4 && !FastROMEN) || // Motherboard ROM
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A[23:20]==4'h5 || // SCSI
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A[23:20]==4'h6 || // empty
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A[23:20]==4'h7 || // empty
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A[23:20]==4'h8 || // empty
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A[23:20]==4'h9 || // SCC read/reset
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A[23:20]==4'hA || // empty
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A[23:20]==4'hB || // SCC write
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(A[23:20]==4'hC && FastROMEN) || // empty / fast ROM
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A[23:20]==4'hD || // IWM
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A[23:20]==4'hE || // VIA
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A[23:20]==4'hF || // IACK
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VidRAMCSWR;
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assign SCSICS = A[23:20]==4'h5; // SCSI
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assign IOPWCS = RAMCS_OverlayOff && ~nWE;
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