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https://github.com/garrettsworkshop/Warp-SE.git
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Make PDS /BR open-drain
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parent
1d48cad261
commit
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@ -201,6 +201,8 @@ module WarpSE(
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.IODONE(IODONE));
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.IODONE(IODONE));
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wire SndQoSReady;
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wire SndQoSReady;
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wire nBR_IOBout;
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assign nBR_IOB = nBR_IOBout ? 1'bZ : 1'b0;
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CNT cnt(
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CNT cnt(
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/* FSB clock, 7.8336 MHz clock, and E clock inputs */
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/* FSB clock, 7.8336 MHz clock, and E clock inputs */
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.CLK(FCLK),
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.CLK(FCLK),
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@ -215,7 +217,7 @@ module WarpSE(
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.nIPL2(nIPL2),
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.nIPL2(nIPL2),
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/* Mac PDS bus master control outputs */
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/* Mac PDS bus master control outputs */
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.AoutOE(AoutOE),
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.AoutOE(AoutOE),
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.nBR_IOB(nBR_IOB),
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.nBR_IOB(nBR_IOBout),
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/* QoS select inputs */
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/* QoS select inputs */
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.BACT(BACT),
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.BACT(BACT),
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.QoSCS(QoSCS),
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.QoSCS(QoSCS),
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