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Eliminate IOBERR

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This commit is contained in:
Zane Kaminski 2024-10-07 01:37:58 -04:00
parent 1f9bd820ac
commit d1cce84963
3 changed files with 23 additions and 19 deletions
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31
cpld/IOBM.v
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@ -7,7 +7,7 @@ module IOBM(
input AoutOE, output nDoutOE, output reg ALE0, output reg nDinLE, input AoutOE, output nDoutOE, output reg ALE0, output reg nDinLE,
/* IO bus slave port interface */ /* IO bus slave port interface */
input IOREQ, input IORW, input IOLDS, input IOUDS, input IOREQ, input IORW, input IOLDS, input IOUDS,
output reg IOACT, output reg IODONE, output reg IOBERR); output reg IOACT, output IODONE);
/* C8M clock registration */ /* C8M clock registration */
reg C8Mr; always @(posedge C16M) C8Mr <= C8M; reg C8Mr; always @(posedge C16M) C8Mr <= C8M;
@ -36,21 +36,26 @@ module IOBM(
else if (ES==0) nVMA <= 1; else if (ES==0) nVMA <= 1;
end end
/* DTACK and BERR synchronization */
always @(negedge C8M, posedge nAS) begin
if (nAS) begin
IODONE <= 0;
IOBERR <= 0;
end else begin
IODONE <= (!nDTACK || ETACK || !nRES);
IOBERR <= !nBERR;
end
end
/* I/O bus state */ /* I/O bus state */
reg [2:0] IOS = 0; reg [2:0] IOS = 0;
reg IOS0; reg IOS0;
/* Cycle termination signal enable */
reg TermEN;
always @(posedge C16M) begin
TermEN <= IOS==2 || IOS==3 || IOS==4 || IOS==5;
end
/* DTACK/"ETACK"/BERR/reset falling edge synchronization */
reg IODONEr;
always @(negedge C8M, posedge nAS) begin
if (nAS) IODONEr <= 0;
else IODONEr <= TermEN && (!nDTACK || ETACK || !nBERR || !nRES);
end
/* DTACK/"ETACK"/BERR/reset output */
assign IODONE = IODONEr && TermEN;
/* I/O bus control */ /* I/O bus control */
always @(posedge C16M) case (IOS[2:0]) always @(posedge C16M) case (IOS[2:0])
3'h0: begin 3'h0: begin
@ -79,7 +84,7 @@ module IOBM(
IOACT <= 1; IOACT <= 1;
ALE0 <= 1; ALE0 <= 1;
end 3'h5: begin end 3'h5: begin
if (!C8Mr && (IODONE || IOBERR)) begin if (!C8Mr && IODONEr) begin
IOS <= 6; IOS <= 6;
IOACT <= 0; IOACT <= 0;
end else begin end else begin

4
cpld/IOBS.v
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@ -11,7 +11,7 @@ module IOBS(
output nDinOE, output nDinOE,
/* IOB master controller interface */ /* IOB master controller interface */
output reg IOREQ, output reg IORW, output reg IOREQ, output reg IORW,
input IOACT, input IODONEin, input IOBERR, input IOACT, input IODONEin, input nBERR_IOB,
/* FIFO primary level control */ /* FIFO primary level control */
output reg ALE0, output reg IOL0, output reg IOU0, output reg ALE0, output reg IOL0, output reg IOU0,
/* FIFO secondary level control */ /* FIFO secondary level control */
@ -139,6 +139,6 @@ module IOBS(
/* BERR control */ /* BERR control */
always @(posedge CLK) begin always @(posedge CLK) begin
if (!BACT) nBERR_FSB <= 1; if (!BACT) nBERR_FSB <= 1;
else if (Sent && IOBERR) nBERR_FSB <= 0; else if (Sent && IODONE && nBERR_IOB) nBERR_FSB <= 0;
end end
endmodule endmodule

7
cpld/WarpSE.v
View File

@ -132,7 +132,7 @@ module WarpSE(
wire ALE0S, ALE0M, ALE1; wire ALE0S, ALE0M, ALE1;
assign nADoutLE0 = ~(ALE0S || ALE0M); assign nADoutLE0 = ~(ALE0S || ALE0M);
assign nADoutLE1 = ~ALE1; assign nADoutLE1 = ~ALE1;
wire IOACT, IODONE, IOBERR; wire IOACT, IODONE;
IOBS iobs( IOBS iobs(
/* MC68HC000 interface */ /* MC68HC000 interface */
.CLK(FCLK), .CLK(FCLK),
@ -157,7 +157,7 @@ module WarpSE(
.IORW(IORW), .IORW(IORW),
.IOACT(IOACT), .IOACT(IOACT),
.IODONEin(IODONE), .IODONEin(IODONE),
.IOBERR(IOBERR), .nBERR_IOB(!nBERR_IOB),
/* FIFO primary level control */ /* FIFO primary level control */
.ALE0(ALE0S), .ALE0(ALE0S),
.IOL0(IOL0), .IOL0(IOL0),
@ -198,8 +198,7 @@ module WarpSE(
.IOLDS(IOL0), .IOLDS(IOL0),
.IOUDS(IOU0), .IOUDS(IOU0),
.IOACT(IOACT), .IOACT(IOACT),
.IODONE(IODONE), .IODONE(IODONE));
.IOBERR(IOBERR));
wire SndQoSReady; wire SndQoSReady;
CNT cnt( CNT cnt(