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New RAM controller
This commit is contained in:
Zane Kaminski
parent
3b97a15817
commit
d557f9e502
@ -22,10 +22,13 @@ module FSB(
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(RAMCS && !QoSEN && RAMReady && IOPWCS && IOPWReady) ||
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(ROMCS && !QoSEN) ||
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(IONPReady && SndQoSReady);
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always @(posedge FCLK) nDTACK <= !(Ready && BACT && !IACS);
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always @(posedge FCLK, posedge nAS) begin
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if (nAS) nDTACK <= 1;
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else nDTACK <= !(Ready && !IACS);
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end
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always @(posedge FCLK, posedge nAS) begin
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if (nAS) nVPA <= 1;
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else nVPA <= !(Ready && BACT && IACS);
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else nVPA <= !(Ready && IACS);
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end
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endmodule
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@ -2,7 +2,7 @@ module IOBS(
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/* MC68HC000 interface */
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input CLK, input nWE, input nAS, input nLDS, input nUDS,
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/* AS cycle detection */
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input BACT,
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input BACT, input BACTr,
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/* Select signals */
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input IOCS, input IORealCS, input IOPWCS,
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/* FSB cycle termination outputs */
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@ -25,7 +25,7 @@ module IOBS(
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wire IODONE = IODONEr;
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/* Read data OE control */
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assign nDinOE = !(!nAS && IORealCS && nWE);
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assign nDinOE = !(!nAS && BACTr && IORealCS && nWE);
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/* I/O transfer state
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* TS0 - I/O bridge idle:
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147
cpld/RAM.v
147
cpld/RAM.v
@ -7,41 +7,40 @@ module RAM(
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/* Select and ready signals */
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input RAMCS, input RAMCS0X, input ROMCS, input ROMCS4X,
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/* RAM ready output */
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output reg RAMReady,
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output RAMReady,
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/* Refresh Counter Interface */
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input RefReqIn, input RefUrgIn,
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/* DRAM and NOR flash interface */
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output [11:0] RA, output nRAS, output reg nCAS,
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output nLWE, output nUWE, output reg nOE, output nROMOE, output nROMWE);
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/* BACT and /DTACK registration */
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reg DTACKr; always @(posedge CLK) DTACKr <= !nDTACK;
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/* RAM control state */
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reg [2:0] RS = 0;
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reg RASEN = 0;
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reg RASEL = 0;
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reg RASrr = 0;
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reg RASrf = 0;
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reg [2:0] RS;
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reg RASEN;
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reg RASEL;
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reg RASrf;
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reg RefCAS;
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reg CASEndEN;
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assign RAMReady = RASEN;
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/* Refresh command generation */
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reg RefDone; // Refresh done "remember"
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always @(posedge CLK) begin
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if (!RefReqIn && !RefUrgIn) RefDone <= 0;
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if (!RefReqIn) RefDone <= 0;
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else if (RS[2]) RefDone <= 1;
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end
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wire RefReq = RefReqIn && !RefDone;
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wire RefUrg = RefUrgIn && !RefDone;
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/* RAM control signals */
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assign nRAS = !((!nAS && RAMCS && RASEN) || RASrr || RASrf);
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assign nLWE = !(!nLDS && !nWE && RASEL);
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assign nUWE = !(!nUDS && !nWE && RASEL);
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always @(posedge CLK) nOE <= !(BACT && nWE && !(BACTr && DTACKr));
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assign nRAS = !((!nAS && RAMCS0X && RASEN) || RASrf);
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assign nOE = 0;//!( !nAS && RAMCS && BACTr);
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assign nLWE = !(!nLDS && RASEL && !nWE);
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assign nUWE = !(!nUDS && RASEL && !nWE);
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/* ROM control signals */
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assign nROMOE = !(ROMCS && !nAS && nWE);
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assign nROMWE = !(ROMCS4X && !nAS && !nWE);
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assign nROMOE = !(!nAS && ROMCS && nWE);
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assign nROMWE = !(!nAS && ROMCS4X && !nWE);
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/* RAM address mux (and ROM address on RA8) */
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// RA11 doesn't do anything so both should be identical.
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@ -65,94 +64,104 @@ module RAM(
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// Urgent refresh while bus inactive
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(RefUrg && !BACT) ||
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// Urgent refresh during non-RAM access
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(RefUrg && BACT && !RAMCS0X) ||
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// Urgent refresh if RAM is disabled
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(RefUrg && !RASEN);
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(RefUrg && BACT && !RAMCS0X);
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wire RS0toRAM = BACT && RAMCS0X && RASEN;
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always @(posedge CLK) begin
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case (RS[2:0])
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0: begin // Idle/ready
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if (RS0toRef) begin // Refresh RAS I
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RS <= 4;
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RASEL <= 0;
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RASrr <= 1;
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RASEN <= 0;
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RAMReady <= 0;
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end else if (BACT && RAMCS && RASEN) begin // Access RAM
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RS <= 1;
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RASEL <= 1;
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RASrr <= 1;
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RASEN <= 1;
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RAMReady <= 1;
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end else begin // Stay in idle/ready
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RS <= 0;
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RASEL <= 0;
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RASrr <= 0;
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RASEN <= 1;
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RAMReady <= 1;
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end
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if (RS0toRAM) RS <= 1; // Access RAM
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else if (RS0toRef) RS <= 4; // To refresh
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else RS <= 0; // Stay in idle/ready
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RASEL <= BACT && RAMCS;
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RefCAS <= RS0toRef;
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RASEN <= !RS0toRef;
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end 1: begin // RAM access
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RS <= 2;
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if (!nDTACK || !BACT) RS <= 2; // Cycle ending
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else RS <= 1; // Cycle not ending yet
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RASEL <= 1;
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RASrr <= 0;
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RASEN <= 0;
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RAMReady <= 1;
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RefCAS <= 0;
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RASEN <= nDTACK;
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end 2: begin // finish RAM access
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if (DTACKr) RS <= 3; // Cycle ending
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else RS <= 2; // Cycle not ending yet
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RS <= 3;
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RASEL <= 0;
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RASrr <= 0;
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RefCAS <= 0;
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RASEN <= 0;
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RAMReady <= 1;
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end 3: begin //AS cycle complete
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if (RefUrg) begin // Refresh RAS
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RS <= 4;
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RASEL <= 0;
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RASrr <= 1;
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RefCAS <= 1;
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RASEN <= 0;
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RAMReady <= 0;
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end else begin // Cycle ended so go abck to idle/ready
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end else begin // Cycle ended so go back to idle/ready
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RS <= 0;
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RASEL <= 0;
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RASrr <= 0;
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RefCAS <= 0;
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RASEN <= 1;
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RAMReady <= 1;
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end
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end 4: begin // Refresh RAS II
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RASEL <= 0;
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end 4: begin // Refresh RAS I
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RS <= 5;
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RASEL <= 0;
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RASrr <= 1;
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RefCAS <= 0;
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RASEN <= 0;
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RAMReady <= 0;
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end 5: begin // Refresh precharge I
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end 5: begin // Refresh RAS II
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RS <= 6;
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RASEL <= 0;
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RASrr <= 0;
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RefCAS <= 0;
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RASEN <= 0;
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RAMReady <= 0;
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end 6: begin // Refresh precharge II
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end 6: begin // Refresh precharge I
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RS <= 7;
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RASEL <= 0;
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RASrr <= 0;
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RefCAS <= 0;
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RASEN <= 0;
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RAMReady <= 0;
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end 7: begin // Reenable RAM and go to idle/ready
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RS <= 0;
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RASEL <= 0;
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RASrr <= 0;
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RefCAS <= 0;
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RASEN <= 1;
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RAMReady <= 1;
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end
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endcase
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end
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always @(negedge CLK) begin
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RASrf <= RS==1;
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case (RS[2:0])
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0: nCAS <= !RS0toRef;
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0: begin
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RASrf <= 0;
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CASEndEN <= 0;
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end 1: begin
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RASrf <= 1;
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CASEndEN <= 1;
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end 2: begin
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RASrf <= 0;
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CASEndEN <= 1;
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end 3: begin
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RASrf <= 0;
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CASEndEN <= 0;
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end 4: begin
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RASrf <= 1;
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CASEndEN <= 0;
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end 5: begin
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RASrf <= 1;
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CASEndEN <= 0;
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end 6: begin
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RASrf <= 0;
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CASEndEN <= 0;
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end 7: begin
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RASrf <= 0;
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CASEndEN <= 0;
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end
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endcase
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end
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wire CASEnd = CASEndEN && nAS;
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always @(negedge CLK, posedge RefCAS, posedge CASEnd) begin
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if (RefCAS) nCAS <= 0;
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else if (CASEnd) nCAS <= 1;
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else case (RS[2:0])
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0: nCAS <= 1;
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1: nCAS <= 0;
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2: nCAS <= DTACKr;
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3: nCAS <= !RefUrg;
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4: nCAS <= !RefUrg;
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2: nCAS <= 0;
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3: nCAS <= 1;
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4: nCAS <= 0;
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5: nCAS <= 1;
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6: nCAS <= 1;
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7: nCAS <= 1;
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@ -140,7 +140,7 @@ module WarpSE(
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.nLDS(nLDS_FSB),
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.nUDS(nUDS_FSB),
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/* AS cycle detection */
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.BACT(BACT),
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.BACT(BACT), .BACTr(BACTr),
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/* Select signals */
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.IOCS(IOCS),
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.IORealCS(IORealCS),
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