mirror of
https://github.com/garrettsworkshop/Warp-SE.git
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Add slowdown settings
This commit is contained in:
Zane Kaminski
parent
cfe5cf936c
commit
d92e235e25
38
cpld/CNT.v
38
cpld/CNT.v
@ -11,11 +11,23 @@ module CNT(
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input nAS,
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input ASrf,
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input BACT,
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input QoSCS,
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input SndQoSCS,
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input IACKCS,
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input VIACS,
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input IWMCS,
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input SCCCS,
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input SCSICS,
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input SndCSWR,
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/* QoS settings inputs */
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input SlowIACK,
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input SlowVIA,
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input SlowIWM,
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input SlowSCC,
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input SlowSCSI,
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input SlowSnd,
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input SlowClockGate,
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input [3:0] SlowTimeout,
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/* QoS outputs */
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output reg QoSEN,
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output SndQoSReady,
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output reg MCKE);
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/* E clock synchronization */
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@ -57,9 +69,16 @@ module CNT(
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always @(posedge CLK) TimerTick <= EFall && TimerTC;
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/* QoS select latches */
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reg QoSCSr, SndQoSCSr;
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always @(posedge CLK) QoSCSr <= (BACT && QoSCS) || !nRESin;
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always @(posedge CLK) SndQoSCSr <= BACT && SndQoSCS;
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reg QoSCSr;
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always @(posedge CLK) begin
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QoSCSr <= !nRESin ||
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(!nAS && SlowIACK && IACKCS) ||
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(!nAS && SlowVIA && VIACS) ||
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(!nAS && SlowIWM && IWMCS) ||
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(!nAS && SlowSCC && SCCCS) ||
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(!nAS && SlowSCSI && SCSICS) ||
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(!nAS && SlowSnd && SndCSWR);
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end
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/* QoS timer
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* In the absence of a QoS trigger, QS==0.
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@ -68,19 +87,18 @@ module CNT(
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* QoS enable period is 196.588 us - 210.630 us */
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reg [3:0] QS;
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always @(posedge CLK) begin
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if (SndQoSCSr || QoSCSr) QS <= 15;
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if (QoSCSr) QS <= 15;
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else if (QS==0) QS <= 0;
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else if (TimerTick) QS <= QS-1;
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end
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/* QoS enable control */
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always @(posedge CLK) if (!BACT) QoSEN <= QS!=0;
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assign SndQoSReady = 1;
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always @(posedge CLK) if (!BACT) QoSEN <= QS!=0 || SlowTimeout==0;
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/* MC68k clock gating during QoS */
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always @(negedge CLK, negedge nAS) begin
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if (!nAS) MCKE <= 1;
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else MCKE <= ASrf || !QoSEN || C8MFall;
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else MCKE <= ASrf || !QoSEN || C8MFall || !SlowClockGate;
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end
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/* Long timer counts from 0 to 4095.
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20
cpld/CS.v
20
cpld/CS.v
@ -9,7 +9,9 @@ module CS(
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output IOCS, output IORealCS, output IOPWCS, output IACS,
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output ROMCS, output ROMCS4X,
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output RAMCS, output RAMCS0X,
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output QoSCS, output SndQoSCS);
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output IACKCS, output VIACS, output IWMCS,
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output SCCCS, output SCSICS, output SndCSWR,
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output SetCSWR);
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/* Overlay control */
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reg Overlay;
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@ -19,11 +21,11 @@ module CS(
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end
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/* I/O select signals */
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wire IACKCS = A[23:20]==4'hF;
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wire VIACS = A[23:20]==4'hE;
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wire IWMCS = A[23:20]==4'hD;
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wire SCCCS = A[23:20]==4'hB || A[23:20]==4'h9;
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wire SCSICS = A[23:20]==4'h5;
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assign IACKCS = A[23:20]==4'hF;
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assign VIACS = A[23:20]==4'hE;
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assign IWMCS = A[23:20]==4'hD;
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assign SCCCS = A[23:20]==4'hB || A[23:20]==4'h9;
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assign SCSICS = A[23:20]==4'h5;
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/* ROM select signals */
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assign ROMCS4X = A[23:20]==4'h4;
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@ -46,11 +48,11 @@ module CS(
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//A[15:12]==4'hD || // 4096 bytes video
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//A[15:12]==4'hE || // 4096 bytes video
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//A[15:12]==4'hF); // 3200 bytes video, 128 bytes RAM (system error space), 768 bytes sound
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wire SndRAMCSWR = VidRAMCSWR64k && (
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assign SndCSWR = VidRAMCSWR64k && (
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((A[15:12]==4'hF) && (A[11:8]==4'hD || A[11:8]==4'hE || A[11:8]==4'hF)) ||
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((A[15:12]==4'hA) && (A[11:8]==4'h1 || A[11:8]==4'h2 || A[11:8]==4'h3)));
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assign QoSCS = IACKCS || VIACS || IWMCS || SCCCS || SCSICS;
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assign SndQoSCS = SndRAMCSWR;
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assign SetCSWR = A[23:20]==4'hF && !A[19];
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/* Select signals - IOB domain */
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assign IACS = A[23:20]==4'hF; // IACK
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11
cpld/FSB.v
11
cpld/FSB.v
@ -7,9 +7,9 @@ module FSB(
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input ROMCS,
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input RAMCS, input RAMReady,
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input IOPWCS, input IOPWReady, input IONPReady,
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input QoSEN, input SndQoSReady,
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input QoSEN,
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/* Interrupt acknowledge select */
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input IACS);
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input IACKCS);
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/* AS cycle detection */
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always @(negedge FCLK) begin ASrf <= !nAS; end
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@ -19,15 +19,14 @@ module FSB(
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/* DTACK/VPA control */
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wire Ready = (RAMCS && !QoSEN && RAMReady && !IOPWCS) ||
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(RAMCS && !QoSEN && RAMReady && IOPWCS && IOPWReady) ||
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(ROMCS && !QoSEN) ||
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(IONPReady && SndQoSReady);
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(ROMCS && !QoSEN) || (IONPReady);
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always @(posedge FCLK, posedge nAS) begin
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if (nAS) nDTACK <= 1;
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else nDTACK <= !(Ready && !IACS);
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else nDTACK <= !(Ready && !IACKCS);
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end
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always @(posedge FCLK, posedge nAS) begin
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if (nAS) nVPA <= 1;
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else nVPA <= !(Ready && IACS);
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else nVPA <= !(Ready && IACKCS);
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end
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endmodule
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30
cpld/SET.v
Normal file
30
cpld/SET.v
Normal file
@ -0,0 +1,30 @@
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module SET(
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input CLK,
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input BACT,
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input [11:1] A,
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input SetCSWR,
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output reg SlowIACK,
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output reg SlowVIA,
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output reg SlowIWM,
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output reg SlowSCC,
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output reg SlowSCSI,
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output reg SlowSnd,
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output reg SlowClockGate,
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output reg [3:0] SlowTimeout);
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reg SetWRr; always @(posedge CLK) SetWRr <= BACT && SetCSWR;
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always @(posedge CLK) begin
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if (SetWRr) begin
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SlowTimeout[3:0] <= A[11:8];
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SlowIACK <= A[7];
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SlowVIA <= A[6];
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SlowIWM <= A[5];
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SlowSCC <= A[4];
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SlowSCSI <= A[3];
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SlowSnd <= A[2];
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SlowClockGate <= A[1];
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end
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end
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endmodule
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@ -63,10 +63,12 @@ module WarpSE(
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wire RefReq, RefUrg;
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/* FSB chip select signals */
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wire IOCS, IORealCS, IOPWCS, IACS;
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wire IOCS, IORealCS, IOPWCS;
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wire ROMCS, ROMCS4X;
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wire RAMCS, RAMCS0X;
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wire QoSCS, SndQoSCS, QoSEN;
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wire QoSEN;
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wire IACKCS, VIACS, IWMCS, SCCCS, SCSICS, SndCSWR;
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wire SetCSWR;
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CS cs(
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/* MC68HC000 interface */
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.A(A_FSB[23:08]),
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@ -81,13 +83,19 @@ module WarpSE(
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.IOCS(IOCS),
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.IORealCS(IORealCS),
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.IOPWCS(IOPWCS),
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.IACS(IACS),
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.ROMCS(ROMCS),
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.ROMCS4X(ROMCS4X),
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.RAMCS(RAMCS),
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.RAMCS0X(RAMCS0X),
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.QoSCS(QoSCS),
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.SndQoSCS(SndQoSCS));
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/* Motherboard I/O device select outputs */
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.IACKCS(IACKCS),
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.VIACS(VIACS),
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.IWMCS(IWMCS),
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.SCCCS(SCCCS),
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.SCSICS(SCSICS),
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.SndCSWR(SndCSWR),
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/* Settings register select output */
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.SetCSWR(SetCSWR));
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wire RAMReady;
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RAM ram(
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@ -196,7 +204,22 @@ module WarpSE(
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.IOACT(IOACT),
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.IODONE(IODONE));
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wire SndQoSReady;
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wire SlowIACK, SlowVIA, SlowIWM, SlowSCC, SlowSCSI, SlowSnd, SlowClockGate;
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wire [3:0] SlowTimeout;
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SET set(
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.CLK(FCLK),
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.BACT(BACT),
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.A(A_FSB[11:1]),
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.SetCSWR(SetCSWR),
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.SlowIACK(SlowIACK),
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.SlowVIA(SlowVIA),
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.SlowIWM(SlowIWM),
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.SlowSCC(SlowSCC),
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.SlowSCSI(SlowSCSI),
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.SlowSnd(SlowSnd),
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.SlowClockGate(SlowClockGate),
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.SlowTimeout(SlowTimeout));
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wire nBR_IOBout;
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assign nBR_IOB = nBR_IOBout ? 1'bZ : 1'b0;
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CNT cnt(
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@ -218,11 +241,23 @@ module WarpSE(
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.nAS(nAS_FSB),
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.ASrf(ASrf),
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.BACT(BACT),
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.QoSCS(QoSCS),
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.SndQoSCS(SndQoSCS),
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.IACKCS(IACKCS),
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.VIACS(VIACS),
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.IWMCS(IWMCS),
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.SCCCS(SCCCS),
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.SCSICS(SCSICS),
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.SndCSWR(SndCSWR),
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/* QoS settings inputs */
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.SlowIACK(SlowIACK),
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.SlowVIA(SlowVIA),
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.SlowIWM(SlowIWM),
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.SlowSCC(SlowSCC),
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.SlowSCSI(SlowSCSI),
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.SlowSnd(SlowSnd),
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.SlowClockGate(SlowClockGate),
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.SlowTimeout(SlowTimeout),
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/* QoS outputs */
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.QoSEN(QoSEN),
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.SndQoSReady(SndQoSReady),
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.MCKE(MCKE));
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FSB fsb(
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@ -243,9 +278,8 @@ module WarpSE(
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.IOPWReady(IOPWReady),
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.IONPReady(IONPReady),
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.QoSEN(QoSEN),
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.SndQoSReady(SndQoSReady),
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/* Interrupt acknowledge select */
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.IACS(IACS));
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.IACKCS(IACKCS));
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endmodule
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