mirror of
https://github.com/garrettsworkshop/Warp-SE.git
synced 2025-01-31 01:32:54 +00:00
0.7a-fastiack-fastscc-fastscsi-35us compiled
This commit is contained in:
Zane Kaminski
parent
8d7b09a2f4
commit
f06f157d29
@ -17,7 +17,7 @@ module SET(
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always @(posedge CLK) begin
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if (!nPOR) begin
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SlowTimeout[3:0] <= 4'hF;
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SlowTimeout[3:0] <= 4'h3;
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SlowIACK <= 0;
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SlowVIA <= 1;
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SlowIWM <= 1;
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5163
cpld/XC95144XL/WarpSE-0.7a-fastiack-fastscc-fastscsi-35us.svf
Normal file
5163
cpld/XC95144XL/WarpSE-0.7a-fastiack-fastscc-fastscsi-35us.svf
Normal file
File diff suppressed because it is too large
Load Diff
@ -30,7 +30,7 @@ NGDBUILD Design Results Summary:
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Number of errors: 0
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Number of warnings: 0
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Total memory usage is 154688 kilobytes
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Total memory usage is 155072 kilobytes
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Writing NGD file "WarpSE.ngd" ...
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Total REAL time to NGDBUILD completion: 3 sec
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@ -1442,3 +1442,14 @@ XSLTProcess WarpSE_build.xml
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tsim -intstyle ise WarpSE WarpSE.nga
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taengine -intstyle ise -f WarpSE -w --format html1 -l WarpSE_html/tim/timing_report.htm
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hprep6 -s IEEE1149 -n WarpSE -i WarpSE
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xst -intstyle ise -ifn "C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL/WarpSE.syr"
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ngdbuild -intstyle ise -dd _ngo -uc C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
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cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
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XSLTProcess WarpSE_build.xml
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xst -intstyle ise -ifn "C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL/WarpSE.syr"
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ngdbuild -intstyle ise -dd _ngo -uc C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
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cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
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XSLTProcess WarpSE_build.xml
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tsim -intstyle ise WarpSE WarpSE.nga
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taengine -intstyle ise -f WarpSE -w --format html1 -l WarpSE_html/tim/timing_report.htm
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hprep6 -s IEEE1149 -n WarpSE -i WarpSE
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@ -62,15 +62,15 @@
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</files>
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<transforms xmlns="http://www.xilinx.com/XMLSchema">
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<transform xil_pn:end_ts="1728475153" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1728475153">
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<transform xil_pn:end_ts="1728713436" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1728713436">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1728475153" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-8819683973431472423" xil_pn:start_ts="1728475153">
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<transform xil_pn:end_ts="1728713436" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-8819683973431472423" xil_pn:start_ts="1728713436">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1728713236" xil_pn:in_ck="1680431259208978880" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="-827049739915084467" xil_pn:start_ts="1728713229">
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<transform xil_pn:end_ts="1728713444" xil_pn:in_ck="1680431259208978880" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="-827049739915084467" xil_pn:start_ts="1728713436">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="WarningsGenerated"/>
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<status xil_pn:value="ReadyToRun"/>
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@ -86,11 +86,11 @@
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<outfile xil_pn:name="webtalk_pn.xml"/>
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<outfile xil_pn:name="xst"/>
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</transform>
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<transform xil_pn:end_ts="1728475161" xil_pn:in_ck="-6638154780101949348" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5069202360897704756" xil_pn:start_ts="1728475161">
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<transform xil_pn:end_ts="1728713444" xil_pn:in_ck="-6638154780101949348" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5069202360897704756" xil_pn:start_ts="1728713444">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1728713242" xil_pn:in_ck="814020912342028692" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="1893441463969615248" xil_pn:start_ts="1728713236">
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<transform xil_pn:end_ts="1728713450" xil_pn:in_ck="814020912342028692" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="1893441463969615248" xil_pn:start_ts="1728713444">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<outfile xil_pn:name="WarpSE.bld"/>
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@ -99,7 +99,7 @@
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<outfile xil_pn:name="_ngo"/>
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<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
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</transform>
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<transform xil_pn:end_ts="1728713261" xil_pn:in_ck="4179227257693753" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="3294015560432670715" xil_pn:start_ts="1728713242">
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<transform xil_pn:end_ts="1728713463" xil_pn:in_ck="4179227257693753" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="3294015560432670715" xil_pn:start_ts="1728713450">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="WarningsGenerated"/>
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<status xil_pn:value="ReadyToRun"/>
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@ -119,12 +119,12 @@
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<outfile xil_pn:name="WarpSE_html"/>
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<outfile xil_pn:name="WarpSE_pad.csv"/>
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</transform>
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<transform xil_pn:end_ts="1728713274" xil_pn:in_ck="4179227257702617" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1728713272">
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<transform xil_pn:end_ts="1728713475" xil_pn:in_ck="4179227257702617" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1728713472">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<outfile xil_pn:name="WarpSE.jed"/>
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</transform>
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<transform xil_pn:end_ts="1728713274" xil_pn:in_ck="4179227257689331" xil_pn:name="TRAN_impactProgrammingTool_CPLD" xil_pn:prop_ck="-207801193714804843" xil_pn:start_ts="1728713274">
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<transform xil_pn:end_ts="1728713475" xil_pn:in_ck="4179227257689331" xil_pn:name="TRAN_impactProgrammingTool_CPLD" xil_pn:prop_ck="-207801193714804843" xil_pn:start_ts="1728713475">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<outfile xil_pn:name="_impactbatch.log"/>
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@ -140,7 +140,7 @@
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<outfile xil_pn:name="_impactbatch.log"/>
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<outfile xil_pn:name="ise_impact.cmd"/>
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</transform>
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<transform xil_pn:end_ts="1728713263" xil_pn:in_ck="4179227257702617" xil_pn:name="TRAN_timRpt" xil_pn:prop_ck="111903974446" xil_pn:start_ts="1728713261">
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<transform xil_pn:end_ts="1728713465" xil_pn:in_ck="4179227257702617" xil_pn:name="TRAN_timRpt" xil_pn:prop_ck="111903974446" xil_pn:start_ts="1728713463">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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@ -1,5 +1,5 @@
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Programmer Jedec Bit Map
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Date Extracted: Sat Oct 12 02:07:53 2024
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Date Extracted: Sat Oct 12 02:11:13 2024
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QF93312*
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QP100*
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@ -422,8 +422,8 @@ L0018912 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0018960 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0019008 00000011 00000000 00000000 00000001 00000000 00000001 00000010 00000000*
|
||||
L0019072 00000001 00000000 00000010 00000011 00000010 00000000 00000000 00000000*
|
||||
L0019136 00000001 00000000 00000000 00000001 00000000 00000010 00000011 00000000*
|
||||
L0019200 00000000 00000000 00000000 00000001 00000000 00000010 00000000 00000010*
|
||||
L0019136 00000001 00000000 00000000 00000000 00000000 00000010 00000011 00000000*
|
||||
L0019200 00000000 00000000 00000000 00000000 00000000 00000010 00000000 00000010*
|
||||
L0019264 00000000 00000000 00000000 00000010 00000010 00000001 00000000 00000010*
|
||||
L0019328 00000001 00000000 00000001 00000011 00000010 00000010 00000000 00000010*
|
||||
L0019392 00000000 00000000 00000001 00000010 00000000 00000001 00000001 00000000*
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@ -431,7 +431,7 @@ L0019456 00000001 00000000 00000001 00000000 00000001 00000011 00000000 00000010
|
||||
L0019520 00000000 00000000 00000001 00000000 00000000 00000000 00000000 00000000*
|
||||
L0019584 000000 000000 000000 000000 000000 000000 000000 000000*
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||||
L0019632 000000 001000 000000 000000 000000 100000 000000 000100*
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||||
L0019680 000000 000000 000000 000100 000000 100000 000000 000000*
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||||
L0019680 000000 000000 000000 000000 000000 100000 000000 000000*
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||||
L0019728 000000 000000 000000 000000 000000 000000 000000 000000*
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||||
L0019776 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0019824 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
@ -446,12 +446,12 @@ L0020320 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001
|
||||
L0020384 00000000 00000000 00000010 00000000 00000000 00000011 00000000 00000010*
|
||||
L0020448 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0020496 000000 000000 000000 000000 000000 000000 000000 000000*
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||||
L0020544 000000 000000 000000 000000 000001 000000 000000 000100*
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||||
L0020544 000000 000000 000000 000100 000001 000000 000000 000100*
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||||
L0020592 000000 000000 000000 000000 000001 000000 000000 000100*
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||||
L0020640 000000 000000 000000 000000 000001 000000 000000 000000*
|
||||
L0020688 000000 000000 000000 000000 000001 000000 000000 000000*
|
||||
L0020736 00000000 00000000 00000000 00000000 00000000 00000000 00000011 00000010*
|
||||
L0020800 00000000 00000000 00000000 00001000 00000000 00000000 00000000 00000010*
|
||||
L0020800 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000010*
|
||||
L0020864 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0020928 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0020992 00000000 00000000 00000000 00000000 00000000 00000000 00001000 00000001*
|
||||
@ -466,7 +466,7 @@ L0021456 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0021504 000000 000000 000000 000000 000000 000000 000000 100000*
|
||||
L0021552 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0021600 00000000 00000000 10000001 00000000 00000000 00001010 00000000 00000000*
|
||||
L0021664 00000000 00000000 00000000 00000000 00000000 00001000 00000011 00000010*
|
||||
L0021664 00000000 00000000 00000000 00001000 00000000 00001000 00000011 00000010*
|
||||
L0021728 00000000 00000000 00000000 00000000 00000000 00001000 00000000 00000010*
|
||||
L0021792 00000000 00000000 00000000 00000000 00000000 00001000 00000000 00000000*
|
||||
L0021856 00000000 00000000 00000000 00000000 10000000 00000000 00000000 00000000*
|
||||
@ -1020,7 +1020,7 @@ L0053376 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0053424 000000 000000 000000 010000 000000 000000 000000 100000*
|
||||
L0053472 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0053520 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0053568 00000010 00000000 00000010 00001010 00000001 00000000 00000000 00000000*
|
||||
L0053568 00000010 00000000 00000010 00000010 00000001 00000000 00000000 00000000*
|
||||
L0053632 00000000 00000010 00000001 00000000 00000001 00000010 00000001 00000010*
|
||||
L0053696 00000000 00000010 00000001 00000010 00000000 00000010 00000011 00000000*
|
||||
L0053760 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
@ -1035,7 +1035,7 @@ L0054240 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0054288 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0054336 000000 000000 000000 000000 000001 000000 000000 000000*
|
||||
L0054384 000000 000000 000000 000000 000001 000000 000000 000000*
|
||||
L0054432 00000000 00000001 00000010 00000010 00000001 00000000 00000001 00000011*
|
||||
L0054432 00000000 00000001 00000010 00001010 00000001 00000000 00000001 00000011*
|
||||
L0054496 00000000 00000001 00000000 00000010 00000001 00000001 00000011 00000001*
|
||||
L0054560 00000001 00000000 00000000 00000010 00000000 00000011 00000010 00000011*
|
||||
L0054624 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
@ -1240,7 +1240,7 @@ L0066048 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
L0066112 00000000 00000000 00000000 00000000 00000000 00000000 00001000 00000000*
|
||||
L0066176 00000000 00000000 00000000 00000000 00000000 00000000 00001000 00000000*
|
||||
L0066240 000000 000000 000000 000000 000000 000000 000010 000000*
|
||||
L0066288 000000 000000 000000 000100 000000 000000 000000 000000*
|
||||
L0066288 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0066336 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0066384 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0066432 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
@ -1255,7 +1255,7 @@ L0066912 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
L0066976 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0067040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0067104 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0067152 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0067152 000000 000000 000000 000100 000000 000000 000000 000000*
|
||||
L0067200 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0067248 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0067296 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
@ -1710,5 +1710,5 @@ L0093120 000000 000000 000000 000000 000000 000010 010000 000000*
|
||||
L0093168 000000 000000 000000 000000 000001 000000 000000 000000*
|
||||
L0093216 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0093264 000000 000000 000001 000000 000001 000000 000000 000000*
|
||||
C4AF6*
|
||||
29E6
|
||||
C49F6*
|
||||
29DC
|
||||
|
||||
@ -671,8 +671,8 @@ INPUTS | 4 | nPOR | SlowTimeout<2> | set/SetWRr | A_FSB<10>
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INPUTMC | 3 | 0 | 17 | 3 | 12 | 6 | 3
|
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INPUTP | 1 | 13
|
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EQ | 3 |
|
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!SlowTimeout<2>.D = !A_FSB<10> & nPOR & set/SetWRr
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# nPOR & !SlowTimeout<2> & !set/SetWRr;
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SlowTimeout<2>.D = A_FSB<10> & nPOR & set/SetWRr
|
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# nPOR & SlowTimeout<2> & !set/SetWRr;
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SlowTimeout<2>.CLK = FCLK; // GCK
|
||||
GLOBALS | 1 | 2 | FCLK
|
||||
|
||||
@ -683,8 +683,8 @@ INPUTS | 4 | nPOR | SlowTimeout<3> | set/SetWRr | A_FSB<11>
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INPUTMC | 3 | 0 | 17 | 3 | 11 | 6 | 3
|
||||
INPUTP | 1 | 15
|
||||
EQ | 3 |
|
||||
!SlowTimeout<3>.D = !A_FSB<11> & nPOR & set/SetWRr
|
||||
# nPOR & !SlowTimeout<3> & !set/SetWRr;
|
||||
SlowTimeout<3>.D = A_FSB<11> & nPOR & set/SetWRr
|
||||
# nPOR & SlowTimeout<3> & !set/SetWRr;
|
||||
SlowTimeout<3>.CLK = FCLK; // GCK
|
||||
GLOBALS | 1 | 2 | FCLK
|
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|
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File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
@ -1,7 +1,7 @@
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Release 8.1i - Fit P.20131013
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Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
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10-12-2024 2:07AM
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10-12-2024 2:10AM
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NOTE: This file is designed to be imported into a spreadsheet program
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such as Microsoft Excel for viewing, printing and sorting. The pipe '|'
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@ -1,7 +1,7 @@
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|
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cpldfit: version P.20131013 Xilinx Inc.
|
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Fitter Report
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Design Name: WarpSE Date: 10-12-2024, 2:07AM
|
||||
Design Name: WarpSE Date: 10-12-2024, 2:10AM
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Device Used: XC95144XL-10-TQ100
|
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Fitting Status: Successful
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@ -1014,12 +1014,12 @@ SlowTimeout_D(1) <= ((nPOR AND NOT SlowTimeout(1) AND NOT set/SetWRr)
|
||||
OR (nPOR AND NOT A_FSB(9) AND set/SetWRr));
|
||||
|
||||
FDCPE_SlowTimeout2: FDCPE port map (SlowTimeout(2),SlowTimeout_D(2),FCLK,'0','0');
|
||||
SlowTimeout_D(2) <= ((NOT A_FSB(10) AND nPOR AND set/SetWRr)
|
||||
OR (nPOR AND NOT SlowTimeout(2) AND NOT set/SetWRr));
|
||||
SlowTimeout_D(2) <= ((A_FSB(10) AND nPOR AND set/SetWRr)
|
||||
OR (nPOR AND SlowTimeout(2) AND NOT set/SetWRr));
|
||||
|
||||
FDCPE_SlowTimeout3: FDCPE port map (SlowTimeout(3),SlowTimeout_D(3),FCLK,'0','0');
|
||||
SlowTimeout_D(3) <= ((NOT A_FSB(11) AND nPOR AND set/SetWRr)
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||||
OR (nPOR AND NOT SlowTimeout(3) AND NOT set/SetWRr));
|
||||
SlowTimeout_D(3) <= ((A_FSB(11) AND nPOR AND set/SetWRr)
|
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OR (nPOR AND SlowTimeout(3) AND NOT set/SetWRr));
|
||||
|
||||
FDCPE_SlowVIA: FDCPE port map (SlowVIA,SlowVIA_D,FCLK,'0','0');
|
||||
SlowVIA_D <= ((nPOR AND NOT SlowVIA AND NOT set/SetWRr)
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||||
|
||||
@ -4,13 +4,13 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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||||
|
||||
|
||||
Total REAL time to Xst completion: 0.00 secs
|
||||
Total CPU time to Xst completion: 0.08 secs
|
||||
Total CPU time to Xst completion: 0.09 secs
|
||||
|
||||
--> Parameter xsthdpdir set to xst
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||||
|
||||
|
||||
Total REAL time to Xst completion: 0.00 secs
|
||||
Total CPU time to Xst completion: 0.08 secs
|
||||
Total CPU time to Xst completion: 0.09 secs
|
||||
|
||||
--> Reading design: WarpSE.prj
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|
||||
@ -446,15 +446,15 @@ Design Statistics
|
||||
# IOs : 80
|
||||
|
||||
Cell Usage :
|
||||
# BELS : 688
|
||||
# AND2 : 212
|
||||
# BELS : 686
|
||||
# AND2 : 214
|
||||
# AND3 : 26
|
||||
# AND4 : 13
|
||||
# AND5 : 3
|
||||
# AND8 : 2
|
||||
# GND : 7
|
||||
# INV : 275
|
||||
# OR2 : 113
|
||||
# INV : 273
|
||||
# OR2 : 111
|
||||
# OR3 : 10
|
||||
# OR4 : 4
|
||||
# OR5 : 1
|
||||
@ -474,11 +474,11 @@ Cell Usage :
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 5.00 secs
|
||||
Total CPU time to Xst completion: 4.99 secs
|
||||
Total CPU time to Xst completion: 5.24 secs
|
||||
|
||||
-->
|
||||
|
||||
Total memory usage is 263008 kilobytes
|
||||
Total memory usage is 263200 kilobytes
|
||||
|
||||
Number of errors : 0 ( 0 filtered)
|
||||
Number of warnings : 3 ( 0 filtered)
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
Binary file not shown.
@ -3,7 +3,7 @@
|
||||
|
||||
cpldfit: version P.20131013 Xilinx Inc.
|
||||
Fitter Report
|
||||
Design Name: WarpSE Date: 10-12-2024, 2:07AM
|
||||
Design Name: WarpSE Date: 10-12-2024, 2:10AM
|
||||
Device Used: XC95144XL-10-TQ100
|
||||
Fitting Status: Successful
|
||||
|
||||
@ -1016,12 +1016,12 @@ SlowTimeout_D(1) <= ((nPOR AND NOT SlowTimeout(1) AND NOT set/SetWRr)
|
||||
OR (nPOR AND NOT A_FSB(9) AND set/SetWRr));
|
||||
|
||||
FDCPE_SlowTimeout2: FDCPE port map (SlowTimeout(2),SlowTimeout_D(2),FCLK,'0','0');
|
||||
SlowTimeout_D(2) <= ((NOT A_FSB(10) AND nPOR AND set/SetWRr)
|
||||
OR (nPOR AND NOT SlowTimeout(2) AND NOT set/SetWRr));
|
||||
SlowTimeout_D(2) <= ((A_FSB(10) AND nPOR AND set/SetWRr)
|
||||
OR (nPOR AND SlowTimeout(2) AND NOT set/SetWRr));
|
||||
|
||||
FDCPE_SlowTimeout3: FDCPE port map (SlowTimeout(3),SlowTimeout_D(3),FCLK,'0','0');
|
||||
SlowTimeout_D(3) <= ((NOT A_FSB(11) AND nPOR AND set/SetWRr)
|
||||
OR (nPOR AND NOT SlowTimeout(3) AND NOT set/SetWRr));
|
||||
SlowTimeout_D(3) <= ((A_FSB(11) AND nPOR AND set/SetWRr)
|
||||
OR (nPOR AND SlowTimeout(3) AND NOT set/SetWRr));
|
||||
|
||||
FDCPE_SlowVIA: FDCPE port map (SlowVIA,SlowVIA_D,FCLK,'0','0');
|
||||
SlowVIA_D <= ((nPOR AND NOT SlowVIA AND NOT set/SetWRr)
|
||||
|
||||
@ -250,12 +250,12 @@ FDCPE_SlowTimeout1: FDCPE port map (SlowTimeout(1),SlowTimeout_D(1),FCLK,'0','0'
|
||||
<br/> OR (nPOR AND NOT A_FSB(9) AND set/SetWRr));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_SlowTimeout2: FDCPE port map (SlowTimeout(2),SlowTimeout_D(2),FCLK,'0','0');
|
||||
<br/> SlowTimeout_D(2) <= ((NOT A_FSB(10) AND nPOR AND set/SetWRr)
|
||||
<br/> OR (nPOR AND NOT SlowTimeout(2) AND NOT set/SetWRr));
|
||||
<br/> SlowTimeout_D(2) <= ((A_FSB(10) AND nPOR AND set/SetWRr)
|
||||
<br/> OR (nPOR AND SlowTimeout(2) AND NOT set/SetWRr));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_SlowTimeout3: FDCPE port map (SlowTimeout(3),SlowTimeout_D(3),FCLK,'0','0');
|
||||
<br/> SlowTimeout_D(3) <= ((NOT A_FSB(11) AND nPOR AND set/SetWRr)
|
||||
<br/> OR (nPOR AND NOT SlowTimeout(3) AND NOT set/SetWRr));
|
||||
<br/> SlowTimeout_D(3) <= ((A_FSB(11) AND nPOR AND set/SetWRr)
|
||||
<br/> OR (nPOR AND SlowTimeout(3) AND NOT set/SetWRr));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_SlowVIA: FDCPE port map (SlowVIA,SlowVIA_D,FCLK,'0','0');
|
||||
<br/> SlowVIA_D <= ((nPOR AND NOT SlowVIA AND NOT set/SetWRr)
|
||||
|
||||
@ -4,7 +4,7 @@
|
||||
var design = "WarpSE";
|
||||
var device = "XC95144XL";
|
||||
signals = new Array("ALE0M","ALE0S","ASrf","BACTr","GA22_SPECSIG","GA23_SPECSIG","IOACT","IODONE","IOL0","IONPReady","IOREQ","IORW","IOU0","MCKE","QoSEN","RA0_SPECSIG","RA10_SPECSIG","RA11_SPECSIG","RA1_SPECSIG","RA2_SPECSIG","RA3_SPECSIG","RA4_SPECSIG","RA5_SPECSIG","RA6_SPECSIG","RA7_SPECSIG","RA8_SPECSIG","RA9_SPECSIG","RAMReady","RefReq","RefUrg","RnW_IOB","SlowClockGate","SlowIACK","SlowIWM","SlowSCC","SlowSCSI","SlowSnd","SlowTimeout0_SPECSIG","SlowTimeout1_SPECSIG","SlowTimeout2_SPECSIG","SlowTimeout3_SPECSIG","SlowVIA","cntC8Mr0_SPECSIG","cntC8Mr1_SPECSIG","cntC8Mr2_SPECSIG","cntC8Mr3_SPECSIG","cntEr0_SPECSIG","cntEr1_SPECSIG","cntIS0_SPECSIG","cntIS1_SPECSIG","cntLTimer0_SPECSIG","cntLTimer10_SPECSIG","cntLTimer11_SPECSIG","cntLTimer1_SPECSIG","cntLTimer2_SPECSIG","cntLTimer3_SPECSIG","cntLTimer4_SPECSIG","cntLTimer5_SPECSIG","cntLTimer6_SPECSIG","cntLTimer7_SPECSIG","cntLTimer8_SPECSIG","cntLTimer9_SPECSIG","cntLTimerTick_SPECSIG","cntQS0_SPECSIG","cntQS1_SPECSIG","cntQS2_SPECSIG","cntQS3_SPECSIG","cntQoSCSr_SPECSIG","cntTimer0_SPECSIG","cntTimer1_SPECSIG","cntTimer2_SPECSIG","cntTimer3_SPECSIG","cntTimerTick_SPECSIG","csOverlay_SPECSIG","iobmC8Mr_SPECSIG","iobmDoutOE_SPECSIG","iobmES0_SPECSIG","iobmES1_SPECSIG","iobmES2_SPECSIG","iobmES3_SPECSIG","iobmEr_SPECSIG","iobmIOREQr_SPECSIG","iobmIOS_FSM_FFd1_SPECSIG","iobmIOS_FSM_FFd2_SPECSIG","iobmIOS_FSM_FFd3_SPECSIG","iobmIOS_FSM_FFd4_SPECSIG","iobmIOS_FSM_FFd5_SPECSIG","iobmIOS_FSM_FFd6_SPECSIG","iobmIOS_FSM_FFd7_SPECSIG","iobmVPAr_SPECSIG","iobsClear1_SPECSIG","iobsIOACTr_SPECSIG","iobsIODONEr0_SPECSIG","iobsIODONEr1_SPECSIG","iobsIODONErf_SPECSIG","iobsIOL1_SPECSIG","iobsIORW1_SPECSIG","iobsIOU1_SPECSIG","iobsLoad1_SPECSIG","iobsSent_SPECSIG","iobsTS_FSM_FFd1_SPECSIG","iobsTS_FSM_FFd2_SPECSIG","nADoutLE0","nADoutLE1","nAS_IOB","nAoutOE","nBERR_FSB","nBR_IOB","nBR_IOBout","nCAS","nDTACK_FSB","nDinLE","nDinOE","nDoutOE","nLDS_IOB","nOE","nPOR","nRAMLWE","nRAMUWE","nRAS","nRES","nRESout","nROMOE","nROMWE","nUDS_IOB","nVMA_IOB","nVPA_FSB","ramCASEndEN_SPECSIG","ramRASEL_SPECSIG","ramRASEN_SPECSIG","ramRASrf_SPECSIG","ramRS0_SPECSIG","ramRS1_SPECSIG","ramRS2_SPECSIG","ramRefCAS_SPECSIG","ramRefDone_SPECSIG","setSetWRr_SPECSIG");
|
||||
sigNegs = new Array("ON","OFF","OFF","ON","OFF","OFF","ON","OFF","OFF","ON","ON","OFF","OFF","ON","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","OFF","OFF","ON","OFF","ON","OFF","OFF","ON","ON","ON","ON","ON","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","ON","OFF","ON","OFF","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","ON","OFF","OFF","OFF","OFF","OFF","OFF","ON","OFF","OFF","OFF","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","OFF","ON","OFF","ON","OFF","OFF","OFF","ON","OFF","ON","ON","ON","OFF","ON","OFF","ON","ON","ON","OFF","OFF","ON","ON","OFF","OFF","ON","OFF","OFF","OFF","OFF","OFF","ON","OFF","OFF","OFF","OFF");
|
||||
sigNegs = new Array("ON","OFF","OFF","ON","OFF","OFF","ON","OFF","OFF","ON","ON","OFF","OFF","ON","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","OFF","OFF","ON","OFF","ON","OFF","OFF","ON","ON","ON","OFF","OFF","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","ON","OFF","ON","OFF","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","ON","OFF","OFF","OFF","OFF","OFF","OFF","ON","OFF","OFF","OFF","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","OFF","ON","OFF","ON","OFF","OFF","OFF","ON","OFF","ON","ON","ON","OFF","ON","OFF","ON","ON","ON","OFF","OFF","ON","ON","OFF","OFF","ON","OFF","OFF","OFF","OFF","OFF","ON","OFF","OFF","OFF","OFF");
|
||||
sigTypes = new Array("D","D","D","D","","","D","D","D","D","D","D","D","D","D","","","","","","","","","","","","","D","D","D","T","D","D","D","D","D","D","D","D","D","D","D","D","D","D","D","D","D","T","D","T","T","T","T","T","T","T","T","T","T","T","T","D","D","D","T","D","D","T","T","T","T","D","T","D","D","T","D","T","T","D","D","D","D","D","D","D","D","D","D","D","D","D","D","D","D","T","D","D","T","D","D","","D","D","D","T","","D","D","D","D","","","D","D","T","","","","","D","","","D","T","D","D","D","D","D","D","T","T","D","D","D");
|
||||
|
||||
|
||||
@ -460,13 +460,13 @@
|
||||
|
||||
pterms["FB4_11_2"]=new Array("nAS_FSB");
|
||||
|
||||
pterms["FB4_12_1"]=new Array("/A_FSB11_SPECSIG","nPOR","setSetWRr_SPECSIG");
|
||||
pterms["FB4_12_1"]=new Array("A_FSB11_SPECSIG","nPOR","setSetWRr_SPECSIG");
|
||||
|
||||
pterms["FB4_12_2"]=new Array("nPOR","/SlowTimeout3_SPECSIG","/setSetWRr_SPECSIG");
|
||||
pterms["FB4_12_2"]=new Array("nPOR","SlowTimeout3_SPECSIG","/setSetWRr_SPECSIG");
|
||||
|
||||
pterms["FB4_13_1"]=new Array("/A_FSB10_SPECSIG","nPOR","setSetWRr_SPECSIG");
|
||||
pterms["FB4_13_1"]=new Array("A_FSB10_SPECSIG","nPOR","setSetWRr_SPECSIG");
|
||||
|
||||
pterms["FB4_13_2"]=new Array("nPOR","/SlowTimeout2_SPECSIG","/setSetWRr_SPECSIG");
|
||||
pterms["FB4_13_2"]=new Array("nPOR","SlowTimeout2_SPECSIG","/setSetWRr_SPECSIG");
|
||||
|
||||
pterms["FB4_14_1"]=new Array("/cntTimer1_SPECSIG","/cntTimer2_SPECSIG","cntTimer3_SPECSIG");
|
||||
|
||||
|
||||
@ -30,7 +30,7 @@
|
||||
<tr>
|
||||
<td width="40%"> <b>Date</b>
|
||||
</td>
|
||||
<td width="60%"> 10-12-2024, 2:07AM</td>
|
||||
<td width="60%"> 10-12-2024, 2:10AM</td>
|
||||
</tr>
|
||||
</table></span><br><span id="sumres" class="pgRef"><h5 align="center">RESOURCES SUMMARY</h5>
|
||||
<table align="center" width="90%" border="1" cellspacing="0" cellpadding="0">
|
||||
|
||||
@ -27,7 +27,7 @@
|
||||
<TD WIDTH="65%" CLASS="cpldta_text_normal"><A HREF="Javascript:popWin('http://www.xilinx.com/literature/index.htm','800','800','test');">XC95144XL</A>, -10 (3.0)</TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD WIDTH="35%" CLASS="cpldta_text_normal_bold"><B>Date Created</B></TD> <TD WIDTH="65%" CLASS="cpldta_text_normal">Sat Oct 12 02:07:42 2024
|
||||
<TD WIDTH="35%" CLASS="cpldta_text_normal_bold"><B>Date Created</B></TD> <TD WIDTH="65%" CLASS="cpldta_text_normal">Sat Oct 12 02:11:04 2024
|
||||
</TD>
|
||||
</TR>
|
||||
<TR>
|
||||
@ -3882,7 +3882,7 @@ function AUTO_TS_F2P_BACTr_Q_to_nDinOE() {
|
||||
<SPAN CLASS="cpldta_text_normal">809</SPAN>
|
||||
<BR><SPAN CLASS="cpldta_text_normal_bold"><B>Number of Timing errors:</B></SPAN>
|
||||
<SPAN CLASS="cpldta_text_normal">809</SPAN>
|
||||
<BR><SPAN CLASS="cpldta_text_normal_bold"><B>Analysis Completed:</B></SPAN> <SPAN CLASS="cpldta_text_normal">Sat Oct 12 02:07:42 2024
|
||||
<BR><SPAN CLASS="cpldta_text_normal_bold"><B>Analysis Completed:</B></SPAN> <SPAN CLASS="cpldta_text_normal">Sat Oct 12 02:11:04 2024
|
||||
</SPAN>
|
||||
<HR>
|
||||
</HTML>
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="NgdBuild" timeStamp="Sat Oct 12 02:07:20 2024">
|
||||
<application stringID="NgdBuild" timeStamp="Sat Oct 12 02:10:49 2024">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
@ -66,7 +66,7 @@
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="212"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="214"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="26"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="13"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND5" value="3"/>
|
||||
@ -76,24 +76,24 @@
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDP" value="4"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="7"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="35"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="275"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="273"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="31"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="113"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="111"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="10"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="4"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR5" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="21"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="212"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="214"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="26"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="13"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND5" value="3"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="72"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="43"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="275"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="273"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="31"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="113"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="111"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="10"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="4"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR5" value="1"/>
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
Release 8.1i - Fit P.20131013
|
||||
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
|
||||
|
||||
10-12-2024 2:07AM
|
||||
10-12-2024 2:10AM
|
||||
|
||||
NOTE: This file is designed to be imported into a spreadsheet program
|
||||
such as Microsoft Excel for viewing, printing and sorting. The comma ','
|
||||
|
||||
|
@ -2,7 +2,7 @@
|
||||
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
|
||||
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>WarpSE Project Status (10/12/2024 - 02:07:54)</B></TD></TR>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>WarpSE Project Status (10/12/2024 - 02:11:15)</B></TD></TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
|
||||
<TD>WarpSE.xise</TD>
|
||||
@ -65,9 +65,9 @@ System Settings</A>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
|
||||
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
|
||||
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\WarpSE.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sat Oct 12 02:07:15 2024</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\_xmsgs/xst.xmsgs?&DataKey=Warning'>3 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\WarpSE.bld'>Translation Report</A></TD><TD>Current</TD><TD>Sat Oct 12 02:07:21 2024</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\WarpSE.rpt'>CPLD Fitter Report (Text)</A></TD><TD>Current</TD><TD>Sat Oct 12 02:07:34 2024</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Warning'>8 Warnings (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\WarpSE.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sat Oct 12 02:10:43 2024</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\_xmsgs/xst.xmsgs?&DataKey=Warning'>3 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\WarpSE.bld'>Translation Report</A></TD><TD>Current</TD><TD>Sat Oct 12 02:10:49 2024</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\WarpSE.rpt'>CPLD Fitter Report (Text)</A></TD><TD>Current</TD><TD>Sat Oct 12 02:10:56 2024</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Warning'>8 Warnings (8 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
</TABLE>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
@ -77,5 +77,5 @@ System Settings</A>
|
||||
</TABLE>
|
||||
|
||||
|
||||
<br><center><b>Date Generated:</b> 10/12/2024 - 02:07:54</center>
|
||||
<br><center><b>Date Generated:</b> 10/12/2024 - 02:11:15</center>
|
||||
</BODY></HTML>
|
||||
@ -5,7 +5,7 @@
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="Xst" timeStamp="Sat Oct 12 02:07:10 2024">
|
||||
<application stringID="Xst" timeStamp="Sat Oct 12 02:10:38 2024">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
@ -118,13 +118,13 @@
|
||||
<item stringID="XST_IOS" value="80"/>
|
||||
</section>
|
||||
<section stringID="XST_CELL_USAGE">
|
||||
<item dataType="int" stringID="XST_BELS" value="688">
|
||||
<item dataType="int" stringID="XST_AND2" value="212"/>
|
||||
<item dataType="int" stringID="XST_BELS" value="686">
|
||||
<item dataType="int" stringID="XST_AND2" value="214"/>
|
||||
<item dataType="int" stringID="XST_AND3" value="26"/>
|
||||
<item dataType="int" stringID="XST_AND4" value="13"/>
|
||||
<item dataType="int" stringID="XST_GND" value="7"/>
|
||||
<item dataType="int" stringID="XST_INV" value="275"/>
|
||||
<item dataType="int" stringID="XST_OR2" value="113"/>
|
||||
<item dataType="int" stringID="XST_INV" value="273"/>
|
||||
<item dataType="int" stringID="XST_OR2" value="111"/>
|
||||
<item dataType="int" stringID="XST_XOR2" value="21"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="113">
|
||||
|
||||
@ -1,2 +1,2 @@
|
||||
C:\Users\GWolf\Documents\GitHub\WarpSE\cpld\XC95144XL\WarpSE.ngc 1728713235
|
||||
C:\Users\GWolf\Documents\GitHub\WarpSE\cpld\XC95144XL\WarpSE.ngc 1728713443
|
||||
OK
|
||||
|
||||
@ -17,25 +17,25 @@
|
||||
<msg type="info" file="Cpld" num="0" delta="new" >Inferring BUFG constraint for signal '<arg fmt="%s" index="1">FCLK</arg>' based upon the LOC constraint '<arg fmt="%s" index="2">P27</arg>'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) '<arg fmt="%s" index="1">DBG<0></arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
|
||||
<msg type="warning" file="Cpld" num="1007" delta="new" >Removing unused input(s) '<arg fmt="%s" index="1">DBG<0></arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) '<arg fmt="%s" index="1">DBG<1></arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
|
||||
<msg type="warning" file="Cpld" num="1007" delta="new" >Removing unused input(s) '<arg fmt="%s" index="1">DBG<1></arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) '<arg fmt="%s" index="1">DBG<2></arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
|
||||
<msg type="warning" file="Cpld" num="1007" delta="new" >Removing unused input(s) '<arg fmt="%s" index="1">DBG<2></arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) '<arg fmt="%s" index="1">DBG<3></arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
|
||||
<msg type="warning" file="Cpld" num="1007" delta="new" >Removing unused input(s) '<arg fmt="%s" index="1">DBG<3></arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) '<arg fmt="%s" index="1">DBG<4></arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
|
||||
<msg type="warning" file="Cpld" num="1007" delta="new" >Removing unused input(s) '<arg fmt="%s" index="1">DBG<4></arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) '<arg fmt="%s" index="1">DBG<5></arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
|
||||
<msg type="warning" file="Cpld" num="1007" delta="new" >Removing unused input(s) '<arg fmt="%s" index="1">DBG<5></arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) '<arg fmt="%s" index="1">nBG_IOB</arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
|
||||
<msg type="warning" file="Cpld" num="1007" delta="new" >Removing unused input(s) '<arg fmt="%s" index="1">nBG_IOB</arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
@ -8,29 +8,8 @@
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<messages>
|
||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/CNT.v" into library work</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/CS.v" into library work</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/FSB.v" into library work</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/IOBM.v" into library work</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/IOBS.v" into library work</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/RAM.v" into library work</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/SET.v" into library work</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/WarpSE.v" into library work</arg>
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
<?xml version='1.0' encoding='UTF-8'?>
|
||||
<report-views version="2.0" >
|
||||
<header>
|
||||
<DateModified>2024-10-12T02:06:47</DateModified>
|
||||
<DateModified>2024-10-12T02:09:53</DateModified>
|
||||
<ModuleName>WarpSE</ModuleName>
|
||||
<SummaryTimeStamp>2024-10-09T06:57:43</SummaryTimeStamp>
|
||||
<SavedFilePath>C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL/iseconfig/WarpSE.xreport</SavedFilePath>
|
||||
|
||||
@ -17,7 +17,7 @@
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Project ID (random number)</B></TD>
|
||||
<TD><xtag-property name="RandomID">b3a7c111c3094ca7bbfba225dd37199f</xtag-property>.<xtag-property name="ProjectID">119c0faaf8624ebdb39ffc10b2fb6fa0</xtag-property>.<xtag-property name="ProjectIteration">1</xtag-property></TD>
|
||||
<TD><xtag-property name="RandomID">b3a7c111c3094ca7bbfba225dd37199f</xtag-property>.<xtag-property name="ProjectID">b3daaca9c5c148c68c747c3e1b540ea0</xtag-property>.<xtag-property name="ProjectIteration">1</xtag-property></TD>
|
||||
<TD BGCOLOR='#FFFF99'><B>Target Package:</B></TD>
|
||||
<TD><xtag-property name="TargetPackage"></xtag-property></TD>
|
||||
</TR>
|
||||
@ -29,7 +29,7 @@
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Date Generated</B></TD>
|
||||
<TD><xtag-property name="Date Generated">2024-10-12T02:09:21</xtag-property></TD>
|
||||
<TD><xtag-property name="Date Generated">2024-10-12T02:12:57</xtag-property></TD>
|
||||
<TD BGCOLOR='#FFFF99'><B>Tool Flow</B></TD>
|
||||
<TD><xtag-property name="ToolFlow">IMPACT</xtag-property></TD>
|
||||
</TR>
|
||||
|
||||
@ -3,7 +3,7 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Project Information
|
||||
--------------------
|
||||
ProjectID=123f7a0f7db94b19a1f73f2dd0bc5f32
|
||||
ProjectID=b3daaca9c5c148c68c747c3e1b540ea0
|
||||
ProjectIteration=1
|
||||
|
||||
WebTalk Summary
|
||||
|
||||
@ -3,9 +3,9 @@
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="impact" timeStamp="Sat Oct 12 02:09:21 2024">
|
||||
<application name="impact" timeStamp="Sat Oct 12 02:12:57 2024">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="119c0faaf8624ebdb39ffc10b2fb6fa0"/>
|
||||
<property name="ProjectID" value="b3daaca9c5c148c68c747c3e1b540ea0"/>
|
||||
<property name="ProjectIteration" value="1"/>
|
||||
</section>
|
||||
<section name="iMPACT Project Info" visible="true">
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pn" timeStamp="Sat Oct 12 02:07:09 2024">
|
||||
<application name="pn" timeStamp="Sat Oct 12 02:10:37 2024">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="B70E14F6F6B943E9BF9FD5113EA04D70" type="project"/>
|
||||
<property name="ProjectIteration" value="0" type="project"/>
|
||||
|
||||
Binary file not shown.
@ -1,8 +1,8 @@
|
||||
MO CNT NULL ../CNT.v vlg65/_c_n_t.bin 1728713230
|
||||
MO CS NULL ../CS.v vlg22/_c_s.bin 1728713230
|
||||
MO FSB NULL ../FSB.v vlg37/_f_s_b.bin 1728713230
|
||||
MO IOBM NULL ../IOBM.v vlg73/_i_o_b_m.bin 1728713230
|
||||
MO WarpSE NULL ../WarpSE.v vlg52/_warp_s_e.bin 1728713230
|
||||
MO IOBS NULL ../IOBS.v vlg79/_i_o_b_s.bin 1728713230
|
||||
MO RAM NULL ../RAM.v vlg14/_r_a_m.bin 1728713230
|
||||
MO SET NULL ../SET.v vlg48/_s_e_t.bin 1728713230
|
||||
MO CNT NULL ../CNT.v vlg65/_c_n_t.bin 1728713438
|
||||
MO CS NULL ../CS.v vlg22/_c_s.bin 1728713438
|
||||
MO FSB NULL ../FSB.v vlg37/_f_s_b.bin 1728713438
|
||||
MO IOBM NULL ../IOBM.v vlg73/_i_o_b_m.bin 1728713438
|
||||
MO WarpSE NULL ../WarpSE.v vlg52/_warp_s_e.bin 1728713438
|
||||
MO IOBS NULL ../IOBS.v vlg79/_i_o_b_s.bin 1728713438
|
||||
MO RAM NULL ../RAM.v vlg14/_r_a_m.bin 1728713438
|
||||
MO SET NULL ../SET.v vlg48/_s_e_t.bin 1728713438
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
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Loading…
x
Reference in New Issue
Block a user