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https://github.com/garrettsworkshop/Warp-SE.git
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151 lines
3.8 KiB
Verilog
151 lines
3.8 KiB
Verilog
module RAM(
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/* MC68HC000 interface */
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input CLK, input [21:1] A, input nWE, input nAS, input nLDS, input nUDS,
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/* AS cycle detection */
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input BACT,
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/* Select and ready signals */
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input RAMCS, input ROMCS, output Ready,
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/* Refresh Counter Interface */
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input RefReq, input RefUrgent, output RefAck,
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/* DRAM and NOR flash interface */
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output [11:0] RA, output nRAS, output reg nCAS,
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output nLWE, output nUWE, output nOE, output nROMCS, output nROMWE);
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/* RAM control state */
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reg [2:0] RS = 0;
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reg Once = 0;
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reg RAMReady = 0;
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reg RASEL = 0; // RASEL controls /CAS signal
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/* Refresh state */
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reg RAMDIS1 = 0;
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reg RAMDIS2 = 0;
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wire RAMDIS = RAMDIS1 || RAMDIS2;
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wire RAMEN = ~RAMDIS;
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reg RefRAS = 0;
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assign nROMCS = ~ROMCS;
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assign nRAS = ~((~nAS && RAMCS && RAMEN && ~RefRAS /* does this add loading to these P-terms? */) || RefRAS);
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assign nOE = ~(~nAS && nWE);
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assign nLWE = ~(~nAS && ~nWE && ~nLDS && RAMEN);
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assign nUWE = ~(~nAS && ~nWE && ~nUDS && RAMEN);
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assign nROMWE = ~(~nAS && ~nWE);
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assign RA[11] = A[19];
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assign RA[10] = A[21];
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assign RA[09] = RASEL ? A[20] : A[19];
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assign RA[08] = (RASEL && RAMCS) ? A[09] : A[18];
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assign RA[07] = RASEL ? A[08] : A[17];
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assign RA[06] = RASEL ? A[07] : A[16];
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assign RA[05] = RASEL ? A[06] : A[15];
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assign RA[04] = RASEL ? A[05] : A[14];
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assign RA[03] = RASEL ? A[04] : A[13];
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assign RA[02] = RASEL ? A[03] : A[12];
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assign RA[01] = RASEL ? A[02] : A[11];
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assign RA[00] = RASEL ? A[01] : A[10];
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always @(posedge CLK) begin
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if (~BACT) Once <= 0;
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else if (RS==0 && BACT && RAMCS) Once <= 1;
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end
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always @(posedge CLK) begin
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if (~BACT) RAMDIS2 <= 0;
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else if ((RS==0 && BACT && RefUrgent && Once && RAMCS) ||
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(RS==7 && BACT && RefUrgent && Once)) RAMDIS2 <= 1;
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end
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reg BACTr;
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always @(posedge CLK) begin BACTr <= BACT; end
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always @(posedge CLK) begin
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if (RS==0) begin
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if (( BACT && RefReq && ~RAMCS && ~BACTr) || // Non-urgent refresh can start during first clock of non-RAM cycle
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(~BACT && RefUrgent) || // Urgent refresh can start during bus idle
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( BACT && RefUrgent && ~RAMCS)) begin // Urgent refresh can start during non-ram cycle
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RS <= 2;
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RAMReady <= 0;
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RASEL <= 1;
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RAMDIS1 <= 1;
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end else if (BACT && RAMCS && ~Once) begin
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// RAM access cycle has priority over urgent refresh if RAM access already begun
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RS <= 5;
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RAMReady <= 0;
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RASEL <= 1;
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RAMDIS1 <= 0;
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end else if (BACT && RAMCS && RefUrgent) begin
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// Urgent refresh can start during prolonged RAM access cycle
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// But we must insert one extra precharge state first.
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RS <= 1;
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RAMReady <= 0;
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RASEL <= 0;
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RAMDIS1 <= 1;
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end else begin
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// No RAM access/refresh requests pending
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RS <= 0;
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RAMReady <= 1;
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RASEL <= 0;
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RAMDIS1 <= 0;
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end
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RefRAS <= 0;
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end else if (RS==1) begin
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RS <= 2;
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RAMReady <= 0;
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RASEL <= 1;
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RAMDIS1 <= 1;
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RefRAS <= 0;
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end else if (RS==2) begin
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RS <= 3;
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RAMReady <= 0;
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RASEL <= 1;
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RAMDIS1 <= 1;
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RefRAS <= 1;
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end else if (RS==3) begin
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RS <= 4;
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RAMReady <= 0;
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RASEL <= 0;
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RAMDIS1 <= 1;
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RefRAS <= 1;
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end else if (RS==4) begin
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RS <= 7;
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RAMReady <= 0;
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RASEL <= 0;
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RAMDIS1 <= 1;
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RefRAS <= 0;
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end else if (RS==5) begin
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RS <= 6;
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RAMReady <= 0;
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RASEL <= 1;
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RAMDIS1 <= 0;
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RefRAS <= 0;
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end else if (RS==6) begin
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RS <= 7;
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RAMReady <= 0;
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RASEL <= 0;
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RAMDIS1 <= 0;
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RefRAS <= 0;
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end else if (RS==7) begin
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if (~BACT && RefUrgent) begin
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RS <= 2;
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RAMReady <= 0;
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RAMDIS1 <= 1;
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RASEL <= 1;
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end else if (BACT && RefUrgent) begin
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RS <= 1;
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RAMReady <= 0;
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RASEL <= 0;
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RAMDIS1 <= 1;
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end else begin
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RS <= 0;
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RAMReady <= 1;
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RASEL <= 0;
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RAMDIS1 <= 0;
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end
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RefRAS <= 0;
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end
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end
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always @(negedge CLK) begin nCAS <= ~RASEL; end
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assign RefAck = RefRAS;
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assign Ready = ~RAMCS || RAMReady;
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endmodule
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