mirror of
https://github.com/garrettsworkshop/Warp-SE.git
synced 2024-09-30 10:54:36 +00:00
315 lines
6.8 KiB
Verilog
315 lines
6.8 KiB
Verilog
`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 07:47:59 12/11/2021
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// Design Name: RAM
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// Module Name: C:/Users/zanek/Documents/GitHub/Warp-SE/cpld/XC95144XL/t_ram.v
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// Project Name: MXSE
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// Target Device:
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// Tool versions:
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// Description:
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//
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// Verilog Test Fixture created by ISE for module: RAM
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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////////////////////////////////////////////////////////////////////////////////
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module t_ram;
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// Inputs
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reg CLK;
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reg [21:1] A;
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reg nWE;
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reg nAS;
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reg nLDS;
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reg nUDS;
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reg BACT;
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reg RAMCS;
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reg ROMCS;
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reg RefReq;
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reg RefUrgent;
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// Outputs
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wire Ready;
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wire RefAck;
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wire [11:0] RA;
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wire nRAS;
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wire nCAS;
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wire nLWE;
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wire nUWE;
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wire nOE;
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wire nROMCS;
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wire nROMWE;
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// Instantiate the Unit Under Test (UUT)
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RAM uut (
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.CLK(CLK),
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.A(A),
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.nWE(nWE),
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.nAS(nAS),
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.nLDS(nLDS),
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.nUDS(nUDS),
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.BACT(BACT),
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.RAMCS(RAMCS),
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.ROMCS(ROMCS),
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.Ready(Ready),
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.RefReq(RefReq),
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.RefUrgent(RefUrgent),
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.RefAck(RefAck),
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.RA(RA),
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.nRAS(nRAS),
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.nCAS(nCAS),
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.nLWE(nLWE),
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.nUWE(nUWE),
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.nOE(nOE),
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.nROMCS(nROMCS),
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.nROMWE(nROMWE)
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);
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initial begin
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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CLK = 0; #20; CLK = 1; #20; CLK = 0; #20; CLK = 1; #20;
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end
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initial begin
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nAS = 1;
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nLDS = 1;
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nUDS = 1;
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BACT = 0;
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#30;
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nAS = 0;
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nLDS = 0;
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nUDS = 0;
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BACT = 1;
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#20; #40; #40;
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nAS = 1;
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nLDS = 1;
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nUDS = 1;
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#20;
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BACT = 0;
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#40;
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nAS = 0;
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nLDS = 0;
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nUDS = 0;
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BACT = 1;
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#20; #40; #40;
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nAS = 1;
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nLDS = 1;
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nUDS = 1;
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#20;
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BACT = 0;
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#40;
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nAS = 0;
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BACT = 1;
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#40;
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nLDS = 0;
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nUDS = 0;
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#20; #40;
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nAS = 1;
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nLDS = 1;
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nUDS = 1;
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#20;
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BACT = 0;
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#40;
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nAS = 0;
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nLDS = 0;
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nUDS = 0;
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BACT = 1;
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#20; #40; #40;
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nAS = 1;
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nLDS = 1;
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nUDS = 1;
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#20;
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BACT = 0;
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#40;
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nAS = 0;
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BACT = 1;
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#40;
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nLDS = 0;
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nUDS = 0;
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#20; #40;
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nAS = 1;
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nLDS = 1;
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nUDS = 1;
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#20;
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BACT = 0;
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#40;
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nAS = 0;
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nLDS = 0;
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nUDS = 0;
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BACT = 1;
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#20; #40; #40;
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nAS = 1;
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nLDS = 1;
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nUDS = 1;
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#20;
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BACT = 0;
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#40;
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nAS = 0;
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nLDS = 0;
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nUDS = 0;
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BACT = 1;
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#20; #40; #40;
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nAS = 1;
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nLDS = 1;
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nUDS = 1;
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#20;
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BACT = 0;
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#40;
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#160;#160;#160;
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nAS = 0;
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nLDS = 0;
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nUDS = 0;
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BACT = 1;
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#20; #40; #40;
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nAS = 1;
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nLDS = 1;
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nUDS = 1;
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#20;
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BACT = 0;
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#40;
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end
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initial begin
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RefReq = 0;
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RefUrgent = 0;
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#10;
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#160; #160; #160;
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RefReq = 1;
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#160; #160; #160; #160;
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#120;
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RefReq = 0;
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#200; #120; #120;
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RefUrgent = 1;
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#120;
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RefUrgent = 0;
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#200;
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end
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initial begin
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#10;
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A = 0;
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RAMCS = 0;
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ROMCS = 0;
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nWE = 0;
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#160;
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A = 24'h400000;
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RAMCS = 0;
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ROMCS = 1;
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nWE = 1;
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#160;
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A = 24'h400000>>1;
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RAMCS = 0;
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ROMCS = 1;
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nWE = 0;
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#160;
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A = 24'h0A5A5A;
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RAMCS = 1;
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ROMCS = 0;
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nWE = 1;
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#160;
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A = 24'h0A5A5A;
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RAMCS = 1;
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ROMCS = 0;
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nWE = 0;
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#160;
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A = 24'h0A5A5A;
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RAMCS = 1;
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ROMCS = 0;
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nWE = 1;
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#160;
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A = 24'h400000;
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RAMCS = 0;
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ROMCS = 1;
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nWE = 1;
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#160;
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#160; #160; #160;
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A = 24'h0A5A5A;
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RAMCS = 1;
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ROMCS = 0;
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nWE = 1;
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#160;
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end
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endmodule
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