Macintosh-HW/Warp-SE
1
0
Fork 0
mirror of https://github.com/garrettsworkshop/Warp-SE.git synced 2024-11-03 10:05:12 +00:00
Code Issues Projects Releases Wiki Activity
5b659cc42a
Warp-SE/cpld/XC95144XL/MXSE.rpt
Zane Kaminski 5b659cc42a idk
2022-01-16 10:56:37 -05:00

1798 lines
95 KiB
Plaintext
Raw Blame History

This file contains invisible Unicode characters

This file contains invisible Unicode characters that are indistinguishable to humans but may be processed differently by a computer. If you think that this is intentional, you can safely ignore this warning. Use the Escape button to reveal them.

cpldfit: version P.20131013 Xilinx Inc.
Fitter Report
Design Name: MXSE Date: 12-11-2021, 6:24AM
Device Used: XC95144XL-10-TQ100
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
110/144 ( 76%) 439 /720 ( 61%) 244/432 ( 56%) 84 /144 ( 58%) 67 /81 ( 83%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 9/18 36/54 80/90 11/11*
FB2 18/18* 35/54 34/90 6/10
FB3 14/18 35/54 77/90 6/10
FB4 10/18 36/54 82/90 10/10*
FB5 17/18 35/54 47/90 4/10
FB6 18/18* 24/54 37/90 10/10*
FB7 17/18 35/54 76/90 10/10*
FB8 7/18 8/54 6/90 10/10*
----- ----- ----- -----
110/144 244/432 439/720 67/81
* - Resource is exhausted
** Global Control Resources **
Signal 'CLK2X_IOB' mapped onto global clock net GCK1.
Signal 'CLK_FSB' mapped onto global clock net GCK2.
Signal 'CLK_IOB' mapped onto global clock net GCK3.
Global output enable net(s) unused.
Signal 'nRES' mapped onto global set/reset net GSR.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 31 31 | I/O : 63 73
Output : 32 32 | GCK/IO : 3 3
Bidirectional : 0 0 | GTS/IO : 0 4
GCK : 3 3 | GSR/IO : 1 1
GTS : 0 0 |
GSR : 1 1 |
---- ----
Total 67 67
** Power Data **
There are 110 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************** Errors and Warnings ***************************
WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
use the default filename of 'MXSE.ise'.
************************* Summary of Mapped Logic ************************
** 32 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
nDTACK_FSB 23 32 FB1_2 11 I/O O STD FAST RESET
nBERR_FSB 3 9 FB1_6 14 I/O O STD FAST
nOE 1 2 FB1_11 17 I/O O STD FAST
nLDS_IOB 3 7 FB2_11 6 I/O O STD FAST RESET
nUDS_IOB 3 7 FB2_12 7 I/O O STD FAST RESET
nDoutOE 2 7 FB2_14 8 I/O O STD FAST RESET
nAS_IOB 1 5 FB2_17 10 I/O O STD FAST RESET
nRAS 3 8 FB3_5 24 I/O O STD FAST
nADoutLE1 2 3 FB3_11 29 I/O O STD FAST SET
nVMA_IOB 2 9 FB3_15 33 I/O O STD FAST RESET
RA<0> 2 3 FB4_2 87 I/O O STD FAST
RA<2> 2 3 FB4_8 91 I/O O STD FAST
RA<4> 2 3 FB4_12 94 I/O O STD FAST
nDinOE 2 6 FB4_17 97 I/O O STD FAST
RA<1> 2 3 FB5_2 35 I/O O STD FAST
RA<3> 2 3 FB5_8 39 I/O O STD FAST
nROMCS 2 5 FB5_12 42 I/O O STD FAST
nCAS 1 1 FB6_2 74 I/O O STD FAST RESET
nRAMLWE 1 5 FB6_6 77 I/O O STD FAST
nRAMUWE 1 5 FB6_9 79 I/O O STD FAST
nROMWE 1 2 FB6_12 81 I/O O STD FAST
nVPA_FSB 1 2 FB6_15 85 I/O O STD FAST
RA<5> 2 3 FB7_2 50 I/O O STD FAST
RA<6> 2 3 FB7_6 53 I/O O STD FAST
RA<7> 2 3 FB7_9 55 I/O O STD FAST
RA<8> 2 3 FB7_12 58 I/O O STD FAST
RA<9> 2 3 FB7_15 60 I/O O STD FAST
RA<11> 1 1 FB8_2 63 I/O O STD FAST
RA<10> 1 1 FB8_6 65 I/O O STD FAST
nADoutLE0 1 2 FB8_9 67 I/O O STD FAST
nAoutOE 0 0 FB8_12 70 I/O O STD FAST
nDinLE 1 2 FB8_15 72 I/O O STD FAST RESET
** 78 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
$OpTx$FX_DC$606 5 12 FB1_4 STD
fsb/Ready1r 7 17 FB1_7 STD RESET
fsb/VPA__or00001/fsb/VPA__or00001_D2 8 20 FB1_10 STD
fsb/Ready2r 9 22 FB1_12 STD RESET
fsb/VPA 22 30 FB1_15 STD RESET
$OpTx$FX_DC$602 2 5 FB1_17 STD
iobm/VPArr 1 1 FB2_1 STD RESET
iobm/VPArf 1 1 FB2_2 STD RESET
iobm/RESrr 1 1 FB2_3 STD RESET
iobm/RESrf 1 1 FB2_4 STD RESET
iobm/IOREQr 1 1 FB2_5 STD RESET
cnt/RefCnt<3> 1 3 FB2_6 STD RESET
cnt/RefCnt<2> 1 2 FB2_7 STD RESET
cnt/RefCnt<1> 1 1 FB2_8 STD RESET
fsb/BERR1r 2 4 FB2_9 STD RESET
cnt/RefDone 2 10 FB2_10 STD RESET
cnt/TimeoutBPre 3 11 FB2_13 STD RESET
TimeoutB 3 12 FB2_15 STD RESET
TimeoutA 3 10 FB2_16 STD RESET
iobs/IOReady 4 8 FB2_18 STD RESET
IORW0 18 20 FB3_3 STD RESET
iobs/IOACTr 1 1 FB3_4 STD RESET
iobs/Clear1 1 3 FB3_6 STD RESET
fsb/ASrf 1 1 FB3_7 STD RESET
ALE0S 1 2 FB3_8 STD RESET
iobs/PS_FSM_FFd2 14 19 FB3_9 STD RESET
iobs/PS_FSM_FFd1 2 3 FB3_12 STD RESET
IOREQ 14 19 FB3_13 STD RESET
iobm/ETACK 1 6 FB3_14 STD RESET
iobs/IORW1 16 19 FB3_17 STD RESET
ram/BACTr 1 2 FB3_18 STD RESET
ram/RASEL 20 15 FB4_1 STD RESET
cs/nOverlay1 2 3 FB4_3 STD RESET
iobs/Load1 14 18 FB4_6 STD RESET
iobs/Once 17 18 FB4_10 STD RESET
ram/RAMDIS1 18 15 FB4_14 STD RESET
fsb/BERR0r 3 8 FB4_16 STD RESET
IOACT 10 15 FB5_1 STD RESET
iobm/IOS_FSM_FFd7 1 3 FB5_3 STD RESET
iobm/IOS_FSM_FFd6 1 1 FB5_4 STD RESET
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
iobm/IOS_FSM_FFd5 1 1 FB5_5 STD RESET
iobm/IOS_FSM_FFd4 1 1 FB5_6 STD RESET
iobm/BERRrr 1 1 FB5_7 STD RESET
iobm/BERRrf 1 1 FB5_9 STD RESET
cnt/RefCnt<0> 0 0 FB5_10 STD RESET
iobm/IOS_FSM_FFd8 2 4 FB5_11 STD SET
ALE0M 2 7 FB5_13 STD RESET
iobm/IOS_FSM_FFd2 4 9 FB5_14 STD RESET
BERR_IOBS 4 8 FB5_15 STD RESET
iobm/IOS_FSM_FFd3 5 10 FB5_16 STD RESET
IOBERR 8 11 FB5_18 STD RESET
iobm/Er2 1 1 FB6_1 STD RESET
iobm/DTACKrr 1 1 FB6_3 STD RESET
iobm/DTACKrf 1 1 FB6_4 STD RESET
RefAck 1 2 FB6_5 STD RESET
iobs/IOU1 2 2 FB6_7 STD RESET
iobs/IOL1 2 2 FB6_8 STD RESET
iobm/ES<3> 3 6 FB6_10 STD RESET
iobm/ES<1> 3 4 FB6_11 STD RESET
iobm/ES<0> 3 7 FB6_13 STD RESET
IOU0 3 5 FB6_14 STD RESET
IOL0 3 5 FB6_16 STD RESET
iobm/ES<4> 4 7 FB6_17 STD RESET
iobm/ES<2> 5 7 FB6_18 STD RESET
cnt/RefCnt<5> 1 5 FB7_1 STD RESET
cnt/RefCnt<4> 1 4 FB7_3 STD RESET
cs/nOverlay0 2 7 FB7_4 STD RESET
ram/RS_FSM_FFd3 11 14 FB7_5 STD RESET
fsb/Ready0r 3 8 FB7_7 STD RESET
ram/RS_FSM_FFd1 5 10 FB7_8 STD RESET
ram/Once 5 10 FB7_10 STD RESET
ram/RAMDIS2 7 15 FB7_11 STD RESET
ram/RS_FSM_FFd2 13 14 FB7_13 STD RESET
cnt/RefCnt<7> 1 7 FB7_14 STD RESET
cnt/RefCnt<6> 1 6 FB7_16 STD RESET
ram/RAMReady 16 15 FB7_17 STD RESET
iobm/IOS_FSM_FFd1 1 1 FB8_17 STD RESET
iobm/Er 1 1 FB8_18 STD RESET
** 35 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
A_FSB<9> FB1_3 12 I/O I
nAS_FSB FB1_5 13 I/O I
A_FSB<5> FB1_8 15 I/O I
A_FSB<2> FB1_9 16 I/O I
nBERR_IOB FB1_12 18 I/O I
A_FSB<6> FB1_14 19 I/O I
A_FSB<7> FB1_15 20 I/O I
CLK2X_IOB FB1_17 22~ GCK/I/O GCK
nRES FB2_2 99~ GSR/I/O GSR/I
A_FSB<22> FB2_15 9 I/O I
CLK_FSB FB3_2 23~ GCK/I/O GCK
nLDS_FSB FB3_6 25 I/O I
CLK_IOB FB3_8 27~ GCK/I/O GCK/I
A_FSB<10> FB4_5 89 I/O I
A_FSB<1> FB4_6 90 I/O I
A_FSB<12> FB4_9 92 I/O I
A_FSB<14> FB4_11 93 I/O I
A_FSB<16> FB4_14 95 I/O I
A_FSB<17> FB4_15 96 I/O I
E_IOB FB5_17 49 I/O I
A_FSB<18> FB6_5 76 I/O I
A_FSB<3> FB6_8 78 I/O I
A_FSB<15> FB6_11 80 I/O I
A_FSB<13> FB6_14 82 I/O I
A_FSB<11> FB6_17 86 I/O I
nUDS_FSB FB7_5 52 I/O I
nDTACK_IOB FB7_8 54 I/O I
A_FSB<4> FB7_11 56 I/O I
nVPA_IOB FB7_14 59 I/O I
nWE_FSB FB7_17 61 I/O I
A_FSB<8> FB8_5 64 I/O I
A_FSB<23> FB8_8 66 I/O I
A_FSB<21> FB8_11 68 I/O I
A_FSB<20> FB8_14 71 I/O I
A_FSB<19> FB8_17 73 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 36/18
Number of signals used by logic mapping into function block: 36
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 \/5 0 FB1_1 (b) (b)
nDTACK_FSB 23 18<- 0 0 FB1_2 11 I/O O
(unused) 0 0 /\5 0 FB1_3 12 I/O I
$OpTx$FX_DC$606 5 3<- /\3 0 FB1_4 (b) (b)
(unused) 0 0 /\3 2 FB1_5 13 I/O I
nBERR_FSB 3 0 \/2 0 FB1_6 14 I/O O
fsb/Ready1r 7 2<- 0 0 FB1_7 (b) (b)
(unused) 0 0 0 5 FB1_8 15 I/O I
(unused) 0 0 \/3 2 FB1_9 16 I/O I
fsb/VPA__or00001/fsb/VPA__or00001_D2
8 3<- 0 0 FB1_10 (b) (b)
nOE 1 0 \/4 0 FB1_11 17 I/O O
fsb/Ready2r 9 4<- 0 0 FB1_12 18 I/O I
(unused) 0 0 \/5 0 FB1_13 (b) (b)
(unused) 0 0 \/5 0 FB1_14 19 I/O I
fsb/VPA 22 17<- 0 0 FB1_15 20 I/O I
(unused) 0 0 /\5 0 FB1_16 (b) (b)
$OpTx$FX_DC$602 2 0 /\2 1 FB1_17 22 GCK/I/O GCK
(unused) 0 0 \/5 0 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$FX_DC$602 13: A_FSB<20> 25: fsb/BERR1r
2: $OpTx$FX_DC$606 14: A_FSB<21> 26: fsb/Ready0r
3: A_FSB<10> 15: A_FSB<22> 27: fsb/Ready1r
4: A_FSB<11> 16: A_FSB<23> 28: fsb/Ready2r
5: A_FSB<12> 17: A_FSB<8> 29: fsb/VPA
6: A_FSB<13> 18: A_FSB<9> 30: fsb/VPA__or00001/fsb/VPA__or00001_D2
7: A_FSB<14> 19: BERR_IOBS 31: iobs/IOReady
8: A_FSB<15> 20: TimeoutA 32: nADoutLE1
9: A_FSB<16> 21: TimeoutB 33: nAS_FSB
10: A_FSB<17> 22: cs/nOverlay1 34: nDTACK_FSB
11: A_FSB<18> 23: fsb/ASrf 35: nWE_FSB
12: A_FSB<19> 24: fsb/BERR0r 36: ram/RAMReady
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
nDTACK_FSB X.XXXXXXXXXXXXXXXXXX.XXXXXXX..XXXXXX.... 32
$OpTx$FX_DC$606 .....XX.XXXXXXX......X.........X..X..... 12
nBERR_FSB ............XXXX..X.X..XX.......X....... 9
fsb/Ready1r .....XX.XXXXXXXX.....XX...X...XXX.X..... 17
fsb/VPA__or00001/fsb/VPA__or00001_D2
..XXXXXXXXXXXXXXXX.X.X.....X......X..... 20
nOE ................................X.X..... 2
fsb/Ready2r ..XXXXXXXXXXXXXXXX.X.XX....X....X.X..... 22
fsb/VPA XXXXXXXXXXXXXXXXXXX..XXXXXX.XXX.X..X.... 30
$OpTx$FX_DC$602 ............XXXX....X................... 5
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 35/19
Number of signals used by logic mapping into function block: 35
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
iobm/VPArr 1 0 0 4 FB2_1 (b) (b)
iobm/VPArf 1 0 0 4 FB2_2 99 GSR/I/O GSR/I
iobm/RESrr 1 0 0 4 FB2_3 (b) (b)
iobm/RESrf 1 0 0 4 FB2_4 (b) (b)
iobm/IOREQr 1 0 0 4 FB2_5 1 GTS/I/O (b)
cnt/RefCnt<3> 1 0 0 4 FB2_6 2 GTS/I/O (b)
cnt/RefCnt<2> 1 0 0 4 FB2_7 (b) (b)
cnt/RefCnt<1> 1 0 0 4 FB2_8 3 GTS/I/O (b)
fsb/BERR1r 2 0 0 3 FB2_9 4 GTS/I/O (b)
cnt/RefDone 2 0 0 3 FB2_10 (b) (b)
nLDS_IOB 3 0 0 2 FB2_11 6 I/O O
nUDS_IOB 3 0 0 2 FB2_12 7 I/O O
cnt/TimeoutBPre 3 0 0 2 FB2_13 (b) (b)
nDoutOE 2 0 0 3 FB2_14 8 I/O O
TimeoutB 3 0 0 2 FB2_15 9 I/O I
TimeoutA 3 0 0 2 FB2_16 (b) (b)
nAS_IOB 1 0 0 4 FB2_17 10 I/O O
iobs/IOReady 4 0 0 1 FB2_18 (b) (b)
Signals Used by Logic in Function Block
1: BERR_IOBS 13: cnt/RefCnt<3> 25: iobm/IOS_FSM_FFd5
2: IOBERR 14: cnt/RefCnt<4> 26: iobm/IOS_FSM_FFd6
3: IOL0 15: cnt/RefCnt<5> 27: iobm/IOS_FSM_FFd7
4: IOREQ 16: cnt/RefCnt<6> 28: iobs/IOACTr
5: IORW0 17: cnt/RefCnt<7> 29: iobs/IOReady
6: IOU0 18: cnt/RefDone 30: iobs/Once
7: RefAck 19: cnt/TimeoutBPre 31: iobs/PS_FSM_FFd2
8: TimeoutA 20: fsb/ASrf 32: nADoutLE1
9: TimeoutB 21: fsb/BERR1r 33: nAS_FSB
10: cnt/RefCnt<0> 22: iobm/IOS_FSM_FFd2 34: nRES
11: cnt/RefCnt<1> 23: iobm/IOS_FSM_FFd3 35: nVPA_IOB
12: cnt/RefCnt<2> 24: iobm/IOS_FSM_FFd4
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
iobm/VPArr ..................................X..... 1
iobm/VPArf ..................................X..... 1
iobm/RESrr .................................X...... 1
iobm/RESrf .................................X...... 1
iobm/IOREQr ...X.................................... 1
cnt/RefCnt<3> .........XXX............................ 3
cnt/RefCnt<2> .........XX............................. 2
cnt/RefCnt<1> .........X.............................. 1
fsb/BERR1r X..................XX...........X....... 4
cnt/RefDone ......X..XXXXXXXXX...................... 10
nLDS_IOB ..X.X.................XXXXX............. 7
nUDS_IOB ....XX................XXXXX............. 7
cnt/TimeoutBPre .........XXXXXXXX.XX............X....... 11
nDoutOE ....X................XXXXXX............. 7
TimeoutB ........XXXXXXXXX.XX............X....... 12
TimeoutA .......X.XXXXXXX...X............X....... 10
nAS_IOB ......................XXXXX............. 5
iobs/IOReady .X.................X.......XXXXXX....... 8
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 35/19
Number of signals used by logic mapping into function block: 35
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 \/4 1 FB3_1 (b) (b)
(unused) 0 0 \/5 0 FB3_2 23 GCK/I/O GCK
IORW0 18 13<- 0 0 FB3_3 (b) (b)
iobs/IOACTr 1 0 /\4 0 FB3_4 (b) (b)
nRAS 3 0 0 2 FB3_5 24 I/O O
iobs/Clear1 1 0 0 4 FB3_6 25 I/O I
fsb/ASrf 1 0 0 4 FB3_7 (b) (b)
ALE0S 1 0 \/4 0 FB3_8 27 GCK/I/O GCK/I
iobs/PS_FSM_FFd2 14 9<- 0 0 FB3_9 28 I/O (b)
(unused) 0 0 /\5 0 FB3_10 (b) (b)
nADoutLE1 2 0 \/2 1 FB3_11 29 I/O O
iobs/PS_FSM_FFd1 2 2<- \/5 0 FB3_12 30 I/O (b)
IOREQ 14 9<- 0 0 FB3_13 (b) (b)
iobm/ETACK 1 0 /\4 0 FB3_14 32 I/O (b)
nVMA_IOB 2 0 \/2 1 FB3_15 33 I/O O
(unused) 0 0 \/5 0 FB3_16 (b) (b)
iobs/IORW1 16 11<- 0 0 FB3_17 34 I/O (b)
ram/BACTr 1 0 /\4 0 FB3_18 (b) (b)
Signals Used by Logic in Function Block
1: A_FSB<13> 13: RefAck 25: iobs/IORW1
2: A_FSB<14> 14: cs/nOverlay1 26: iobs/Load1
3: A_FSB<16> 15: fsb/ASrf 27: iobs/Once
4: A_FSB<17> 16: iobm/ES<0> 28: iobs/PS_FSM_FFd1
5: A_FSB<18> 17: iobm/ES<1> 29: iobs/PS_FSM_FFd2
6: A_FSB<19> 18: iobm/ES<2> 30: nADoutLE1
7: A_FSB<20> 19: iobm/ES<3> 31: nAS_FSB
8: A_FSB<21> 20: iobm/ES<4> 32: nVMA_IOB
9: A_FSB<22> 21: iobm/VPArf 33: nWE_FSB
10: A_FSB<23> 22: iobm/VPArr 34: ram/RAMDIS1
11: IOACT 23: iobs/Clear1 35: ram/RAMDIS2
12: IORW0 24: iobs/IOACTr
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
IORW0 XXXXXXXXXX.X.XX.........X.XXXXX.X....... 20
iobs/IOACTr ..........X............................. 1
nRAS .......XXX..XX................X..XX..... 8
iobs/Clear1 ...........................XXX.......... 3
fsb/ASrf ..............................X......... 1
ALE0S ...........................XX........... 2
iobs/PS_FSM_FFd2 XXXXXXXXXX...XX........X..XXXXX.X....... 19
nADoutLE1 ......................X..X...X.......... 3
iobs/PS_FSM_FFd1 .......................X...XX........... 3
IOREQ XXXXXXXXXX...XX........X..XXXXX.X....... 19
iobm/ETACK ...............XXXXX...........X........ 6
nVMA_IOB ..........X....XXXXXXX.........X........ 9
iobs/IORW1 XXXXXXXXXX...XX.........X.XXXXX.X....... 19
ram/BACTr ..............X...............X......... 2
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 36/18
Number of signals used by logic mapping into function block: 36
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
ram/RASEL 20 15<- 0 0 FB4_1 (b) (b)
RA<0> 2 2<- /\5 0 FB4_2 87 I/O O
cs/nOverlay1 2 0 /\2 1 FB4_3 (b) (b)
(unused) 0 0 0 5 FB4_4 (b)
(unused) 0 0 \/4 1 FB4_5 89 I/O I
iobs/Load1 14 9<- 0 0 FB4_6 90 I/O I
(unused) 0 0 /\5 0 FB4_7 (b) (b)
RA<2> 2 0 \/2 1 FB4_8 91 I/O O
(unused) 0 0 \/5 0 FB4_9 92 I/O I
iobs/Once 17 12<- 0 0 FB4_10 (b) (b)
(unused) 0 0 /\5 0 FB4_11 93 I/O I
RA<4> 2 0 \/3 0 FB4_12 94 I/O O
(unused) 0 0 \/5 0 FB4_13 (b) (b)
ram/RAMDIS1 18 13<- 0 0 FB4_14 95 I/O I
(unused) 0 0 /\5 0 FB4_15 96 I/O I
fsb/BERR0r 3 0 \/2 0 FB4_16 (b) (b)
nDinOE 2 2<- \/5 0 FB4_17 97 I/O O
(unused) 0 0 \/5 0 FB4_18 (b) (b)
Signals Used by Logic in Function Block
1: A_FSB<10> 13: A_FSB<23> 25: iobs/Once
2: A_FSB<12> 14: A_FSB<3> 26: iobs/PS_FSM_FFd1
3: A_FSB<13> 15: A_FSB<5> 27: iobs/PS_FSM_FFd2
4: A_FSB<14> 16: TimeoutB 28: nADoutLE1
5: A_FSB<16> 17: cnt/RefCnt<5> 29: nAS_FSB
6: A_FSB<17> 18: cnt/RefCnt<6> 30: nWE_FSB
7: A_FSB<18> 19: cnt/RefCnt<7> 31: ram/BACTr
8: A_FSB<19> 20: cnt/RefDone 32: ram/Once
9: A_FSB<1> 21: cs/nOverlay0 33: ram/RASEL
10: A_FSB<20> 22: cs/nOverlay1 34: ram/RS_FSM_FFd1
11: A_FSB<21> 23: fsb/ASrf 35: ram/RS_FSM_FFd2
12: A_FSB<22> 24: fsb/BERR0r 36: ram/RS_FSM_FFd3
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
ram/RASEL ..........XXX...XXXX.XX.....X.XX.XXX.... 15
RA<0> X.......X.......................X....... 3
cs/nOverlay1 ....................X.X.....X........... 3
iobs/Load1 ..XXXXXX.XXXX........XX.XXXXXX.......... 18
RA<2> .X...........X..................X....... 3
iobs/Once ..XXXXXX.XXXX........XX.XXXXXX.......... 18
RA<4> ...X..........X.................X....... 3
ram/RAMDIS1 ..........XXX...XXXX.XX.....X.XX.XXX.... 15
fsb/BERR0r .........XXXX..X......XX....X........... 8
nDinOE .........XXXX...............XX.......... 6
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB5 ***********************************
Number of function block inputs used/remaining: 35/19
Number of signals used by logic mapping into function block: 35
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
IOACT 10 5<- 0 0 FB5_1 (b) (b)
RA<1> 2 0 /\3 0 FB5_2 35 I/O O
iobm/IOS_FSM_FFd7 1 0 0 4 FB5_3 (b) (b)
iobm/IOS_FSM_FFd6 1 0 0 4 FB5_4 (b) (b)
iobm/IOS_FSM_FFd5 1 0 0 4 FB5_5 36 I/O (b)
iobm/IOS_FSM_FFd4 1 0 0 4 FB5_6 37 I/O (b)
iobm/BERRrr 1 0 0 4 FB5_7 (b) (b)
RA<3> 2 0 0 3 FB5_8 39 I/O O
iobm/BERRrf 1 0 0 4 FB5_9 40 I/O (b)
cnt/RefCnt<0> 0 0 0 5 FB5_10 (b) (b)
iobm/IOS_FSM_FFd8 2 0 0 3 FB5_11 41 I/O (b)
nROMCS 2 0 0 3 FB5_12 42 I/O O
ALE0M 2 0 0 3 FB5_13 (b) (b)
iobm/IOS_FSM_FFd2 4 0 0 1 FB5_14 43 I/O (b)
BERR_IOBS 4 0 0 1 FB5_15 46 I/O (b)
iobm/IOS_FSM_FFd3 5 0 0 0 FB5_16 (b) (b)
(unused) 0 0 \/5 0 FB5_17 49 I/O I
IOBERR 8 5<- \/2 0 FB5_18 (b) (b)
Signals Used by Logic in Function Block
1: A_FSB<11> 13: fsb/ASrf 25: iobm/IOS_FSM_FFd7
2: A_FSB<13> 14: iobm/BERRrf 26: iobm/IOS_FSM_FFd8
3: A_FSB<20> 15: iobm/BERRrr 27: iobm/RESrf
4: A_FSB<21> 16: iobm/DTACKrf 28: iobm/RESrr
5: A_FSB<22> 17: iobm/DTACKrr 29: iobs/IOACTr
6: A_FSB<23> 18: iobm/ETACK 30: iobs/Once
7: A_FSB<2> 19: iobm/IOREQr 31: iobs/PS_FSM_FFd2
8: A_FSB<4> 20: iobm/IOS_FSM_FFd1 32: nADoutLE1
9: BERR_IOBS 21: iobm/IOS_FSM_FFd3 33: nAS_FSB
10: CLK_IOB 22: iobm/IOS_FSM_FFd4 34: nBERR_IOB
11: IOBERR 23: iobm/IOS_FSM_FFd5 35: ram/RASEL
12: cs/nOverlay1 24: iobm/IOS_FSM_FFd6
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
IOACT .........X...XXXXXX.XXXXXXXX............ 15
RA<1> X.....X...........................X..... 3
iobm/IOS_FSM_FFd7 .........X........X......X.............. 3
iobm/IOS_FSM_FFd6 ........................X............... 1
iobm/IOS_FSM_FFd5 .......................X................ 1
iobm/IOS_FSM_FFd4 ......................X................. 1
iobm/BERRrr .................................X...... 1
RA<3> .X.....X..........................X..... 3
iobm/BERRrf .................................X...... 1
cnt/RefCnt<0> ........................................ 0
iobm/IOS_FSM_FFd8 .........X........XX.....X.............. 4
nROMCS ..XXXX.....X............................ 5
ALE0M ..................X.XXXXXX.............. 7
iobm/IOS_FSM_FFd2 .........X...XXXXX..X.....XX............ 9
BERR_IOBS ........X.X.X...............XXXXX....... 8
iobm/IOS_FSM_FFd3 .........X...XXXXX..XX....XX............ 10
IOBERR .........XX..XXXXX..X.....XX.....X...... 11
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB6 ***********************************
Number of function block inputs used/remaining: 24/30
Number of signals used by logic mapping into function block: 24
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
iobm/Er2 1 0 0 4 FB6_1 (b) (b)
nCAS 1 0 0 4 FB6_2 74 I/O O
iobm/DTACKrr 1 0 0 4 FB6_3 (b) (b)
iobm/DTACKrf 1 0 0 4 FB6_4 (b) (b)
RefAck 1 0 0 4 FB6_5 76 I/O I
nRAMLWE 1 0 0 4 FB6_6 77 I/O O
iobs/IOU1 2 0 0 3 FB6_7 (b) (b)
iobs/IOL1 2 0 0 3 FB6_8 78 I/O I
nRAMUWE 1 0 0 4 FB6_9 79 I/O O
iobm/ES<3> 3 0 0 2 FB6_10 (b) (b)
iobm/ES<1> 3 0 0 2 FB6_11 80 I/O I
nROMWE 1 0 0 4 FB6_12 81 I/O O
iobm/ES<0> 3 0 0 2 FB6_13 (b) (b)
IOU0 3 0 0 2 FB6_14 82 I/O I
nVPA_FSB 1 0 0 4 FB6_15 85 I/O O
IOL0 3 0 0 2 FB6_16 (b) (b)
iobm/ES<4> 4 0 0 1 FB6_17 86 I/O I
iobm/ES<2> 5 0 0 0 FB6_18 (b) (b)
Signals Used by Logic in Function Block
1: fsb/VPA 9: iobs/IOL1 17: nLDS_FSB
2: iobm/ES<0> 10: iobs/IOU1 18: nUDS_FSB
3: iobm/ES<1> 11: iobs/Load1 19: nWE_FSB
4: iobm/ES<2> 12: iobs/PS_FSM_FFd1 20: ram/RAMDIS1
5: iobm/ES<3> 13: iobs/PS_FSM_FFd2 21: ram/RAMDIS2
6: iobm/ES<4> 14: nADoutLE1 22: ram/RASEL
7: iobm/Er 15: nAS_FSB 23: ram/RS_FSM_FFd1
8: iobm/Er2 16: nDTACK_IOB 24: ram/RS_FSM_FFd2
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
iobm/Er2 ......X................................. 1
nCAS .....................X.................. 1
iobm/DTACKrr ...............X........................ 1
iobm/DTACKrf ...............X........................ 1
RefAck ......................XX................ 2
nRAMLWE ..............X.X.XXX................... 5
iobs/IOU1 ..........X......X...................... 2
iobs/IOL1 ..........X.....X....................... 2
nRAMUWE ..............X..XXXX................... 5
iobm/ES<3> .XXXX.XX................................ 6
iobm/ES<1> .XX...XX................................ 4
nROMWE ..............X...X..................... 2
iobm/ES<0> .XXXXXXX................................ 7
IOU0 .........X.XXX...X...................... 5
nVPA_FSB X.............X......................... 2
IOL0 ........X..XXX..X....................... 5
iobm/ES<4> .XXXXXXX................................ 7
iobm/ES<2> .XXXXXXX................................ 7
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB7 ***********************************
Number of function block inputs used/remaining: 35/19
Number of signals used by logic mapping into function block: 35
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
cnt/RefCnt<5> 1 0 /\1 3 FB7_1 (b) (b)
RA<5> 2 0 0 3 FB7_2 50 I/O O
cnt/RefCnt<4> 1 0 0 4 FB7_3 (b) (b)
cs/nOverlay0 2 0 \/3 0 FB7_4 (b) (b)
ram/RS_FSM_FFd3 11 6<- 0 0 FB7_5 52 I/O I
RA<6> 2 0 /\3 0 FB7_6 53 I/O O
fsb/Ready0r 3 0 0 2 FB7_7 (b) (b)
ram/RS_FSM_FFd1 5 0 0 0 FB7_8 54 I/O I
RA<7> 2 0 \/3 0 FB7_9 55 I/O O
ram/Once 5 3<- \/3 0 FB7_10 (b) (b)
ram/RAMDIS2 7 3<- \/1 0 FB7_11 56 I/O I
RA<8> 2 1<- \/4 0 FB7_12 58 I/O O
ram/RS_FSM_FFd2 13 8<- 0 0 FB7_13 (b) (b)
cnt/RefCnt<7> 1 0 /\4 0 FB7_14 59 I/O I
RA<9> 2 0 \/1 2 FB7_15 60 I/O O
cnt/RefCnt<6> 1 1<- \/5 0 FB7_16 (b) (b)
ram/RAMReady 16 11<- 0 0 FB7_17 61 I/O I
(unused) 0 0 /\5 0 FB7_18 (b) (b)
Signals Used by Logic in Function Block
1: A_FSB<15> 13: A_FSB<9> 25: fsb/ASrf
2: A_FSB<16> 14: cnt/RefCnt<0> 26: fsb/Ready0r
3: A_FSB<17> 15: cnt/RefCnt<1> 27: nAS_FSB
4: A_FSB<18> 16: cnt/RefCnt<2> 28: ram/BACTr
5: A_FSB<19> 17: cnt/RefCnt<3> 29: ram/Once
6: A_FSB<20> 18: cnt/RefCnt<4> 30: ram/RAMDIS2
7: A_FSB<21> 19: cnt/RefCnt<5> 31: ram/RAMReady
8: A_FSB<22> 20: cnt/RefCnt<6> 32: ram/RASEL
9: A_FSB<23> 21: cnt/RefCnt<7> 33: ram/RS_FSM_FFd1
10: A_FSB<6> 22: cnt/RefDone 34: ram/RS_FSM_FFd2
11: A_FSB<7> 23: cs/nOverlay0 35: ram/RS_FSM_FFd3
12: A_FSB<8> 24: cs/nOverlay1
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
cnt/RefCnt<5> .............XXXXX...................... 5
RA<5> X........X.....................X........ 3
cnt/RefCnt<4> .............XXXX....................... 4
cs/nOverlay0 .....XXXX.............X.X.X............. 7
ram/RS_FSM_FFd3 ......XXX.........XXXX.XX.X.X...XXX..... 14
RA<6> .X........X....................X........ 3
fsb/Ready0r ......XXX..............XXXX...X......... 8
ram/RS_FSM_FFd1 ......XXX..............XX.X.X...XXX..... 10
RA<7> ..X........X...................X........ 3
ram/Once ......XXX..............XX.X.X...XXX..... 10
ram/RAMDIS2 ......XXX.........XXXX.XX.X.XX..XXX..... 15
RA<8> ...X........X..................X........ 3
ram/RS_FSM_FFd2 ......XXX.........XXXX.XX.XX....XXX..... 14
cnt/RefCnt<7> .............XXXXXXX.................... 7
RA<9> ....XX.........................X........ 3
cnt/RefCnt<6> .............XXXXXX..................... 6
ram/RAMReady ......XXX.........XXXX.XX.XXX...XXX..... 15
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB8 ***********************************
Number of function block inputs used/remaining: 8/46
Number of signals used by logic mapping into function block: 8
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB8_1 (b)
RA<11> 1 0 0 4 FB8_2 63 I/O O
(unused) 0 0 0 5 FB8_3 (b)
(unused) 0 0 0 5 FB8_4 (b)
(unused) 0 0 0 5 FB8_5 64 I/O I
RA<10> 1 0 0 4 FB8_6 65 I/O O
(unused) 0 0 0 5 FB8_7 (b)
(unused) 0 0 0 5 FB8_8 66 I/O I
nADoutLE0 1 0 0 4 FB8_9 67 I/O O
(unused) 0 0 0 5 FB8_10 (b)
(unused) 0 0 0 5 FB8_11 68 I/O I
nAoutOE 0 0 0 5 FB8_12 70 I/O O
(unused) 0 0 0 5 FB8_13 (b)
(unused) 0 0 0 5 FB8_14 71 I/O I
nDinLE 1 0 0 4 FB8_15 72 I/O O
(unused) 0 0 0 5 FB8_16 (b)
iobm/IOS_FSM_FFd1 1 0 0 4 FB8_17 73 I/O I
iobm/Er 1 0 0 4 FB8_18 (b) (b)
Signals Used by Logic in Function Block
1: ALE0M 4: A_FSB<21> 7: iobm/IOS_FSM_FFd3
2: ALE0S 5: E_IOB 8: iobm/IOS_FSM_FFd4
3: A_FSB<19> 6: iobm/IOS_FSM_FFd2
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
RA<11> ..X..................................... 1
RA<10> ...X.................................... 1
nADoutLE0 XX...................................... 2
nAoutOE ........................................ 0
nDinLE ......XX................................ 2
iobm/IOS_FSM_FFd1 .....X.................................. 1
iobm/Er ....X................................... 1
0----+----1----+----2----+----3----+----4
0 0 0 0
******************************* Equations ********************************
********** Mapped Logic **********
$OpTx$FX_DC$602 <= ((NOT TimeoutB)
OR (NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20)));
$OpTx$FX_DC$606 <= ((A_FSB(14) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB)
OR (A_FSB(14) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
cs/nOverlay1 AND NOT nWE_FSB AND NOT nADoutLE1)
OR (A_FSB(13) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
cs/nOverlay1 AND NOT nWE_FSB AND NOT nADoutLE1)
OR (A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20))
OR (A_FSB(13) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB));
FDCPE_ALE0M: FDCPE port map (ALE0M,ALE0M_D,CLK2X_IOB,'0','0');
ALE0M_D <= ((NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd7 AND
NOT iobm/IOREQr)
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd7 AND
NOT iobm/IOS_FSM_FFd8));
FDCPE_ALE0S: FDCPE port map (ALE0S,ALE0S_D,CLK_FSB,'0','0');
ALE0S_D <= (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1);
FTCPE_BERR_IOBS: FTCPE port map (BERR_IOBS,BERR_IOBS_T,CLK_FSB,'0','0');
BERR_IOBS_T <= ((BERR_IOBS AND nAS_FSB AND NOT fsb/ASrf)
OR (iobs/Once AND BERR_IOBS AND NOT IOBERR AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr AND nADoutLE1)
OR (iobs/Once AND NOT BERR_IOBS AND IOBERR AND NOT nAS_FSB AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr AND nADoutLE1)
OR (iobs/Once AND NOT BERR_IOBS AND IOBERR AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr AND fsb/ASrf AND nADoutLE1));
FDCPE_IOACT: FDCPE port map (IOACT,IOACT_D,CLK2X_IOB,'0','0');
IOACT_D <= ((NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
NOT iobm/IOS_FSM_FFd6 AND CLK_IOB AND NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd8 AND
iobm/BERRrf AND iobm/BERRrr)
OR (NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
NOT iobm/IOS_FSM_FFd6 AND CLK_IOB AND NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd8 AND
iobm/DTACKrf AND iobm/DTACKrr)
OR (NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
NOT iobm/IOS_FSM_FFd6 AND CLK_IOB AND NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd8 AND
iobm/RESrf AND iobm/RESrr)
OR (NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
NOT iobm/IOS_FSM_FFd6 AND CLK_IOB AND NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOREQr AND
iobm/DTACKrf AND iobm/DTACKrr)
OR (NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
NOT iobm/IOS_FSM_FFd6 AND CLK_IOB AND NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOREQr AND
iobm/RESrf AND iobm/RESrr)
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd7 AND
NOT iobm/IOREQr)
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd7 AND
NOT iobm/IOS_FSM_FFd8)
OR (NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
NOT iobm/IOS_FSM_FFd6 AND CLK_IOB AND NOT iobm/IOS_FSM_FFd7 AND iobm/ETACK AND
NOT iobm/IOREQr)
OR (NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
NOT iobm/IOS_FSM_FFd6 AND CLK_IOB AND NOT iobm/IOS_FSM_FFd7 AND iobm/ETACK AND
NOT iobm/IOS_FSM_FFd8)
OR (NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
NOT iobm/IOS_FSM_FFd6 AND CLK_IOB AND NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOREQr AND
iobm/BERRrf AND iobm/BERRrr));
FTCPE_IOBERR: FTCPE port map (IOBERR,IOBERR_T,CLK2X_IOB,'0','0');
IOBERR_T <= ((nBERR_IOB AND IOBERR AND iobm/IOS_FSM_FFd3 AND
CLK_IOB AND iobm/DTACKrf AND iobm/DTACKrr)
OR (nBERR_IOB AND IOBERR AND iobm/IOS_FSM_FFd3 AND
CLK_IOB AND iobm/RESrf AND iobm/RESrr)
OR (NOT nBERR_IOB AND NOT IOBERR AND iobm/IOS_FSM_FFd3 AND
CLK_IOB AND iobm/BERRrf AND iobm/BERRrr)
OR (NOT nBERR_IOB AND NOT IOBERR AND iobm/IOS_FSM_FFd3 AND
CLK_IOB AND iobm/DTACKrf AND iobm/DTACKrr)
OR (NOT nBERR_IOB AND NOT IOBERR AND iobm/IOS_FSM_FFd3 AND
CLK_IOB AND iobm/RESrf AND iobm/RESrr)
OR (nBERR_IOB AND IOBERR AND iobm/IOS_FSM_FFd3 AND
CLK_IOB AND iobm/ETACK)
OR (NOT nBERR_IOB AND NOT IOBERR AND iobm/IOS_FSM_FFd3 AND
CLK_IOB AND iobm/ETACK)
OR (nBERR_IOB AND IOBERR AND iobm/IOS_FSM_FFd3 AND
CLK_IOB AND iobm/BERRrf AND iobm/BERRrr));
FDCPE_IOL0: FDCPE port map (IOL0,IOL0_D,CLK_FSB,'0','0',IOL0_CE);
IOL0_D <= ((NOT nLDS_FSB AND nADoutLE1)
OR (iobs/IOL1 AND NOT nADoutLE1));
IOL0_CE <= (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1);
FDCPE_IOREQ: FDCPE port map (IOREQ,IOREQ_D,CLK_FSB,'0','0');
IOREQ_D <= ((NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21) AND
NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/nOverlay1 AND
NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(19) AND
NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(16) AND
NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
OR (NOT A_FSB(23) AND A_FSB(21) AND nWE_FSB AND
NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(18) AND
NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(17) AND
NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
OR (NOT A_FSB(14) AND NOT A_FSB(13) AND NOT A_FSB(23) AND A_FSB(21) AND
NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
cs/nOverlay1 AND NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
OR (NOT iobs/PS_FSM_FFd2 AND iobs/PS_FSM_FFd1)
OR (iobs/PS_FSM_FFd1 AND iobs/IOACTr)
OR (iobs/Once AND NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(20) AND NOT iobs/PS_FSM_FFd2 AND
nADoutLE1)
OR (nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT fsb/ASrf AND
nADoutLE1));
FTCPE_IORW0: FTCPE port map (IORW0,IORW0_T,CLK_FSB,'0','0');
IORW0_T <= ((EXP22_.EXP)
OR (A_FSB(23) AND NOT iobs/Once AND NOT IORW0 AND nWE_FSB AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf AND nADoutLE1)
OR (A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20) AND NOT iobs/Once AND
IORW0 AND NOT nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND
NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
OR (A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20) AND NOT iobs/Once AND
IORW0 AND NOT nWE_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND
fsb/ASrf AND nADoutLE1)
OR (A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20) AND NOT iobs/Once AND
NOT IORW0 AND nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND
NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
OR (A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20) AND NOT iobs/Once AND
NOT IORW0 AND nWE_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND
fsb/ASrf AND nADoutLE1)
OR (A_FSB(14) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND
NOT iobs/Once AND IORW0 AND NOT nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND
NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
OR (A_FSB(14) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND
NOT iobs/Once AND IORW0 AND NOT nWE_FSB AND NOT iobs/PS_FSM_FFd2 AND
NOT iobs/PS_FSM_FFd1 AND fsb/ASrf AND nADoutLE1)
OR (A_FSB(13) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND
NOT iobs/Once AND IORW0 AND NOT nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND
NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
OR (A_FSB(13) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND
NOT iobs/Once AND IORW0 AND NOT nWE_FSB AND NOT iobs/PS_FSM_FFd2 AND
NOT iobs/PS_FSM_FFd1 AND fsb/ASrf AND nADoutLE1)
OR (IORW0 AND NOT iobs/IORW1 AND NOT iobs/PS_FSM_FFd2 AND
NOT iobs/PS_FSM_FFd1 AND NOT nADoutLE1)
OR (NOT IORW0 AND iobs/IORW1 AND NOT iobs/PS_FSM_FFd2 AND
NOT iobs/PS_FSM_FFd1 AND NOT nADoutLE1)
OR (A_FSB(23) AND NOT iobs/Once AND IORW0 AND NOT nWE_FSB AND
NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
OR (A_FSB(23) AND NOT iobs/Once AND IORW0 AND NOT nWE_FSB AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf AND nADoutLE1)
OR (A_FSB(23) AND NOT iobs/Once AND NOT IORW0 AND nWE_FSB AND
NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1));
FDCPE_IOU0: FDCPE port map (IOU0,IOU0_D,CLK_FSB,'0','0',IOU0_CE);
IOU0_D <= ((NOT nUDS_FSB AND nADoutLE1)
OR (iobs/IOU1 AND NOT nADoutLE1));
IOU0_CE <= (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1);
RA(0) <= ((A_FSB(10) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(1)));
RA(1) <= ((A_FSB(11) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(2)));
RA(2) <= ((A_FSB(12) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(3)));
RA(3) <= ((A_FSB(13) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(4)));
RA(4) <= ((A_FSB(14) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(5)));
RA(5) <= ((A_FSB(15) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(6)));
RA(6) <= ((A_FSB(16) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(7)));
RA(7) <= ((A_FSB(8) AND ram/RASEL)
OR (A_FSB(17) AND NOT ram/RASEL));
RA(8) <= ((A_FSB(9) AND ram/RASEL)
OR (A_FSB(18) AND NOT ram/RASEL));
RA(9) <= ((A_FSB(20) AND ram/RASEL)
OR (A_FSB(19) AND NOT ram/RASEL));
RA(10) <= A_FSB(21);
RA(11) <= A_FSB(19);
FDCPE_RefAck: FDCPE port map (RefAck,RefAck_D,CLK_FSB,'0','0');
RefAck_D <= (ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1);
FTCPE_TimeoutA: FTCPE port map (TimeoutA,TimeoutA_T,CLK_FSB,'0','0');
TimeoutA_T <= ((TimeoutA AND nAS_FSB AND NOT fsb/ASrf)
OR (NOT TimeoutA AND NOT nAS_FSB AND NOT cnt/RefCnt(0) AND
NOT cnt/RefCnt(5) AND NOT cnt/RefCnt(6) AND NOT cnt/RefCnt(1) AND NOT cnt/RefCnt(2) AND
NOT cnt/RefCnt(3) AND NOT cnt/RefCnt(4))
OR (NOT TimeoutA AND NOT cnt/RefCnt(0) AND NOT cnt/RefCnt(5) AND
NOT cnt/RefCnt(6) AND NOT cnt/RefCnt(1) AND NOT cnt/RefCnt(2) AND NOT cnt/RefCnt(3) AND
NOT cnt/RefCnt(4) AND fsb/ASrf));
FTCPE_TimeoutB: FTCPE port map (TimeoutB,TimeoutB_T,CLK_FSB,'0','0');
TimeoutB_T <= ((TimeoutB AND nAS_FSB AND NOT fsb/ASrf)
OR (NOT TimeoutB AND cnt/TimeoutBPre AND NOT nAS_FSB AND
NOT cnt/RefCnt(0) AND NOT cnt/RefCnt(5) AND NOT cnt/RefCnt(6) AND NOT cnt/RefCnt(1) AND
NOT cnt/RefCnt(2) AND NOT cnt/RefCnt(3) AND NOT cnt/RefCnt(4) AND NOT cnt/RefCnt(7))
OR (NOT TimeoutB AND cnt/TimeoutBPre AND NOT cnt/RefCnt(0) AND
NOT cnt/RefCnt(5) AND NOT cnt/RefCnt(6) AND NOT cnt/RefCnt(1) AND NOT cnt/RefCnt(2) AND
NOT cnt/RefCnt(3) AND NOT cnt/RefCnt(4) AND NOT cnt/RefCnt(7) AND fsb/ASrf));
FTCPE_cnt/RefCnt0: FTCPE port map (cnt/RefCnt(0),'1',CLK_FSB,'0','0');
FTCPE_cnt/RefCnt1: FTCPE port map (cnt/RefCnt(1),cnt/RefCnt(0),CLK_FSB,'0','0');
FTCPE_cnt/RefCnt2: FTCPE port map (cnt/RefCnt(2),cnt/RefCnt_T(2),CLK_FSB,'0','0');
cnt/RefCnt_T(2) <= (cnt/RefCnt(0) AND cnt/RefCnt(1));
FTCPE_cnt/RefCnt3: FTCPE port map (cnt/RefCnt(3),cnt/RefCnt_T(3),CLK_FSB,'0','0');
cnt/RefCnt_T(3) <= (cnt/RefCnt(0) AND cnt/RefCnt(1) AND cnt/RefCnt(2));
FTCPE_cnt/RefCnt4: FTCPE port map (cnt/RefCnt(4),cnt/RefCnt_T(4),CLK_FSB,'0','0');
cnt/RefCnt_T(4) <= (cnt/RefCnt(0) AND cnt/RefCnt(1) AND cnt/RefCnt(2) AND
cnt/RefCnt(3));
FTCPE_cnt/RefCnt5: FTCPE port map (cnt/RefCnt(5),cnt/RefCnt_T(5),CLK_FSB,'0','0');
cnt/RefCnt_T(5) <= (cnt/RefCnt(0) AND cnt/RefCnt(1) AND cnt/RefCnt(2) AND
cnt/RefCnt(3) AND cnt/RefCnt(4));
FTCPE_cnt/RefCnt6: FTCPE port map (cnt/RefCnt(6),cnt/RefCnt_T(6),CLK_FSB,'0','0');
cnt/RefCnt_T(6) <= (cnt/RefCnt(0) AND cnt/RefCnt(5) AND cnt/RefCnt(1) AND
cnt/RefCnt(2) AND cnt/RefCnt(3) AND cnt/RefCnt(4));
FTCPE_cnt/RefCnt7: FTCPE port map (cnt/RefCnt(7),cnt/RefCnt_T(7),CLK_FSB,'0','0');
cnt/RefCnt_T(7) <= (cnt/RefCnt(0) AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND
cnt/RefCnt(1) AND cnt/RefCnt(2) AND cnt/RefCnt(3) AND cnt/RefCnt(4));
FDCPE_cnt/RefDone: FDCPE port map (cnt/RefDone,cnt/RefDone_D,CLK_FSB,'0','0');
cnt/RefDone_D <= ((NOT cnt/RefDone AND NOT RefAck)
OR (NOT cnt/RefCnt(0) AND NOT cnt/RefCnt(5) AND NOT cnt/RefCnt(6) AND
NOT cnt/RefCnt(1) AND NOT cnt/RefCnt(2) AND NOT cnt/RefCnt(3) AND NOT cnt/RefCnt(4) AND
NOT cnt/RefCnt(7)));
FTCPE_cnt/TimeoutBPre: FTCPE port map (cnt/TimeoutBPre,cnt/TimeoutBPre_T,CLK_FSB,'0','0');
cnt/TimeoutBPre_T <= ((cnt/TimeoutBPre AND nAS_FSB AND NOT fsb/ASrf)
OR (NOT cnt/TimeoutBPre AND NOT nAS_FSB AND NOT cnt/RefCnt(0) AND
NOT cnt/RefCnt(5) AND NOT cnt/RefCnt(6) AND NOT cnt/RefCnt(1) AND NOT cnt/RefCnt(2) AND
NOT cnt/RefCnt(3) AND NOT cnt/RefCnt(4) AND NOT cnt/RefCnt(7))
OR (NOT cnt/TimeoutBPre AND NOT cnt/RefCnt(0) AND NOT cnt/RefCnt(5) AND
NOT cnt/RefCnt(6) AND NOT cnt/RefCnt(1) AND NOT cnt/RefCnt(2) AND NOT cnt/RefCnt(3) AND
NOT cnt/RefCnt(4) AND NOT cnt/RefCnt(7) AND fsb/ASrf));
FTCPE_cs/nOverlay0: FTCPE port map (cs/nOverlay0,cs/nOverlay0_T,CLK_FSB,NOT nRES,'0');
cs/nOverlay0_T <= ((NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20) AND
NOT cs/nOverlay0 AND NOT nAS_FSB)
OR (NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20) AND
NOT cs/nOverlay0 AND fsb/ASrf));
FDCPE_cs/nOverlay1: FDCPE port map (cs/nOverlay1,cs/nOverlay0,CLK_FSB,'0','0',cs/nOverlay1_CE);
cs/nOverlay1_CE <= (nAS_FSB AND NOT fsb/ASrf);
FDCPE_fsb/ASrf: FDCPE port map (fsb/ASrf,NOT nAS_FSB,NOT CLK_FSB,'0','0');
FDCPE_fsb/BERR0r: FDCPE port map (fsb/BERR0r,fsb/BERR0r_D,CLK_FSB,'0','0');
fsb/BERR0r_D <= ((NOT TimeoutB AND NOT fsb/BERR0r)
OR (nAS_FSB AND NOT fsb/ASrf)
OR (NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20) AND
NOT fsb/BERR0r));
FDCPE_fsb/BERR1r: FDCPE port map (fsb/BERR1r,fsb/BERR1r_D,CLK_FSB,'0','0');
fsb/BERR1r_D <= ((NOT BERR_IOBS AND NOT fsb/BERR1r)
OR (nAS_FSB AND NOT fsb/ASrf));
FDCPE_fsb/Ready0r: FDCPE port map (fsb/Ready0r,fsb/Ready0r_D,CLK_FSB,'0','0');
fsb/Ready0r_D <= ((nAS_FSB AND NOT fsb/ASrf)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND
NOT fsb/Ready0r AND NOT ram/RAMReady)
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
NOT cs/nOverlay1 AND NOT fsb/Ready0r AND NOT ram/RAMReady));
FDCPE_fsb/Ready1r: FDCPE port map (fsb/Ready1r,fsb/Ready1r_D,CLK_FSB,'0','0');
fsb/Ready1r_D <= ((A_FSB(14) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
cs/nOverlay1 AND NOT nWE_FSB AND NOT fsb/Ready1r AND NOT iobs/IOReady AND
NOT nADoutLE1)
OR (A_FSB(13) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
cs/nOverlay1 AND NOT nWE_FSB AND NOT fsb/Ready1r AND NOT iobs/IOReady AND
NOT nADoutLE1)
OR (nAS_FSB AND NOT fsb/ASrf)
OR (A_FSB(23) AND NOT fsb/Ready1r AND NOT iobs/IOReady)
OR (A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20) AND NOT fsb/Ready1r AND
NOT iobs/IOReady)
OR (A_FSB(14) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND
NOT fsb/Ready1r AND NOT iobs/IOReady)
OR (A_FSB(13) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND
NOT fsb/Ready1r AND NOT iobs/IOReady));
FDCPE_fsb/Ready2r: FDCPE port map (fsb/Ready2r,fsb/Ready2r_D,CLK_FSB,'0','0');
fsb/Ready2r_D <= ((nAS_FSB AND NOT fsb/ASrf)
OR (A_FSB(8) AND A_FSB(15) AND A_FSB(14) AND A_FSB(13) AND
A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT A_FSB(23) AND A_FSB(22) AND
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
OR (A_FSB(8) AND A_FSB(15) AND A_FSB(14) AND A_FSB(13) AND
A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT A_FSB(23) AND NOT A_FSB(22) AND
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
A_FSB(16) AND cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
OR (A_FSB(8) AND A_FSB(15) AND NOT A_FSB(14) AND A_FSB(13) AND
NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND NOT A_FSB(23) AND NOT A_FSB(22) AND
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
A_FSB(16) AND cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
OR (A_FSB(9) AND A_FSB(15) AND A_FSB(14) AND A_FSB(13) AND
A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT A_FSB(23) AND A_FSB(22) AND
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
OR (A_FSB(9) AND A_FSB(15) AND A_FSB(14) AND A_FSB(13) AND
A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT A_FSB(23) AND NOT A_FSB(22) AND
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
A_FSB(16) AND cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
OR (A_FSB(9) AND A_FSB(15) AND NOT A_FSB(14) AND A_FSB(13) AND
NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND NOT A_FSB(23) AND A_FSB(22) AND
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
OR (A_FSB(9) AND A_FSB(15) AND NOT A_FSB(14) AND A_FSB(13) AND
NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND NOT A_FSB(23) AND NOT A_FSB(22) AND
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
A_FSB(16) AND cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
OR (A_FSB(8) AND A_FSB(15) AND NOT A_FSB(14) AND A_FSB(13) AND
NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND NOT A_FSB(23) AND A_FSB(22) AND
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r));
FDCPE_fsb/VPA: FDCPE port map (fsb/VPA,fsb/VPA_D,CLK_FSB,'0','0');
fsb/VPA_D <= ((EXP18_.EXP)
OR (BERR_IOBS AND fsb/VPA AND fsb/ASrf)
OR (fsb/BERR0r AND fsb/VPA AND fsb/ASrf)
OR (fsb/BERR1r AND fsb/VPA AND fsb/ASrf)
OR (fsb/VPA AND fsb/ASrf AND
fsb/VPA__or00001/fsb/VPA__or00001_D2)
OR (fsb/VPA AND fsb/ASrf AND NOT $OpTx$FX_DC$602)
OR ($OpTx$FX_DC$602.EXP)
OR (NOT fsb/Ready1r AND fsb/VPA AND NOT iobs/IOReady AND NOT nAS_FSB AND
$OpTx$FX_DC$606)
OR (NOT fsb/Ready1r AND fsb/VPA AND NOT iobs/IOReady AND fsb/ASrf AND
$OpTx$FX_DC$606)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND
NOT fsb/Ready0r AND fsb/VPA AND NOT nAS_FSB AND NOT ram/RAMReady)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND
NOT fsb/Ready0r AND fsb/VPA AND fsb/ASrf AND NOT ram/RAMReady)
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
NOT cs/nOverlay1 AND NOT fsb/Ready0r AND fsb/VPA AND NOT nAS_FSB AND NOT ram/RAMReady)
OR (BERR_IOBS AND fsb/VPA AND NOT nAS_FSB)
OR (fsb/BERR0r AND fsb/VPA AND NOT nAS_FSB)
OR (fsb/BERR1r AND fsb/VPA AND NOT nAS_FSB)
OR (fsb/VPA AND NOT nAS_FSB AND
fsb/VPA__or00001/fsb/VPA__or00001_D2)
OR (fsb/VPA AND NOT nAS_FSB AND NOT $OpTx$FX_DC$602));
fsb/VPA__or00001/fsb/VPA__or00001_D2 <= ((A_FSB(9) AND A_FSB(15) AND A_FSB(14) AND A_FSB(13) AND
A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT A_FSB(23) AND A_FSB(22) AND
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
OR (A_FSB(9) AND A_FSB(15) AND NOT A_FSB(14) AND A_FSB(13) AND
NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND NOT A_FSB(23) AND A_FSB(22) AND
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
OR (A_FSB(8) AND A_FSB(15) AND NOT A_FSB(14) AND A_FSB(13) AND
NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND NOT A_FSB(23) AND A_FSB(22) AND
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
OR (A_FSB(9) AND A_FSB(15) AND A_FSB(14) AND A_FSB(13) AND
A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT A_FSB(23) AND NOT A_FSB(22) AND
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
A_FSB(16) AND cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
OR (A_FSB(9) AND A_FSB(15) AND NOT A_FSB(14) AND A_FSB(13) AND
NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND NOT A_FSB(23) AND NOT A_FSB(22) AND
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
A_FSB(16) AND cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
OR (A_FSB(8) AND A_FSB(15) AND A_FSB(14) AND A_FSB(13) AND
A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT A_FSB(23) AND A_FSB(22) AND
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
OR (A_FSB(8) AND A_FSB(15) AND A_FSB(14) AND A_FSB(13) AND
A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT A_FSB(23) AND NOT A_FSB(22) AND
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
A_FSB(16) AND cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
OR (A_FSB(8) AND A_FSB(15) AND NOT A_FSB(14) AND A_FSB(13) AND
NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND NOT A_FSB(23) AND NOT A_FSB(22) AND
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
A_FSB(16) AND cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r));
FDCPE_iobm/BERRrf: FDCPE port map (iobm/BERRrf,NOT nBERR_IOB,NOT CLK2X_IOB,'0','0');
FDCPE_iobm/BERRrr: FDCPE port map (iobm/BERRrr,NOT nBERR_IOB,CLK2X_IOB,'0','0');
FDCPE_iobm/DTACKrf: FDCPE port map (iobm/DTACKrf,NOT nDTACK_IOB,NOT CLK2X_IOB,'0','0');
FDCPE_iobm/DTACKrr: FDCPE port map (iobm/DTACKrr,NOT nDTACK_IOB,CLK2X_IOB,'0','0');
FTCPE_iobm/ES0: FTCPE port map (iobm/ES(0),iobm/ES_T(0),CLK2X_IOB,'0','0');
iobm/ES_T(0) <= ((iobm/ES(0) AND NOT iobm/Er AND iobm/Er2)
OR (NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
NOT iobm/ES(3) AND NOT iobm/ES(4) AND iobm/Er)
OR (NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
NOT iobm/ES(3) AND NOT iobm/ES(4) AND NOT iobm/Er2));
FDCPE_iobm/ES1: FDCPE port map (iobm/ES(1),iobm/ES_D(1),CLK2X_IOB,'0','0');
iobm/ES_D(1) <= ((iobm/ES(0) AND iobm/ES(1))
OR (NOT iobm/ES(0) AND NOT iobm/ES(1))
OR (NOT iobm/Er AND iobm/Er2));
FDCPE_iobm/ES2: FDCPE port map (iobm/ES(2),iobm/ES_D(2),CLK2X_IOB,'0','0');
iobm/ES_D(2) <= ((NOT iobm/ES(0) AND NOT iobm/ES(2))
OR (NOT iobm/ES(1) AND NOT iobm/ES(2))
OR (NOT iobm/Er AND iobm/Er2)
OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2))
OR (NOT iobm/ES(2) AND NOT iobm/ES(3) AND iobm/ES(4)));
FTCPE_iobm/ES3: FTCPE port map (iobm/ES(3),iobm/ES_T(3),CLK2X_IOB,'0','0');
iobm/ES_T(3) <= ((iobm/ES(3) AND NOT iobm/Er AND iobm/Er2)
OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND iobm/Er)
OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND NOT iobm/Er2));
FTCPE_iobm/ES4: FTCPE port map (iobm/ES(4),iobm/ES_T(4),CLK2X_IOB,'0','0');
iobm/ES_T(4) <= ((iobm/ES(4) AND NOT iobm/Er AND iobm/Er2)
OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND
iobm/ES(3) AND iobm/Er)
OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND
iobm/ES(3) AND NOT iobm/Er2)
OR (iobm/ES(0) AND iobm/ES(1) AND NOT iobm/ES(2) AND
NOT iobm/ES(3) AND iobm/ES(4)));
FDCPE_iobm/ETACK: FDCPE port map (iobm/ETACK,iobm/ETACK_D,CLK2X_IOB,'0','0');
iobm/ETACK_D <= (NOT nVMA_IOB AND NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
NOT iobm/ES(3) AND iobm/ES(4));
FDCPE_iobm/Er: FDCPE port map (iobm/Er,E_IOB,NOT CLK_IOB,'0','0');
FDCPE_iobm/Er2: FDCPE port map (iobm/Er2,iobm/Er,CLK2X_IOB,'0','0');
FDCPE_iobm/IOREQr: FDCPE port map (iobm/IOREQr,IOREQ,NOT CLK2X_IOB,'0','0');
FDCPE_iobm/IOS_FSM_FFd1: FDCPE port map (iobm/IOS_FSM_FFd1,iobm/IOS_FSM_FFd2,CLK2X_IOB,'0','0');
FDCPE_iobm/IOS_FSM_FFd2: FDCPE port map (iobm/IOS_FSM_FFd2,iobm/IOS_FSM_FFd2_D,CLK2X_IOB,'0','0');
iobm/IOS_FSM_FFd2_D <= ((iobm/IOS_FSM_FFd3 AND CLK_IOB AND iobm/ETACK)
OR (iobm/IOS_FSM_FFd3 AND CLK_IOB AND iobm/BERRrf AND
iobm/BERRrr)
OR (iobm/IOS_FSM_FFd3 AND CLK_IOB AND iobm/DTACKrf AND
iobm/DTACKrr)
OR (iobm/IOS_FSM_FFd3 AND CLK_IOB AND iobm/RESrf AND
iobm/RESrr));
FDCPE_iobm/IOS_FSM_FFd3: FDCPE port map (iobm/IOS_FSM_FFd3,iobm/IOS_FSM_FFd3_D,CLK2X_IOB,'0','0');
iobm/IOS_FSM_FFd3_D <= ((NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4)
OR (NOT iobm/IOS_FSM_FFd4 AND CLK_IOB AND iobm/ETACK)
OR (NOT iobm/IOS_FSM_FFd4 AND CLK_IOB AND iobm/BERRrf AND
iobm/BERRrr)
OR (NOT iobm/IOS_FSM_FFd4 AND CLK_IOB AND iobm/DTACKrf AND
iobm/DTACKrr)
OR (NOT iobm/IOS_FSM_FFd4 AND CLK_IOB AND iobm/RESrf AND
iobm/RESrr));
FDCPE_iobm/IOS_FSM_FFd4: FDCPE port map (iobm/IOS_FSM_FFd4,iobm/IOS_FSM_FFd5,CLK2X_IOB,'0','0');
FDCPE_iobm/IOS_FSM_FFd5: FDCPE port map (iobm/IOS_FSM_FFd5,iobm/IOS_FSM_FFd6,CLK2X_IOB,'0','0');
FDCPE_iobm/IOS_FSM_FFd6: FDCPE port map (iobm/IOS_FSM_FFd6,iobm/IOS_FSM_FFd7,CLK2X_IOB,'0','0');
FDCPE_iobm/IOS_FSM_FFd7: FDCPE port map (iobm/IOS_FSM_FFd7,iobm/IOS_FSM_FFd7_D,CLK2X_IOB,'0','0');
iobm/IOS_FSM_FFd7_D <= (NOT CLK_IOB AND iobm/IOREQr AND iobm/IOS_FSM_FFd8);
FDCPE_iobm/IOS_FSM_FFd8: FDCPE port map (iobm/IOS_FSM_FFd8,iobm/IOS_FSM_FFd8_D,CLK2X_IOB,'0','0');
iobm/IOS_FSM_FFd8_D <= ((NOT iobm/IOS_FSM_FFd8 AND NOT iobm/IOS_FSM_FFd1)
OR (NOT CLK_IOB AND iobm/IOREQr AND NOT iobm/IOS_FSM_FFd1));
FDCPE_iobm/RESrf: FDCPE port map (iobm/RESrf,NOT nRES,NOT CLK2X_IOB,'0','0');
FDCPE_iobm/RESrr: FDCPE port map (iobm/RESrr,NOT nRES,CLK2X_IOB,'0','0');
FDCPE_iobm/VPArf: FDCPE port map (iobm/VPArf,NOT nVPA_IOB,NOT CLK2X_IOB,'0','0');
FDCPE_iobm/VPArr: FDCPE port map (iobm/VPArr,NOT nVPA_IOB,CLK2X_IOB,'0','0');
FDCPE_iobs/Clear1: FDCPE port map (iobs/Clear1,iobs/Clear1_D,CLK_FSB,'0','0');
iobs/Clear1_D <= (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND NOT nADoutLE1);
FDCPE_iobs/IOACTr: FDCPE port map (iobs/IOACTr,IOACT,CLK_FSB,'0','0');
FDCPE_iobs/IOL1: FDCPE port map (iobs/IOL1,NOT nLDS_FSB,CLK_FSB,'0','0',iobs/Load1);
FTCPE_iobs/IORW1: FTCPE port map (iobs/IORW1,iobs/IORW1_T,CLK_FSB,'0','0');
iobs/IORW1_T <= ((iobs/Once)
OR (NOT nADoutLE1)
OR (nVMA_IOB_OBUF.EXP)
OR (NOT nWE_FSB AND NOT iobs/IORW1)
OR (nAS_FSB AND NOT fsb/ASrf)
OR (NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21))
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/nOverlay1)
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(19))
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(18))
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(17))
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(16))
OR (NOT A_FSB(23) AND NOT A_FSB(20))
OR (nWE_FSB AND iobs/IORW1)
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT iobs/IORW1));
FTCPE_iobs/IOReady: FTCPE port map (iobs/IOReady,iobs/IOReady_T,CLK_FSB,'0','0');
iobs/IOReady_T <= ((iobs/IOReady AND nAS_FSB AND NOT fsb/ASrf)
OR (iobs/Once AND IOBERR AND iobs/IOReady AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr AND nADoutLE1)
OR (iobs/Once AND NOT IOBERR AND NOT iobs/IOReady AND NOT nAS_FSB AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr AND nADoutLE1)
OR (iobs/Once AND NOT IOBERR AND NOT iobs/IOReady AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr AND fsb/ASrf AND nADoutLE1));
FDCPE_iobs/IOU1: FDCPE port map (iobs/IOU1,NOT nUDS_FSB,CLK_FSB,'0','0',iobs/Load1);
FDCPE_iobs/Load1: FDCPE port map (iobs/Load1,iobs/Load1_D,CLK_FSB,'0','0');
iobs/Load1_D <= ((iobs/Once)
OR (NOT nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21))
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/nOverlay1)
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(19))
OR (NOT A_FSB(23) AND A_FSB(21) AND nWE_FSB)
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(18))
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(17))
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(16))
OR (NOT A_FSB(14) AND NOT A_FSB(13) AND NOT A_FSB(23) AND A_FSB(21))
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
cs/nOverlay1)
OR (NOT A_FSB(23) AND NOT A_FSB(20))
OR (nAS_FSB AND NOT fsb/ASrf)
OR (NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1));
FDCPE_iobs/Once: FDCPE port map (iobs/Once,iobs/Once_D,CLK_FSB,'0','0');
iobs/Once_D <= ((RA_2_OBUF.EXP)
OR (A_FSB(23) AND NOT iobs/Once AND iobs/PS_FSM_FFd1)
OR (NOT iobs/Once AND iobs/PS_FSM_FFd2 AND NOT nADoutLE1)
OR (NOT iobs/Once AND iobs/PS_FSM_FFd1 AND NOT nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21) AND NOT iobs/Once)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/nOverlay1 AND
NOT iobs/Once)
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(19) AND NOT iobs/Once)
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(18) AND NOT iobs/Once)
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(17) AND NOT iobs/Once)
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(16) AND NOT iobs/Once)
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT iobs/Once AND nWE_FSB)
OR (nAS_FSB AND NOT fsb/ASrf)
OR (A_FSB(23) AND NOT iobs/Once AND iobs/PS_FSM_FFd2)
OR (NOT A_FSB(23) AND NOT A_FSB(20) AND NOT iobs/Once)
OR (A_FSB(22) AND NOT iobs/Once AND iobs/PS_FSM_FFd2)
OR (A_FSB(22) AND NOT iobs/Once AND iobs/PS_FSM_FFd1));
FDCPE_iobs/PS_FSM_FFd1: FDCPE port map (iobs/PS_FSM_FFd1,iobs/PS_FSM_FFd1_D,CLK_FSB,'0','0');
iobs/PS_FSM_FFd1_D <= ((iobs/PS_FSM_FFd2)
OR (iobs/PS_FSM_FFd1 AND iobs/IOACTr));
FDCPE_iobs/PS_FSM_FFd2: FDCPE port map (iobs/PS_FSM_FFd2,iobs/PS_FSM_FFd2_D,CLK_FSB,'0','0');
iobs/PS_FSM_FFd2_D <= ((NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21) AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/nOverlay1 AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(19) AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
OR (NOT A_FSB(23) AND A_FSB(21) AND nWE_FSB AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(18) AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(17) AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(16) AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
OR (NOT A_FSB(14) AND NOT A_FSB(13) AND NOT A_FSB(23) AND A_FSB(21) AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
cs/nOverlay1 AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
OR (iobs/PS_FSM_FFd2 AND iobs/PS_FSM_FFd1 AND
iobs/IOACTr)
OR (NOT iobs/PS_FSM_FFd2 AND iobs/PS_FSM_FFd1 AND
NOT iobs/IOACTr)
OR (iobs/Once AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND
nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(20) AND NOT iobs/PS_FSM_FFd2 AND
NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
OR (nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND
NOT fsb/ASrf AND nADoutLE1));
nADoutLE0 <= (NOT ALE0M AND NOT ALE0S);
FDCPE_nADoutLE1: FDCPE port map (nADoutLE1,nADoutLE1_D,CLK_FSB,'0','0');
nADoutLE1_D <= ((iobs/Load1)
OR (NOT iobs/Clear1 AND NOT nADoutLE1));
FDCPE_nAS_IOB: FDCPE port map (nAS_IOB,nAS_IOB_D,NOT CLK2X_IOB,'0','0');
nAS_IOB_D <= (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd7);
nAoutOE <= '0';
nBERR_FSB <= ((nAS_FSB)
OR (NOT BERR_IOBS AND NOT TimeoutB AND NOT fsb/BERR0r AND NOT fsb/BERR1r)
OR (NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20) AND
NOT BERR_IOBS AND NOT fsb/BERR0r AND NOT fsb/BERR1r));
FDCPE_nCAS: FDCPE port map (nCAS,NOT ram/RASEL,NOT CLK_FSB,'0','0');
FDCPE_nDTACK_FSB: FDCPE port map (nDTACK_FSB,nDTACK_FSB_D,CLK_FSB,'0','0');
nDTACK_FSB_D <= ((EXP21_.EXP)
OR (A_FSB(23) AND NOT fsb/Ready1r AND NOT iobs/IOReady AND
nDTACK_FSB)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND
NOT fsb/Ready0r AND nDTACK_FSB AND NOT ram/RAMReady)
OR (A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20) AND NOT fsb/Ready1r AND
NOT iobs/IOReady AND nDTACK_FSB)
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
NOT cs/nOverlay1 AND NOT fsb/Ready0r AND nDTACK_FSB AND NOT ram/RAMReady)
OR (A_FSB(14) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND
NOT fsb/Ready1r AND NOT iobs/IOReady AND nDTACK_FSB)
OR ($OpTx$FX_DC$606.EXP)
OR (A_FSB(13) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND
NOT fsb/Ready1r AND NOT iobs/IOReady AND nDTACK_FSB)
OR (A_FSB(14) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
cs/nOverlay1 AND NOT nWE_FSB AND NOT fsb/Ready1r AND NOT iobs/IOReady AND
nDTACK_FSB AND NOT nADoutLE1)
OR (A_FSB(13) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
cs/nOverlay1 AND NOT nWE_FSB AND NOT fsb/Ready1r AND NOT iobs/IOReady AND
nDTACK_FSB AND NOT nADoutLE1)
OR (A_FSB(9) AND A_FSB(15) AND A_FSB(14) AND A_FSB(13) AND
A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT A_FSB(23) AND NOT A_FSB(22) AND
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
A_FSB(16) AND cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r AND
nDTACK_FSB)
OR (A_FSB(8) AND A_FSB(15) AND A_FSB(14) AND A_FSB(13) AND
A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT A_FSB(23) AND NOT A_FSB(22) AND
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
A_FSB(16) AND cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r AND
nDTACK_FSB)
OR (BERR_IOBS AND nDTACK_FSB)
OR (fsb/BERR0r AND nDTACK_FSB)
OR (fsb/BERR1r AND nDTACK_FSB)
OR (nAS_FSB AND NOT fsb/ASrf)
OR (nDTACK_FSB AND NOT $OpTx$FX_DC$602));
FDCPE_nDinLE: FDCPE port map (nDinLE,nDinLE_D,NOT CLK2X_IOB,'0','0');
nDinLE_D <= (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4);
nDinOE <= ((A_FSB(23) AND nWE_FSB AND NOT nAS_FSB)
OR (A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20) AND nWE_FSB AND
NOT nAS_FSB));
FDCPE_nDoutOE: FDCPE port map (nDoutOE,nDoutOE_D,CLK2X_IOB,'0','0');
nDoutOE_D <= ((NOT IORW0)
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd7 AND
NOT iobm/IOS_FSM_FFd2));
FDCPE_nLDS_IOB: FDCPE port map (nLDS_IOB,nLDS_IOB_D,NOT CLK2X_IOB,'0','0');
nLDS_IOB_D <= ((NOT IOL0)
OR (IORW0 AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
NOT iobm/IOS_FSM_FFd5)
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd7));
nOE <= NOT ((nWE_FSB AND NOT nAS_FSB));
nRAMLWE <= NOT ((NOT nWE_FSB AND NOT nLDS_FSB AND NOT ram/RAMDIS2 AND NOT nAS_FSB AND
NOT ram/RAMDIS1));
nRAMUWE <= NOT ((NOT nWE_FSB AND NOT nUDS_FSB AND NOT ram/RAMDIS2 AND NOT nAS_FSB AND
NOT ram/RAMDIS1));
nRAS <= NOT (((RefAck)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND
NOT ram/RAMDIS2 AND NOT nAS_FSB AND NOT ram/RAMDIS1)
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
NOT cs/nOverlay1 AND NOT ram/RAMDIS2 AND NOT nAS_FSB AND NOT ram/RAMDIS1)));
nROMCS <= NOT (((NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20))
OR (NOT A_FSB(23) AND NOT A_FSB(21) AND NOT A_FSB(20) AND
NOT cs/nOverlay1)));
nROMWE <= NOT ((NOT nWE_FSB AND NOT nAS_FSB));
FDCPE_nUDS_IOB: FDCPE port map (nUDS_IOB,nUDS_IOB_D,NOT CLK2X_IOB,'0','0');
nUDS_IOB_D <= ((NOT IOU0)
OR (IORW0 AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
NOT iobm/IOS_FSM_FFd5)
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd7));
FTCPE_nVMA_IOB: FTCPE port map (nVMA_IOB,nVMA_IOB_T,CLK2X_IOB,'0','0');
nVMA_IOB_T <= ((NOT nVMA_IOB AND NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
NOT iobm/ES(3) AND NOT iobm/ES(4))
OR (nVMA_IOB AND iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND
NOT iobm/ES(3) AND NOT iobm/ES(4) AND IOACT AND iobm/VPArf AND iobm/VPArr));
nVPA_FSB <= NOT ((fsb/VPA AND NOT nAS_FSB));
FDCPE_ram/BACTr: FDCPE port map (ram/BACTr,ram/BACTr_D,CLK_FSB,'0','0');
ram/BACTr_D <= (nAS_FSB AND NOT fsb/ASrf);
FTCPE_ram/Once: FTCPE port map (ram/Once,ram/Once_T,CLK_FSB,'0','0');
ram/Once_T <= ((NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND NOT ram/Once AND
NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND fsb/ASrf)
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
NOT cs/nOverlay1 AND NOT ram/Once AND NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
NOT cs/nOverlay1 AND NOT ram/Once AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
NOT ram/RS_FSM_FFd3 AND fsb/ASrf)
OR (ram/Once AND nAS_FSB AND NOT fsb/ASrf)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND NOT ram/Once AND
NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
NOT ram/RS_FSM_FFd3));
FDCPE_ram/RAMDIS1: FDCPE port map (ram/RAMDIS1,ram/RAMDIS1_D,CLK_FSB,'0','0');
ram/RAMDIS1_D <= ((RA_4_OBUF.EXP)
OR (A_FSB(22) AND NOT A_FSB(21) AND NOT cnt/RefDone AND NOT nAS_FSB AND
NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
OR (A_FSB(22) AND NOT A_FSB(21) AND NOT cnt/RefDone AND
NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
OR (A_FSB(22) AND cs/nOverlay1 AND NOT cnt/RefDone AND
NOT nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
OR (A_FSB(22) AND cs/nOverlay1 AND NOT cnt/RefDone AND
NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
OR (NOT A_FSB(22) AND NOT cs/nOverlay1 AND NOT cnt/RefDone AND
NOT nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
OR (A_FSB(23) AND NOT cnt/RefDone AND NOT ram/RS_FSM_FFd1 AND
cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7))
OR (NOT A_FSB(22) AND NOT cs/nOverlay1 AND NOT cnt/RefDone AND
NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
OR (ram/Once AND NOT cnt/RefDone AND NOT ram/RS_FSM_FFd1 AND
cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7))
OR (NOT cnt/RefDone AND ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd3 AND
cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7))
OR (NOT cnt/RefDone AND nAS_FSB AND NOT ram/RS_FSM_FFd1 AND
cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND NOT fsb/ASrf)
OR (ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1)
OR (NOT ram/RS_FSM_FFd1 AND ram/RS_FSM_FFd3)
OR (NOT ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND
NOT ram/RS_FSM_FFd3)
OR (A_FSB(23) AND NOT cnt/RefDone AND NOT nAS_FSB AND
NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
OR (A_FSB(23) AND NOT cnt/RefDone AND NOT ram/RS_FSM_FFd1 AND
NOT ram/BACTr AND fsb/ASrf));
FTCPE_ram/RAMDIS2: FTCPE port map (ram/RAMDIS2,ram/RAMDIS2_T,CLK_FSB,'0','0');
ram/RAMDIS2_T <= ((NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND ram/Once AND
NOT cnt/RefDone AND NOT ram/RAMDIS2 AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
NOT ram/RS_FSM_FFd3 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND
fsb/ASrf)
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
NOT cs/nOverlay1 AND ram/Once AND NOT cnt/RefDone AND NOT ram/RAMDIS2 AND NOT nAS_FSB AND
NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7))
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
NOT cs/nOverlay1 AND ram/Once AND NOT cnt/RefDone AND NOT ram/RAMDIS2 AND
NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND fsb/ASrf)
OR (ram/RAMDIS2 AND nAS_FSB AND NOT fsb/ASrf)
OR (ram/Once AND NOT cnt/RefDone AND NOT ram/RAMDIS2 AND NOT nAS_FSB AND
ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND ram/RS_FSM_FFd3 AND
cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7))
OR (ram/Once AND NOT cnt/RefDone AND NOT ram/RAMDIS2 AND
ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND ram/RS_FSM_FFd3 AND
cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND fsb/ASrf)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND ram/Once AND
NOT cnt/RefDone AND NOT ram/RAMDIS2 AND NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND
cnt/RefCnt(7)));
FDCPE_ram/RAMReady: FDCPE port map (ram/RAMReady,ram/RAMReady_D,CLK_FSB,'0','0');
ram/RAMReady_D <= ((NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND NOT ram/Once AND
NOT nAS_FSB AND NOT ram/RS_FSM_FFd1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND NOT ram/Once AND
NOT ram/RS_FSM_FFd1 AND fsb/ASrf)
OR (A_FSB(22) AND cs/nOverlay1 AND NOT cnt/RefDone AND
NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
OR (NOT A_FSB(22) AND NOT cs/nOverlay1 AND NOT cnt/RefDone AND
NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
NOT cs/nOverlay1 AND NOT ram/Once AND NOT ram/RS_FSM_FFd1 AND fsb/ASrf)
OR (cnt/RefCnt(5).EXP)
OR (ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3)
OR (NOT ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1)
OR (NOT ram/RS_FSM_FFd1 AND ram/RS_FSM_FFd3)
OR (A_FSB(23) AND NOT cnt/RefDone AND NOT nAS_FSB AND
NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
OR (A_FSB(23) AND NOT cnt/RefDone AND NOT ram/RS_FSM_FFd1 AND
NOT ram/BACTr AND fsb/ASrf)
OR (A_FSB(22) AND cs/nOverlay1 AND NOT cnt/RefDone AND
NOT nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
OR (NOT A_FSB(22) AND NOT cs/nOverlay1 AND NOT cnt/RefDone AND
NOT nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
OR (NOT A_FSB(21) AND NOT cs/nOverlay1 AND NOT cnt/RefDone AND
NOT nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
OR (NOT A_FSB(21) AND NOT cs/nOverlay1 AND NOT cnt/RefDone AND
NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
NOT cs/nOverlay1 AND NOT ram/Once AND NOT nAS_FSB AND NOT ram/RS_FSM_FFd1));
FDCPE_ram/RASEL: FDCPE port map (ram/RASEL,ram/RASEL_D,CLK_FSB,'0','0');
ram/RASEL_D <= ((A_FSB(22) AND cs/nOverlay1 AND NOT cnt/RefDone AND
NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
OR (NOT A_FSB(22) AND NOT cs/nOverlay1 AND NOT cnt/RefDone AND
NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
OR (NOT A_FSB(22) AND NOT cs/nOverlay1 AND NOT cnt/RefDone AND
NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
OR (NOT cnt/RefDone AND nAS_FSB AND NOT ram/RS_FSM_FFd2 AND
NOT ram/RS_FSM_FFd1 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND
NOT fsb/ASrf)
OR (NOT cnt/RefDone AND nAS_FSB AND ram/RS_FSM_FFd1 AND
ram/RS_FSM_FFd3 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND
NOT fsb/ASrf)
OR (nDinOE_OBUF.EXP)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND NOT ram/Once AND
NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND NOT ram/Once AND
NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND fsb/ASrf)
OR (A_FSB(22) AND NOT A_FSB(21) AND NOT cnt/RefDone AND NOT nAS_FSB AND
NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
OR (A_FSB(22) AND NOT A_FSB(21) AND NOT cnt/RefDone AND
NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
OR (A_FSB(22) AND cs/nOverlay1 AND NOT cnt/RefDone AND
NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
OR (NOT ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd3)
OR (ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
NOT ram/RS_FSM_FFd3)
OR (A_FSB(23) AND NOT cnt/RefDone AND NOT nAS_FSB AND
NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
OR (A_FSB(23) AND NOT cnt/RefDone AND NOT ram/RS_FSM_FFd2 AND
NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
OR (A_FSB(23) AND NOT cnt/RefDone AND NOT ram/RS_FSM_FFd2 AND
NOT ram/RS_FSM_FFd1 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7)));
FTCPE_ram/RS_FSM_FFd1: FTCPE port map (ram/RS_FSM_FFd1,ram/RS_FSM_FFd1_T,CLK_FSB,'0','0');
ram/RS_FSM_FFd1_T <= ((ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd3)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND NOT ram/Once AND
NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
NOT ram/RS_FSM_FFd3)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND NOT ram/Once AND
NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND fsb/ASrf)
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
NOT cs/nOverlay1 AND NOT ram/Once AND NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
NOT cs/nOverlay1 AND NOT ram/Once AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
NOT ram/RS_FSM_FFd3 AND fsb/ASrf));
FTCPE_ram/RS_FSM_FFd2: FTCPE port map (ram/RS_FSM_FFd2,ram/RS_FSM_FFd2_T,CLK_FSB,'0','0');
ram/RS_FSM_FFd2_T <= ((nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
NOT cnt/RefCnt(5) AND NOT fsb/ASrf)
OR (nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
NOT cnt/RefCnt(6) AND NOT fsb/ASrf)
OR (nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
NOT cnt/RefCnt(7) AND NOT fsb/ASrf)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND NOT nAS_FSB AND
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND fsb/ASrf)
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
NOT cs/nOverlay1 AND NOT nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
NOT cs/nOverlay1 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND fsb/ASrf)
OR (NOT cnt/RefDone AND nAS_FSB AND ram/RS_FSM_FFd2 AND
ram/RS_FSM_FFd1 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND
NOT fsb/ASrf)
OR (ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3)
OR (cnt/RefDone AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
OR (NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
NOT cnt/RefCnt(5) AND ram/BACTr)
OR (NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
NOT cnt/RefCnt(6) AND ram/BACTr)
OR (NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND ram/BACTr AND
NOT cnt/RefCnt(7)));
FTCPE_ram/RS_FSM_FFd3: FTCPE port map (ram/RS_FSM_FFd3,ram/RS_FSM_FFd3_T,CLK_FSB,'0','0');
ram/RS_FSM_FFd3_T <= ((A_FSB(22) AND NOT A_FSB(21) AND NOT ram/RS_FSM_FFd2 AND
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
OR (A_FSB(22) AND cs/nOverlay1 AND NOT ram/RS_FSM_FFd2 AND
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
OR (nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
NOT ram/RS_FSM_FFd3 AND NOT fsb/ASrf)
OR (NOT A_FSB(22) AND NOT cs/nOverlay1 AND NOT ram/RS_FSM_FFd2 AND
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
OR (NOT cnt/RefDone AND NOT nAS_FSB AND ram/RS_FSM_FFd2 AND
ram/RS_FSM_FFd1 AND ram/RS_FSM_FFd3 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND
cnt/RefCnt(7))
OR (NOT cnt/RefDone AND ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND
ram/RS_FSM_FFd3 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND
fsb/ASrf)
OR (A_FSB(23) AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
NOT ram/RS_FSM_FFd3)
OR (ram/Once AND cnt/RefDone AND NOT ram/RS_FSM_FFd2 AND
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
OR (ram/Once AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
NOT ram/RS_FSM_FFd3 AND NOT cnt/RefCnt(5))
OR (ram/Once AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
NOT ram/RS_FSM_FFd3 AND NOT cnt/RefCnt(6))
OR (ram/Once AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
NOT ram/RS_FSM_FFd3 AND NOT cnt/RefCnt(7)));
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XC95144XL-10-TQ100
--------------------------------------------------
/100 98 96 94 92 90 88 86 84 82 80 78 76 \
| 99 97 95 93 91 89 87 85 83 81 79 77 |
| 1 75 |
| 2 74 |
| 3 73 |
| 4 72 |
| 5 71 |
| 6 70 |
| 7 69 |
| 8 68 |
| 9 67 |
| 10 66 |
| 11 65 |
| 12 64 |
| 13 XC95144XL-10-TQ100 63 |
| 14 62 |
| 15 61 |
| 16 60 |
| 17 59 |
| 18 58 |
| 19 57 |
| 20 56 |
| 21 55 |
| 22 54 |
| 23 53 |
| 24 52 |
| 25 51 |
| 27 29 31 33 35 37 39 41 43 45 47 49 |
\26 28 30 32 34 36 38 40 42 44 46 48 50 /
--------------------------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 KPR 51 VCC
2 KPR 52 nUDS_FSB
3 KPR 53 RA<6>
4 KPR 54 nDTACK_IOB
5 VCC 55 RA<7>
6 nLDS_IOB 56 A_FSB<4>
7 nUDS_IOB 57 VCC
8 nDoutOE 58 RA<8>
9 A_FSB<22> 59 nVPA_IOB
10 nAS_IOB 60 RA<9>
11 nDTACK_FSB 61 nWE_FSB
12 A_FSB<9> 62 GND
13 nAS_FSB 63 RA<11>
14 nBERR_FSB 64 A_FSB<8>
15 A_FSB<5> 65 RA<10>
16 A_FSB<2> 66 A_FSB<23>
17 nOE 67 nADoutLE0
18 nBERR_IOB 68 A_FSB<21>
19 A_FSB<6> 69 GND
20 A_FSB<7> 70 nAoutOE
21 GND 71 A_FSB<20>
22 CLK2X_IOB 72 nDinLE
23 CLK_FSB 73 A_FSB<19>
24 nRAS 74 nCAS
25 nLDS_FSB 75 GND
26 VCC 76 A_FSB<18>
27 CLK_IOB 77 nRAMLWE
28 KPR 78 A_FSB<3>
29 nADoutLE1 79 nRAMUWE
30 KPR 80 A_FSB<15>
31 GND 81 nROMWE
32 KPR 82 A_FSB<13>
33 nVMA_IOB 83 TDO
34 KPR 84 GND
35 RA<1> 85 nVPA_FSB
36 KPR 86 A_FSB<11>
37 KPR 87 RA<0>
38 VCC 88 VCC
39 RA<3> 89 A_FSB<10>
40 KPR 90 A_FSB<1>
41 KPR 91 RA<2>
42 nROMCS 92 A_FSB<12>
43 KPR 93 A_FSB<14>
44 GND 94 RA<4>
45 TDI 95 A_FSB<16>
46 KPR 96 A_FSB<17>
47 TMS 97 nDinOE
48 TCK 98 VCC
49 E_IOB 99 nRES
50 RA<5> 100 GND
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
KPR = Unused I/O with weak keeper (leave unconnected)
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc95144xl-10-TQ100
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Ground on Unused IOs : OFF
Set I/O Pin Termination : KEEPER
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Input Limit : 54
Pterm Limit : 25
Reference in New Issue View Git Blame Copy Permalink