mirror of
https://github.com/garrettsworkshop/Warp-SE.git
synced 2024-06-15 06:29:28 +00:00
984 lines
65 KiB
Plaintext
984 lines
65 KiB
Plaintext
Performance Summary Report
|
|
--------------------------
|
|
|
|
Design: WarpSE
|
|
Device: XC95144XL-10-TQ100
|
|
Speed File: Version 3.0
|
|
Program: Timing Report Generator: version P.20131013
|
|
Date: Fri Apr 07 00:23:44 2023
|
|
|
|
Performance Summary:
|
|
|
|
Pad to Pad (tPD) : 10.0ns (1 macrocell levels)
|
|
Pad 'nAS_FSB' to Pad 'nOE'
|
|
|
|
Clock net 'FCLK' path delays:
|
|
|
|
Clock Pad to Output Pad (tCO) : 14.5ns (2 macrocell levels)
|
|
Clock Pad 'FCLK' to Output Pad 'nRES' (GCK)
|
|
|
|
Clock to Setup (tCYC) : 11.0ns (1 macrocell levels)
|
|
Clock to Q, net 'iobs/Sent.Q' to DFF Setup(D) at 'iobs/Sent.D' (GCK)
|
|
Target FF drives output net 'iobs/Sent'
|
|
|
|
Setup to Clock at the Pad (tSU) : 7.5ns (0 macrocell levels)
|
|
Data signal 'A_FSB<23>' to DFF D input Pin at 'iobs/Sent.D'
|
|
Clock pad 'FCLK' (GCK)
|
|
|
|
Minimum Clock Period: 11.0ns
|
|
Maximum Internal Clock Speed: 90.9Mhz
|
|
(Limited by Cycle Time)
|
|
|
|
Clock net 'C16M' path delays:
|
|
|
|
Clock Pad to Output Pad (tCO) : 13.5ns (2 macrocell levels)
|
|
Clock Pad 'C16M' to Output Pad 'nADoutLE0' (GCK)
|
|
|
|
Clock to Setup (tCYC) : 11.0ns (1 macrocell levels)
|
|
Clock to Q, net 'iobm/IOS_FSM_FFd7.Q' to DFF Setup(D) at 'nLDS_IOB.D' (GCK)
|
|
Target FF drives output net 'nLDS_IOB'
|
|
|
|
Setup to Clock at the Pad (tSU) : 6.5ns (0 macrocell levels)
|
|
Data signal 'C8M' to DFF D input Pin at 'iobm/C8Mr.D'
|
|
Clock pad 'C16M' (GCK)
|
|
|
|
Minimum Clock Period: 11.0ns
|
|
Maximum Internal Clock Speed: 90.9Mhz
|
|
(Limited by Cycle Time)
|
|
|
|
Clock net 'C8M' path delays:
|
|
|
|
Clock Pad to Output Pad (tCO) : 5.8ns (1 macrocell levels)
|
|
Clock Pad 'C8M' to Output Pad 'nVMA_IOB' (GCK)
|
|
|
|
Clock to Setup (tCYC) : 11.0ns (1 macrocell levels)
|
|
Clock to Q, net 'nVMA_IOB.Q' to DFF Setup(D) at 'IODONE.D' (GCK)
|
|
Target FF drives output net 'IODONE'
|
|
|
|
Setup to Clock at the Pad (tSU) : 6.5ns (0 macrocell levels)
|
|
Data signal 'nBERR_IOB' to DFF D input Pin at 'IOBERR.D'
|
|
Clock pad 'C8M' (GCK)
|
|
|
|
Minimum Clock Period: 11.0ns
|
|
Maximum Internal Clock Speed: 90.9Mhz
|
|
(Limited by Cycle Time)
|
|
|
|
--------------------------------------------------------------------------------
|
|
Pad to Pad (tPD) (nsec)
|
|
|
|
\ From A A A A A A A A A A A
|
|
\ _ _ _ _ _ _ _ _ _ _ _
|
|
\ F F F F F F F F F F F
|
|
\ S S S S S S S S S S S
|
|
\ B B B B B B B B B B B
|
|
\ < < < < < < < < < < <
|
|
\ 1 1 1 1 1 1 1 1 1 1 2
|
|
\ 0 1 2 3 4 5 6 7 8 9 0
|
|
\ > > > > > > > > > > >
|
|
To \------------------------------------------------------------------
|
|
|
|
RA<0>
|
|
RA<10> 10.0
|
|
RA<11> 10.0
|
|
RA<1> 10.0
|
|
RA<2> 10.0
|
|
RA<3> 10.0
|
|
RA<4> 10.0
|
|
RA<5> 10.0
|
|
RA<6> 10.0
|
|
RA<7> 10.0
|
|
RA<8> 10.0
|
|
RA<9> 10.0
|
|
nDinOE 10.0
|
|
nOE
|
|
nRAMLWE
|
|
nRAMUWE
|
|
nROMCS 10.0
|
|
nROMWE
|
|
|
|
--------------------------------------------------------------------------------
|
|
Pad to Pad (tPD) (nsec)
|
|
|
|
\ From A A A A n n n n
|
|
\ _ _ _ _ A L U W
|
|
\ F F F F S D D E
|
|
\ S S S S _ S S _
|
|
\ B B B B F _ _ F
|
|
\ < < < < S F F S
|
|
\ 2 2 2 9 B S S B
|
|
\ 1 2 3 > B B
|
|
\ > > >
|
|
To \------------------------------------------------
|
|
|
|
RA<0> 10.0
|
|
RA<10>
|
|
RA<11>
|
|
RA<1>
|
|
RA<2>
|
|
RA<3>
|
|
RA<4>
|
|
RA<5>
|
|
RA<6>
|
|
RA<7>
|
|
RA<8>
|
|
RA<9>
|
|
nDinOE 10.0 10.0 10.0 10.0 10.0
|
|
nOE 10.0 10.0
|
|
nRAMLWE 10.0 10.0 10.0
|
|
nRAMUWE 10.0 10.0 10.0
|
|
nROMCS 10.0 10.0 10.0
|
|
nROMWE 10.0 10.0
|
|
|
|
--------------------------------------------------------------------------------
|
|
Clock Pad to Output Pad (tCO) (nsec)
|
|
|
|
\ From C C F
|
|
\ 1 8 C
|
|
\ 6 M L
|
|
\ M K
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
To \------------------
|
|
|
|
nADoutLE0 13.5 13.5
|
|
nADoutLE1 5.8
|
|
nAS_IOB 5.8 14.5
|
|
nAoutOE 5.8
|
|
nBERR_FSB 5.8
|
|
nBR_IOB 5.8
|
|
nCAS 5.8
|
|
nDTACK_FSB 5.8
|
|
nDinLE 5.8
|
|
nDinOE 13.5
|
|
nDoutOE 13.5 13.5
|
|
nLDS_IOB 5.8 14.5
|
|
nRAMLWE 13.5
|
|
nRAMUWE 13.5
|
|
nRAS 5.8
|
|
nRES 14.5
|
|
nROMCS 13.5
|
|
nUDS_IOB 5.8 14.5
|
|
nVMA_IOB 5.8 14.5
|
|
nVPA_FSB 5.8
|
|
|
|
--------------------------------------------------------------------------------
|
|
Setup to Clock at Pad (tSU or tSUF) (nsec)
|
|
|
|
\ From C C F
|
|
\ 1 8 C
|
|
\ 6 M L
|
|
\ M K
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
To \------------------
|
|
|
|
A_FSB<18> 7.5
|
|
A_FSB<19> 7.5
|
|
A_FSB<20> 7.5
|
|
A_FSB<21> 7.5
|
|
A_FSB<22> 7.5
|
|
A_FSB<23> 7.5
|
|
C8M 6.5
|
|
E 6.5 6.5
|
|
nAS_FSB 7.5
|
|
nBERR_IOB 6.5
|
|
nDTACK_IOB 6.5
|
|
nIPL2 6.5
|
|
nLDS_FSB 6.5
|
|
nRES 6.5 6.5
|
|
nUDS_FSB 6.5
|
|
nVPA_IOB 6.5
|
|
nWE_FSB 7.5
|
|
|
|
--------------------------------------------------------------------------------
|
|
Clock to Setup (tCYC) (nsec)
|
|
(Clock: FCLK)
|
|
|
|
\ From I I I I I I R R c c
|
|
\ O O O O O O e e n n
|
|
\ L N P R U W f f t t
|
|
\ 0 P W D 0 R R U / /
|
|
\ . R R R . R e r E E
|
|
\ Q e e E Q E q g r r
|
|
\ a a Q Q . . < <
|
|
\ d d . . Q Q 0 1
|
|
\ y y Q Q > >
|
|
\ . . . .
|
|
\ Q Q Q Q
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
To \------------------------------------------------------------
|
|
|
|
ALE0S.D
|
|
IOL0.D 11.0
|
|
IONPReady.D 10.0
|
|
IOPWReady.D 10.0
|
|
IORDREQ.D 10.0
|
|
IOU0.D 11.0
|
|
IOWRREQ.D 10.0
|
|
RefReq.CE 10.0 10.0
|
|
RefReq.D 10.0
|
|
RefUrg.CE 10.0 10.0
|
|
RefUrg.D 10.0 10.0 10.0
|
|
cnt/Er<1>.D 10.0
|
|
cnt/INITS_FSM_FFd1.D 10.0 10.0
|
|
cnt/INITS_FSM_FFd2.D 10.0 10.0
|
|
cnt/LTimer<0>.CE 10.0 10.0
|
|
cnt/LTimer<10>.CE 10.0 10.0
|
|
cnt/LTimer<10>.D
|
|
cnt/LTimer<11>.CE 10.0 10.0
|
|
cnt/LTimer<11>.D
|
|
cnt/LTimer<12>.CE 10.0 10.0
|
|
cnt/LTimer<12>.D
|
|
cnt/LTimer<1>.CE 10.0 10.0
|
|
cnt/LTimer<1>.D
|
|
cnt/LTimer<2>.CE 10.0 10.0
|
|
cnt/LTimer<2>.D
|
|
cnt/LTimer<3>.CE 10.0 10.0
|
|
cnt/LTimer<3>.D
|
|
cnt/LTimer<4>.CE 10.0 10.0
|
|
cnt/LTimer<4>.D
|
|
cnt/LTimer<5>.CE 10.0 10.0
|
|
cnt/LTimer<5>.D
|
|
cnt/LTimer<6>.CE 10.0 10.0
|
|
cnt/LTimer<6>.D
|
|
cnt/LTimer<7>.CE 10.0 10.0
|
|
cnt/LTimer<7>.D
|
|
cnt/LTimer<8>.CE 10.0 10.0
|
|
cnt/LTimer<8>.D
|
|
cnt/LTimer<9>.CE 10.0 10.0
|
|
cnt/LTimer<9>.D
|
|
cnt/LTimerTC.CE 10.0 10.0
|
|
cnt/LTimerTC.D
|
|
cnt/Timer<0>.CE 10.0 10.0
|
|
cnt/Timer<0>.D 10.0 10.0
|
|
cnt/Timer<1>.CE 10.0 10.0
|
|
cnt/Timer<1>.D 10.0 10.0
|
|
cnt/Timer<2>.CE 10.0 10.0
|
|
cnt/Timer<2>.D 10.0 10.0
|
|
cnt/TimerTC.CE 10.0 10.0
|
|
cnt/TimerTC.D 10.0
|
|
cs/ODCSr.D
|
|
cs/nOverlay.D
|
|
iobs/Clear1.D
|
|
iobs/IOL1.CE
|
|
iobs/IORW1.D
|
|
iobs/IOU1.CE
|
|
iobs/Load1.D
|
|
iobs/Sent.D
|
|
iobs/TS_FSM_FFd1.D
|
|
iobs/TS_FSM_FFd2.D
|
|
nADoutLE1.D
|
|
nAoutOE.D
|
|
nBERR_FSB.D
|
|
nBR_IOB.D
|
|
nCAS.D
|
|
nDTACK_FSB.D 11.0 11.0
|
|
nRAS.D
|
|
nRESout.D
|
|
nVPA_FSB.D 10.0
|
|
ram/BACTr.D
|
|
ram/CAS.D 10.0 10.0
|
|
ram/Once.CE
|
|
ram/Once.D
|
|
ram/RAMEN.D 11.0 11.0
|
|
ram/RS_FSM_FFd1.D
|
|
ram/RS_FSM_FFd2.D
|
|
ram/RS_FSM_FFd3.D
|
|
ram/RS_FSM_FFd4.D
|
|
ram/RS_FSM_FFd6.D 10.0 10.0
|
|
ram/RS_FSM_FFd8.D 10.0 10.0
|
|
ram/RefDone.D 10.0 10.0
|
|
|
|
--------------------------------------------------------------------------------
|
|
Clock to Setup (tCYC) (nsec)
|
|
(Clock: FCLK)
|
|
|
|
\ From c c c c c c c c c c
|
|
\ n n n n n n n n n n
|
|
\ t t t t t t t t t t
|
|
\ / / / / / / / / / /
|
|
\ I I L L L L L L L L
|
|
\ N N T T T T T T T T
|
|
\ I I i i i i i i i i
|
|
\ T T m m m m m m m m
|
|
\ S S e e e e e e e e
|
|
\ _ _ r r r r r r r r
|
|
\ F F < < < < < < < <
|
|
\ S S 0 1 1 1 1 2 3 4
|
|
\ M M > 0 1 2 > > > >
|
|
\ _ _ . > > > . . . .
|
|
\ F F Q . . . Q Q Q Q
|
|
\ F F Q Q Q
|
|
\ d d
|
|
\ 1 2
|
|
\ . .
|
|
\ Q Q
|
|
To \------------------------------------------------------------
|
|
|
|
ALE0S.D
|
|
IOL0.D
|
|
IONPReady.D
|
|
IOPWReady.D
|
|
IORDREQ.D
|
|
IOU0.D
|
|
IOWRREQ.D
|
|
RefReq.CE
|
|
RefReq.D
|
|
RefUrg.CE
|
|
RefUrg.D
|
|
cnt/Er<1>.D
|
|
cnt/INITS_FSM_FFd1.D 10.0 10.0
|
|
cnt/INITS_FSM_FFd2.D 10.0 10.0
|
|
cnt/LTimer<0>.CE
|
|
cnt/LTimer<10>.CE
|
|
cnt/LTimer<10>.D 10.0 10.0 10.0 10.0 10.0
|
|
cnt/LTimer<11>.CE
|
|
cnt/LTimer<11>.D 10.0 10.0 10.0 10.0 10.0 10.0
|
|
cnt/LTimer<12>.CE
|
|
cnt/LTimer<12>.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
|
cnt/LTimer<1>.CE
|
|
cnt/LTimer<1>.D 10.0
|
|
cnt/LTimer<2>.CE
|
|
cnt/LTimer<2>.D 10.0 10.0
|
|
cnt/LTimer<3>.CE
|
|
cnt/LTimer<3>.D 10.0 10.0 10.0
|
|
cnt/LTimer<4>.CE
|
|
cnt/LTimer<4>.D 10.0 10.0 10.0 10.0
|
|
cnt/LTimer<5>.CE
|
|
cnt/LTimer<5>.D 10.0 10.0 10.0 10.0 10.0
|
|
cnt/LTimer<6>.CE
|
|
cnt/LTimer<6>.D 10.0 10.0 10.0 10.0 10.0
|
|
cnt/LTimer<7>.CE
|
|
cnt/LTimer<7>.D 10.0 10.0 10.0 10.0 10.0
|
|
cnt/LTimer<8>.CE
|
|
cnt/LTimer<8>.D 10.0 10.0 10.0 10.0 10.0
|
|
cnt/LTimer<9>.CE
|
|
cnt/LTimer<9>.D 10.0 10.0 10.0 10.0 10.0
|
|
cnt/LTimerTC.CE
|
|
cnt/LTimerTC.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
|
cnt/Timer<0>.CE
|
|
cnt/Timer<0>.D
|
|
cnt/Timer<1>.CE
|
|
cnt/Timer<1>.D
|
|
cnt/Timer<2>.CE
|
|
cnt/Timer<2>.D
|
|
cnt/TimerTC.CE
|
|
cnt/TimerTC.D
|
|
cs/ODCSr.D
|
|
cs/nOverlay.D
|
|
iobs/Clear1.D
|
|
iobs/IOL1.CE
|
|
iobs/IORW1.D
|
|
iobs/IOU1.CE
|
|
iobs/Load1.D
|
|
iobs/Sent.D
|
|
iobs/TS_FSM_FFd1.D
|
|
iobs/TS_FSM_FFd2.D
|
|
nADoutLE1.D
|
|
nAoutOE.D 10.0 10.0
|
|
nBERR_FSB.D
|
|
nBR_IOB.D 10.0 10.0
|
|
nCAS.D
|
|
nDTACK_FSB.D
|
|
nRAS.D
|
|
nRESout.D 10.0 10.0
|
|
nVPA_FSB.D
|
|
ram/BACTr.D
|
|
ram/CAS.D
|
|
ram/Once.CE
|
|
ram/Once.D
|
|
ram/RAMEN.D
|
|
ram/RS_FSM_FFd1.D
|
|
ram/RS_FSM_FFd2.D
|
|
ram/RS_FSM_FFd3.D
|
|
ram/RS_FSM_FFd4.D
|
|
ram/RS_FSM_FFd6.D
|
|
ram/RS_FSM_FFd8.D
|
|
ram/RefDone.D
|
|
|
|
--------------------------------------------------------------------------------
|
|
Clock to Setup (tCYC) (nsec)
|
|
(Clock: FCLK)
|
|
|
|
\ From c c c c c c c c c c
|
|
\ n n n n n n n n n n
|
|
\ t t t t t t t t t t
|
|
\ / / / / / / / / / /
|
|
\ L L L L L L T T T T
|
|
\ T T T T T T i i i i
|
|
\ i i i i i i m m m m
|
|
\ m m m m m m e e e e
|
|
\ e e e e e e r r r r
|
|
\ r r r r r r < < < T
|
|
\ < < < < < T 0 1 2 C
|
|
\ 5 6 7 8 9 C > > > .
|
|
\ > > > > > . . . . Q
|
|
\ . . . . . Q Q Q Q
|
|
\ Q Q Q Q Q
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
To \------------------------------------------------------------
|
|
|
|
ALE0S.D
|
|
IOL0.D
|
|
IONPReady.D
|
|
IOPWReady.D
|
|
IORDREQ.D
|
|
IOU0.D
|
|
IOWRREQ.D
|
|
RefReq.CE
|
|
RefReq.D 10.0 10.0
|
|
RefUrg.CE
|
|
RefUrg.D 10.0 10.0 10.0 10.0
|
|
cnt/Er<1>.D
|
|
cnt/INITS_FSM_FFd1.D 10.0 10.0
|
|
cnt/INITS_FSM_FFd2.D 10.0 10.0
|
|
cnt/LTimer<0>.CE 10.0
|
|
cnt/LTimer<10>.CE 10.0
|
|
cnt/LTimer<10>.D 10.0 10.0 10.0 10.0 10.0
|
|
cnt/LTimer<11>.CE 10.0
|
|
cnt/LTimer<11>.D 10.0 10.0 10.0 10.0 10.0
|
|
cnt/LTimer<12>.CE 10.0
|
|
cnt/LTimer<12>.D 10.0 10.0 10.0 10.0 10.0
|
|
cnt/LTimer<1>.CE 10.0
|
|
cnt/LTimer<1>.D
|
|
cnt/LTimer<2>.CE 10.0
|
|
cnt/LTimer<2>.D
|
|
cnt/LTimer<3>.CE 10.0
|
|
cnt/LTimer<3>.D
|
|
cnt/LTimer<4>.CE 10.0
|
|
cnt/LTimer<4>.D
|
|
cnt/LTimer<5>.CE 10.0
|
|
cnt/LTimer<5>.D
|
|
cnt/LTimer<6>.CE 10.0
|
|
cnt/LTimer<6>.D 10.0
|
|
cnt/LTimer<7>.CE 10.0
|
|
cnt/LTimer<7>.D 10.0 10.0
|
|
cnt/LTimer<8>.CE 10.0
|
|
cnt/LTimer<8>.D 10.0 10.0 10.0
|
|
cnt/LTimer<9>.CE 10.0
|
|
cnt/LTimer<9>.D 10.0 10.0 10.0 10.0
|
|
cnt/LTimerTC.CE 10.0
|
|
cnt/LTimerTC.D 10.0 10.0 10.0 10.0 10.0
|
|
cnt/Timer<0>.CE
|
|
cnt/Timer<0>.D 10.0 10.0
|
|
cnt/Timer<1>.CE
|
|
cnt/Timer<1>.D 10.0 10.0 10.0
|
|
cnt/Timer<2>.CE
|
|
cnt/Timer<2>.D 10.0 10.0 10.0 10.0
|
|
cnt/TimerTC.CE
|
|
cnt/TimerTC.D 10.0 10.0 10.0
|
|
cs/ODCSr.D
|
|
cs/nOverlay.D
|
|
iobs/Clear1.D
|
|
iobs/IOL1.CE
|
|
iobs/IORW1.D
|
|
iobs/IOU1.CE
|
|
iobs/Load1.D
|
|
iobs/Sent.D
|
|
iobs/TS_FSM_FFd1.D
|
|
iobs/TS_FSM_FFd2.D
|
|
nADoutLE1.D
|
|
nAoutOE.D
|
|
nBERR_FSB.D
|
|
nBR_IOB.D
|
|
nCAS.D
|
|
nDTACK_FSB.D
|
|
nRAS.D
|
|
nRESout.D
|
|
nVPA_FSB.D
|
|
ram/BACTr.D
|
|
ram/CAS.D
|
|
ram/Once.CE
|
|
ram/Once.D
|
|
ram/RAMEN.D
|
|
ram/RS_FSM_FFd1.D
|
|
ram/RS_FSM_FFd2.D
|
|
ram/RS_FSM_FFd3.D
|
|
ram/RS_FSM_FFd4.D
|
|
ram/RS_FSM_FFd6.D
|
|
ram/RS_FSM_FFd8.D
|
|
ram/RefDone.D
|
|
|
|
--------------------------------------------------------------------------------
|
|
Clock to Setup (tCYC) (nsec)
|
|
(Clock: FCLK)
|
|
|
|
\ From c c c f i i i i i i
|
|
\ n s s s o o o o o o
|
|
\ t / / b b b b b b b
|
|
\ / O n / s s s s s s
|
|
\ n D O A / / / / / /
|
|
\ I C v S C I I I I I
|
|
\ P S e r l O O O O O
|
|
\ L r r f e A D L R U
|
|
\ 2 . l . a C O 1 W 1
|
|
\ r Q a Q r T N . 1 .
|
|
\ . y 1 r E Q . Q
|
|
\ Q . . . r Q
|
|
\ Q Q Q <
|
|
\ 0
|
|
\ >
|
|
\ .
|
|
\ Q
|
|
\
|
|
\
|
|
\
|
|
To \------------------------------------------------------------
|
|
|
|
ALE0S.D
|
|
IOL0.D 11.0 11.0 11.0
|
|
IONPReady.D 11.0 10.0
|
|
IOPWReady.D 10.0 10.0
|
|
IORDREQ.D 11.0 11.0 10.0 11.0
|
|
IOU0.D 11.0 11.0 11.0
|
|
IOWRREQ.D 11.0 11.0 10.0 11.0
|
|
RefReq.CE
|
|
RefReq.D
|
|
RefUrg.CE
|
|
RefUrg.D
|
|
cnt/Er<1>.D
|
|
cnt/INITS_FSM_FFd1.D 10.0
|
|
cnt/INITS_FSM_FFd2.D
|
|
cnt/LTimer<0>.CE
|
|
cnt/LTimer<10>.CE
|
|
cnt/LTimer<10>.D
|
|
cnt/LTimer<11>.CE
|
|
cnt/LTimer<11>.D
|
|
cnt/LTimer<12>.CE
|
|
cnt/LTimer<12>.D
|
|
cnt/LTimer<1>.CE
|
|
cnt/LTimer<1>.D
|
|
cnt/LTimer<2>.CE
|
|
cnt/LTimer<2>.D
|
|
cnt/LTimer<3>.CE
|
|
cnt/LTimer<3>.D
|
|
cnt/LTimer<4>.CE
|
|
cnt/LTimer<4>.D
|
|
cnt/LTimer<5>.CE
|
|
cnt/LTimer<5>.D
|
|
cnt/LTimer<6>.CE
|
|
cnt/LTimer<6>.D
|
|
cnt/LTimer<7>.CE
|
|
cnt/LTimer<7>.D
|
|
cnt/LTimer<8>.CE
|
|
cnt/LTimer<8>.D
|
|
cnt/LTimer<9>.CE
|
|
cnt/LTimer<9>.D
|
|
cnt/LTimerTC.CE
|
|
cnt/LTimerTC.D
|
|
cnt/Timer<0>.CE
|
|
cnt/Timer<0>.D
|
|
cnt/Timer<1>.CE
|
|
cnt/Timer<1>.D
|
|
cnt/Timer<2>.CE
|
|
cnt/Timer<2>.D
|
|
cnt/TimerTC.CE
|
|
cnt/TimerTC.D
|
|
cs/ODCSr.D 10.0
|
|
cs/nOverlay.D 10.0 10.0 10.0
|
|
iobs/Clear1.D
|
|
iobs/IOL1.CE
|
|
iobs/IORW1.D 10.0 10.0
|
|
iobs/IOU1.CE
|
|
iobs/Load1.D 10.0
|
|
iobs/Sent.D 11.0 10.0
|
|
iobs/TS_FSM_FFd1.D 10.0
|
|
iobs/TS_FSM_FFd2.D 11.0 11.0 10.0
|
|
nADoutLE1.D 10.0
|
|
nAoutOE.D
|
|
nBERR_FSB.D 10.0
|
|
nBR_IOB.D 10.0
|
|
nCAS.D
|
|
nDTACK_FSB.D 10.0
|
|
nRAS.D
|
|
nRESout.D
|
|
nVPA_FSB.D 10.0
|
|
ram/BACTr.D 11.0
|
|
ram/CAS.D 10.0
|
|
ram/Once.CE 10.0
|
|
ram/Once.D 10.0
|
|
ram/RAMEN.D 11.0
|
|
ram/RS_FSM_FFd1.D
|
|
ram/RS_FSM_FFd2.D
|
|
ram/RS_FSM_FFd3.D
|
|
ram/RS_FSM_FFd4.D
|
|
ram/RS_FSM_FFd6.D 10.0
|
|
ram/RS_FSM_FFd8.D 10.0
|
|
ram/RefDone.D
|
|
|
|
--------------------------------------------------------------------------------
|
|
Clock to Setup (tCYC) (nsec)
|
|
(Clock: FCLK)
|
|
|
|
\ From i i i i n n n n r r
|
|
\ o o o o A A B B a a
|
|
\ b b b b D o E R m m
|
|
\ s s s s o u R _ / /
|
|
\ / / / / u t R I B C
|
|
\ L S T T t O _ O A A
|
|
\ o e S S L E F B C S
|
|
\ a n _ _ E . S . T .
|
|
\ d t F F 1 Q B Q r Q
|
|
\ 1 . S S . . .
|
|
\ . Q M M Q Q Q
|
|
\ Q _ _
|
|
\ F F
|
|
\ F F
|
|
\ d d
|
|
\ 1 2
|
|
\ . .
|
|
\ Q Q
|
|
\
|
|
\
|
|
To \------------------------------------------------------------
|
|
|
|
ALE0S.D 10.0
|
|
IOL0.D 10.0 10.0 11.0 11.0
|
|
IONPReady.D 10.0
|
|
IOPWReady.D 10.0
|
|
IORDREQ.D 10.0 10.0 11.0 11.0
|
|
IOU0.D 10.0 10.0 11.0 11.0
|
|
IOWRREQ.D 10.0 10.0 11.0 11.0
|
|
RefReq.CE
|
|
RefReq.D
|
|
RefUrg.CE
|
|
RefUrg.D
|
|
cnt/Er<1>.D
|
|
cnt/INITS_FSM_FFd1.D
|
|
cnt/INITS_FSM_FFd2.D
|
|
cnt/LTimer<0>.CE
|
|
cnt/LTimer<10>.CE
|
|
cnt/LTimer<10>.D
|
|
cnt/LTimer<11>.CE
|
|
cnt/LTimer<11>.D
|
|
cnt/LTimer<12>.CE
|
|
cnt/LTimer<12>.D
|
|
cnt/LTimer<1>.CE
|
|
cnt/LTimer<1>.D
|
|
cnt/LTimer<2>.CE
|
|
cnt/LTimer<2>.D
|
|
cnt/LTimer<3>.CE
|
|
cnt/LTimer<3>.D
|
|
cnt/LTimer<4>.CE
|
|
cnt/LTimer<4>.D
|
|
cnt/LTimer<5>.CE
|
|
cnt/LTimer<5>.D
|
|
cnt/LTimer<6>.CE
|
|
cnt/LTimer<6>.D
|
|
cnt/LTimer<7>.CE
|
|
cnt/LTimer<7>.D
|
|
cnt/LTimer<8>.CE
|
|
cnt/LTimer<8>.D
|
|
cnt/LTimer<9>.CE
|
|
cnt/LTimer<9>.D
|
|
cnt/LTimerTC.CE
|
|
cnt/LTimerTC.D
|
|
cnt/Timer<0>.CE
|
|
cnt/Timer<0>.D
|
|
cnt/Timer<1>.CE
|
|
cnt/Timer<1>.D
|
|
cnt/Timer<2>.CE
|
|
cnt/Timer<2>.D
|
|
cnt/TimerTC.CE
|
|
cnt/TimerTC.D
|
|
cs/ODCSr.D
|
|
cs/nOverlay.D
|
|
iobs/Clear1.D 10.0 10.0
|
|
iobs/IOL1.CE 10.0
|
|
iobs/IORW1.D 10.0 10.0 10.0 10.0
|
|
iobs/IOU1.CE 10.0
|
|
iobs/Load1.D 10.0 10.0 10.0 10.0
|
|
iobs/Sent.D 11.0 11.0 11.0 10.0
|
|
iobs/TS_FSM_FFd1.D 10.0 10.0
|
|
iobs/TS_FSM_FFd2.D 10.0 10.0 11.0 11.0
|
|
nADoutLE1.D 10.0 10.0
|
|
nAoutOE.D 10.0 10.0
|
|
nBERR_FSB.D 10.0 10.0
|
|
nBR_IOB.D 10.0
|
|
nCAS.D 10.0
|
|
nDTACK_FSB.D
|
|
nRAS.D
|
|
nRESout.D
|
|
nVPA_FSB.D
|
|
ram/BACTr.D
|
|
ram/CAS.D 10.0
|
|
ram/Once.CE
|
|
ram/Once.D
|
|
ram/RAMEN.D 11.0
|
|
ram/RS_FSM_FFd1.D
|
|
ram/RS_FSM_FFd2.D
|
|
ram/RS_FSM_FFd3.D
|
|
ram/RS_FSM_FFd4.D
|
|
ram/RS_FSM_FFd6.D 10.0
|
|
ram/RS_FSM_FFd8.D 10.0
|
|
ram/RefDone.D
|
|
|
|
--------------------------------------------------------------------------------
|
|
Clock to Setup (tCYC) (nsec)
|
|
(Clock: FCLK)
|
|
|
|
\ From r r r r r r r r r
|
|
\ a a a a a a a a a
|
|
\ m m m m m m m m m
|
|
\ / / / / / / / / /
|
|
\ O R R R R R R R R
|
|
\ n A S S S S S S e
|
|
\ c M _ _ _ _ _ _ f
|
|
\ e E F F F F F F D
|
|
\ . N S S S S S S o
|
|
\ Q . M M M M M M n
|
|
\ Q _ _ _ _ _ _ e
|
|
\ F F F F F F .
|
|
\ F F F F F F Q
|
|
\ d d d d d d
|
|
\ 1 2 3 4 6 8
|
|
\ . . . . . .
|
|
\ Q Q Q Q Q Q
|
|
\
|
|
\
|
|
\
|
|
To \------------------------------------------------------
|
|
|
|
ALE0S.D
|
|
IOL0.D
|
|
IONPReady.D
|
|
IOPWReady.D
|
|
IORDREQ.D
|
|
IOU0.D
|
|
IOWRREQ.D
|
|
RefReq.CE
|
|
RefReq.D
|
|
RefUrg.CE
|
|
RefUrg.D
|
|
cnt/Er<1>.D
|
|
cnt/INITS_FSM_FFd1.D
|
|
cnt/INITS_FSM_FFd2.D
|
|
cnt/LTimer<0>.CE
|
|
cnt/LTimer<10>.CE
|
|
cnt/LTimer<10>.D
|
|
cnt/LTimer<11>.CE
|
|
cnt/LTimer<11>.D
|
|
cnt/LTimer<12>.CE
|
|
cnt/LTimer<12>.D
|
|
cnt/LTimer<1>.CE
|
|
cnt/LTimer<1>.D
|
|
cnt/LTimer<2>.CE
|
|
cnt/LTimer<2>.D
|
|
cnt/LTimer<3>.CE
|
|
cnt/LTimer<3>.D
|
|
cnt/LTimer<4>.CE
|
|
cnt/LTimer<4>.D
|
|
cnt/LTimer<5>.CE
|
|
cnt/LTimer<5>.D
|
|
cnt/LTimer<6>.CE
|
|
cnt/LTimer<6>.D
|
|
cnt/LTimer<7>.CE
|
|
cnt/LTimer<7>.D
|
|
cnt/LTimer<8>.CE
|
|
cnt/LTimer<8>.D
|
|
cnt/LTimer<9>.CE
|
|
cnt/LTimer<9>.D
|
|
cnt/LTimerTC.CE
|
|
cnt/LTimerTC.D
|
|
cnt/Timer<0>.CE
|
|
cnt/Timer<0>.D
|
|
cnt/Timer<1>.CE
|
|
cnt/Timer<1>.D
|
|
cnt/Timer<2>.CE
|
|
cnt/Timer<2>.D
|
|
cnt/TimerTC.CE
|
|
cnt/TimerTC.D
|
|
cs/ODCSr.D
|
|
cs/nOverlay.D
|
|
iobs/Clear1.D
|
|
iobs/IOL1.CE
|
|
iobs/IORW1.D
|
|
iobs/IOU1.CE
|
|
iobs/Load1.D
|
|
iobs/Sent.D
|
|
iobs/TS_FSM_FFd1.D
|
|
iobs/TS_FSM_FFd2.D
|
|
nADoutLE1.D
|
|
nAoutOE.D
|
|
nBERR_FSB.D
|
|
nBR_IOB.D
|
|
nCAS.D
|
|
nDTACK_FSB.D
|
|
nRAS.D 10.0 10.0
|
|
nRESout.D
|
|
nVPA_FSB.D
|
|
ram/BACTr.D
|
|
ram/CAS.D 10.0 10.0 10.0 10.0
|
|
ram/Once.CE
|
|
ram/Once.D
|
|
ram/RAMEN.D 10.0 10.0 10.0 11.0 11.0
|
|
ram/RS_FSM_FFd1.D 10.0
|
|
ram/RS_FSM_FFd2.D 10.0
|
|
ram/RS_FSM_FFd3.D 10.0
|
|
ram/RS_FSM_FFd4.D 10.0
|
|
ram/RS_FSM_FFd6.D 10.0 10.0 10.0
|
|
ram/RS_FSM_FFd8.D 10.0 10.0 10.0 10.0
|
|
ram/RefDone.D 10.0 10.0 10.0
|
|
|
|
--------------------------------------------------------------------------------
|
|
Clock to Setup (tCYC) (nsec)
|
|
(Clock: C16M)
|
|
|
|
\ From A I i i i i i i i i
|
|
\ L O o o o o o o o o
|
|
\ E A b b b b b b b b
|
|
\ 0 C m m m m m m m m
|
|
\ M T / / / / / / / /
|
|
\ . . C D I I I I I I
|
|
\ Q Q 8 o O O O O O O
|
|
\ M u R S S S S S
|
|
\ r t D 0 _ _ _ _
|
|
\ . O R . F F F F
|
|
\ Q E E Q S S S S
|
|
\ . Q M M M M
|
|
\ Q r _ _ _ _
|
|
\ . F F F F
|
|
\ Q F F F F
|
|
\ d d d d
|
|
\ 1 2 3 4
|
|
\ . . . .
|
|
\ Q Q Q Q
|
|
To \------------------------------------------------------------
|
|
|
|
ALE0M.D 10.0 10.0 10.0 10.0 10.0 10.0
|
|
IOACT.D 11.0 10.0 10.0 11.0 11.0 11.0 10.0
|
|
iobm/DoutOE.D 10.0 10.0 10.0 10.0
|
|
iobm/IOS0.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
|
iobm/IOS_FSM_FFd1.D 10.0
|
|
iobm/IOS_FSM_FFd2.D 10.0 10.0
|
|
iobm/IOS_FSM_FFd3.D 10.0 10.0 10.0
|
|
iobm/IOS_FSM_FFd4.D
|
|
iobm/IOS_FSM_FFd5.D
|
|
iobm/IOS_FSM_FFd6.D 10.0 10.0
|
|
iobm/IOS_FSM_FFd7.D 10.0 10.0 10.0
|
|
nAS_IOB.D 10.0 10.0 10.0 10.0
|
|
nDinLE.D 10.0 10.0
|
|
nLDS_IOB.D 11.0 11.0 10.0 10.0
|
|
nUDS_IOB.D 11.0 11.0 10.0 10.0
|
|
|
|
--------------------------------------------------------------------------------
|
|
Clock to Setup (tCYC) (nsec)
|
|
(Clock: C16M)
|
|
|
|
\ From i i i i n n
|
|
\ o o o o L U
|
|
\ b b b b D D
|
|
\ m m m m S S
|
|
\ / / / / _ _
|
|
\ I I I I I I
|
|
\ O O O O O O
|
|
\ S S S W B B
|
|
\ _ _ _ R . .
|
|
\ F F F R Q Q
|
|
\ S S S E
|
|
\ M M M Q
|
|
\ _ _ _ r
|
|
\ F F F .
|
|
\ F F F Q
|
|
\ d d d
|
|
\ 5 6 7
|
|
\ . . .
|
|
\ Q Q Q
|
|
To \------------------------------------
|
|
|
|
ALE0M.D 10.0 10.0 10.0 10.0
|
|
IOACT.D 10.0 10.0 11.0 11.0
|
|
iobm/DoutOE.D 10.0 10.0 10.0 10.0
|
|
iobm/IOS0.D 10.0 10.0 10.0 10.0
|
|
iobm/IOS_FSM_FFd1.D
|
|
iobm/IOS_FSM_FFd2.D
|
|
iobm/IOS_FSM_FFd3.D
|
|
iobm/IOS_FSM_FFd4.D 10.0
|
|
iobm/IOS_FSM_FFd5.D 10.0
|
|
iobm/IOS_FSM_FFd6.D 10.0 10.0
|
|
iobm/IOS_FSM_FFd7.D 10.0 10.0
|
|
nAS_IOB.D 10.0 10.0 10.0 10.0
|
|
nDinLE.D
|
|
nLDS_IOB.D 10.0 10.0 11.0 10.0
|
|
nUDS_IOB.D 10.0 10.0 11.0 10.0
|
|
|
|
--------------------------------------------------------------------------------
|
|
Clock to Setup (tCYC) (nsec)
|
|
(Clock: C8M)
|
|
|
|
\ From i i i i i i n
|
|
\ o o o o o o V
|
|
\ b b b b b b M
|
|
\ m m m m m m A
|
|
\ / / / / / / _
|
|
\ E E E E E V I
|
|
\ S S S S r P O
|
|
\ < < < < . A B
|
|
\ 0 1 2 3 Q r .
|
|
\ > > > > . Q
|
|
\ . . . . Q
|
|
\ Q Q Q Q
|
|
To \------------------------------------------
|
|
|
|
IODONE.D 11.0 11.0 11.0 11.0 11.0
|
|
iobm/ES<0>.D 10.0 10.0 10.0 10.0 10.0
|
|
iobm/ES<1>.D 10.0 10.0 10.0 10.0 10.0
|
|
iobm/ES<2>.D 10.0 10.0 10.0 10.0
|
|
iobm/ES<3>.D 10.0 10.0 10.0 10.0 10.0
|
|
nVMA_IOB.D 10.0 10.0 10.0 10.0 10.0 10.0
|
|
|
|
Path Type Definition:
|
|
|
|
Pad to Pad (tPD) - Reports pad to pad paths that start
|
|
at input pads and end at output pads.
|
|
Paths are not traced through
|
|
registers.
|
|
|
|
Clock Pad to Output Pad (tCO) - Reports paths that start at input
|
|
pads trace through clock inputs of
|
|
registers and end at output pads.
|
|
Paths are not traced through PRE/CLR
|
|
inputs of registers.
|
|
|
|
Setup to Clock at Pad (tSU or tSUF) - Reports external setup time of data
|
|
to clock at pad. Data path starts at
|
|
an input pad and ends at register
|
|
(Fast Input Register for tSUF) D/T
|
|
input. Clock path starts at input pad
|
|
and ends at the register clock input.
|
|
Paths are not traced through
|
|
registers. Pin-to-pin setup
|
|
requirement is not reported or
|
|
guaranteed for product-term clocks
|
|
derived from macrocell feedback
|
|
signals.
|
|
|
|
Clock to Setup (tCYC) - Register to register cycle time.
|
|
Include source register tCO and
|
|
destination register tSU. Note that
|
|
when the computed Maximum Clock Speed
|
|
is limited by tCYC it is computed
|
|
assuming that all registers are
|
|
rising-edge sensitive.
|
|
|