mirror of
https://github.com/garrettsworkshop/Warp-SE.git
synced 2024-11-16 00:10:12 +00:00
14 lines
226 B
Verilog
14 lines
226 B
Verilog
module CLK(
|
|
input CLK, output reg [2:0] SS,
|
|
output reg MCLK, output RCLK);
|
|
|
|
always @(posedge CLK) begin
|
|
SS[1:0] <= SS[1:0]+1;
|
|
end
|
|
|
|
always @(posedge CLK) begin
|
|
MCLK <= SS[1:0]==2'b01 || SS[1:0]==2'b10;
|
|
end
|
|
|
|
endmodule
|