mirror of
https://github.com/garrettsworkshop/Warp-SE.git
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244 lines
6.7 KiB
HTML
244 lines
6.7 KiB
HTML
<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
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<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
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<center><big><big><b>System Settings</b></big></big></center><br>
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<A NAME="Environment Settings"></A>
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<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
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<TD ALIGN=CENTER COLSPAN='3'><B> Environment Settings </B></TD>
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</tr>
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<tr bgcolor='#ffff99'>
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<td><b>Environment Variable</b></td>
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<td><b>xst</b></td>
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<td><b>ngdbuild</b></td>
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</tr>
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<tr>
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<td>PATHEXT</td>
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<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
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<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
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</tr>
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<tr>
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<td>Path</td>
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<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\Program Files (x86)\AMD APP\bin\x86_64;<br>C:\Program Files (x86)\AMD APP\bin\x86;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\intelFPGA_lite\19.1\modelsim_ase\win32aloem;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\Wolf\AppData\Local\GitHubDesktop\bin</td>
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<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\Program Files (x86)\AMD APP\bin\x86_64;<br>C:\Program Files (x86)\AMD APP\bin\x86;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\intelFPGA_lite\19.1\modelsim_ase\win32aloem;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\Wolf\AppData\Local\GitHubDesktop\bin</td>
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</tr>
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<tr>
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<td>XILINX</td>
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<td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
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<td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
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</tr>
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<tr>
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<td>XILINX_DSP</td>
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<td>C:\Xilinx\14.7\ISE_DS\ISE</td>
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<td>C:\Xilinx\14.7\ISE_DS\ISE</td>
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</tr>
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<tr>
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<td>XILINX_EDK</td>
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<td>C:\Xilinx\14.7\ISE_DS\EDK</td>
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<td>C:\Xilinx\14.7\ISE_DS\EDK</td>
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</tr>
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<tr>
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<td>XILINX_PLANAHEAD</td>
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<td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
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<td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
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</tr>
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</TABLE>
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<A NAME="Synthesis Property Settings"></A>
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<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
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<TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
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</tr>
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<tr bgcolor='#ffff99'>
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<td><b>Switch Name</b></td>
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<td><b>Property Name</b></td>
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<td><b>Value</b></td>
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<td><b>Default Value</b></td>
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</tr>
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<tr>
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<td>-ifn</td>
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<td> </td>
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<td>WarpSE.prj</td>
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<td> </td>
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</tr>
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<tr>
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<td>-ifmt</td>
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<td> </td>
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<td>mixed</td>
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<td>MIXED</td>
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</tr>
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<tr>
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<td>-ofn</td>
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<td> </td>
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<td>WarpSE</td>
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<td> </td>
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</tr>
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<tr>
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<td>-ofmt</td>
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<td> </td>
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<td>NGC</td>
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<td>NGC</td>
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</tr>
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<tr>
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<td>-p</td>
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<td> </td>
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<td>xc9500xl</td>
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<td> </td>
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</tr>
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<tr>
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<td>-top</td>
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<td> </td>
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<td>WarpSE</td>
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<td> </td>
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</tr>
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<tr>
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<td>-opt_mode</td>
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<td>Optimization Goal</td>
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<td>Speed</td>
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<td>SPEED</td>
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</tr>
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<tr>
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<td>-opt_level</td>
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<td>Optimization Effort</td>
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<td>1</td>
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<td>1</td>
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</tr>
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<tr>
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<td>-iuc</td>
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<td>Use synthesis Constraints File</td>
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<td>NO</td>
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<td>NO</td>
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</tr>
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<tr>
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<td>-keep_hierarchy</td>
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<td>Keep Hierarchy</td>
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<td>Yes</td>
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<td>YES</td>
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</tr>
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<tr>
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<td>-netlist_hierarchy</td>
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<td>Netlist Hierarchy</td>
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<td>As_Optimized</td>
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<td>as_optimized</td>
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</tr>
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<tr>
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<td>-rtlview</td>
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<td>Generate RTL Schematic</td>
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<td>Yes</td>
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<td>NO</td>
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</tr>
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<tr>
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<td>-bus_delimiter</td>
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<td>Bus Delimiter</td>
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<td><></td>
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<td><></td>
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</tr>
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<tr>
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<td>-verilog2001</td>
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<td>Verilog 2001</td>
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<td>YES</td>
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<td>YES</td>
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</tr>
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<tr>
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<td>-fsm_extract</td>
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<td> </td>
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<td>YES</td>
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<td>YES</td>
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</tr>
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<tr>
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<td>-fsm_encoding</td>
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<td> </td>
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<td>Auto</td>
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<td>AUTO</td>
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</tr>
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<tr>
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<td>-safe_implementation</td>
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<td> </td>
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<td>No</td>
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<td>NO</td>
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</tr>
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<tr>
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<td>-resource_sharing</td>
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<td> </td>
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<td>YES</td>
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<td>YES</td>
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</tr>
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<tr>
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<td>-iobuf</td>
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<td> </td>
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<td>YES</td>
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<td>YES</td>
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</tr>
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<tr>
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<td>-equivalent_register_removal</td>
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<td> </td>
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<td>YES</td>
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<td>YES</td>
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</tr>
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</TABLE>
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<A NAME="Translation Property Settings"></A>
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<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
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<TD ALIGN=CENTER COLSPAN='4'><B>Translation Property Settings </B></TD>
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</tr>
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<tr bgcolor='#ffff99'>
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<td><b>Switch Name</b></td>
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<td><b>Property Name</b></td>
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<td><b>Value</b></td>
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<td><b>Default Value</b></td>
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</tr>
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<tr>
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<td>-intstyle</td>
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<td> </td>
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<td>ise</td>
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<td>None</td>
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</tr>
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<tr>
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<td>-dd</td>
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<td> </td>
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<td>_ngo</td>
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<td>None</td>
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</tr>
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<tr>
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<td>-p</td>
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<td> </td>
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<td>xc95144xl-TQ100-10</td>
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<td>None</td>
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</tr>
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<tr>
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<td>-uc</td>
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<td> </td>
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<td>WarpSE-XC95144XL.ucf</td>
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<td>None</td>
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</tr>
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</TABLE>
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<A NAME="Operating System Information"></A>
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<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
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<TD ALIGN=CENTER COLSPAN='3'><B> Operating System Information </B></TD>
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</tr>
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<tr bgcolor='#ffff99'>
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<td><b>Operating System Information</b></td>
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<td><b>xst</b></td>
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<td><b>ngdbuild</b></td>
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</tr>
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<tr>
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<td>CPU Architecture/Speed</td>
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<td>AMD FX(tm)-8320 Eight-Core Processor /3792 MHz</td>
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<td>AMD FX(tm)-8320 Eight-Core Processor /3792 MHz</td>
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</tr>
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<tr>
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<td>Host</td>
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<td>LabWin7</td>
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<td>LabWin7</td>
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</tr>
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<tr>
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<td>OS Name</td>
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<td>Microsoft Windows 7 , 64-bit</td>
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<td>Microsoft Windows 7 , 64-bit</td>
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</tr>
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<tr>
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<td>OS Release</td>
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<td>Service Pack 1 (build 7601)</td>
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<td>Service Pack 1 (build 7601)</td>
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</tr>
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</TABLE>
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</BODY> </HTML> |