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BBU work-in-progress, fix a few documentation issues.
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@ -28,8 +28,8 @@ a huge number of pins, its purpose can be summarized as follows.
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* 2 (0x800000-0xbfffff): Select SCC.
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* 3 (0xc00000-0xffffff): Select IWM or VIA.
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In particular, the zones are further subdivided as follows,
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according to MESS/MAME source code:
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In particular, the zones are further subdivided as follows for the
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Macintosh Plus, according to MESS/MAME source code:
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* 0x000000 - 0x3fffff: RAM/ROM (switches based on overlay)
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* 0x400000 - 0x4fffff: ROM
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@ -42,22 +42,46 @@ a huge number of pins, its purpose can be summarized as follows.
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* 0xf00000 - 0xffffef: ??? (the ROM appears to be accessing here)
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* 0xfffff0 - 0xffffff: Auto Vector
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The Macintosh SE goes a step further and adds invalid address guard
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zones around the SCC and IWM mappings:
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* 0x000000 - 0x3fffff: RAM/ROM (switches based on overlay)
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* 0x400000 - 0x4fffff: ROM
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* 0x580000 - 0x5fffff: 5380 NCR/Symbios SCSI peripherals chip
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* 0x600000 - 0x6fffff: RAM, boot-time overlay only
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* 0x900000 - 0x9fffff: Zilog 8530 SCC (Serial Control Chip) Read
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* 0xb00000 - 0xbfffff: Zilog 8530 SCC (Serial Control Chip) Write
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* 0xd00000 - 0xdfffff: IWM (Integrated Woz Machine; floppy)
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* 0xe80000 - 0xefffff: Rockwell 6522 VIA
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* 0xf00000 - 0xffffef: ??? (the ROM appears to be accessing here)
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* 0xfffff0 - 0xffffff: Auto Vector
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Note that all of these address ranges specified can be handled by
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only checking the upper 5 bits of the address (A19-A23), which route
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directly into the BBU from the main address bus. Well, except for
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the last one, but our BBU doens't need to do any specially handling
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for the sake of that zone.
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* Control the RAM and ROM switches to expose the ROM overlay at
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0x000000 and RAM at 0x600000 at startup.
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TODO VERIFY: Does the Macintosh Plus and Macintosh SE really not
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expose the boot-time RAM address remapping, just the ROM address
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remapping? This is what MESS/MAME source code seems to claim.
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* Set the ROM/RAM control signals depending on the particular address
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requested, i.e. `*EN245`, `*ROMEN`, `*RAS`, `*CAS0L`, `*CAS0H`,
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`*CAS1L`, `*CAS1H`, `RAM R/*W`. `*PMCYC` is apparently used to
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totally disable DRAM row and column access strobes only during
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startup. The F257 chips are used to select separate address
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portions for the DRAM row and column access strobes. The LS245
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chips are used to disable DRAM access during ROM access.
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* Control the RAM and ROM switches to expose the ROM overlay at
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0x000000 and RAM at 0x600000 at startup. Snoop the address bus to
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detect the first access to the standard ROM address mapping and
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disable the boot-time ROM overlay, until the next RESET.
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Also, apparently, according to MESS/MAME source code, the first
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write to the regular RAM address zone also disables the ROM overlay.
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* Act as a DRAM controller. Set the ROM/RAM control signals depending
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on the particular address requested, i.e. `*EN245`, `*ROMEN`,
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`*RAS`, `*CAS0L`, `*CAS0H`, `*CAS1L`, `*CAS1H`, `RAM R/*W`.
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`*PMCYC` is apparently used to totally disable DRAM row and column
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access strobes only during startup. The F257 chips are used to
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select separate address portions for the DRAM row and column access
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strobes. The LS245 chips are used to disable DRAM access during ROM
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access.
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DRAM is accessed by sending the row access strobe first, the column
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access strobe second.
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@ -73,12 +97,13 @@ a huge number of pins, its purpose can be summarized as follows.
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much RAM is installed.
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If only 64K RAM SIMMs are installed (which is an unsupported
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configuration), then RA7 is either A10 (row) or A9 (column). If
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there are two rows of DRAM SIMMs, A17 is used to determine which one
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to use. It could be possible that one of the unused, unlabeled BBU
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pins controls this setting. With the minimum configuration of one
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row of DRAM SIMMs, this means you can configure a Macintosh SE with
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only 128K of RAM. Hilarious!
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configuration), then RA7 is either A9 (row) or A10 (column). Bus
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snooping must be used to copy RA8 over to RA7 on the column access
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strobe. If there are two rows of DRAM SIMMs, A17 is used to
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determine which one to use. It could be possible that one of the
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unused, unlabeled BBU pins controls this setting. With the minimum
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configuration of one row of DRAM SIMMs, this means you can configure
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a Macintosh SE with only 128K of RAM. Hilarious!
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If only 256K RAM SIMMs are installed, then RA7 is either A17 (row)
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or A9 (column). RA9 is not used. If there are two rows of DRAM
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@ -125,7 +150,9 @@ a huge number of pins, its purpose can be summarized as follows.
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the same time.
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* Generate the PWM signals for sound output and disk drive speed
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control. Read directly from RAM buffers as required.
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control. Read directly from RAM buffers as required. Note that the
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Macintosh SE deprecated the alternate sound buffer found in previous
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compact Macintoshes.
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* Handle SCSI DMA transfers, if the mode is enabled by the ROM.
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However, as I understand it, the Macintosh SE ROM does not actually
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