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Documentation updates.
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@ -45,7 +45,8 @@ a huge number of pins, its purpose can be summarized as follows.
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* 0xfffff0 - 0xffffff: Auto Vector
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The Macintosh SE goes a step further and adds invalid address guard
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zones around the SCC and IWM mappings:
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zones around the SCC and IWM mappings... these are simply available
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for use by PDS expansion cards:
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* 0x000000 - 0x3fffff: RAM/ROM (switches based on overlay)
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* 0x400000 - 0x4fffff: ROM
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@ -218,17 +219,17 @@ DRAM. Guide to the Macintosh family hardware, page 84.
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* `RA9` is only controlled when the `MBRAM` input is TRUE, i.e. +5V.
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This indicates that 1MB RAM SIMMs are being used. Otherwise, it is
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kept at zero and high memory addresses are marked as bus errors.
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256K RAM SIMMs are used in this case.
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kept at zero and high memory addresses wrap around. 256K RAM SIMMs
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are used in this case.
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* When `ROW2` input is TRUE, i.e. +5V, it indicates that both RAM SIMM
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rows are in use. Otherwise, only the first row of RAM SIMM is used
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and high addresses are marked as bus errors. And, `CAS1L` and
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`CAS1H` are not driven.
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and high addresses wrap around. And, `CAS1L` and `CAS1H` are not
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driven.
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* If both `MBRAM` and `ROW2` are TRUE, i.e. +5V, it is also possible
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for the BBU to detect a 2.5MB RAM configuration and adjust bus
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errors flagging accordingly.
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for the BBU to detect a 2.5MB RAM configuration and address
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wrap-around will change accordingly.
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* `RDQ0` - `RDQ15` are bidirectional data signals, they are the
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primary means by which single-pin I/O devices and the like are
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@ -236,28 +237,25 @@ DRAM. Guide to the Macintosh family hardware, page 84.
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CPU, in conjunction with the address inputs. Namely, the BBU reads
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and writes to RAM, and the CPU accesses that RAM on its own time.
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* I do not know if the C8M and C3.7M clock signals are inputs or
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outputs. The master clock crystal is C16M, 16 MHz, generated by the
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"FOX" crystal oscillator on the MLB. If the clock frequency is
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divided down by the BBU, then these are outputs. In any case, C16M
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is definitely an input.
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* The C8M and C3.7M clock signals are outputs. The master clock
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crystal is C16M, 16 MHz, generated by the "FOX" crystal oscillator
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on the MLB. C16M is an input to the BBU.
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Please note: The "F" suffixes is a good hint saying that a signal is
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"filtered," which only happens after a signal has already been
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output from the primary device. So, if you are connecting to an "F"
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signal, that means you're an input. Otherwise, you're an output.
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Therefore, that's pretty strong evidence that the lower frequency
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clock signals are divided down by the BBU.
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* All peripheral/device chip select/enable signals are output signals.
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* MC68000 output signals directly connected to the BBU are BBU input
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signals. Namely: `*LDS`, `*UDS`, `R/*W`, `*AS`.
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* Output signals that connect to MC68000 inputs: `*DTACK`, `*BERR`,
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`*IPL0`, `*IPL1`, `*IPL2`, `*VPA`. Or are the interrupt signals BBU
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inputs?
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`*IPL0`, `*VPA`.
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* `*IPL1` is an input, it is generated by the SCC and the BBU yields
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to it if necessary by not generating `*IPL0`.
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* Is `*RES` an input only? I would assume so, assuming there is
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another, dedicated circuit to control hard board resets. Note that
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@ -267,22 +265,29 @@ DRAM. Guide to the Macintosh family hardware, page 84.
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itself.
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Note that the BBU needs a RESET input pin for its own sake since it
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includes sequential logic to scan the CRT and sound buffers.
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includes sequential logic to scan the CRT and sound buffers. BUT,
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this is the key to remember: if you hold down the programmer's reset
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button on a Macintosh computer, that doesn't cause the CRT to blank
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out to black. That's how we know the BBU only relies on an internal
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power-on reset for at least for some circuits. Other circuits like
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the ROM overlay switch are reset by the external reset too.
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* `C2M` is an output signal, it primarily controls the address
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multiplexers to select either the row address (zero) or column
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address (one). Connecting directly to a simple 2 MHz clock could be
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adequate, or a more tailored method may be used for higher
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performance and lower memory access time.
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address (one). Older Macintoshes connected directly to a 2 MHz
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signal, but this is actually a misnomer in the case of the Macintosh
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SE because is uses a more tailored approach for higher performance
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through the use of DRAM Fast Page Mode (FPM).
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* `*PMCYC` is an output signal. Its primary conceptual purpose is to
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define "whose turn" it is to access DRAM, the CPU or the BBU? In
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the Macintosh Plus, this was a simple 1 MHz clock, since the CPU
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always takes a multiple of 4 clock cycles at 8 MHz to access DRAM.
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But the Macintosh SE uses a more sophisticated pattern to give the
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CPU as large of a time share as possible to access DRAM. The symbol
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is probably short for Processor Memory CYCle. It only connects to
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the PDS slot and the F257 chips.
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the Macintosh Plus, this was a simple 1 MHz clock (that was masked
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during the vertical blanking interval), since the CPU always takes a
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multiple of 4 clock cycles at 8 MHz to access DRAM. But the
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Macintosh SE uses a more sophisticated pattern to give the CPU as
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large of a time share as possible to access DRAM. The symbol is
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probably short for Processor Memory CYCle. It only connects to the
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PDS slot and the F257 chips.
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----------
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@ -312,8 +317,8 @@ Peripheral device signals, input or output?
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we don't need to actually implement this signal because it is marked
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as "reserved" in the PDS slot documentation.
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* Output signals: `*SCCRD`, `*PWM`?, `*DACK`, `SND`,
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`*VSYNC`, `*HSYNC`, `VIDOUT`.
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* Output signals: `*SCCRD`, `*PWM`, `*DACK`, `SND`, `*VSYNC`,
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`*HSYNC`, `VIDOUT`.
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* Output SELECT signals: `IWM`, `*SCCEN`. `VIA.CS1`.
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@ -568,7 +568,8 @@ endmodule
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These are the particular address zones for Macintosh SE, according
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to MESS/MAME source code. In particular, SCC and IWM are
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surrounded with invalid address guard zones:
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surrounded with invalid address guard zones... these are simply
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available for use by PDS expansion cards:
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* 0x000000 - 0x3fffff: RAM/ROM (switches based on overlay)
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* 0x400000 - 0x4fffff: ROM
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