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166 lines
6.8 KiB
Plaintext
166 lines
6.8 KiB
Plaintext
This chapter documents the backend for the 8080/z80/gbz80/64180/RCMx000
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microprocessor family.
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@section Legal
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This module is copyright in 2009 by Dominic Morris.
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@example
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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@end example
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@section Additional options for this module
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This module provides the following additional options:
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@table @option
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@item -8080
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Turns on 8080 compatibility mode. Any use of z80 (or higher)
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opcodes will result in an error being generated.
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@item -gbz80
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Turns on gbz80 compatibility mode. Any use of non-supported
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opcodes will result in an error being generated.
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@item -hd64180
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Turns on 64180 mode supporting additional 64180 opcodes.
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@item -intel-syntax
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Turns on the older Intel 8080 syntax mode. When this mode is
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activated, mnemonics and oprand types from the Intel 8080 syntax
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instead of the Zilog Z80 syntax (such as @code{STA 1234h}
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instead of @code{ld (1234h),a}) will be valid. This option can
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be used in parallel with -8080 to use both sets of mnemonics,
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although this is discouraged, as two instructions (@code{jp} and
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@code{cp}) mean different things in each syntax. In this case,
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these instructions will be assembled as the Intel syntax, and a
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warning will be emitted.
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@item -rcm2000
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@item -rcm3000
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@item -rcm4000
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Turns on Rabbit compatibility mode, generating the correct
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codes for moved opcodes and supporting the additional Rabbit
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instructions. In this mode, 8 bit access to the 16 bit index
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registers is not permitted.
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@item -rcmemu
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Turns on emulation of some instructions which aren't available
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on the Rabbit processors.
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@item -swapixiy
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Swaps the usage of ix and iy registers. This is useful
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for compiling generic code that uses an index register that
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is reserved on the target machine.
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@item -z80asm
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Switches on z80asm mode. This translates ASMPC to $ and accepts
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some pseudo opcodes that z80asm supports. Most emulation of
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z80asm directives is provided by the oldsyntax syntax module.
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@end table
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@section General
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This backend accepts z80 family instructions in standard
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Zilog syntax. Rabbit opcodes are accepted as defined in the
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publically available reference material from Rabbit Semiconductor,
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with the exception that the @code{ljp} and @code{lcall} opcodes need
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to be supplied with a 24 bit number rather than an 8 bit @code{xpc} and a
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16 bit address.
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The target address type is 16 bit.
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Instructions consist of one up to six bytes and require no alignment.
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There is also no alignment requirement for sections and data.
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@section Extensions
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This backend provides the following specific extensions:
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@itemize @minus
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@item Certain Rabbit opcodes can be prefixed by the @code{altd} and/or the
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@code{ioi}/@code{ioe} modifier.
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For details of which instructions these are valid for please
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see the documentation from Rabbit.
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@item The parser understands a lo/hi-modifier to select low- or high-byte
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of a 16-bit word. The character @code{<} is used to select the low-byte
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and @code{>} for the high-byte. It has to be the first character before
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an expression.
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@item When applying the operation @code{/256}, @code{%256} or @code{&256}
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on a label, an appropriate lo/hi-byte relocation will automatically be
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generated.
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@end itemize
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@section Optimisations
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This backend supports the emulation of certain z80 instructions on the
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Rabbit/gbz80 processor. These instructions are @code{rld}, @code{rrd},
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@code{cpi}, @code{cpir}, @code{cpd} and @code{cpdr}.
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The link stage should provide routines with the opcode name prefixed with
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@code{rcmx_} (eg @code{rcmx_rld}) which implements the same functionality.
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Example implementations are available within the z88dk CVS tree.
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Additionally, for the Rabbit targets the missing call @code{cc}, opcodes
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will be emulated.
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@section Known Problems
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Some known problems of this module at the moment:
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@itemize @minus
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@item Not all RCM4000 opcodes are supported (@code{llcall}, @code{lljp}
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are not available).
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@end itemize
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@section Error Messages
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This module has the following error messages:
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@itemize @minus
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@item 2001: index offset out of bounds (%d)
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@item 2002: Opcode not supported by %s (%s)
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@item 2003: Index registers not available on 8080
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@item 2004: out of range for 8 bit expression (%d)
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@item 2005: invalid bit number (%d) should be in range 0..7
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@item 2006: rst value out of range (%d/0x%02x)
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@item 2007: %s value out of range (%d)
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@item 2008: index offset should be a constant
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@item 2009: invalid branch type for jr
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@item 2010: Rabbit target doesn't support rst %d
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@item 2011: Rabbit target doesn't support 8 bit index registers
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@item 2012: z180 target doesn't support 8 bit index registers
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@item 2013: invalid branch type for jre
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@item 2014: Opcode not supported by %s (%s) but it can be emulated (-rcmemu)
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@item 2015: %s specifier is only valid for Rabbit processors
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@item 2016: Only one of ioi and ioe can be specified at a time
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@item 2017: %s specifier is not valid for the opcode %s
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@item 2018: %s specifier redundant for the opcode %s
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@item 2019: %s specifier has no effect on the opcode %s
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@item 2020: Operand value must evaluate to a constant for opcode %s
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@item 2021: Unhandled operand type wanted 0x%x got 0x%x
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@item 2022: Missed matched index registers on %s
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@item 2023: Only out (c),0 is supported for the opcode %s
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@item 2024: Operations between different index registers are forbidden
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@item 2025: Operations between ix/iy/hl are forbidden
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@item 2026: Double indirection forbidden
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@item 2027: Instruction %s will be assembled as '%s'
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@end itemize
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