;__________________________________________________________________________________________________ ; ; File: SCSIMgrInit96BIOS.a ; ; Contains: SCSI Manager BIOS based 53c96 initialization routines ; ; Written by: James Blair ; ; Copyright: © 1992-1993 by Apple Computer, Inc., All rights reserved. ; ; Change History (most recent first): ; ; 11/17/93 KW load scsibase into a3 before using ; 2/5/93 CSS Checkin from Horror. ; <1> 9/6/92 jab first checked in ;__________________________________________________________________________________________________ BLANKS ON ; assembler accepts spaces & tabs in operand field STRING ASIS ; generate string as specified PRINT OFF ; do not send subsequent lines to the listing file ; don't print includes LOAD 'StandardEqu.d' ; from StandardEqu.a and for building ROMs INCLUDE 'SCSI.a' ; CSS INCLUDE 'HardwareEqu.a' INCLUDE 'SCSIPriv.a' INCLUDE 'UniversalEqu.a' ; for TestFor INCLUDE 'SCSIEqu96.a' PRINT ON ; do send subsequent lines to the listing files SCSIInit96BIOS PROC EXPORT ; EXPORT InitMgr_SCSI96_BIOS ; From SCSIMgr96.a --- ; From SCSIMgr96BIOS.a --- IMPORT SCSIMgr_96_BIOS, DoSCSIMsgIn_96_BIOS IMPORT SCSIErr_96_BIOS, DoSCSIReset_96_BIOS IMPORT Unimplemented_96_BIOS, DoSCSIGet_96_BIOS IMPORT DoSCSICmd_96_BIOS, DoSCSIComplete_96_BIOS IMPORT DoSCSISelect_S96_BIOS, DoSCSISelAtn_S96_BIOS ; IMPORT DoSCSIStat_96_BIOS, CyclePhase_96_BIOS ; IMPORT DoSCSIReset_96_BIOS, DoSCSIMsgOut_96_BIOS IMPORT NewSCSIRead_96_BIOS, NewSCSIWrite_96_BIOS IMPORT NewSCSIWBlind_96_BIOS, NewSCSIRBlind_96_BIOS ; From SCSIMgrHW96.a --- ; From SCSIMgrHW96BIOS.a --- IMPORT BusErrHandler_96_BIOS, ResetBus_96_BIOS IMPORT SlowRead_96_BIOS, Transfer_96_BIOS IMPORT SlowWrite_96_BIOS, SlowComp_96_BIOS IMPORT FastRead_96_BIOS, FastWrite_96_BIOS IMPORT InitHW_SCSI96_BIOS, FastComp_96_BIOS WITH scsiGlobalRecord ;------------------------------------------------------------- ; ; Initialization code for the SCSI Manager 5394/5396 InitMgr_SCSI96_BIOS movem.l intrRegs, -(sp) ; save all registers, for convenience moveq.l #0, zeroReg ; initialize "zeroReg" movea.l SCSIGlobals, a4 ; get ptr to structure moveq.l #numSelectors-1, d1 ; loop count lea.l SCSIMgr_96_BIOS, a1 ; get start of SCSI Mgr code move.l a1, d0 ; remember base address lea OffsetTbl96_BIOS, a1 ; address of offset table movea.l a4, a0 ; point to base of old SCSI Mgr jump table @MakeJmpTbl moveq.l #0, d2 ; clear high word move.w (a1)+, d2 ; get the next offset add.l d0, d2 ; compute the address move.l d2, (a0)+ ; install it in the jump table dbra d1, @MakeJmpTbl ; loop for all vectors lea.l Transfer_96_BIOS, a1 ; move.l a1, jvTransfer(a4) ; use this Transfer routine lea.l CyclePhase_96_BIOS, a1 ; move.l a1, jvCyclePhase(a4) ; use this CyclePhase routine lea.l ResetBus_96_BIOS, a1 move.l a1, jvResetBus(a4) ; use this Bus Reset routine lea.l BusErrHandler_96_BIOS, a1 ; move.l a1, jvBusErr(a4) ; use this SCSI Bus Error handler lea.l SlowRead_96_BIOS, a1 move.l a1, jvVSRO(a4) ; use this Slow Read routine lea.l SlowWrite_96_BIOS, a1 move.l a1, jvVSWO(a4) ; use this Slow Write routine lea.l FastRead_96_BIOS, a1 move.l a1, jvVFRO(a4) ; use this Fast Read routine lea.l FastWrite_96_BIOS, a1 move.l a1, jvVFWO(a4) ; use this Fast Write routine lea.l SlowComp_96_BIOS, a1 ; move.l a1, jvCSO(a4) ; use this Slow Compare routine lea.l FastComp_96_BIOS, a1 move.l a1, jvCFO(a4) ; use this Fast Compare routine lea.l SCSIErr_96_BIOS, a1 move.l a1, jvErr(a4) ; use this Error routine lea.l Unimplemented_96_BIOS, a1 move.l a1, jvSel15(a4) ; Selector 15 routine move.l a1, jvSel16(a4) ; Selector 16 routine move.l a1, jvSel17(a4) ; Selector 17 routine move.l zeroReg, d0 ; disable SCSI interrupts movea.l jvDisEnable(a4), a0 ; addr of interrupt enable/disable routine jsr (a0) ; disable interrupts clr.l G_IntrpStat(a4) ; clear our Intrp Status clr.l G_FakeStat(a4) ; clear fake stat clr.l G_State96(a4) ; clear our indicators of 53c96 state clr.l G_SCSIDevMap0(a4) ; initialize SCSI Device Map 0 clr.l G_SCSIDevMap1(a4) ; initialize SCSI Device Map 1 clr.l base539x1(a4) ; init second SCSI base address clr.l G_SCSIDREQ(a4) ; initialize SCSI DREQ regr ; All this time we've been using a default host ID = 7. Just in case that ever changes ; load whatever SCSIMgrInit got from PRAM as our host ID. move.b G_ID(a4), d1 ; get SCSI host ID mask move.b #7, d0 ; load shift count @1 lsl.b #1, d1 ; shift out mask bit until all 0's dbeq d0, @1 ; remaining count in d0 will be SCSI ID ori.b #initCF1, d0 ; use this our designated SCSI host ID move.l SCSIBase, a3 ; load addr of first SCSI chip move.b d0, rCF1(a3) ; use this new config regr. value, hopefully ; nobody has changed the setting since HW init time NOT!!! move.l SCSIBase, base539x0(a4) ; load addr of first SCSI chip move.b #bDREQ_BIOS,G_bitDREQ(a4) ; setup bit location of DREQ check move.l #SCSI0_DREQ_BIOS,pdma5380(a4) ; setup DREQ location @InitDone move.b #mgrVersion2, state2(a4) ; save the version number movem.l (sp)+, intrRegs ; restore registers rts ;------------------------------------------------------------- ; OffsetTbl96_BIOS DC.W DoSCSIReset_96_BIOS-SCSIMgr_96_BIOS ; 0: SCSIReset DC.W DoSCSIGet_96_BIOS-SCSIMgr_96_BIOS ; 1: SCSIGet DC.W DoSCSISelect_S96_BIOS-SCSIMgr_96_BIOS ; 2: SCSISelect DC.W DoSCSICmd_96_BIOS-SCSIMgr_96_BIOS ; 3: SCSICmd DC.W DoSCSIComplete_96_BIOS-SCSIMgr_96_BIOS ; 4: SCSIComplete DC.W NewSCSIRead_96_BIOS-SCSIMgr_96_BIOS ; 5: SCSIRead DC.W NewSCSIWrite_96_BIOS-SCSIMgr_96_BIOS ; 6: SCSIWrite DC.W Unimplemented_96_BIOS-SCSIMgr_96_BIOS ; 7: Was SCSIInstall DC.W NewSCSIRBlind_96_BIOS-SCSIMgr_96_BIOS ; 8: SCSIRBlind DC.W NewSCSIWBlind_96_BIOS-SCSIMgr_96_BIOS ; 9: SCSIWBlind DC.W DoSCSIStat_96_BIOS-SCSIMgr_96_BIOS ; 10: SCSIStat DC.W DoSCSISelAtn_S96_BIOS-SCSIMgr_96_BIOS ; 11: SCSISelAtn DC.W DoSCSIMsgIn_96_BIOS-SCSIMgr_96_BIOS ; 12: SCSIMsgIn DC.W DoSCSIMsgOut_96_BIOS-SCSIMgr_96_BIOS ; 13: SCSIMsgOut ;========================================================================== ENDWITH END