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mac-rom/DeclData/DeclNet/Sonic/SonicEqu.a

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Bring in CubeE sources Resource forks are included only for .rsrc files. These are DeRezzed into their data fork. 'ckid' resources, from the Projector VCS, are not included. The Tools directory, containing mostly junk, is also excluded.
2017-09-17 09:09:04 +00:00
;
; File: SonicEqu.a
;
; Contains: Sonic-specific equates
;
; Written by: Sean Findley
;
; Copyright: <09> 1990, 1992 by Apple Computer, Inc., all rights reserved.
;
; This file is used in these builds: Mac32
;
; Change History (most recent first):
;
; <1> 10/6/92 GDW New location for ROMLink tool.
; <1> 6/12/92 RLM first checked in
; <P2> 02/07/92 jmp (jmp,H2/BG/SJF,Z4) Rolled in SMOVE macro def and SonicAddress
; def.
; <1> 2/4/92 mal first checked in
; <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
; Pre-Pandora ROM comments begin here.
; <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
; <3> 2/26/91 JK Added extended Motorola mode equates.
; <2> 1/30/91 JK Added code review changes.
; <1> 12/14/90 JK Added to build
;
; To Do:
;
; SonicEqu.a - Equates for SONIC
; written by Sean J. Findley Jan. 1990
; Copyright (c) 1990 Apple Computer, Inc.
MACRO
CtlRegPad
IF CTLPAD THEN
ORG *+2
ENDIF
ENDM
MACRO ; <Z4> thru next <Z4>
SMOVE &src,&dest
IF SONIC32 THEN
MOVE.L &src,&dest
ELSE
MOVE.W &src,&dest
ENDIF
ENDM ; <Z4>
;<3B><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> SONIC Registers
SONICRegs RECORD 0
IF SONIC32 THEN
Command DS.L 1 ; (CR) SONIC control
Data_Config DS.L 1 ; (DCR) packet configuration
Recv_Control DS.L 1 ; (RCR) pkt reception control
Trans_Control DS.L 1 ; (TCR) Transmission control
Int_Mask DS.L 1 ; (IMR) interrupt mask
Int_Status DS.L 1 ; (ISR) interrupts status bits
Upper_TDA DS.L 1 ; (UTDA) upper 16 bits of TDA address
Current_TDA DS.L 1 ; (CTDA) 16 bit ptr to current TDA
Trans_PktSize DS.L 1 ; (TPS) total size of outbound pkt
Trans_FragCount DS.L 1 ; (TFC) transmit fragment count
Trans_PktStart0 DS.L 1 ; (TSA0) lower 16 bit of pkt addr
Trans_PktStart1 DS.L 1 ; (TSA1) upper "
Trans_FragSize DS.L 1 ; (TFS) current fragment size
Upper_RDA DS.L 1 ; (URDA) upper 16 bits of RDA address
Current_RDA DS.L 1 ; (CRDA) 16 bit ptr to current RDA
Recv_RBA0 DS.L 1 ; (CRBA0) lower 16 bit receive addr in RBA
Recv_RBA1 DS.L 1 ; (CRBA1) upper 16 bit recive addr in RBA
Buff_Cnt0 DS.L 1 ; (RBWC0) lower 16 bit of word count in RBA
Buff_Cnt1 DS.L 1 ; (RBWC1) upper "
End_Buff DS.L 1 ; (EOBC) end of buffer word count
Upper_RRA DS.L 1 ; (URRA) upper 16 bits of RRA address
RRA_Start DS.L 1 ; (RSA) 16 bit ptr to RRA
RRA_End DS.L 1 ; (REA) 16 bit ptr to end of RRA
RRA_Read DS.L 1 ; (RRP) where SONIC gets next read resource
RRA_Write DS.L 1 ; (RWP) where host puts new read resources
TRBA0 DS.L 1 ; (TRBA0) used by SONIC
TRBA1 DS.L 1 ; (TRBA1) "
TBWC0 DS.L 1 ; (TBWC0) "
TBWC1 DS.L 1 ; (TBWC1) "
ADDR0 DS.L 1 ; (ADDR0) "
ADDR1 DS.L 1 ; (ADDR1) "
LLFA DS.L 1 ; (LLFA) "
TTDA DS.L 1 ; (TTDA) "
CAM_EntryPtr DS.L 1 ; (CEP) points to CAM cell
CAM_Port2 DS.L 1 ; (CAP2) selects upper 16 bits of CAM cell
CAM_Port1 DS.L 1 ; (CAP1) selects middle 16 bits of CAM cell
CAM_Port0 DS.L 1 ; (CAP0) selects lower 16 bits of CAM cell
CAM_Enable DS.L 1 ; (CE) CAM enable register turns cells on/off
CAM_DescPtr DS.L 1 ; (CDP) 16 bit ptr to current CAM descriptor
CAM_Count DS.L 1 ; (CDC) count of CAM descriptors
Silicon_Rev DS.L 1 ; (SR) rev info on SONIC chip
Timer0 DS.L 1 ; (WT0) lower 16 bits of SONCIC timer
Timer1 DS.L 1 ; (WT1) upper 16 "
Recv_SeqCnt DS.L 1 ; (RSC) receive sequence counter
CRC_Err DS.L 1 ; (CRCT) CRC error count
FAE_Err DS.L 1 ; (FAET) frame alignment error count
MissedPkt_Err DS.L 1 ; (MPT) missed packet error count
MDT DS.L 1 ; (MDT) max. deferral timer
RTC DS.L 1 ; (RTC) receive test control
TTC DS.L 1 ; (TTC) transmit test control
DTC DS.L 1 ; (DTC) DMA test control
CC0 DS.L 1 ; (CC0) CAM comparison 0
CC1 DS.L 1 ; (CC1) CAM comparison 1
CC2 DS.L 1 ; (CC2) CAM comparison 2
CM DS.L 1 ; (CM) CAM match
res1 DS.L 2 ; reserved by National Semiconductor
RBC DS.L 1 ; (RBC) receiver byte count
res2 DS.L 1 ; reserved by National Semiconductor
TBO DS.L 1 ; (TBO) transmit backoff counter
TRC DS.L 1 ; (TRC) transmit random counter
TBM DS.L 1 ; (TBM) transmit backoff mask
res3 DS.L 1 ; reserved by National Semiconductor
Data_Config2 DS.L 1 ; extended data configiguration
ELSE
Command DS.W 1 ; (CR) SONIC control
CtlRegPad
Data_Config DS.W 1 ; (DCR) packet configuration
CtlRegPad
Recv_Control DS.W 1 ; (RCR) pkt reception control
CtlRegPad
Trans_Control DS.W 1 ; (TCR) Transmission control
CtlRegPad
Int_Mask DS.W 1 ; (IMR) interrupt mask
CtlRegPad
Int_Status DS.W 1 ; (ISR) interrupts status bits
CtlRegPad
Upper_TDA DS.W 1 ; (UTDA) upper 16 bits of TDA address
CtlRegPad
Current_TDA DS.W 1 ; (CTDA) 16 bit ptr to current TDA
CtlRegPad
Trans_PktSize DS.W 1 ; (TPS) total size of outbound pkt
CtlRegPad
Trans_FragCount DS.W 1 ; (TFC) transmit fragment count
CtlRegPad
Trans_PktStart0 DS.W 1 ; (TSA0) lower 16 bit of pkt addr
CtlRegPad
Trans_PktStart1 DS.W 1 ; (TSA1) upper "
CtlRegPad
Trans_FragSize DS.W 1 ; (TFS) current fragment size
CtlRegPad
Upper_RDA DS.W 1 ; (URDA) upper 16 bits of RDA address
CtlRegPad
Current_RDA DS.W 1 ; (CRDA) 16 bit ptr to current RDA
CtlRegPad
Recv_RBA0 DS.W 1 ; (CRBA0) lower 16 bit receive addr in RBA
CtlRegPad
Recv_RBA1 DS.W 1 ; (CRBA1) upper 16 bit recive addr in RBA
CtlRegPad
Buff_Cnt0 DS.W 1 ; (RBWC0) lower 16 bit of word count in RBA
CtlRegPad
Buff_Cnt1 DS.W 1 ; (RBWC1) upper "
CtlRegPad
End_Buff DS.W 1 ; (EOBC) end of buffer word count
CtlRegPad
Upper_RRA DS.W 1 ; (URRA) upper 16 bits of RRA address
CtlRegPad
RRA_Start DS.W 1 ; (RSA) 16 bit ptr to RRA
CtlRegPad
RRA_End DS.W 1 ; (REA) 16 bit ptr to end of RRA
CtlRegPad
RRA_Read DS.W 1 ; (RRP) where SONIC gets next read resource
CtlRegPad
RRA_Write DS.W 1 ; (RWP) where host puts new read resources
CtlRegPad
TRBA0 DS.W 1 ; (TRBA0) used by SONIC
CtlRegPad
TRBA1 DS.W 1 ; (TRBA1) "
CtlRegPad
TBWC0 DS.W 1 ; (TBWC0) "
CtlRegPad
TBWC1 DS.W 1 ; (TBWC1) "
CtlRegPad
ADDR0 DS.W 1 ; (ADDR0) "
CtlRegPad
ADDR1 DS.W 1 ; (ADDR1) "
CtlRegPad
LLFA DS.W 1 ; (LLFA) "
CtlRegPad
TTDA DS.W 1 ; (TTDA) "
CtlRegPad
CAM_EntryPtr DS.W 1 ; (CEP) points to CAM cell
CtlRegPad
CAM_Port2 DS.W 1 ; (CAP2) selects upper 16 bits of CAM cell
CtlRegPad
CAM_Port1 DS.W 1 ; (CAP1) selects middle 16 bits of CAM cell
CtlRegPad
CAM_Port0 DS.W 1 ; (CAP0) selects lower 16 bits of CAM cell
CtlRegPad
CAM_Enable DS.W 1 ; (CE) CAM enable register turns cells on/off
CtlRegPad
CAM_DescPtr DS.W 1 ; (CDP) 16 bit ptr to current CAM descriptor
CtlRegPad
CAM_Count DS.W 1 ; (CDC) count of CAM descriptors
CtlRegPad
Silicon_Rev DS.W 1 ; (SR) rev info on SONIC chip
CtlRegPad
Timer0 DS.W 1 ; (WT0) lower 16 bits of SONCIC timer
CtlRegPad
Timer1 DS.W 1 ; (WT1) upper 16 "
CtlRegPad
Recv_SeqCnt DS.W 1 ; (RSC) receive sequence counter
CtlRegPad
CRC_Err DS.W 1 ; (CRCT) CRC error count
CtlRegPad
FAE_Err DS.W 1 ; (FAET) frame alignment error count
CtlRegPad
MissedPkt_Err DS.W 1 ; (MPT) missed packet error count
CtlRegPad
MDT DS.W 1 ; (MDT) max. deferral timer
CtlRegPad
RTC DS.W 1 ; (RTC) receive test control
CtlRegPad
TTC DS.W 1 ; (TTC) transmit test control
CtlRegPad
DTC DS.W 1 ; (DTC) DMA test control
CtlRegPad
CC0 DS.W 1 ; (CC0) CAM comparison 0
CtlRegPad
CC1 DS.W 1 ; (CC1) CAM comparison 1
CtlRegPad
CC2 DS.W 1 ; (CC2) CAM comparison 2
CtlRegPad
CM DS.W 1 ; (CM) CAM match
CtlRegPad
res1 DS.W 2 ; reserved by National Semiconductor
CtlRegPad
RBC DS.W 1 ; (RBC) receiver byte count
CtlRegPad
res2 DS.W 1 ; reserved by National Semiconductor
CtlRegPad
TBO DS.W 1 ; (TBO) transmit backoff counter
CtlRegPad
TRC DS.W 1 ; (TRC) transmit random counter
CtlRegPad
TBM DS.W 1 ; (TBM) transmit backoff mask
CtlRegPad
res3 DS.W 1 ; reserved by National Semiconductor
CtlRegPad
Data_Config2 DS.W 1 ; extended data configiguration
ENDIF
ENDR
;<3B><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Content Addressable Memory (CAM) Descriptor Area CDA
CAMDesc RECORD 0
IF SONIC32 THEN
Entry_ptr DS.L 1 ; base zero index to CAM cell
Port2 DS.L 1 ; lower 16 bits in cell
Port1 DS.L 1 ; middle 16 bits in cell
Port0 DS.L 1 ; upper 16 bits in cell
enable DS.L 1 ; CAM cell enable mask
ELSE
Entry_ptr DS.W 1 ; base zero index to CAM cell
Port2 DS.W 1 ; lower 16 bits in cell
Port1 DS.W 1 ; middle 16 bits in cell
Port0 DS.W 1 ; upper 16 bits in cell
enable DS.W 1 ; CAM cell enable mask
ENDIF
CAMDescSz EQU *
ENDR
;<3B><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Receive Resource Descriptor Area RRA
RRArec RECORD 0
IF SONIC32 THEN
buff_ptr0 DS.L 1 ; lower 16 bits of RBA address
buff_ptr1 DS.L 1 ; upper 16 bits of RBA address
buff_wc0 DS.L 1 ; lower 16 bits of RBA word count
buff_wc1 DS.L 1 ; upper 16 bits of RBA word count
ELSE
buff_ptr0 DS.W 1 ; lower 16 bits of RBA address
buff_ptr1 DS.W 1 ; upper 16 bits of RBA address
buff_wc0 DS.W 1 ; lower 16 bits of RBA word count
buff_wc1 DS.W 1 ; upper 16 bits of RBA word count
ENDIF
RRArecSz EQU *
ENDR
;<3B><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Receive Descriptor Area RDA
Rxpkt RECORD 0
; this link is used to keep rx descriptors on our own list(s) when SONIC is not using them
nextRD DS.L 1 ; internal ptr to next descriptor
isFree DS.B 1 ; = true if desc has been freed
ORG nextRD
IF SONIC32 THEN
status DS.L 1 ; receive status
byte_count DS.L 1 ; size of packet read
pkt_ptr0 DS.L 1 ; lower 16 bits of packet addr. in RBA
pkt_ptr1 DS.L 1 ; upper 16 bits of packet addr. in RBA
seq_no DS.L 1 ; sequence number
link DS.L 1 ; link to other RD
in_use DS.L 1 ; use flag
ELSE
status DS.W 1 ; receive status
byte_count DS.W 1 ; size of packet read
pkt_ptr0 DS.W 1 ; lower 16 bits of packet addr. in RBA
pkt_ptr1 DS.W 1 ; upper 16 bits of packet addr. in RBA
seq_no DS.W 1 ; sequence number
link DS.W 1 ; link to other RD
in_use DS.W 1 ; use flag
ENDIF
RxRDAsize EQU *
ENDR
;<3B><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Transmit Descriptor Area TDA
Max_Tx_Frags EQU 16 ; maximum fragments supported for a transmit
Txpkt RECORD 0 ; Transmit Descriptor
; this link is used to keep tx descriptors on our own list when SONIC is not using them
nextTD DS.L 1 ; internal ptr to next descriptor
ORG nextTD
IF SONIC32 THEN
status DS.L 1 ; status info written by SONIC
config DS.L 1 ; pre-transmit config data
pkt_size DS.L 1 ; size of packet
frag_count DS.L 1 ; fragment count
frag_start EQU * ; start of individual fragments
; the following 3 fields are repeated 1..frag_count
frag_ptr0 DS.L 1 ; lower 16 bits of address
frag_ptr1 DS.L 1 ; upper "
frag_size DS.L 1 ; fragment size
frag_esize EQU * - frag_start ; size of individual fragments
ORG * + (Max_Tx_Frags-1) * frag_esize
; allocate rest of fragments
link DS.L 1 ; lower 16 bits of next TD (if any)
ELSE
status DS.W 1 ; status info written by SONIC
config DS.W 1 ; pre-transmit config data
pkt_size DS.W 1 ; size of packet
frag_count DS.W 1 ; fragment count
frag_start EQU * ; start of individual fragments
; the following 3 fields are repeated 1..frag_count
frag_ptr0 DS.W 1 ; lower 16 bits of address
frag_ptr1 DS.W 1 ; upper "
frag_size DS.W 1 ; fragment size
frag_esize EQU * - frag_start ; size of individual fragments
ORG * + (Max_Tx_Frags-1) * frag_esize
; allocate rest of fragments
link DS.W 1 ; lower 16 bits of next TD (if any)
ENDIF
TxTDAsize EQU * ; size of a single frame TD
ENDR
;<3B><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Initialization Parameters
SONICinitParms RECORD 0
SONICbase DS.L 1 ; base address of SONIC registers
IntInstall DS.L 1 ; addr of proc that installs interrupt handler
RECVRtn DS.L 1 ; address of receive routine
RECVPrms DS.L 1 ; parms to pass @ receive
TRANRtn DS.L 1 ; address of xmit complete routine
TRANPrms DS.L 1 ; parms to pass @ xmit complete
MemStart DS.L 1 ; address of memory usage area
MemSize DS.L 1 ; size of memory usage area
NumRxBuffs DS.L 1 ; proposed # of receive buffers
IntDisable DS.L 1 ; proc to disable interrupts
IntEnable DS.L 1 ; proc to reenable interrupts
NetStatArray DS.L 1 ; ptr to network statistics array
DataConfig DS.L 1 ; data configuration value
TransAddr DS.L 1 ; ->proc to translate logical->physical address
ParmSize EQU *
ENDR
;<3B><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> CAM Parameters
CAMparms RECORD 0
SONICPtr DS.L 1 ; SONIC base address <Z4>
EAddr DS.B 6 ; Ethernet address
LoadorClear DS.L 1 ; <20> 0 if adding CAM entry
ParmSize EQU *
ENDR
;<3B><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> (CR) Command Register Bits
LoadCAM EQU 9 ; load content addressable memory
ReadRRA EQU 8 ; read next read resource descriptor
SoftReset EQU 7 ; do a software reset
StartTimer EQU 5 ; start watchdog timer
StopTimer EQU 4 ; stop "
RxEnable EQU 3 ; receive packets
RxDisable EQU 2 ; stop receiving packets
TxEnable EQU 1 ; transmit packets
TxDisable EQU 0 ; stop transmitting packets
;<3B><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> (RCR) Receive Control/Status Register Bits
RecvErrors EQU 15 ; accept/reject packets with errors
RecvRunts EQU 14 ; accept/reject runt packets
RecvBroadCast EQU 13 ; accept/reject broadcasts
RecvAll EQU 12 ; turn on/off promiscuious mode
RecvMultiCast EQU 11 ; accept/reject multicasts
NoLoopBack EQU $0000 ; mask for no loopback
MACLoopBack EQU $0200 ; mask for MAC loopback
ENDECLoopBack EQU $0400 ; mask for ENDEC loopback
TxRxLoopBack EQU $0600 ; mask for Transceiver loopback
MultiRecd EQU 8 ; set when multicast is received
BroadRecd EQU 7 ; set when broadcast is received
RBAEmpty EQU 6 ; set when out of buffers in RBA
CarrierSense EQU 5 ; set when net busy and CRS is active
CollisionSense EQU 4 ; set when collision occurs if COL active
CRCErr EQU 3 ; set if packet has CRC error
FramAlignErr EQU 2 ; set if frame not aligned
LoopBackRecd EQU 1 ; set when loopback is received
ReceivedOK EQU 0 ; set upon successful packet reception
;<3B><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> (TCR) Transmit Control/Status Register Bits
TxProgInt EQU 15 ; generate a software interrupt
OWCTimer EQU 14 ; "out of window collision" timer control
CRCInhibit EQU 13 ; turn on/off FCS field
ExDeferTimer EQU 12 ; turn on/off excessive defer timer
ExcessDefer EQU 10 ; excessive deferrals detected
DeferredTx EQU 9 ; set when packet is being deferred
NoCRS EQU 8 ; CRS not present during transmission
CRSLost EQU 7 ; bad CRS during transmission
ExcessColl EQU 6 ; > 16 collisions detected
OutWindow EQU 5 ; "out of window" collision detected
PktMonitorBad EQU 3 ; packet monitored as bad
FIFOUnderRun EQU 2 ; Tx FIFO underrun
BCMismatch EQU 1 ; TxPkt_size <20> sum(TxFrag_size)
TransmitOK EQU 0 ; packet transmitted successfuly
;<3B><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> (DCR) Data Configuration Register Bits
EXBUS EQU 15 ; extended bus mode
LatchBusRetry EQU 13 ; LBR
DConfig_Usr1 EQU 12 ; sets/resets pin USR1
DConfig_Usr0 EQU 11 ; sets/resets pin USR0
SynchTerm EQU 10 ; select sync/async input to DMA
WaitCtl0 EQU $0000 ; 0 bus cycles added to DMA
WaitCtl1 EQU $0040 ; 1 bus cycle added to DMA
WaitCtl2 EQU $0080 ; 2 bus cycles added to DMA
WaitCtl3 EQU $00C0 ; 3 bus cycles added to DMA
DataWidth EQU 5 ; 16/32 bit path width for DMA
BlockMode EQU 4 ; DMA block mode selection
RFT2 EQU $0000 ; 2 word recv FIFO threshold
RFT4 EQU $0004 ; 4 word recv FIFO threshold
RFT8 EQU $0008 ; 8 word recv FIFO threshold
RFT12 EQU $000C ; 12 word recv FIFO threshold
TFT4 EQU $0000 ; 4 word trans FIFO threshold
TFT8 EQU $0001 ; 8 word trans FIFO threshold
TFT12 EQU $0002 ; 12 word trans FIFO threshold
TFT14 EQU $0003 ; 14 word trans FIFO threshold
;<3B><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> (DCR2) Extended Data Configuration Register Bits
EXUSR3 EQU 15 ; extended user bits
EXUSR2 EQU 14
EXUSR1 EQU 13
EXUSR0 EQU 12
;<3B><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> (ISR) Interrupt Status Register Bits
BusRetry EQU 14 ; set when bus needed retry
LostHeartBeat EQU 13 ; set when heartbeat is lost
DoneLoadCAM EQU 12 ; set when load CAM operation is done
GetProgInt EQU 11 ; set when programmable int. occurs
RecdPkt EQU 10 ; set when a packet has been recd.
TransDone EQU 9 ; set when trans is finished
TransError EQU 8 ; set when trans finished with an error
TimerElapsed EQU 7 ; set when timer reaches zero
EmptyRDA EQU 6 ; set when receive descriptors exhausted
EmptyRRA EQU 5 ; set when receive resources exhausted
RBAOverFLow EQU 4 ; set when buffer area is full
CRCRollover EQU 3 ; set when CRC tally has reached $FFFF
FAERollover EQU 2 ; set when FAE tally has reached $FFFF
MPRollover EQU 1 ; set when MP tally has reached $FFFF
RxFIFORollover EQU 0 ; set when Rx FIFO overflows
OurIntsMask EQU (1 << BusRetry) + \
(1 << RecdPkt) + \
(1 << TransDone) + \
(1 << TimerElapsed) + \
(1 << RxFIFORollover) + \
(1 << RBAOverFlow) + \
(1 << EmptyRRA)
;<3B><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Network Statistics
NetStats RECORD 0 ; network management stats.
TxOK DS.L 1 ; frames transmitted OK
sCollFrame DS.L 1 ; single collision frames
mCollFrame DS.L 1 ; multiple collision frames
CollFrame DS.L 1 ; collision frames
DefTx DS.L 1 ; deferred transmissions
LateColl DS.L 1 ; late collisions
ExcessColl DS.L 1 ; excessive collisions
ExcessDef DS.L 1 ; excessive defferals
InMACTxErr DS.L 1 ; internal MAC transmit errors
RxOK DS.L 1 ; frames received OK
MultiRxOK DS.L 1 ; multicast frames recd OK
BroadRxOK DS.L 1 ; broadcast frames recd OK
FCSerr DS.L 1 ; frame check sequence errors
FAerr DS.L 1 ; frame alignment errors
MPerr DS.L 1 ; missed packet errors
Size EQU *
ENDR
;<3B><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> General Equates
TalliesPerSec EQU 5000000 ; number of timer ticks/second
TxMaxRetries EQU 4 ; max attempts to retry aborted xmits
Max_Tx_Packets EQU 16 ; maximum # of chained Tx packets
Min_Pkt_Size EQU 60 ; minimum packet size
Min_Rx_Buffs EQU 2 ; minimum # of recv descriptors/buffers
Max_Pkt_Size EQU 1518 ; maximum packet size (inc. CRC)
EOL_Bit EQU 0 ; end-of-link bit
Ctl_Mem_Size EQU Txpkt.TxTDAsize*Max_Tx_Packets+ \; up to Max_Tx_Packets chained transmits
RRArec.RRArecSz+ \; 1 RRA descriptor
CAMDesc.CAMDescSz ; 1 CAM descriptor
Min_Mem_Size EQU Ctl_Mem_Size+ \
Max_Pkt_Size*Min_Rx_Buffs+ \; max. size packets
Rxpkt.RxRDAsize*Min_Rx_Buffs; recv. descriptors
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