; ; File: AMICEqu.a ; ; Contains: Equates for accessing the Apple Macintosh I/O Controller (AMIC) on PDM ; ; Written by: Dave Calvert ; ; Copyright: © 1992-1993 by Apple Computer, Inc. All rights reserved. ; ; This file is used in these builds: ROM RISC (PDM ENET) ; ; Change History (most recent first): ; ; 11/10/93 fau From SuperMunggio: Changed the check to see if the file has ; already been included. ; 10/14/93 pdw ; 9/13/93 SAM Backed out the last rev. The multipier that was changed in ; indicates the number of bytes in each entry. Two longs = ; 8 bytes. ; 9/13/93 RC Fixed a bug with the number of Vectors which were being ; allocated for the AMIC DMA handlers ; 9/13/93 SAM Changed the ddVectCount to be a byte quantity instead of a long. ; 9/10/93 pdw Pulled the SCC Lvl 4 Port A and B interrupt vectors/refcons out ; of the DMA Dispatch portion of DMADispatchGlobals. ; 9/9/93 pdw Another rearrangement of the DMADispatchGlobals structure. ; 9/1/93 chp Added a slightly less verbose version DMADispGlobals (formerly ; in InternalOnlyEqu.a). Added symbolic constants previously ; defined in SonySWIM3.a. ; 8/30/93 chp Add an interrupt handler selector for level 3 MACE interrupts, ; which are now dispatched through InterruptHandlers.a as well. ; 8/1/93 pdw Adding SCSI equates. ; 6/14/93 kc Moved some AMIC vectors from obsolete DMAMgrEqu.a. ; 6/2/93 GMR Changed name of DMA reset bit, so it won't conflict with same ; definition in other include file. ; 6/1/93 dwc Support for work-around to wait for MACE transmit status valid. ; 5/27/93 dwc Added _GetMicroSeconds trap definition to use in AMIC ; work-around code. ; 5/4/93 dwc Added debug code to work around AMIC's returning FF's on the ; first read. ; 4/16/93 dwc Add equates for SonoraPrimaryInit.a to mask and clear MACE ; interrupts. ; 4/6/93 dwc Updated for level 4 DMA interrupts. ; 3/24/93 dwc Added code to try to recover when interrupt level is lowered ; during packet handling. ; 3/9/93 jmp Moved an equate that was originally placed in ; SonoraPrimaryInit.a to this file. ; 3/5/93 dwc Removed some more debugging code. ; 2/25/93 dwc Enable receive, remove some debug equates. ; 2/24/93 dwc Cleaned up some debug equates, added some more debug equates, ; disabled receive for the PDM D5 ROM build. ; ; IF &TYPE('__INCLUDINGAMICEQU__') = 'UNDEFINED' THEN __INCLUDINGAMICEQU__ SET 1 ; Ethernet MACE equate for SonoraPrimaryInit.a MACE_INT EQU $80 ; MACE interrupt status register offset MACE_INT_MSK EQU $90 ; MACE interrupt mask register offset MACE_BIU_CNFG EQU $B0 ; BIU config register offset to reset MACE ; ; AMIC DMA Register offsets ; ; AMIC Interrupt Register offsets AMIC_INT_CTL EQU -$7000 ; AMIC Interrupt Control register AMIC_DMA_ISR0 EQU -$6FF8 ; AMIC Interrupt Status register 0 AMIC_DMA_ISR1 EQU -$6FF6 ; AMIC Interrupt Status register 1 ; AMIC interrupt control register bits MACEIE EQU 3 ; Enable ENET interrupt from MACE to AMIC ENETIRQ EQU 3 ; Ethernet interrupt asserted DMAIRQ EQU 4 ; DMA interrupt asserted INTMODE EQU 6 ; AMIC interrupt mode bit CPUINT EQU 7 ; AMIC CPU interrupt bit ; AMIC DMA status register bits ERXIRQ EQU 4 ; Ethernet receive DMA interrupt pending ETXIRQ EQU 5 ; Ethernet transmit DMA interrupt pending ; ; AMIC DMA recv packet status record ; AMIC_DMA_STAT_REC RECORD 0 ; AMIC DMA status record RFS0 DS.B 1 ; RCVCNT [7-0] Recv'd message byte count RFS1 DS.W 1 ; RCVCNT [11-8] Receive status, recv message byte count CmdStat DS.W 1 ENDR ; Absolutes bufferLogicalBase EQU $61000000 ; DMA buffer logical address emulatorOffset EQU $60F40000 ; Emulator's offset D5 ROM AMIC_DMA_BASE_REG EQU $50F31000 ; DMA base address register 3 [31:24] ; ¥¥ Temps for the PDM ENET driver ¥¥ XMIT_BUFF0 EQU $14000 ; Offset from recv buffer start to xmit buff 0 XMIT_BUFF1 EQU $14800 ; Offset from recv buffer start to xmit buff 1 XMITSET0 EQU $00 ; Offset for xmit byte count reg 0 HIGH BYTE XMITSET1 EQU $10 ; Offset for xmit byte count reg 1 HIGH BYTE ; Receive register offsets AMIC_DMA_RECV_HEAD EQU $1030 ; Receive head pointer [AMIC] à AMIC_DMA_RECV_TAIL EQU $1034 ; Receive tail pointer à AMIC_DMA_RECV_CNTL EQU $1028 ; Receive DMA Control/Status register ; Transmit register offsets, 8 bits AMIC_DMA_XMIT_CNTL EQU $0C20 ; Transmit DMA channel control/status register offset ; AMIC XMIT Register offsets - Set 0 AMIC_DMA_XMIT_BUFF0 EQU $14000 ; Register Set 0 address register AMIC_DMA_XMIT_CNT0L EQU $1045 ; Register Set 0 count register LOW AMIC_DMA_XMIT_CNT0H EQU $1044 ; Register Set 0 count register HIGH ; AMIC XMIT Register offsets - Set 1 AMIC_DMA_XMIT_BUFF1 EQU $14800 ; Register Set 1 address register AMIC_DMA_XMIT_CNT1L EQU $1055 ; Register Set 1 count register LOW AMIC_DMA_XMIT_CNT1H EQU $1054 ; Register Set 1 count register HIGH ; AMIC FDC Register offsets DMAFloppyBase equ $1060 ; address offset for floppy DMA DMAFloppyCount equ $1064 ; count for floppy DMA DMAFloppyCS equ $1068 ; DMA control/status for the floppy ; Test these to see if the xmit reg set is available ; If = 1, reg buffer is 'empty', set is available SET0 EQU 5 SET1 EQU 6 AMIC_DMA_BASE_ADDR0 EQU $0003 ; DMA base address register 0 [7:0] AMIC_DMA_BASE_ADDR1 EQU $0002 ; DMA base address register 1 [15:8] AMIC_DMA_BASE_ADDR2 EQU $0001 ; DMA base address register 2 [23:16] AMIC_DMA_BASE_ADDR3 EQU $0000 ; DMA base address register 3 [31:24] ; ; DMA interrupt handler selectors bit #s: $50f2a00a ($FÉ8) | $50f2a008 (7É0) ; hwAmicRXB EQU 0 ; SCC Port B Receive hwAmicTXB EQU 1 ; Transmit hwAmicRXA EQU 2 ; SCC Port A Receive hwAmicTXA EQU 3 ; Transmit hwAmicERX EQU 4 ; Ethernet Receive hwAmicETX EQU 5 ; Transmit hwAmicFDC EQU 6 ; Floppy hwAmicUnused EQU 7 ; Unused hwAmicSIN EQU 8 ; Sound In hwAmicSOUT EQU 9 ; Out ddVectCount EQU $A ; # of implemented vectors ; ; AMIC Interrupt Dispatcher vector table ; DMADispGlobals RECORD 0, INCREMENT ; (Generic DMA dispatch table) ddDMAbase DS.L 1 ; DMA controller's base address ddVector0 DS.L 1 ; Source 0 IRQ vector ddRefCon0 DS.L 1 ; Source 0 Handler RefCon DS.B (ddVectCount-1)*8 ; one for each remaining vector SCCLvl4Avector DS.L 1 ; Level 4 SCC port A vector SCCLvl4Arefcon DS.L 1 ; Level 4 SCC port A refCon SCCLvl4Bvector DS.L 1 ; Level 4 SCC port B vector SCCLvl4Brefcon DS.L 1 ; Level 4 SCC port B refCon maceVector DS.L 1 ; MACE enet interrupt vector maceRefcon DS.L 1 ; MACE enet interrupt refCon ddSize EQU * ; size of this record ENDR ; ; AMIC DMA Channel Register Bit defines ; ; DMA Control/Status Register bit offsets DMARST EQU 0 ; Soft reset (xmit & rcv) DMARUN EQU 1 ; DMA enable (xmit & rcv) DMAIE EQU 3 ; DMA Interrupt Enable (xmit & rcv) DMADIR EQU 6 ; DMA Direction (SCSI, FDC) OVRRUN EQU 6 ; Rcv Head ptr has tried to pass Tail Ptr (ENET) DMAIF EQU 7 ; DMA Interrupt Flag (xmit & rcv) XMTMSK EQU (1<