;
;	File:		InternalOnlyEqu.a
;
;	Contains:	Internal Only Equates
;
;	Written by:	Everybody and their Mother
;
;	Copyright:	© 1990-1993 by Apple Computer, Inc., all rights reserved.
;
;	Change History (most recent first):
;
;	  <SM54>	12/22/93	RM		Recycle boxFlags for new CPU's that will be shipping with
;									Capone. Reusable boxFlags made available by Rich Biasi. This
;									change by R. Montagne (4-6255).
;	  <SM53>	12/13/93	PN		Roll in Kaos and Horrors code to support AJ and Malcom machines.
;	  <SM52>	11/23/93	rab		Recycled boxCarnation33. Now is boxSoftmacSUN. Changed boxlfag
;									#127 to boxExtended to signify new extended boxflag mechanism.
;	  <SM51>	11/11/93	rab		Added boxflags for SoftmacΙ
;	  <SM50>	11/10/93	fau		Update from SuperMunggio <SMG2>.
;	  <SMG2>	 8/25/93	chp		Defined a box flag for TNT, reusing the Tesseract-in-a-Lego-box
;									flag already reserved but not used.
;	  <SM49>	 11/9/93	RLE		added box flags for 603-based PowerBooks
;	  <SM48>	 11/9/93	KW		Added boxflags for STP machines
;	  <SM47>	 11/8/93	JRH		boxDBLite16 is now boxPowerBookDuo250. boxDBLite20 is now
;									boxPenLite. boxEscher25 is now boxYeagerFSTN. boxEscher33 is now
;									boxPowerBookDuo270C.
;	  <SM46>	11/08/93	HY		Added boxJedi to boxflag list.
;	  <SM45>	10/25/93	SAM		Roll in <MC2> from mc900ftjesus.  Love changing this file! :-)
;	   <MC2>	10/25/93	SAM		Changed MMFlags mmCacheUnk1 to MMFigEnable.  Added emo fields to
;									the nkDiag info block.
;	  <SM44>	  9/9/93	SAM		Updated nkSystemInfo ptrs, added warmstart fields to the
;									nkDiagInfo, added a NanoKernalInfo block.
;	  <SM43>	  9/1/93	chp		Removed DMADispGlobals structure to AMICEqu.a since thatΥs where
;									this structure is significant.
;	  <SM42>	08-13-93	jmp		Added BlackBirdBFD to the BoxFlag list.
;	  <SM41>	 8/12/93	BG		Added boxflags for various Carl Sagans.  Updated boxflag list to
;									use "official" names for released machines.
;	  <SM40>	 8/11/93	KW		adding some new Smurf box flags. Also renamed exisiting
;									boxRiscQuadra and boxRiscWombat
;	  <SM39>	 7/21/93	JRH		moved PenLite boxFlag, and added two new ones for Yeager
;	  <SM38>	  6/3/93	SAM		Straightened out the PDM boxflag names and added two more to the
;									end of the list
;	  <SM37>	 5/18/93	BT		Add missing bits to MMFlags breakout, still need some
;									explanation though.
;	  <SM36>	  5/5/93	BG		Added boxflags for Slimus (Optimus board in Color Classic box).
;	  <SM35>	 4/27/93	BG		Added boxflags for WLCD II ("Malcolm") @ 25/33MHz for the
;									SpeedBump project.
;	  <SM34>	 4/22/93	SAM		Fixed the ddVectorCount calculation in DMADispGlobals.
;	  <SM33>	  4/5/93	RC		Added SCC level 4 vectors to DMA interrupt handler data struct
;	  <SM32>	 3/11/93	SAM		Added some fields in PDM's DMA dispatch table.
;	  <SM31>	  3/5/93	BG		Added some more boxflags for other forms of Primus and Optimus
;									(25/33MHz) and all 3 forms of Aladdin (aka ELB).
;	  <SM30>	03/05/93	HY		Added boxflag for boxPeterPan (32MHz 030 w/TV Tuner)
;	  <SM29>	 2/20/93	SAM		Moved MemDispGlobals from hwPriv.a and added DMADispGlobals.
;	  <SM28>	  2/5/93	rab		Added boxflags for boxPrimus20 (LC/040) and boxOptimus20
;									(Hook/040)and updated boxLastKnown.
;	  <SM27>	  2/5/93	SAM		Added NanoKernel info block descriptors.
;	  <SM26>	 1/28/93	jmp		Added the Norad and BudMan BoxFlag numbers.
;	  <SM25>	 1/20/93	GMA		Adding slice33
;	  <SM24>	 1/11/93	GMA		Adding Hook33 and Slice25, bumping RISCWombat +2 to justify with
;									Horror.
;	  <SM23>	01-11-93	jmp		Updated various BoxFlag names (from HORROR).
;	  <SM22>	12/23/92	RC		Added Support for Smurf on Wombat
;	  <SM21>	 12/7/92	GMA		Moving new boxflags for cyclone and tempest (+2), justifying
;									with Horror.
;	  <SM20>	 12/4/92	fau		Had a typo in last checkin.  Arghhh.
;	  <SM19>	 12/4/92	fau		Put in temporary equates for BoxCyclone and BoxTempest 'cause S.
;									Christensen has some files checked out that I can't modify to
;									use the new box flags.
;	  <SM18>	 12/4/92	fau		Changed BoxCyclone to BoxCyclone33 and BoxTempest to
;									BoxTempest25.  Added BoxCyclone40 and BoxTempest33.
;	  <SM17>	10-29-92	jmp		SyncΥed-up the BoxFlag list with the HORROR, Excelsior, and
;									Reality projects.
;	  <SM16>	10/27/92	fau		Changed BoxCycloneEVT1 to BoxTempest.
;	  <SM15>	 9/25/92	RB		Changed the BSR macros to take advantage that we only run on
;									020's and better CPUs. The change was needed to make all jumps
;									pc relative in order to boot from RAM.
;	  <SM14>	 8/17/92	CCH		Added equates for new universal flag longwords.
;	  <SM13>	  8/9/92	CCH		Added boxflags for PDM and Tesseract.
;	  <SM12>	  7/7/92	CSS		Note that with this update we are current upto Reality
;									<R22>.  Update from Reality:
;									<21> 4/8/92	JSM #1026795: Add boxMacLCII (a.k.a. Foster Farms).
;	  <SM11>	  7/1/92	GA		change old boxflagwombat20 to boxwombat33f
;	  <SM10>	  7/1/92	GA		adding new boxflags for wombat and moving boxcycloneevt1 from 49
;									to 54
;	   <SM9>	 6/21/92	RB		Added a temporary boxCycloneEVT1 so that we can support EVT1
;									boards for a couple of weeks by doing runtime checks.
;	   <SM8>	  6/4/92	KW		roll back in SM5,SM6
;	   <SM7>	  6/4/92	KW		rolled back to SM4 until I get other video stuff building and
;									added
;	   <SM6>	  6/4/92	KW		Adding boxWombat25... Missed it with last checkin
;	   <SM5>	  6/4/92	KW		(NJV,H20) Added LongBSR6 macro.
;									(djw,H22) Add boxFlag for powerbook 145
;									(BG,H21) Changed boxWombatLC to boxWombat20, boxWombat to
;									boxWombat25. Added boxWombat40, boxWLCD20, boxWLCD25.
;	   <SM4>	 5/17/92	kc		Roll in Horror Changes. Add boxFlags for new machines. Add
;									DockingGlobals equ. Add BigBSR5 macor
;	   <SM3>	  4/7/92	JSM		Renumber boxVail, boxCarnation, and boxDBLite; roll-in changes from Reality:
;		<20>	 3/24/92	JSM		Nuke more code names: boxAuroraCX25 is boxMacIIci, boxF19 is
;									boxMacIIfx.
;	   <SM2>	 2/11/92	RB		Updated box flag values
;		<19>	12/26/91	RB		Removed PowerMgr definitions, these are now in their own file.
;									PowerPrivEqu.a
;		<18>	 12/2/91	SAM		Changed boxFlag names for the released CPUs to their official
;									names.
;		<17>	10/28/91	SAM/KSM	Rolled in Regatta changes.
;		
;									 <9>	 8/30/91	SAM		(ag) changed low power warn level on TIM to 5.85
;									 <8>	 8/22/91	SAM		Updating equates to more closely resemble the TERROR sources.
;									 <7>	  8/1/91	SAM		Added box flag for Zydeco (which equals Eclipse33). Updating
;																InVidFlags.
;									 <6>	 7/25/91	SAM		Reconfiguring the box flag values for the new CPUs.
;									 <5>	 7/18/91	SAM		Added a boxFlag for Eclipse33
;									 <4>	  7/1/91	SAM		Added fields to the PmgrRec for Bad Battery stuff.
;									 <3>	 6/14/91	SAM		Added boxDBLite and boxAsahi. (HJR) Updated this file so its
;																equal with the one in TERROR. (ag) added definition of new bit
;																in pmgrflag.
;									 <1>	 5/22/91	SAM		Split off from 7.0 GM sources.
;
;		<16>	  8/6/91	KIP		Add boxflag values for new CPUs.
;		<15>	 7/24/91	MH		Added conditional wrapper(s) to prevent duplication of public
;									interface declarations: SleepRequest, SleepDemand, SleepWakeUp,
;									SleepqType, NoCalls, NoRequest, ADBBase, SlotQDT, SlotPrTbl,
;									SlotVBLQ, ScrnVBLPtr, SlotTICKS
;		<14>	 4/10/91	ag		change pmfree word to pmgrflag and pmfree bytes. changed bit
;									definition of insleep flag.
;		<13>	 2/15/91	ag		MSH: #BRC 80886 - Added a bit definition in sleep flags.
;		<12>	 1/30/91	gbm		sab, #38: Change the Τalready including this fileΥ variable to
;									all uppercase (for security reasons)
;		<11>	  1/8/91	SAM		Added BoxFlags for Spike and Apollo.
;		<10>	10/22/90	JJ		Rex V8: Change all box flag references to use boxMacLC. Get rid
;									of boxElsie and boxElsieV8.
;		 <9>	 9/25/90	SAM		Changing boxFlag names for XO, Elsie & Erickson to Classic, LC ,
;									and IIsi BoxMacLC/MacIIsi.
;		 <8>	 9/13/90	MSH		Added some LCD video RAM locations to be used by TIM for power
;									cycling and sleep.
;		 <7>	  7/9/90	JJ		Add box flag for V8 Elsie.
;		 <6>	  5/8/90	MSH		Add new power cycling equs for Waimea.
;		 <4>	  4/4/90	MSH		Add Waimea box flag.
;		 <3>	  2/8/90	HJR		Change box flag to those of Private.a, Rev. 5.
;		 <2>	  2/4/90	GA		Added Low Mem global definition for Egret Manager "EgretBase"
;		 <1>	 1/30/90	CCH		Moved in REAL private equates from Private.a.
;

; Memory Manager
;ΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡ
;
;	This file contains proprietary information and should not be released outside
;	of Apple Computer.  This is important!  
;
;ΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡ
;
;

	IF &TYPE('__INCLUDINGINTERNALONLYEQU__') = 'UNDEFINED' THEN
__INCLUDINGINTERNALONLYEQU__	SET	1

;  **********  IMPORTANT ****************
;  *******    DO NOT RELEASE FOLLOWING EQUs TO OUTSIDE of Apple Computer *********
;  *********
tagBC32			EQU  		0	 					; Tag field [byte]								<v1.7>
MPtag32			EQU  		1	 					; Master Pointer Tag field [byte]				<v1.7>
SizeCor32		EQU	 		3	 					; size correction field [byte]					<v1.7>
blkSize32		EQU  		4	 					; physical block size [long]					<v1.7>
handle32		EQU  		8	 					; back pointer to master pointer [pointer]		<v1.7>
blkData32		EQU  		12	 					; data starts here								<v1.7>

tagBC24 		EQU 		0 						; Tag and Byte Count field [long]				<v1.7>
handle24		EQU 		4 						; back pointer to master pointer [pointer]		<v1.7>
blkData24   	EQU 		8 						; data starts here								<v1.7>

minFree   		EQU 		12    					; (minimum block size) for old MemManager		<v2.0>
minFree24   	EQU 		12    					; (minimum block size) for 24 bit MemManager	<v2.0>
minFree32   	EQU 		16    					; (minimum block size) for 32 bit MemManager	<v2.0>
freeTag   		EQU 		$0    					; Tag for Free block
nRelTag   		EQU 		$40000000 				; Tag for Non-Relocatable block
relTag			EQU 		$80000000 				; Tag for Relocatable block
minAddr   		EQU 		$0    					; Min legal address
maxAddr   		EQU 		$800000   				; Max legal address for 512K machine
maxMasters		EQU 		$1000 					; Ridiculously large allocation chunk size
dfltMasters   	EQU 		32    					; Default to 32 master pointers

MMPRAMloc		EQU		$0001008A			; PRAM location for memory manager flag (1 byte) 		<v2.1>
MMFlags			EQU		$1EFC				; (1 byte) low memory location to store the flags		<v2.1>

; bit settings in MMflags:

MMStartMode		EQU		$0					; .... ...n, n=0 for 24 bit, n=1 for 32 bit				<v2.1>
MMMixed			EQU		$1					; .... ..n., n=0 for no mixed mode, n=1 for mixed 23/32 mode		<v2.1>
MMSysheap		EQU		$2					; .... .n.., n=0 for 24 bit system heap, n=1 for 32 bit system heap	<v2.1>
MMROZheap		EQU		$3					; .... n..., n=0 for 24 bit ROZ heap, n=1 for 32 bit ROZ heap		<v2.1>
mmHighSysHeap 	EQU 	$4					; ...n ...., n=1 for system heap starting way high, 0 for normal	<3.3>
mmFigEnable		EQU		$5					; ..n. ...., n=1 for "new" memory mgr (Figment)						; <MC2>
mmCacheUnk2		EQU		$6					; .n.. ...., unknown, for Quadra caches								; <SM37> bt
mmInhibitAllCache EQU	$7					; n... ...., n=0 to use Quadra caches, n=1 to inhibit them			; <SM37> bt
SystemInfo		EQU		$0B73				; System Info Byte										<v3.7>

MMFlagsDefault	EQU		(1<<mmFigEnable) |\	; When PRAM is reset, use this as a default.			<MC2>
						(1<<MMSysheap)	 |\
						(1<<MMStartMode)

; bit settings in SystemInfo byte

Systemis24bit	EQU		$0					; .... ...n, n=1 for 24 bit, n=0 for 32 bit	system		<v3.7>
Sysheapis24bit	EQU		$1					; .... ..n., n=1 for 24 bit, n=0 for 32 bit	system heap	<v4.1>


PhysMemTop		EQU		$1EF8				; Total physical RAM --- including memory for screen buffer			<v2.8>
RealMemTop		EQU		$1EF4				; amount of physcial RAM available for system use					<v2.8>
											; --- not including memory for screen buffer						<v2.8>
Phys2Log		EQU		$1EF0				; Physical to logical address convertion for MMU translation table	<v2.8>

vMMNoPrologue	EQU		$1EE0				; jump vector to MMnoPrologue							<v3.7>
vMMPPrologue	EQU		$1EE4				; jump vector to MMPPrologue							<v3.7>
vMMPrologue		EQU		$1EE8				; jump vector to MMPrologue								<v3.7>
vMMHPrologue	EQU		$1EEC				; jump vector to MMHPrologue							<v3.7>
vMMRHPrologue	EQU		$1FE0				; jump vector to MMRHPrologue							<v3.7>
vMMMMPrologue	EQU		$1FE4				; jump vector to MMMMPrologue
vMMEpilogue		EQU		$1FE8				; jump vector to MMEpilogue								<v3.7>
vMMNoErrEpilogue EQU	$1FEC				; jump vector to MMNoErrEpilogue						<v3.7>

LockMemCT		EQU		$1FF4				; (4) bytes, Lock Memory count							<v3.9>
DockingGlobals	EQU		$1FF8				; pointer to docking globals							<H12>
;
;  **********  DO NOT RELEASE ANYTHING IN THIS FILE TO OUTSIDE of Apple Computer *******************
;  **********  IMPORTANT ****************

;ΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡ	<SM27> SAM
; Nanokernel Private
;ΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡ


;_______________________________________________________________________
;	Configuration Info Record
;	Used to pass Configuration information from the Boot Program to the
;	NanoKernel for data structure and address mapping initialization.
;_______________________________________________________________________

NKConfigurationInfo		record	0,increment
ROMByteCheckSums		ds.l	8					; 000 ; ROM Checksums - one word for each of 8 byte lanes
ROMCheckSum64			ds.l	2					; 020 ; ROM Checksum - 64 bit sum of doublewords

ROMImageBaseOffset		ds.l	1					; 028 ; Offset of Base of total ROM image
ROMImageSize			ds.l	1					; 02c ; Number of bytes in ROM image
ROMImageVersion			ds.l	1					; 030 ; ROM Version number for entire ROM

Mac68KROMOffset			ds.l	1					; 034 ; Offset of base of Macintosh 68K ROM
Mac68KROMSize			ds.l	1					; 038 ; Number of bytes in Macintosh 68K ROM
	
ExceptionTableOffset	ds.l	1					; 03c ; Offset of base of PowerPC Exception Table Code
ExceptionTableSize		ds.l	1					; 040 ; Number of bytes in PowerPC Exception Table Code

HWInitCodeOffset		ds.l	1					; 044 ; Offset of base of Hardware Init Code (field moved!)
HWInitCodeSize			ds.l	1					; 048 ; Number of bytes in Hardware Init Code

KernelCodeOffset		ds.l	1					; 04c ; Offset of base of NanoKernel Code
KernelCodeSize			ds.l	1					; 050 ; Number of bytes in NanoKernel Code

EmulatorCodeOffset		ds.l	1					; 054 ; Offset of base of Emulator Code
EmulatorCodeSize		ds.l	1					; 058 ; Number of bytes in Emulator Code

OpcodeTableOffset		ds.l	1					; 05c ; Offset of base of Opcode Table
OpcodeTableSize			ds.l	1					; 060 ; Number of bytes in Opcode Table

BootstrapVersion		ds.b	16					; 064 ; Bootstrap loader version info
BootVersionOffset		ds.l	1					; 074 ; offset within EmulatorData of BootstrapVersion
ECBOffset				ds.l	1					; 078 ; offset within EmulatorData of ECB
IplValueOffset			ds.l	1					; 07c ; offset within EmulatorData of IplValue

EmulatorEntryOffset		ds.l	1					; 080 ; offset within Emulator Code of entry point
KernelTrapTableOffset	ds.l	1					; 084 ; offset within Emulator Code of KernelTrapTable

TestIntMaskInit			ds.l	1					; 088 ; initial value for test interrupt mask
ClearIntMaskInit		ds.l	1					; 08c ; initial value for clear interrupt mask
PostIntMaskInit			ds.l	1					; 090 ; initial value for post interrupt mask
LA_InterruptCtl			ds.l	1					; 094 ; logical address of Interrupt Control I/O page
InterruptHandlerKind	ds.b	1					; 098 ; kind of handler to use
						ds.b	3					; 099 ; filler

LA_InfoRecord			ds.l	1					; 09c ; logical address of InfoRecord page
LA_KernelData			ds.l	1					; 0a0 ; logical address of KernelData page
LA_EmulatorData			ds.l	1					; 0a4 ; logical address of EmulatorData page
LA_DispatchTable		ds.l	1					; 0a8 ; logical address of Dispatch Table
LA_EmulatorCode			ds.l	1					; 0ac ; logical address of Emulator Code

MacLowMemInitOffset		ds.l	1					; 0b0 ; offset to list of LowMem addr/data values

PageAttributeInit		ds.l	1					; 0b4 ; default WIMG/PP settings for PTE creation
PageMapInitSize			ds.l	1					; 0b8 ; size of page mapping info
PageMapInitOffset		ds.l	1					; 0bc ; offset to page mapping info (from base of ConfigInfo)
PageMapIRPOffset		ds.l	1					; 0c0 ; offset of InfoRecord map info (from base of PageMap)
PageMapKDPOffset		ds.l	1					; 0c4 ; offset of KernelData map info (from base of PageMap)
PageMapEDPOffset		ds.l	1					; 0c8 ; offset of EmulatorData map info (from base of PageMap)

SegMaps
SegMap32SupInit			ds.l	32					; 0cc ; 32 bit mode Segment Map Supervisor space
SegMap32UsrInit			ds.l	32					; 14c ; 32 bit mode Segment Map User space
SegMap32CPUInit			ds.l	32					; 1cc ; 32 bit mode Segment Map CPU space
SegMap32OvlInit			ds.l	32					; 24c ; 32 bit mode Segment Map Overlay mode

BATRangeInit			ds.l	32					; 2cc ; BAT mapping ranges

BatMap32SupInit			ds.l	1					; 34c ; 32 bit mode BAT Map Supervisor space
BatMap32UsrInit			ds.l	1					; 350 ; 32 bit mode BAT Map User space
BatMap32CPUInit			ds.l	1					; 354 ; 32 bit mode BAT Map CPU space
BatMap32OvlInit			ds.l	1					; 358 ; 32 bit mode BAT Map Overlay mode

SharedMemoryAddr		ds.l	1					; 35c ; physical address of Mac/Smurf shared message mem

PA_RelocatedLowMemInit	ds.l	1					; 360 ; physical address of RelocatedLowMem

OpenFWBundleOffset		ds.l	1					; 364 ; Offset of base of OpenFirmware PEF Bundle
OpenFWBundleSize		ds.l	1					; 368 ; Number of bytes in OpenFirmware PEF Bundle

LA_OpenFirmware			ds.l	1					; 36c ; logical address of Open Firmware
PA_OpenFirmware			ds.l	1					; 370 ; physical address of Open Firmware
LA_HardwarePriv			ds.l	1					; 374 ; logical address of HardwarePriv callback

;	Used to stop here, plus 8 bytes for cache block alignment (0x380 bytes).
;	Now there be more!

Debug					ds.w	1					; 378 ; > 256 required for screen log
DebugThreshold			equ		257

						org		$388
DebugFlags				ds.l	1					; 388 ; bit 1<< 1 required for screen log
NanodbgrFlagShift		equ		0
NanodbgrFlagBit			equ		31 - NanodbgrFlagShift
LogFlagShift			equ		1
LogFlagBit				equ		31 - LogFlagShift

						org		$100
Size					equ		*
						endr



;_______________________________________________________________________
;	System Info Record
;
;	Used to pass System information from the NanoKernel to user mode
;	software.
;_______________________________________________________________________

NKSystemInfoPtr			equ		$68FFEFF0	; logical address of NKSystemInfo record
NKSystemInfoVer			equ		$68FFEFF4	; version number of NKSystemInfo record
NKSystemInfoLen			equ		$68FFEFF6	; length of NKSystemInfo record

NKSystemInfo			record	0,increment
PhysicalMemorySize		ds.l	1			; 000, irp+dc0 ; Number of bytes in Physical RAM
UsableMemorySize		ds.l	1			; 004, irp+dc4 ; Number of bytes in Usable RAM
LogicalMemorySize		ds.l	1			; 008, irp+dc8 ; Number of bytes in Logical RAM
HashTableSize			ds.l	1			; 00c, irp+dcc ; Number of bytes in Memory Hash Table

L2DataCacheTotalSize	ds.l	1			; 010, irp+dd0 ; number of bytes in the L2 Data Cache
L2InstCacheTotalSize	ds.l	1			; 014, irp+dd4 ; number of bytes in the L2 Instruction Cache
L2CombinedCaches		ds.w	1			; 018, irp+dd8 ; 1 <- combined or no cache, 0 <- split cache
L2InstCacheBlockSize	ds.w	1			; 01a, irp+dda ; number of bytes in a Block of the L2 Instruction Cache
L2DataCacheBlockSize	ds.w	1			; 01c, irp+ddc ; number of bytes in a Block of the L2 Data Cache
L2InstCacheAssociativity ds.w	1			; 01e, irp+dde ; Associativity of the L2 Instruction Cache
L2DataCacheAssociativity ds.w	1			; 020, irp+de0 ; Associativity of the L2 Data Cache
						ds.b	2			; 022, irp+de2 ; unused

						ds.b	2			; 024, irp+de4 ; unused
FlashManufacturerCode	ds.b	1			; 026, irp+de6 ; Flash ROM Manufacturer code
FlashDeviceCode			ds.b	1			; 027, irp+de7 ; Flash ROM Device code
FlashStart				ds.l	1			; 028, irp+de8 ; Starting address of Flash ROM
FlashSize				ds.l	1			; 02c, irp+dec ; Number of bytes in  Flash ROM

Bank0Start				ds.l	1			; 030, irp+df0 ; Starting address of RAM bank 0
Bank0Size				ds.l	1			; 034, irp+df4 ; Number of bytes in  RAM bank 0
Bank1Start				ds.l	1			; 038, irp+df8 ; Starting address of RAM bank 1
Bank1Size				ds.l	1			; 03c, irp+dfc ; Number of bytes in  RAM bank 1
Bank2Start				ds.l	1			; 040, irp+e00 ; Starting address of RAM bank 2
Bank2Size				ds.l	1			; 044, irp+e04 ; Number of bytes in  RAM bank 2
Bank3Start				ds.l	1			; 048, irp+e08 ; Starting address of RAM bank 3
Bank3Size				ds.l	1			; 04c, irp+e0c ; Number of bytes in  RAM bank 3
Bank4Start				ds.l	1			; 050, irp+e10 ; Starting address of RAM bank 4
Bank4Size				ds.l	1			; 054, irp+e14 ; Number of bytes in  RAM bank 4
Bank5Start				ds.l	1			; 058, irp+e18 ; Starting address of RAM bank 5
Bank5Size				ds.l	1			; 05c, irp+e1c ; Number of bytes in  RAM bank 5
Bank6Start				ds.l	1			; 060, irp+e20 ; Starting address of RAM bank 6
Bank6Size				ds.l	1			; 064, irp+e24 ; Number of bytes in  RAM bank 6
Bank7Start				ds.l	1			; 068, irp+e28 ; Starting address of RAM bank 7
Bank7Size				ds.l	1			; 06c, irp+e2c ; Number of bytes in  RAM bank 7
Bank8Start				ds.l	1			; 070, irp+e30 ; Starting address of RAM bank 8
Bank8Size				ds.l	1			; 074, irp+e34 ; Number of bytes in  RAM bank 8
Bank9Start				ds.l	1			; 078, irp+e38 ; Starting address of RAM bank 9
Bank9Size				ds.l	1			; 07c, irp+e3c ; Number of bytes in  RAM bank 9
Bank10Start				ds.l	1			; 080, irp+e40 ; Starting address of RAM bank 10
Bank10Size				ds.l	1			; 084, irp+e44 ; Number of bytes in  RAM bank 10
Bank11Start				ds.l	1			; 088, irp+e48 ; Starting address of RAM bank 11
Bank11Size				ds.l	1			; 08c, irp+e4c ; Number of bytes in  RAM bank 11
Bank12Start				ds.l	1			; 090, irp+e50 ; Starting address of RAM bank 12
Bank12Size				ds.l	1			; 094, irp+e54 ; Number of bytes in  RAM bank 12
Bank13Start				ds.l	1			; 098, irp+e58 ; Starting address of RAM bank 13
Bank13Size				ds.l	1			; 09c, irp+e5c ; Number of bytes in  RAM bank 13
Bank14Start				ds.l	1			; 0a0, irp+e60 ; Starting address of RAM bank 14
Bank14Size				ds.l	1			; 0a4, irp+e64 ; Number of bytes in  RAM bank 14
Bank15Start				ds.l	1			; 0a8, irp+e68 ; Starting address of RAM bank 15
Bank15Size				ds.l	1			; 0ac, irp+e6c ; Number of bytes in  RAM bank 15
Bank16Start				ds.l	1			; 0b0, irp+e70 ; Starting address of RAM bank 16
Bank16Size				ds.l	1			; 0b4, irp+e74 ; Number of bytes in  RAM bank 16
Bank17Start				ds.l	1			; 0b8, irp+e78 ; Starting address of RAM bank 17
Bank17Size				ds.l	1			; 0bc, irp+e7c ; Number of bytes in  RAM bank 17
Bank18Start				ds.l	1			; 0c0, irp+e80 ; Starting address of RAM bank 18
Bank18Size				ds.l	1			; 0c4, irp+e84 ; Number of bytes in  RAM bank 18
Bank19Start				ds.l	1			; 0c8, irp+e88 ; Starting address of RAM bank 19
Bank19Size				ds.l	1			; 0cc, irp+e8c ; Number of bytes in  RAM bank 19
Bank20Start				ds.l	1			; 0d0, irp+e90 ; Starting address of RAM bank 20
Bank20Size				ds.l	1			; 0d4, irp+e94 ; Number of bytes in  RAM bank 20
Bank21Start				ds.l	1			; 0d8, irp+e98 ; Starting address of RAM bank 21
Bank21Size				ds.l	1			; 0dc, irp+e9c ; Number of bytes in  RAM bank 21
Bank22Start				ds.l	1			; 0e0, irp+ea0 ; Starting address of RAM bank 22
Bank22Size				ds.l	1			; 0e4, irp+ea4 ; Number of bytes in  RAM bank 22
Bank23Start				ds.l	1			; 0e8, irp+ea8 ; Starting address of RAM bank 23
Bank23Size				ds.l	1			; 0ec, irp+eac ; Number of bytes in  RAM bank 23
Bank24Start				ds.l	1			; 0f0, irp+eb0 ; Starting address of RAM bank 24
Bank24Size				ds.l	1			; 0f4, irp+eb4 ; Number of bytes in  RAM bank 24
Bank25Start				ds.l	1			; 0f8, irp+eb8 ; Starting address of RAM bank 25
Bank25Size				ds.l	1			; 0fc, irp+ebc ; Number of bytes in  RAM bank 25
EndOfBanks
MaxBanks				equ		26			; Pads out to old struct len (cache block), more to come...

											; Interrupt Support Data
IntCntrBaseAddr			ds.l	1			; 100, irp+ec0 ; Interrupt Controller Base Address  (variable is used since this is a PCI Dev and address is relocatable)
IntPendingReg			ds.l 	2			; 104, irp+ec4 ; Data of current interrupts pending register

											; These fields were added to report information about tightly-coupled L2 caches.
											; The inline L2 information should be used in situations where there is a CPU
											; card L2 cache that can coexist with a motherboard L2.

InlineL2DSize			ds.l	1			; 10c, irp+ecc ; Size of in-line L2 Dcache
InlineL2ISize			ds.l	1			; 110, irp+ed0 ; Size of in-line L2 Icache
InlineL2Combined		ds.w	1			; 114, irp+ed4 ; 1 <- combined or no cache, 0 <- split cache
InlineL2IBlockSize		ds.w	1			; 116, irp+ed6 ; Block size of in-line I L2 cache
InlineL2DBlockSize		ds.w	1			; 118, irp+ed8 ; Block size of in-line D L2 cache
InlineL2IAssoc			ds.w	1			; 11a, irp+eda ; Associativity of L2 I
InlineL2DAssoc			ds.w	1			; 11c, irp+edc ; Associativity of L2 D
						ds.w	1			; 11e, irp+ede ; pad

											; More Interrupt Support Data
IntsCompleted			ds.l 	2			; 120, irp+ee0 ; completed interrupts

						ds.b	$18
Size					equ		*
						endr



;_______________________________________________________________________
;	Diagnostic Info Record
;
;	Used to pass Diagnostic information from the power on Diagnostics to
;	the NanoKernel, and from the NanoKernel to user mode software.
;_______________________________________________________________________

NKDiagInfoPtr			equ		$68FFEFE8	; logical address of DiagnosticInfo record
NKDiagInfoVer			equ		$68FFEFEC	; version number of DiagnosticInfo record
NKDiagInfoLen			equ		$68FFEFEE	; length of DiagnosticInfo record

NKDiagInfo				record	0,increment
BankMBFailOffset		ds.l	1			; 000 ; Mother Board RAM failure code
BankAFailOffset			ds.l	1			; 004 ; Bank A RAM failure code
BankBFailOffset			ds.l	1			; 008 ; Bank B RAM failure code
BankCFailOffset			ds.l	1			; 00c ; Bank C RAM failure code

BankDFailOffset			ds.l	1			; 010 ; Bank D RAM failure code
BankEFailOffset			ds.l	1			; 014 ; Bank E RAM failure code
BankFFailOffset			ds.l	1			; 018 ; Bank F RAM failure code
BankGFailOffset			ds.l	1			; 01c ; Bank G RAM failure code

BankHFailOffset			ds.l	1			; 020 ; Bank H RAM failure code
CacheFailOffset			ds.l	1			; 024 ; cache failure code
LongBootParamOffset		ds.l	1			; 028 ; on longBoot this is where the params will be
POSTTraceOffset			ds.l	1			; 02c ; this tells us what route the POST took

POSTOldWarmOffset		ds.l	1			; 030 ; logged address of old warmstart flag
POSTOldLongOffset		ds.l	1			; 034 ; logged address of old long boot flag
POSTOldGlobbOffset		ds.l	1			; 038 ; logged address of old Diagnostic Info Record
POSTOldParamOffset		ds.l	1			; 03c ; the params from the old diag globb

POSTStartRTCUOffset		ds.l	1			; 040 ; PPC Real Time Clock Upper at start of POST
POSTStartRTCLOffset		ds.l	1			; 044 ; PPC Real Time Clock Lower at start of POST
POSTEndRTCUOffset		ds.l	1			; 048 ; PPC Real Time Clock Upper at end of POST
POSTEndRTCLOffset		ds.l	1			; 04c ; PPC Real Time Clock Lower at end of POST

POSTTestTypeOffset		ds.l	1			; 050 ; when long RAM tests fail test type which failed is put here
POSTError2Offset		ds.l	1			; 054 ; result codes from tests
POSTError3Offset		ds.l	1			; 058 ; result codes from tests
POSTError4Offset		ds.l	1			; 05c ; result codes from tests

RegistersStore			ds.b	140			; 060 ; store all 60x registers here, still fit into 256 bytes size.

;	Everything BEFORE here is new (hence the funny-sized register store)

DiagPOSTResult2			ds.l	1			; 0ec ; POST results
DiagPOSTResult1			ds.l	1			; 0f0 ; POST results
DiagLongBootSig			ds.l	1			; 0f4 ; Burn in restart flag
DiagWarmStartHigh		ds.l	1			; 0f8 ; First long of native warm start  (WLSC)		<SM44>
DiagWarmStartLow		ds.l	1			; 0fc ; Second long of native warm start (SamB)		<SM44>

Size					equ		*
						endr



;_______________________________________________________________________
;	NanoKernel Info Record
;
;	Used to pass NanoKernel statistics from the NanoKernel to user mode
;	software.
;_______________________________________________________________________

NKNanoKernelInfoPtr		equ		$68FFEFE0	; logical address of NanoKernelInfo record
NKNanoKernelInfoVer		equ		$68FFEFE4	; version number of NanoKernelInfo record
NKNanoKernelInfoLen		equ		$68FFEFE6	; length of NanoKernelInfo record

NKNanoKernelInfo		record	0,increment
ExceptionCauseCounts	ds.l	32			; 000, kdp+dc0 ; counters per exception cause
NanoKernelCallCounts	ds.l	16			; 080, kdp+e40 ; counters per NanoKernel call
ExternalIntCount		ds.l	1			; 0c0, kdp+e80 ; count of External Interrupts
MisalignmentCount		ds.l	1			; 0c4, kdp+e84 ; count of Misalignment Interrupts
FPUReloadCount			ds.l	1			; 0c8, kdp+e88 ; count of FPU reloads on demand
DecrementerIntCount		ds.l	1			; 0cc, kdp+e8c ; count of Decrementer Interrupts
QuietWriteCount			ds.l	1			; 0d0, kdp+e90 ; count of Writes to Quiet Read-Only memory
HashTableCreateCount	ds.l	1			; 0d4, kdp+e94 ; count of Hash Table Entry creations
HashTableDeleteCount	ds.l	1			; 0d8, kdp+e98 ; count of Hash Table Entry deletions
HashTableOverflowCount	ds.l	1			; 0dc, kdp+e9c ; count of Hash Table Entry overflows
EmulatedUnimpInstCount	ds.l	1			; 0e0, kdp+ea0 ; count of Emulated unimplemented instructions
NCBPtrCacheMissCount	ds.l	1			; 0e4, kdp+ea4 ; count of NCB Pointer cache misses
ExceptionPropagateCount	ds.l	1			; 0e8, kdp+ea8 ; count of Exceptions propagated to system
ExceptionForcedCount	ds.l	1			; 0ec, kdp+eac ; count of Exceptions forced to system
SysContextCpuTime		ds.l	2			; 0f0, kdp+eb0 ; CPU Time used by System Context
AltContextCpuTime		ds.l	2			; 0f8, kdp+eb4 ; CPU Time used by Alternate Context

;	This stuff is new (starts at 0x100)

blueProcessID			ds.l	1			; 100, kdp+ec0 ; ID of the blue process.
blueTaskID				ds.l	1			; 104, kdp+ec4 ; ID of the blue task.
pageQueueID				ds.l	1			; 108, kdp+ec8 ; ID of the page fault queue.
TaskCount				ds.l	1			; 10c, kdp+ecc ; Number of tasks.
FreePoolExtendCount		ds.l	1			; 110, kdp+ed0 ; Number of pages given to the nanokernel.

;rsrv1					ds.l	3			; 114, kdp+ed4 ; reserved???

;	My additions

						org		$11c
ConfigFlags				ds.l	1			; 11c, kdp+edc ; includes ScreenConsole ... TODO put flag equs here
NanodbgrFlagShift		equ		1
NanodbgrFlagBit			equ		31 - NanodbgrFlagShift
LogFlagShift			equ		3
LogFlagBit				equ		31 - LogFlagShift
;	bit 31 always set on replacement, bit 27 set on replacement with ROM 2.7f3 or later

						org		$128
VMDispatchCountTblPtr	ds.l	1			; 128, kdp+ee8
						ds.l	1
						ds.l	1
MPDispatchCountTblPtr	ds.l	1			; 134, kdp+ef4 ; ???????
AddrSpcSetCtr			ds.l	1			; 138, kdp+ef8 ; incremented by SetAddrSpcRegisters
IDCtr					ds.l	1			; 13c, kdp+efc

						ds.b	$20
Size					equ		*
						endr



;_______________________________________________________________________
;	Processor Info Record
;
;	Used to pass Processor information from the NanoKernel to user mode
;	software.
;_______________________________________________________________________

ProcessorInfoPtr		equ		$68FFEFD8	; logical address of ProcessorInfo record
ProcessorInfoVer		equ		$68FFEFDC	; version number of ProcessorInfo record
ProcessorInfoLen		equ		$68FFEFDE	; length of ProcessorInfo record

ProcessorInfo			record	0,increment
ProcessorVersionReg		ds.l	1			; 000, kdp+f20 ; contents of the PVR special purpose register
CpuClockRateHz			ds.l	1			; 004, kdp+f24 ; CPU Clock frequency
BusClockRateHz			ds.l	1			; 008, kdp+f28 ; Bus Clock frequency
DecClockRateHz			ds.l	1			; 00c, kdp+f2c ; Decrementer Clock frequency

Ovr
PageSize				ds.l	1			; 010, kdp+f30 ; number of bytes in a memory page
DataCacheTotalSize		ds.l	1			; 014, kdp+f34 ; number of bytes in the Data Cache
InstCacheTotalSize		ds.l	1			; 018, kdp+f38 ; number of bytes in the Instruction Cache
CoherencyBlockSize		ds.w	1			; 01c, kdp+f3c ; number of bytes in a Coherency Block
ReservationGranuleSize	ds.w	1			; 01e, kdp+f3e ; number of bytes in a Reservation Granule
CombinedCaches			ds.w	1			; 020, kdp+f40 ; 1 <- combined or no cache, 0 <- split cache
InstCacheLineSize		ds.w	1			; 022, kdp+f42 ; number of bytes in a Line of the Instruction Cache
DataCacheLineSize		ds.w	1			; 024, kdp+f44 ; number of bytes in a Line of the Data Cache
DataCacheBlockSizeTouch	ds.w	1			; 026, kdp+f46 ; number of bytes in a Block for DCBT DCBTST
InstCacheBlockSize		ds.w	1			; 028, kdp+f48 ; number of bytes in a Block of the Instruction Cache
DataCacheBlockSize		ds.w	1			; 02a, kdp+f4a ; number of bytes in a Block of the Data Cache
InstCacheAssociativity	ds.w	1			; 02c, kdp+f4c ; Associativity of the Instruction Cache
DataCacheAssociativity	ds.w	1			; 02e, kdp+f4e ; Associativity of the Data Cache

TransCacheTotalSize		ds.w	1			; 030, kdp+f50 ; number of entries in the Translation Cache
TransCacheAssociativity	ds.w	1			; 032, kdp+f52 ; Associativity of the Translation Cache
OvrEnd

;	These fields were added to report information about back-side L2 caches

ProcessorL2DSize		ds.l	1			; 034, kdp+f54 ; Size of back-side L2 Dcache
ProcessorL2ISize		ds.l	1			; 038, kdp+f58 ; Size of back-side L2 Icache
ProcessorL2Combined		ds.w	1			; 03c, kdp+f5c ; 1 <- combined or no cache, 0 <- split cache
ProcessorL2IBlockSize	ds.w	1			; 03e, kdp+f5e ; Block size of back-side I L2 cache
ProcessorL2DBlockSize	ds.w	1			; 040, kdp+f60 ; Block size of back-side D L2 cache
ProcessorL2IAssoc		ds.w	1			; 042, kdp+f62 ; Associativity of L2 I
ProcessorL2DAssoc		ds.w	1			; 044, kdp+f64 ; Associativity of L2 D

filler1					ds.w	1			; 046, kdp+f66 ; align to long

;	   ProcessorFlags - Definitions for the processor flags field. These are bit positions,
;						as in 1 << hasVMX, and not masks.
hasL2CR					equ		0
hasPLRUL1				equ		1
hasTAU					equ		2
hasVMX					equ		3
unknownFlag				equ		4
hasExtraBATs			equ		5
ProcessorFlags			ds.l	1			; 048, kdp+f68 ; flags to specify processor features

						align	5			; pad to nice cache block alignment
						
						org		$05e
SetToZero				ds.w	1			; 05e, kdp+f7e ; by same code that sets below
CpuClockRateHzCopy		ds.l	1			; 060, kdp+f80 ; copies by Init.s
BusClockRateHzCopy		ds.l	1			; 064, kdp+f84 ; copies by Init.s
DecClockRateHzCopy		ds.l	1			; 068, kdp+f88 ; copies by Init.s

						ds.b	$34
Size					equ		*
						endr



;_______________________________________________________________________
;	Hardware Info Record
;
;	Used to pass hardware information from the NanoKernel to user mode
;	software.
;_______________________________________________________________________

NKHWInfoPtr				equ		$68FFEFD0	; logical address of HWInfo record
NKHWInfoVer				equ		$68FFEFD4	; version number of HWInfo record
NKHWInfoLen				equ		$68FFEFD6	; length of HWInfo record

NKHWInfo				record	0,increment
MacROM_Base				ds.l	1			; 000, irp+f00 ; base address (physical) of Mac ROM
DeviceTreeBase			ds.l	1			; 004, irp+f04 ; base address of the copied device tree properties
UniversalInfoTableBase	ds.l	1			; 008, irp+f08 ; base address of the Universal Info Table
ConfigInfoTableBase		ds.l	1			; 00c, irp+f0c ; base address of the Config Info Table
VectorLookupTable		ds.l	1			; 010, irp+f10 ; base address of the interrupt vector lookup table (short *)
VectorMaskTable			ds.l	1			; 014, irp+f14 ; base address of the interrupt vector mask table (long *)

OpenPICBaseAddr			ds.l	1			; 018, irp+f18 ; OpenPIC base address

ISAMaster8259			ds.l	1			; 01c, irp+f1c ; ISA Master 8259 ports (char *)
ISASlave8259			ds.l	1			; 020, irp+f20 ; ISA Slave 8259 ports (char *)
InterruptAck8259		ds.l	1			; 024, irp+f24 ; address to read to ack 8259 interrupt (long *)

											; interrupt pending bits (actively changing)

PendingInts				ds.l	2			; 028, irp+f28 ; 64 bits of pending interrupts

											; some Mac I/O device base addresses

ADB_Base				ds.l	1			; 030, irp+f30 ; base address of ADB
SCSI_DMA_Base			ds.l	1			; 034, irp+f34 ; base address of SCSI DMA registers

											; RTAS related stuff

RTAS_PrivDataArea		ds.l	1			; 038, irp+f38 ; RTAS private data area 
MacOS_NVRAM_Offset		ds.l	1			; 03c, irp+f3c ; offset into nvram to MacOS data

RTAS_NVRAM_Fetch		ds.l	1			; 040, irp+f40 ; token for RTAS NVRAM fetch
RTAS_NVRAM_Store		ds.l	1			; 044, irp+f44 ; token for RTAS NVRAM store
RTAS_Get_Clock			ds.l	1			; 048, irp+f48 ; token for RTAS clock get
RTAS_Set_Clock			ds.l	1			; 04c, irp+f4c ; token for RTAS clock set
RTAS_Restart			ds.l	1			; 050, irp+f50 ; token for RTAS Restart
RTAS_Shutdown			ds.l	1			; 054, irp+f54 ; token for RTAS Shutdown
RTAS_Restart_At			ds.l	1			; 058, irp+f58 ; token for RTAS system startup at specified time
RTAS_EventScan			ds.l	1			; 05c, irp+f5c ; token for RTAS event scan
RTAS_Check_Exception	ds.l	1			; 060, irp+f60 ; token for RTAS check exception
RTAS_Read_PCI_Config	ds.l	1			; 064, irp+f64 ; token for RTAS read PCI config
RTAS_Write_PCI_Config	ds.l	1			; 068, irp+f68 ; token for RTAS write PCI config

											; SIO interrupt source numbers for the MPIC

SIOIntVect				ds.w	1			; 06c, irp+f6c ; SIO (8259 cascade vector) vector number
SIOIntBit				ds.w	1			; 06e, irp+f6e ; SIO (8259 cascade vector) bit number

Signature				ds.l	1			; 070, irp+f70 ; signature for this record ('Hnfo')

											; more interrupt source numbers

SpuriousIntVect			ds.w	1			; 074, irp+f74 ; spurious vector number

CPU_ID					ds.w	1			; 076, irp+f76 ; the ID of this CPU (universal-tables-related)

SCCAIntVect				ds.w	1			; 078, irp+f78 ; SCC A (non-DMA) vector number
SCCBIntVect				ds.w	1			; 07a, irp+f7a ; SCC B (non-DMA) vector number
SCSIIntVect				ds.w	1			; 07c, irp+f7c ; SCSI vector number
SCSIDMAIntVect			ds.w	1			; 07e, irp+f7e ; SCSI DMA vector number
VIAIntVect				ds.w	1			; 080, irp+f80 ; VIA vector number
VIAIntBit				ds.w	1			; 082, irp+f82 ; VIA bit number
ADBIntVect				ds.w	1			; 084, irp+f84 ; vector number
NMIIntVect				ds.w	1			; 086, irp+f86 ; NMI vector number
NMIIntBit				ds.w	1			; 088, irp+f88 ; NMI bit number

											; current (actively changing) interrupt handling variables

ISAPendingInt			ds.w	1			; 08a, irp+f8a ; currently pending ISA/8259 interrupt
CompletedInts			ds.b	8			; 08c, irp+f8c ; completed interrupts

nkHWInfoFlagSlowMESH	equ		1			; set if fast MESH doesn't work on this box
nkHWInfoFlagAsynchMESH	equ		2			; set if Synchronous MESH doesn't work on this box
nkHWInfoFlagNoCopySWTLB	equ		4			; set if the software TLB walk code for 603 should NOT be copied
HardwareInfoFlags		ds.l	1			; 094, irp+f94 ; 32 bits of flags (see enum above)

RTAS_Get_PowerOn_Time	ds.l	1			; 098, irp+f98 ; token for RTAS getting time for system startup

						ds.b	$24
Size					equ		*
						endr



;_______________________________________________________________________
;	Processor State Record
;
;	Used to save the state of the processor across sleep.
;_______________________________________________________________________

NKProcessorStatePtr		equ		$68FFEFC8	; logical address of ProcessorState record
NKProcessorStateVer		equ		$68FFEFCC	; version number of ProcessorState record
NKProcessorStateLen		equ		$68FFEFCE	; length of ProcessorState record

NKProcessorState		record	0,increment
saveDBAT0u				ds.l	1			; 000 ; place to store DBAT0U
saveDBAT0l				ds.l	1			; 004 ; place to store DBAT0L
saveDBAT1u				ds.l	1			; 008 ; place to store DBAT1U
saveDBAT1l				ds.l	1			; 00c ; place to store DBAT1L
saveDBAT2u				ds.l	1			; 010 ; place to store DBAT2U
saveDBAT2l				ds.l	1			; 014 ; place to store DBAT2L
saveDBAT3u				ds.l	1			; 018 ; place to store DBAT3U
saveDBAT3l				ds.l	1			; 01c ; place to store DBAT3L

saveIBAT0u				ds.l	1			; 020 ; place to store IBAT0U
saveIBAT0l				ds.l	1			; 024 ; place to store IBAT0L
saveIBAT1u				ds.l	1			; 028 ; place to store IBAT1U
saveIBAT1l				ds.l	1			; 02c ; place to store IBAT1L
saveIBAT2u				ds.l	1			; 030 ; place to store IBAT2U
saveIBAT2l				ds.l	1			; 034 ; place to store IBAT2L
saveIBAT3u				ds.l	1			; 038 ; place to store IBAT3U
saveIBAT3l				ds.l	1			; 03c ; place to store IBAT3L

saveSPRG0				ds.l	1			; 040 ; place to store SPRG0
saveSPRG1				ds.l	1			; 044 ; place to store SPRG1
saveSPRG2				ds.l	1			; 048 ; place to store SPRG2
saveSPRG3				ds.l	1			; 04c ; place to store SPRG3

saveL2CR				ds.l	1			; 050 ; place to store Arthur's L2CR

saveSRR0				ds.l	1			; 054 ; place to store SRR0
saveSRR1				ds.l	1			; 058 ; place to store SRR1
saveTBU					ds.l	1			; 05c ; place to store TBU
saveTBL					ds.l	1			; 060 ; place to store TBL
saveHID0				ds.l	1			; 064 ; place to store HID0
saveDEC					ds.l	1			; 068 ; place to store DEC
saveMSR					ds.l	1			; 06c ; place to store MSR
saveSDR1				ds.l	1			; 070 ; place to store SDR1

											; saveKernelDataPtr needs to always be right after saveReturnAddr
											; because of how the code works.  DO NOT CHANGE THIS ORDERING!

saveReturnAddr			ds.l	1			; 074 ; place to store the addr to jump to.
saveKernelDataPtr		ds.l	1			; 078 ; place to store the KernelDataPtr
saveContextPtr			ds.l	1			; 07c ; place to store the ContextPtr
Size					equ		*
						endr






;ΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡ


; <SM15> rb, start
  				MACRO
  				BigLea  	&label,&reg
			lclc &OLDMACH
&OLDMACH		SETC		&Setting('MACHINE')		; save the current Machine setting
				MACHINE		MC68020
  				LEA 		(&label-*).L,&reg
  				LEA 		*-6(pc,&concat(&reg,'.l')),&reg
				MACHINE		&OLDMACH				; reset Machine setting
  				ENDM

  				MACRO
				BigJmp  	&label,&scratch
			lclc &OLDMACH
&OLDMACH		SETC		&Setting('MACHINE')		; save the current Machine setting
				MACHINE		MC68020
  				BRA.L 		(&label)
				MACHINE		&OLDMACH				; reset Machine setting
  				ENDM

  				MACRO
				BigJsr  	&label,&scratch
			lclc &OLDMACH
&OLDMACH		SETC		&Setting('MACHINE')		; save the current Machine setting
				MACHINE		MC68020
				BSR.L 		&label
				MACHINE		&OLDMACH				; reset Machine setting
  				ENDM

  				MACRO								; <t19>
				BigBSR5		&label,&scratch
			lclc &OLDMACH
&OLDMACH		SETC		&Setting('MACHINE')		; save the current Machine setting
				MACHINE		MC68020
				LEA 		@1,A5
  				BRA.L 		(&label)
				MACHINE		&OLDMACH				; reset Machine setting
@1
  				ENDM

  				MACRO								; <CEL - 6/9/89>
				BigBSR6		&label,&scratch
			lclc &OLDMACH
&OLDMACH		SETC		&Setting('MACHINE')		; save the current Machine setting
				MACHINE		MC68020
				LEA 		@1,A6
  				BRA.L 		(&label)
				MACHINE		&OLDMACH				; reset Machine setting
@1
  				ENDM

  				MACRO								; <NJV - 4/30/92><SM5>
  				LongBSR6	&label
			lclc &OLDMACH
&OLDMACH		SETC		&Setting('MACHINE')		; save the current Machine setting
				MACHINE		MC68020
				LEA 		@1,A6
  				BRA.L 		(&label)
				MACHINE		&OLDMACH				; reset Machine setting
@1
  				ENDM

;_________________________________
;
; RAM-less subroutine call macros
;_________________________________


  				MACRO
  				BSR5		&label
			lclc &OLDMACH
&OLDMACH		SETC		&Setting('MACHINE')		; save the current Machine setting
				MACHINE		MC68020
				LEA 		@1,A5
  				BRA.L 		&label
				MACHINE		&OLDMACH				; reset Machine setting
@1
  				ENDM

  				MACRO
  				RTS5
  				JMP 		(A5)
  				ENDM

  				MACRO
  				BSR6		&label
			lclc &OLDMACH
&OLDMACH		SETC		&Setting('MACHINE')		; save the current Machine setting
				MACHINE		MC68020
				LEA 		@1,A6
  				BRA.L 		&label
				MACHINE		&OLDMACH				; reset Machine setting
@1
  				ENDM


; <SM15> rb, end



  				MACRO
  				RTS6
  				JMP 		(A6)
  				ENDM

  				MACRO
  				_GetWaitFlags
  				MOVEA.W 	#2,A0
  				_InternalWait
  				ENDM

  				MACRO
  				_SetWaitFlags
  				MOVEA.W 	#3,A0
  				_InternalWait
  				ENDM

  				MACRO
  				_DisableDynWait
  				MOVEA.W 	#4,A0
  				_InternalWait
  				ENDM

  				MACRO
  				_EnableDynWait
  				MOVEA.W 	#5,A0
  				_InternalWait
  				ENDM

  				MACRO
  				_DisablePermWait
  				MOVEA.W 	#6,A0
  				_InternalWait
  				ENDM

  				MACRO
  				_EnablePermWait
  				MOVEA.W 	#7,A0
  				_InternalWait
  				ENDM

;
; _AssumeEq  Arg1, Arg2 -- macro to generate a compile-time error if two
;                          arguments are unequal.
;
;	To optimize code size, we will be making various assumptions,
;	mainly as to offset values. This macro is a way of formalizing
;	those assumptions within the code.
;
	IF (&TYPE('_AssumeEq') = 'UNDEFINED') THEN
		MACRO              
		_AssumeEq	&Arg1,&Arg2
			IF  &Eval(&Arg1) <> &Eval(&Arg2) THEN
				AERROR 'Bad assumption'
			ENDIF
		ENDM
	ENDIF

;_________________________________________________________________________________			<SM29>
; Memory Dispatch Private Globals
;

MemDispGlobals	RECORD	0, INCREMENT
mdSize			DS.L	1					; size of structure (including lock table)
mdPageSize		DS.L	1					; page size on bytes
mdLog2PageSize	DS.L	1					; Log2(page size)
mdPages24		DS.L	1					; number of logical pages in 24-bit mode
mdPages32		DS.L	1					; number of logical pages in 32-bit mode
mdReserved1		DS.L	1					; reserved
mdPageFrames	DS.L	1					; number of entries in page frame lock table
mdLockTable		EQU		*-MemDispGlobals	; start of page frame lock count table
mdGlobalSize	EQU		*-MemDispGlobals	; size of globals
				ENDR
				
;-------------------------------------------------------------------
;
; Time Manager Local Variable Struct
;

TimeVars  		EQU 		$B30  					; the low memory pointer to the variable struct

;	the following only apply to the old time manager, and may be used in patch files.
TTInt 			EQU 		0 						; time of this interrupt cycle [long]
TTAppoint 		EQU 		4 						; pointer to next appointment in MSQueue [long]
MSQueue   		EQU 		8 						; queue header for MS Queue [10 bytes]
MSLSize   		EQU 		18    					; size of these variables for allocation purposes

;-------------------------------------------------------------------
;	Misc low memory private variables
;
SCCIOPFlag		EQU			$0BFE		; low mem copy of SCC IOP mode PRAM byte as of startup time		<4.9>
IOPMgrVars		EQU			$0C28		; low memory pointer to IOPmgr data structures		<3.1>
				IF &TYPE('__SysEqu__') = 'UNDEFINED' THEN
ADBBase   		EQU 		$0CF8 		; (long) pointer to Front Desk Buss Variables		<3.1>
				ENDIF
EgretBase		EQU			$0DE0		; Egret Manager global variables <2>

				IF &TYPE('__SysEqu__') = 'UNDEFINED' THEN
SlotQDT   		EQU 		$0D04 		; ptr to slot Int queue table						<3.1>
SlotPrTbl 		EQU 		$0D08 		; ptr to slot priority table (ROM $78 only)			<3.1>
SlotVBLQ  		EQU 		$0D0C 		; ptr to slot VBL queue table (ROM $78 only)		<3.1>
ScrnVBLPtr		EQU 		$0D10 		; save for ptr to main screen VBL queue				<3.1>
SlotTICKS 		EQU 		$0D14 		; ptr to slot tickcount table (ROM $78 only)		<3.1>
				ENDIF

AddrMapFlags	EQU			$0DD0		; (long) valid bits for base addresses 0-31  (universal ROM)	<2.7>
AddrMapFlags1	EQU			$2400		; (long) valid bits for base addresses 32-63 (universal ROM)	<SM14>
AddrMapFlags2	EQU			$2404		; (long) valid bits for base addresses 64-95 (universal ROM)	<SM14>
UnivROMFlags	EQU			$0DD4		; (long) product specific flags for universal ROM  0-31			<2.7>
UnivROMFlags1	EQU			$2408		; (long) product specific flags for universal ROM 32-63			<SM14>
UnivROMFlags2	EQU			$240C		; (long) product specific flags for universal ROM 64-95			<SM14>
UnivInfoPtr		EQU			$0DD8		; (long) Pointer to configuration information for universal ROM	<2.7>


;-------------------------------------------------------------------
; Equates for values that the BoxFlag global may take:  each identifies
; a particular logic board.

BoxFlag   			EQU 		$0CB3 		; (byte) identifies which product we are running on				<3.6>

boxUnknown			EQU			$FD			; unknown product												<3.6>
boxPlus				EQU			$FE			; a Mac Plus													<3.6>
boxSE 				EQU 		$FF   		; a Mac SE														<3.6>
boxMacII  			EQU 		0 			; a Mac II														<3.6>
boxMacIIx			EQU 		1 			; a Mac IIx														<3.6>
boxMacIIcx			EQU 		2 			; a Mac IIcx													<3.6>
boxSE30 			EQU 		3   		; a Mac SE 30													<3.6>
boxPortable   		EQU 		4 			; a Mac Portable												<3.6>
boxMacIIci			EQU			5			; Aurora 25MHz 3 slot package									<3.6>
boxFourSquare		EQU			6			; a Four Square (030, 68882, 6 slots, MDU, 2 IOPs, SCSI DMA) (never shipped)	<3.6>
boxMacIIfx			EQU			7			; a F19 (030, 68882, 6 slots, OSS, BIUs, MC, 2 IOPs, SCSI DMA)	<3.6>
boxAuroraCX16		EQU			8			; Aurora 16MHz 3 slot package (never shipped)					<3.6>
boxAuroraSE25		EQU			9			; Aurora 25MHz SE30 package (reserved for future)				<3.6>
boxAuroraSE16		EQU			10			; Aurora 16MHz SE30 package (reserved for future)				<3.6>
boxMacClassic		EQU			11			; XO (SE with 1 int floppy, brightness PWM)						<3>		<9>
boxMacIIsi			EQU			12			; Erickson (20MHz, 030, optl 68882, MDU, RBV,1 direct slot)		<3>		<9>
boxMacLC			EQU			13			; Elsie (16 MHz, 020, 1 direct slot, V8 chip)					<3><7>	<9>
boxQuadra900		EQU			14			; Eclipse (040, 5 slots+PDS, VIA1&2, Orwell MCA, 2 IOPs, SCSI DMA)	<5.1>
boxPowerBook170		EQU			15			; Tim (25 MHz, 030, optional FPU, VIA1&2, JAWS, PMGR, 1 direct slot <4>
boxQuadra700		EQU			16			; Spike (25MHz 040)
boxClassicII		EQU			17			; Apollo
boxPowerBook100		EQU			18			; Asahi (Its a Sony!) Portable									<2>
boxPowerBook140		EQU			19			; TimLC 16 Mhz Tim; no FPU
boxQuadra950		EQU			20			; a Mac Quadra 950 (33MHz 040, 5 slots+PDS, VIA1&2, Orwell MCA, 2 IOPs, SCSI 2*53c96)	<H18>
boxLCIII			EQU			21			; Vail (25 MHz, 030, optional FPU, 1 PDS, Sonora)					<H14><SM41>
boxSoftmacSUN		EQU			22			; Softmac on Sun, (recycled, was boxCarnation33)					<SM52>
boxPowerBookDuo210	EQU			23			; a PowerBook Duo 210 (25MHz 030, PMGR, expansion connector, no floppy)					<H35>
boxCentris650		EQU			24			; Wombat (25MHz 040 or 040LC, 3 slots+PDS, VIA1&2, djMEMC, SCSI 53c96, optional enet)<H21><SM41>
boxColumbia			EQU			25			; Columbia (25 Mhz, 030, PDS, Atlantis Decoder, Color Classic)
boxPowerBookDuo230	EQU			26			; a PowerBook Duo 230 (33MHz 030, PMGR, expansion connector, no floppy)					<H35>
boxPowerBook180		EQU			27			; a PowerBook 180 (33Mhz, 030, FPU, VIA1&2, Niagra, PMGR, 1 direct slot)				<H10> 
boxPowerBook160		EQU			28			; a PowerBook 160 (25Mhz, 030, FPU, VIA1&2, Niagra, PMGR, 1 direct slot)
boxQuadra800		EQU			29			; Wombat (20MHz 040LC, 3 slots+PDS, VIA1&2, djMEMC, SCSI 53c96, optional enet)			<H21><SM41>
boxQuadra650		EQU			30			; Wombat (33Mhz 040, 3 slots+PDS, VIA1&2, djMEMC, SCSI53c96, enet)						<H21><SM41>
boxMacLCII			EQU			31			; Foster Farms (68030 LC)
boxPowerBookDuo250	EQU			32			; Ansel																<SM47>
boxDBLite20			EQU			33			; Pen-based DUO
boxVail16			EQU			34			; Vail (16 MHz, 030, optional FPU, 1 PDS, Sonora)					<H14>
boxCarnation25		EQU			35			; Carnation (25 MHz, 030, FPU, 3 NuBus slots)						<H14>
boxCarnation16		EQU			36			; Carnation (16 MHz, 030, FPU, 3 NuBus slots)						<SM16>
boxCyclone33		EQU			37			; Cyclone <33 Mhz, 040, FPU, 3NuBus slots+DAVE+PUS)				<H14>
boxBrazil16L		EQU			38			; Brazil (16Mhz, Lego package)										<H15>
boxBrazil32L		EQU			39			; Brazil (32MHz on motherboard, Lego package)						<H15>
boxBrazil16F		EQU			40			; Brazil (16MHz, Fridgidaire minitower package)						<H15>
boxBrazil32F		EQU			41			; Brazil (32MHz on motherboard, Fridgidaire package)				<H15>
boxBrazilC			EQU			42			; Brazil (any speed, any package for consumer release)				<H15>
boxSlice			EQU			43			; Slice																<H17>
boxMonet			EQU			44			; Monet (33MHz 030/FPU, VIA1&2, Niagara, PMGR, 16 color LCD, 1 direct slot)	<H19>
boxWombat40			EQU			45			; Wombat (40MHz 040, 3 slots+PDS, VIA1&2, djMEMC, SCSI 53c96, enet)						<H21>
boxCentris610		EQU			46			; WLCD (20 MHz 040LC, PDS only, VIA1&2, djMEMC, SCSI 53c96, optional enet)				<H21><SM41>
boxQuadra610		EQU			47			; WLCD (25 MHz 040LC, PDS only, VIA1&2, djMEMC, SCSI 53c96, optional enet)				<H21><SM41>
boxPowerBook145		EQU			48			; PowerBook 145 (25MHz 030, no FPU, otherwise same as 140)								<H22>
boxBrazil32cF		EQU			49			; Brazil (32MHz w/ext cache, Fridgidaire package)										<H24>
boxHook				EQU			50			; Hook																					<H25>
boxUnused			EQU			51			; (was a Consumer WLCD ... now unused) 													<H26><SM41>
boxWombat20			EQU			52			; Wombat (20MHz 040LC, 3 slots+PDS, VIA1&2, djMEMC, SCSI 53c96, optional enet, Lego)	<H26>
boxWombat40F		EQU			53			; Wombat (40MHz 040, 3 slots+PDS, VIA1&2, djMEMC, SCSI 53c96, enet, Frigidaire package)	<H26>
boxCentris660AV		EQU			54			; (In HORROR, Reality, and Excelsior, this is called BoxCycloneEVT1.)
boxPDM				EQU			55			; Mac/RISC dude (88100 ... (temp) )
boxRiscQuadra700	EQU			55			; Quadra 700 w/Risc Card																<SM40>
boxVail33			EQU			56			; Vail (33 MHz, 030, optional FPU, 1 PDS, ENET, Sonora)									<H31>
boxWLCD33			EQU			57			; WLCD (33 MHz 040, PDS only, VIA1&2, djMEMC, SCSI 53c96, optional enet, QFC)			<H31>
boxPDM66F			EQU			58			; PDM/Cold Fusion (66 Mhz 601, Fridge)													<SM41>
boxPDM80F			EQU			59			; PDM/Cold Fusion (80 Mhz 601, Fridge)													<SM41>
boxPDM100F			EQU			60			; PDM/Cold Fusion (100 Mhz 601, Fridge)													<SM41>
boxTNTProto1		EQU			61			; TNT bringup board
boxTesseractF		EQU			62			; Tesseract (66 Mhz 601, Frigidaire)													<H31>
boxTesseractC		EQU			63			; Tesseract (66 Mhz 601, Consumer)														<H31>
boxJust930			EQU			64			; 930																					<H31>
boxHokusai			EQU			65			; Hokusai (33MHz 030/FPU, VIA1&2, Niagara, PMGR, 256 color TFT LCD, 1 direct slot)		<H31>
boxBlackbird		EQU			66			; Blackbird (50/25MHz 040,   VIA1&2, Pratt, PGE, 256 color 9.4" TFT LCD, 1 direct slot)			<H31>
boxBlackbirdLC		EQU			67			; Blackbird (50/25MHz 040LC, VIA1&2, Pratt, PGE, 256 color 9.4" STN LCD, 1 direct slot)		<H31>
boxPDMEvt1			EQU			68			; PDM (? Mhz 601, WLCD, Evt1)		<SAM>												<H31>
boxPDM50WLCD		EQU			69			; PDM (50 Mhz 601, WLCD)			<SAM>												<H31>
boxYeagerFSTN		EQU			70			; LC040 Duo with FSTN																	<SM47>
boxPowerBookDuo270C	EQU			71			; 33MHz Escher (030, PMGR, expansion connector, no floppy, 256 color TFT LCD, FPU)		<SM47>
boxQuadra840AV		EQU			72			; Cyclone <40 Mhz, 040, FPU, 3NuBus slots+DAVE+PUS)										<SM18>
boxTempest33		EQU			73			; Tempest <33 Mhz, 040LC, 1 Direct Slot slots+DAVE+PUS)									<SM18>
boxHook33			EQU			74			; Hook 33MHz
boxSlice25			EQU			75			; Slice 25MHz
boxRiscCentris650	EQU			76			; Centris650 w/RISC Smurf card															<SM40>
boxSlice33			EQU			77			; 								<15>
boxNorad			Equ			78			; a PowerBook 160 at 33Mhz (see above)
boxBudMan			Equ			79			; 25MHz DBLite with SWIM-2 Floppy and Midas (touchpad)
boxPrimus20			EQU			80			; Primus  (20MHz 040LC, 1 LC slot, VIA1&2, MEMCjr, SCSI 53c96, LC package)				<H37><SM28>
boxOptimus20		EQU			81			; Optimus (20MHz 040LC, 1 LC slot, 1 CommSlot, VIA1&2, MEMCjr, SCSI 53c96, Hook package)<H37><SM28>
boxHookTV			EQU			82			; HookTV  (32MHz 030, no slots, TV Tuner, VIA1&2, VISA decoder, 512k VRAM soldered)	<SM30>
boxLC475			EQU			83			; Primus  (25MHz 040LC, 1 LC slot, VIA1&2, MEMCjr, SCSI 53c96, LC package)				<H38><SM31><SM41>
boxPrimus33			EQU			84			; Primus  (33MHz 040LC, 1 LC slot, VIA1&2, MEMCjr, SCSI 53c96, LC package)				<H38><SM31>
boxOptimus25		EQU			85			; Optimus (25MHz 040LC, 1 LC slot, 1 CommSlot, VIA1&2, MEMCjr, SCSI 53c96, Hook package)<H38><SM31>
boxLC575			EQU			86			; Optimus (33MHz 040  , 1 LC slot, 1 CommSlot, VIA1&2, MEMCjr, SCSI 53c96, Hook package)<H38><SM31><SM41>
boxAladdin20		EQU			87			; Aladdin (20MHz 040LC, 1 LC slot, VIA1&2, MEMCjr, SCSI 53c96, ELB package)				<H38><SM31>
boxQuadra605		EQU			88			; Aladdin (25MHz 040LC, 1 LC slot, VIA1&2, MEMCjr, SCSI 53c96, ELB package)				<H38><SM31><SM41>
boxAladdin33		EQU			89			; Aladdin (33MHz 040  , 1 LC slot, VIA1&2, MEMCjr, SCSI 53c96, ELB package)				<H38><SM31>
boxMalcolm25		EQU			90			; Malcolm (25MHz 040(,LC), PDS only, VIA1&2, MEMCjr, SCSI 53c96, optional ENet, QFC)	<SM35>
boxMalcolm33		EQU			91			; Malcolm (33MHz 040, PDS only, VIA1&2, MEMCjr, SCSI 53c96, optional ENet, QFC)	<SM35>
boxSlimus25			EQU			92			; Slimus  (25MHz 040LC, exactly like an Optimus except in a Color Classic box)			<SM36>
boxSlimus33			EQU			93			; Slimus  (33MHz 040LC, exactly like an Optimus except in a Color Classic box)			<SM36>
boxPDM66WLCD		EQU			94			; PDM (66Mhz 601, WLCD)
boxPDM80WLCD		EQU			95			; PDM (80Mhz 601, WLCD)
boxYeagerG			EQU			96			; Yeager DUO (25MHz 040LC, PMGR, expansion connector, no floppy, MBT, Gray AM)
boxYeagerC			EQU			97			; Yeager DUO (25MHz 040LC, PMGR, expansion connector, no floppy, MBT, Color AM)
boxRiscQuadra900	EQU			98			; 900 with Smurf card																	<SM40>
boxRiscQuadra950	EQU			99			; 950 with Smurf card																	<SM40>
boxRiscCentris610	EQU			100			; C610 with Smurf card																	<SM40>
boxRiscQuadra800	EQU			101			; Q800 with Smurf card																	<SM40>
boxRiscQuadra610	EQU			102			; Q610 with Smurf card																	<SM40>
boxRiscQuadra650	EQU			103			; Q650 with Smurf card																	<SM40>
boxRiscTempest		EQU			104			; Tempest with Smurf card																<SM40>
boxPDM50L			EQU			105			; PDM/Carl Sagan (50MHz 601, HMC, AMIC, AWACS, Mace ENet, Lego package)					<SM41>
boxPDM66L			EQU			106			; PDM/Carl Sagan (66MHz 601, HMC, AMIC, AWACS, Mace ENet, Lego package)					<SM41>
boxPDM80L			EQU			107			; PDM/Carl Sagan (80MHz 601, HMC, AMIC, AWACS, Mace ENet, Lego package)					<SM41>
boxBlackbirdBFD		EQU			108			; Blackbird (66/33MHz 040LC, VIA1&2, Pratt, PGE, 256 color 10.X" TFT LCD, 1 direct slot)<H31>
boxJedi				EQU			109			; Jedi (33MHz, 030, low cost AIO powerbook, MSC, IDE, floppy )							<SM46>
boxSTPQ700			EQU			110			; Q700 with STP card																	<SM48>
boxSTPQ900			EQU			111			; Q900 with STP card																	<SM48>
boxSTPQ950			EQU			112			; Q950 with STP card																	<SM48>
boxSTPC610			EQU			113			; C610 with STP card																	<SM48>
boxSTPC650			EQU			114			; C650 with STP card																	<SM48>
boxSTPQ610			EQU			115			; Q610 with STP card																	<SM48>
boxSTPQ650			EQU			116			; Q650 with STP card																	<SM48>
boxSTPQ800			EQU			117			; Q800 with STP card																	<SM48>
boxAJ				EQU			118			; AJ (66 MHz 603, duo powerbook)														<SM49>
boxAJ80				EQU			119			; AJ (80 MHz 603, duo powerbook)														<SM49>
boxMalcolmBB		EQU			120			; Malcolm (argh, same name as WLCD II)(66 MHz 603 upgrade to Blackbird)					<SM49>
boxMalcolmBB80		EQU			121			; Malcolm (argh, same name as WLCD II)(80 MHz 603 upgrade to Blackbird)					<SM49>
boxM2				EQU			122			; M2 (66 MHz 603, duo powerbook)														<SM49>
boxM280				EQU			123			; M2 (80 MHz 603, duo powerbook)														<SM49>
boxSoftmacHP		EQU			124			; Softmac on HP																			<SM51>
boxSoftmacIBM		EQU			125			; Softmac on IBM																		<SM51>
boxSoftmacAUX		EQU			126			; Softmac on AUX																		<SM51>
boxExtended			EQU			127			; Uses new extended boxflag mechanism													<SM52>
boxLastKnown		EQU			boxExtended	; Please, always update this entry!

;-------------------------------------------------------------------
;	The following boxFlags are being recycled for new CPU's that will be shipping
;	with Capone.  These flags were originally assigned to projects that have never
;	been shipped.  Availability of these boxFlags from list supplied by R. Biasi.
;
boxTellShow			EQU			92			; Tell  (any MHz 040LC, exactly like an Optimus except in a Show or ShowBiz enclosure)	<SM54>
boxTellXfmr			EQU			93			; Tell  (any MHz 040LC, exactly like an Optimus except in a Transformer enclosure)		<SM54>

	ENDIF	; ...already included