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397 lines
17 KiB
Plaintext
397 lines
17 KiB
Plaintext
;
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; File: USTPostProc.a
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;
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; Contains: This file includes the error handling routines and the ram testing routine called
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; by StartInit.
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;
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;
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; Copyright: © 1983-1990, 1992 by Apple Computer, Inc., all rights reserved.
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;
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; Change History (most recent first):
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;
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; <SM3> 11/18/92 fau Modified the Error1-4Handlers to check whether they are running
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; on a YMCADecoder-based machine (A Cyclone). If so, then we will
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; call the correct "death chimes" for Cyclone, using the DSP and
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; not the non-existent ASC.
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; <SM2> 5/1/92 kc Roll in Horror. Comments Follow:
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; <H3> 3/6/92 AL Made a couple of branches and BSR6 branches to long branches
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; because they reference routines in the file USTTestMgr.a, which
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; was moved into USTStartTest1.a after the PROC parts were
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; conditionalized (the UST files outgrew their space, so a couple
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; of them had to be moved elsewhere).
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; <H2> 01/27/92 jmp Conditionalized the PROC parts of this file for use in lining up
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; the UST part of HORROR with that of TERROR/Zydeco.
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; ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
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; Pre-Horror ROM comments begin here.
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; ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
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; <T3> 12/14/90 HJR Changed how non critical tests are reported in PRAM.
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; <T2> 9/17/90 CCH Modified a cache flush routine to b e 68040-friendly.
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; ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
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; Pre-Terror ROM comments begin here.
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; ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
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; <6> 5/18/90 CV Rolling in changes from mainproj. Original comments below.
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; {7} 5/7/90 SS Removed IMPORT of TMVectors because it wasn't used in here
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; anyway.
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; {6} 4/26/90 SS At Error1Handler, set up the stack first thing because if we got
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; there from a failure of SizeMemory, a7 will not be set to
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; anything meaningful.
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; <5> 4/2/90 CV Rolling in changes from mainproj. Original comments below.
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; {5} 3/27/90 SS In the non-critical test error handler I no longer clear the
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; error register (d6) upon exit. I need that result later if I'm
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; in test, so I can't clear it.
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; <4> 3/2/90 CV Replacing file with file from mainproj.
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; {4} 2/27/90 SS Changed the error handler so that if you're in test mode (with
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; burn-in jumper installed) it checks for diagnostic ROMs and
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; returns to them if present. If there are no diagnostic ROMs,
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; operation is the same as before.
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; {3} 2/16/90 SS Added flags to statements which were changed to support Ericson.
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; {2} 2/12/90 MA Writes to PRAM used to use D5 as index into PRAM. Now uses D4.
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; D5 would be destroyed by quasi-power manager or EGRET.
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; <1.7> 11/22/89 rle needed for ZoneV: fix parameters for StartTimer within
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; <1.6> 11/13/89 rle fixed bug in error1handler to enable instruction burst mode
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; <1.5> 11/12/89 CCH Fixed comment in version 1.4 (: instead of a ;)
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; <1.4> 11/11/89 rle needed for ZoneV: corrected bugs inadvertantly introduced when
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; <1.3> 8/22/89 GMR Made Error1Handler jmp directly to test manager, instead of
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; falling
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; <1.2> 6/13/89 GGD Modified to work with latest version of Beep.a, leave cache on,
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; pass
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; <1.1> 6/11/89 GMR Removed INCLUDES, now in header file which includes all others.
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; <1.0> 6/11/89 GMR Added new universal StartTest files for first time to EASE.
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; <1.9> 5/26/89 rle cleaned up file (removed obsolete code); doRAMTest no longer
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; exists
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; <1.8> 5/16/89 rle turn off cache when calling error beeps; don't need RAMTest
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; anymore!
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; <1.7> 4/28/89 rle save/restore register d7 upon calls to error beep within
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; error2handler
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; <1.6> 4/11/89 rle clear results register upon exit from NCErrorHandler
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; <1.5> 3/28/89 rle updated RAMTest for use on all MMU-based machines, in keeping
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; with the new, consistent memory test model
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; <1.4> 2/14/89 RLE test results register when control returned from mod3test for
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; MMU machines
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; <1.3> 2/10/89 RLE update equates to support minimal f-19 build
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; <1.2> 2/6/89 RLE replaced NuMac conditionals with more generic identifiers
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; <1.1> 2/2/89 RLE STPostProc.a is now an independent file, responsible for
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; importting and exportting the procedures it needs and others
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; need; fixed a lot of conditional statements to make them more
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; generic and less CPU-specific; changed NCErrorHandler to log d6
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; and d7 to parameter ram, implementation depending upon the CPU
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; in question; fixed NCErrorHandler to turn off clock chip write
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; protect; changed doRAMTest to handle MMU systems--StartInit
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; still passes in physical addresses and we just turn the MMU off
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; temporarily
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; <1.0> 1/11/89 RLE derived from version 1.4 of StartTest.a modified version history
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; markers for all old versions to start with "[" instead of
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; "<"--this allows changes in STPostProc to be tracked separately
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; changed NCErrorHandler to indicate an error by setting LSB in
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; byte 0 of test parameter ram ($70 on Harpo); d6 and d7 are
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; logged by NCErrorHandler to the bottom eight bytes of test
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; parameter ram ($78 on Harpo) in the event of an error
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;
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; To Do:
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;
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;------------------------------------------------------------------------------
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PostProc PROC ; <v1.1>
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WITH DecoderInfo
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INCLUDE 'UniversalEqu.a' ; <7> rb
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EXPORT goTM
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EXPORT Error1Handler
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EXPORT Error2Handler
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EXPORT Error3Handler
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EXPORT Error4Handler
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EXPORT NCErrorHandler
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IMPORT ErrorBeep1
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IMPORT ErrorBeep2
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IMPORT ErrorBeep3
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IMPORT CritErr
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IMPORT RdXByte
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IMPORT WrXByte
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IMPORT TMEntry1
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IMPORT StartTimer
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IMPORT CycloneBeep ; <SM3> fau
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IMPORT QuasiPwrMgr
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IMPORT Mod3Test
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IMPORT JGetHardwareInfo ; [C43>
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IMPORT ClkWpOff ; <v1.1>
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;-----------**If here, then in board burn in or Service**-------------------
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; We in board burn in (or board tester) because of loopback on VIA SV0-SV1, and/or failure.
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; If no failure, set d6 to reflect good power on tests.
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goTM tst.w d7 ;was any error during tests? [C660>
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bne.s @710 ;yes, d6 has minor code [C660>
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move.l #$87654321,d6 ;no, set good result code
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@710
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; bra Error1Handler ;vector through error handler <v1.9>
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;---------------------------------------------------------------------------
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; Entry to Error1Handler indicates a fatal error on StartTest1 tests. We
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; must assume the screen wasn't cleared or anything. We don't even know
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; where the video card is, so for now lets not do any error display. Leave
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; the screen garbaged.....
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;
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; Entry to Error2Handler indicates a fatal error on StartTest2 tests. The
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; screen should be cleared and the low memory screen globals should be ok.
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; This means we can display some error data on the screen, then continue
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; on to the Test Manager and wait for possible further instructions via
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; the serial port. CritError routine will verify that the video is inited
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; with the "VideoMagic" global.
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;
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; On entry, d6 = minor fail code or failed bit mask for RAM failures.
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; d7.lw = major fail code as per equates and exceptions above.
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; d7.hw = current flag bits, perhaps of minor interest.
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;
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; Registers d7 and d6 are displayed on the screen as follows:
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;
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;
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; Sad "Mac"
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; Icon
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;
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; XXXXXXXX X = D7 contents
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; YYYYYYYY Y = D6 contents
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;
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; We must also check the flag bits in d7 to make sure we aren't in board
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; burn in or service.
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;
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; ErrorBeep1 is called for any error that comes through Error1Handler. That
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; includes the early failures, low RAM, ROM, or an NMI hit while testing.
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;---------------------------------------------------------------------------
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;
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WITH ProductInfo, DecoderInfo, DecoderKinds ; <SM??> fau
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Error1Handler ;first check if we are running on a board tester (burn-in flag set and diag ROM response)
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move.l #aStack,a7 ;set stack pointer value <6>
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moveq #0,d2 ; <4>
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BSR6 JGetHardwareInfo ;Get info on this machine (This sets up A1 - among other things -- to point to product info)
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btst #test,d7 ;burn-in flag set? <4>
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bne.s @OnTester ;yes,we're on a tester so perform the diagRom check<4>
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; If not in test, we want to make a squawk here, so set up regs for Error Beep. <4>
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cmp.b #YMCADecoder,DecoderKind(a1) ; Do we have a YMCA (can't test for DSP 'cause we have no memory and it's in the ; <SM3> fau
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bne.s @DoASC ; no, assume it's an ASC <SM3> fau
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movea.l #1,a1 ; Tell CycloneBeep to play sound #1 <SM3> fau
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BigBSR6 CycloneBeep,a0 ; And go play it... <SM3> fau
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bra.l TMEntry1 ; then go to Test Manager <4>
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@DoASC
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movea.l ASCAddr(a0),a3 ;setup ASC address for BootBeep6 <4>
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movea.l VIA1Addr(a0),a5 ;setup VIA1 address for Beep <1.2><4>
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BigBSR6 ErrorBeep1,a0 ;the first of several squawks... <4>
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bra.l TMEntry1 ;then go to Test Manager <4>
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@OnTester ; <4>
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btst.l #DiagROMExists,d0 ;do we support a diagnostic rom? <9><4>
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beq.s @noDiagRom ;no, continue <4>
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lea @noDiagRom,a6 ;yes, load up return address <4>
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bset #beok,d7 ;then tell the handler its ok <4>
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move.l DiagROMAddr(a0),a1 ;get start of diagnostic ROM <4>
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movem.l (a1)+,d0/a0 ;getting the vector....bus error to @noDiagRom <4>
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cmpi.l #TROMCode,d0 ;didn't bus error, see if codes match <4>
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bne.s @noDiagRom ;don't match,we're not on a tester continue <4>
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lea @noDiagRom,a1 ;in case we're returning via A1... <4>
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jmp (a0) ;jump into diagnostic rom <4>
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@noDiagRom ; <4>
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bclr #beok,d7 ;clear the BusError is OK flag <4>
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;removed conditionals for HcMac (laguna) since laguna is not meant to run this code [v1.2>
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;i.e. the error1handler for laguna and 68000 based macs is in reality error2handler [v1.2>
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; Now if we got here and we are testing (VIA looped) then lets queue
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; up the boot message for the host.
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bset #MsgQ,d7 ;queue up the message
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bset #timer,d7 ;use timer for message timing
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; The VIA 1 timer must be started up with extended count in d4.hw
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move.w #sec,d4 ;set extended timer count
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BigBSR6 StartTimer,a0 ;start timer <v1.4>
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; Flush and enable the appropriate I-Cache
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movec CACR,d0 ; retrieve current CACR <T2>|
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bset #15,d0 ; set 040 "enable I-Cache" bit to see if we're on an 040 V
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movec d0,CACR ; set the bit to see if it sticks
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movec CACR,d0 ;
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btst #15,d0 ; are we on an 040?
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beq.s @notAn040 ; IF we're on an 040 THEN
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MACHINE MC68040 ; perform 040 cache flush, I-cache is already enabled
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cinva ic ; invalidate (flush) the instruction cache
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bra.s @go ; continue
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MACHINE MC68030 ;
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@notAn040 ; ELSE
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movec CACR,d0 ; examine cache control register
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bset #3,d0 ; flush instruction cache
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movec d0,CACR ; execute flush
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movec CACR,d0 ; read new cache control register
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ori.b #$11,d0 ; enable i-cache and burst mode
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movec d0,CACR ; do it
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@go ; ENDIF <T2>
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bra.l TMEntry1 ;then go to Test Manager
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;-----------------
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; Handle an error that occurred after the video was initialized, unless
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; we happen to be in service, then just continue to Test Manager.
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Error2Handler
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moveq #0,d2
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BSR6 JGetHardwareInfo ;Get info on this machine (This sets up A1 - among other things -- to point to product info)
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movea.l ASCAddr(a0),a3 ;setup ASC address for BootBeep6
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movea.l VIA1Addr(a0),a2 ;setup VIA1 address for quasi call <1.2>
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btst #test,d7 ;in service? [C202>
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bne.s @10 ;yes, go to Test Manager [C202>
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cmp.b #YMCADecoder,DecoderKind(a1) ; Do we have a YMCA (can't test for DSP 'cause we have no memory and it's in the <SM3> fau
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bne.s @DoASC ; no, assume it's an ASC <SM3> fau
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movea.l #2,a1 ; Tell CycloneBeep to play sound #1 <SM3> fau
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BigBSR6 CycloneBeep,a0 ; And go play it... <SM3> fau
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BigJmp CritErr,a0 ;display the error data if possible,
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@DoASC
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movea.l a2,a5 ;get VIA1 base in a5 now
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BigBSR6 ErrorBeep1,a0 ;the first of several squawks...
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BigJmp CritErr,a0 ;display the error data if possible,
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;CritErr will return to Test Manager
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@10
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@20 bra.l TMEntry1 ;go to Test Manager
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;-----------------
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; An error occurred during RAMTest call, beep appropriately and display error
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Error3Handler
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moveq #0,d2
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BSR6 JGetHardwareInfo ;Get info on this machine (This sets up A1 - among other things -- to point to product info)
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movea.l ASCAddr(a0),a3 ;setup ASC address for BootBeep6
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movea.l VIA1Addr(a0),a5 ;setup VIA1 address for Beep <1.2>
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cmp.b #YMCADecoder,DecoderKind(a1) ; Do we have a YMCA (can't test for DSP 'cause we have no memory and it's in the <SM3> fau
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bne.s @DoASC ; no, assume it's an ASC <SM3> fau
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movea.l #3,a1 ; Tell CycloneBeep to play sound #1 <SM3> fau
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BigBSR6 CycloneBeep,a0 ; And go play it... <SM3> fau
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BigJmp CritErr,a0 ; display the error data if possible,
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@DoASC
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BigBSR6 ErrorBeep2,a0 ;the second of several squawks...
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BigJmp CritErr,a0 ;display the error data if possible,
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;CritErr will return to Test Manager
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Error4Handler
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moveq #0,d2
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BSR6 JGetHardwareInfo ;Get info on this machine (This sets up A1 - among other things -- to point to product info)
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movea.l ASCAddr(a0),a3 ;setup ASC address for BootBeep6
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movea.l VIA1Addr(a0),a5 ;setup VIA1 address for Beep <1.2>
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cmp.b #YMCADecoder,DecoderKind(a1) ; Do we have a YMCA (can't test for DSP 'cause we have no memory and it's in the <SM3> fau
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bne.s @DoASC ; no, assume it's an ASC <SM3> fau
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movea.l #4,a1 ; Tell CycloneBeep to play sound #1 <SM3> fau
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BigBSR6 CycloneBeep,a0 ; And go play it... <SM3> fau
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BigJmp CritErr,a0 ; display the error data if possible,
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@DoASC
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BigBSR6 ErrorBeep3,a0 ;the third of several squawks...
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BigJmp CritErr,a0 ;display the error data if possible,
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;CritErr will return to Test Manager
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ENDWITH
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;--------------------------------------- [v1.5>
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; Entry to NCErrorHandler indicates that a non-critical error has occurred [v1.5>
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; sometime while running a "nonessential" subsystem like the SCC or Sound [v1.5>
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; results are logged to the last 8 bytes of parameter ram as follows: <v1.0>
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; byte 120 (240) - d6.uub <v1.1>
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; 121 (241) - d6.mub <v1.1>
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; 122 (242) - d6.mlb <v1.1>
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; 123 (243) - d6.llb <v1.1>
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; 124 (---) - d7.uub <v1.1>
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; 125 (---) - d7.mub <v1.1>
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; 126 (250) - d7.mlb <v1.1>
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; 127 (251) - d7.llb <v1.1>
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; <v1.1>
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; In addition, the flag byte (112 for PowerMgr systems, 249 for 030 systems) <v1.1>
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; has its lsbit set to indicate that parameter ram contains non-critical error <v1.1>
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; information. <v1.1>
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;
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NCErrorHandler ; <v1.5>
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cmpi.l #-1,d6 ;is this a fail/no-log? <v1.5>
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beq.w @finish ;yes, return immediately
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move.l DecoderInfo.VIA1Addr(a0),a2 ;else, get VIA1 base address
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@log
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; <v1.1>
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BSR6 ClkWpOff ;turn off write protect to clock chip <v1.1>
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move.w #NCFailFlag,d1 ;read flag byte <v1.1>
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BSR6 RdXbyte ;read parameter ram <v1.1>
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bset.l #0,d1 ;set lsb of flag to indicate non-crit data <v1.1>
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bne.s @not1st ;if this is not the first error, continue
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move.b d1,d2 ;move new flag into data byte <v1.1>
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move.w #NCFailFlag,d1 ;get address byte to send <v1.1>
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BSR6 WrXByte ;write parameter ram <v1.1>
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move.l #(NCFailHist<<16 | NCHistBytes-1),d4 ;prepare to zero history
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@zero swap d4 ;get the PRAM address
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move.w d4,d1 ;put it in the proper register
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addq.w #1,d4 ;go to next location
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moveq.l #0,d2 ;value to write (zero)
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BSR6 WrXByte ;go write it
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swap d4 ;see if we're done
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dbra.w d4,@zero ;continue until done
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@not1st
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move.l #((NCFailHist+NCHistBytes)<<16 | NCHistBytes-2),d4 ;prepare to roll history
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@roll swap d4 ;get source address
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subq.w #2,d4 ;adjust it
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move.w d4,d1 ;read from this address
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BSR6 RdXByte ;perform the read
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move.b d1,d2 ;take the result
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addq.w #1,d4 ;and write it to the next location
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move.w d4,d1 ;modified address goes here
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BSR6 WrXByte ;perform the write
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swap d4 ;retrieve the count
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dbra.w d4,@roll ;and keep going until we're done
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move.w #NCFailHist,d1 ;now store the new failed test #
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move.b d7,d2 ;here's the test number
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BSR6 WrXByte ;write it
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move.l #(NCLastFailure<<16 | NCLstFailBytes-1),d4 ;prepare to store the error code
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@result
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swap d4 ;get the destination address
|
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move.w d4,d1 ;prepare it for the PRAM write
|
|
addq.l #1,d4 ;increment it
|
|
rol.l #8,d6 ;get the next byte of d6
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|
move.b d6,d2 ;prepare to write it
|
|
BSR6 WrXByte ;perform the write
|
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swap d4 ;now retrieve the byte count
|
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dbra.w d4,@result ;and keep going until done
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@finish
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rts ;return to caller <v1.1>
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EndProc
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