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304 lines
11 KiB
Plaintext
304 lines
11 KiB
Plaintext
;
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; File: FPPrivTrap.a
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;
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; Contains: Floating point privileged functions
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;
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; Written by: Apple Numerics Group, DSG
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;
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; Copyright: © 1985-1992 by Apple Computer, Inc., all rights reserved.
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;
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; This file is used in these builds:
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; Change History (most recent first):
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;
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; <2> 1/24/92 KC Add conditional to _SysBreak Macro.
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; Terror Change History:
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;
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; <2> 3/18/91 BG Modified the check for whether or not PrivTrap gets installed to
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; be more general regarding which CPUs have FPUs.
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; <1> 1/21/91 BG first checked in
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LOAD 'StandardEqu.d' ; needed for HWCfgFlags check
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INCLUDE 'HardwarePrivateEqu.a' ; needed for 'UniversalEqu.a'
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; This is not a standard definition in the System Equates, so it is included here
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If &TYPE('_SysBreak') = 'UNDEFINED' Then
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MACRO
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_SysBreak
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MOVE.W #-490, D0
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_SysError
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ENDM
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ENDIF
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MACHINE MC68040
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*
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* THE FOLLOWING CODE IS DIRECTLY LIFTED FROM MPW3.2'S CSANELIBRT881.A SOURCE CODE,
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* WRITTEN BY PAUL FINLAYSON, BRIAN MCGHIE, JON OKADA AND STUART MCDONALD.
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*
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* IF THIS CODE IS ROMMED, tFPPriv TRAP ($A097) SHOULD BE ROMMED, TOO! THEN WE
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* WON'T BE CONTINUALLY INSTALLING IT ON THE FLY. A/UX & VM PEOPLE, ARE YOU LISTENING???
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* THIS ISOLATION OF PRIVILEGED INSTRUCTIONS TO A SINGLE TRAP WAS FOR YOUR BENEFIT.
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* WHY, AS OF THE MAC IICI, HAS NO ONE BURNT tFPPriv TRAP INTO ROM? INSTALLING IT
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* ON THE FLY IS SURELY A NO-NO IN THE A/UX WORLD AND I BET THE A/UX FOLKS AREN'T
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* OVERRIDDING IT... HOW COULD THEY IF INSTALLING IT IS A NO-NO?
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; ***************************************
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; * "Ask and ye shall receive ... " *
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; ***************************************
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tFPPriv EQU $A097 ; privileged instruction trap number
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; _________________________________________________________________________________________
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;
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; InstallPrivTrap - Set up the _FPPriv trap for use, if required
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;
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; Expects: -None-
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; Trashes: A0, D0
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;
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; _________________________________________________________________________________________
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InstallPrivTrap PROC EXPORT
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btst.b #hwCbFPU-8,HWCfgFlags; FPU installed on board? <T2>
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beq.s @exit ; exit if we don't have a HW FPU <T2>
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lea PrivTrap881,A0 ; A0 = PrivTrap881()
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cmp.b #cpu68040,CPUFlag ; are we running on an 040 or 050?
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blt.s @goForIt ; IF CPU >= 040 THEN
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lea PrivTrap040,A0 ; A0 = PrivTrap040()
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@goForIt ; ENDIF
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MOVE.W #tFPPriv,D0 ; D0 = $A097
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_SetTrapAddress ,NEWOS ; Install A-Trap
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@exit rts ; return to caller
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; privileged instruction trap
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;; This routine calls trap code containing privileged instructions. If the trap
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;; has not been installed it installs it. The purpose of this routine is to provide
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;; compatability with future architectures which will not allow user-mode library
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;; code to execute privileged instructions. TO BE ADDED: FSAVE/FRESTORE ENTRIES?
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;;
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;; Trap conventions:
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;; Registers D1,D2,A0,A1,A2 are restored to their pre-call values after the
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;; trap call. Registers D0,A0,A1 are visible to the trap code and provide the
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;; mechanism for input values to the trap code. D0 is the only register that
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;; can be changed by the trap code (after return to the caller). TST.W D0 is
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;; the last instruction before return to the program calling the trap.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; 888888888888 888888888888 1111
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; 88 88 88 88 11 11
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; 88 88 88 88 11 11
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; 88 88 88 88 11
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; 888888888888 888888888888 11
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; 88 88 88 88 11
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; 88 88 88 88 11
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; 88 88 88 88 11
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; 888888888888 888888888888 1111111111
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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ALIGN 16 ; align on nearest cache line boundary
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EXPORT PrivTrap881 ; needed for SANE / Startup code
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PrivTrap881
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CMP.W #0,D0
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BEQ.S SetExcept881 ; Set the exceptions contained in A0
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CMP.W #1,D0
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BEQ.S GetTrapVec881 ; GetTrapVector code
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CMP.W #2,D0
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BEQ.S SetTrapVec881 ; SetTrapVector code
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_SysBreak ; Error in selector code
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rts ; .. exit <T2>
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; SkipMarkRel dc.w SkipMark-QADDX ; offset to SkipMark from QADDX <9/30/90-S.McD.>
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SetExcept881
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FNOP ; Ensure 881 is idle
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MOVE.L A0,D1 ; Copy exceptions into D1
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FSAVE -(SP) ; Save 881 environment
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FMOVE.L FPSR,D0 ; D0 <- FPSR
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AND.W #$00FF,D0 ; Clear previous op flags <5/12/90-S.McD.>
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OR.W D1,D0 ; Set proper exceptions
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FMOVE.L D0,FPSR ; Move results back to FPSR
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FMOVE.L FPCR,D0 ; D0 <- FPCR
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AND.W D1,D0 ; Find exception intersection
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ANDI.L #$FF00,D0 ; Mask off low byte and high word
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BEQ.S SkipMark ; If no intersection, then don't
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; mark exception pending bit
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LEA SkipMark,A0 ; A0 := @FRESTORE <8/31/90-S.McD.>
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FMOVEM.L A0,FPIAR ; FPIAR := A0 <8/31/90-S.McD.>
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;*
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;* Alas, once tFPPriv trap has installed itself, SkipMark is no longer in PACK4!
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;* Since we want FPIAR to always point to something inside PACK4, we must be more
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;* careful how we set it up. Here's how using QADDX's JMP island at $0B6C:
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;*
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; --- Actually, with this code installed in ROM, you DO know where SkipMark
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; --- is, so you can use the address as before. B. Galcher (1/16/91)
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;
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; MOVEA.L $0B6E,A0 ; A0 := &QADDX <9/30/90-S.McD.>
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; ADDA.W SkipMarkRel,A0 ; A0 := &SkipMark in PACK4 <9/30/90-S.McD.>
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CLR.L D0
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MOVE.B 1(SP),D0 ; Load state frame size
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BCLR #3,(SP,D0) ; Clear bit 27 of BIU
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SkipMark
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FRESTORE (SP)+ ; Restore 881 environment
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RTS
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GetTrapVec881
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MOVE.L #$0C0,A1 ; A1 <- &Unordered vector in table
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MOVE.L (A1)+,(A0)+ ; Traps.Unordered <- &Unordered vector
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MOVE.L (A1)+,(A0)+ ; Traps.Inexact <- &Inexact vector
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MOVE.L (A1)+,(A0)+ ; Traps.DivByZero <- &DivByZero vector
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MOVE.L (A1)+,(A0)+ ; Traps.Underflow <- &Underflow vector
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MOVE.L (A1)+,(A0)+ ; Traps.OpError <- &OpError vector
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MOVE.L (A1)+,(A0)+ ; Traps.Overflow <- &Overflow vector
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MOVE.L (A1)+,(A0)+ ; Traps.SigNaN <- &SigNaN vector
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RTS
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SetTrapVec881
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MOVE.L #$0C0,A1 ; A1 <- &Unordered vector in table
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MOVE.L (A0)+,(A1)+ ; &Unordered vector <- Traps.Unordered
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MOVE.L (A0)+,(A1)+ ; &Inexact vector <- Traps.Inexact
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MOVE.L (A0)+,(A1)+ ; &DivByZero vector <- Traps.DivByZero
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MOVE.L (A0)+,(A1)+ ; &Underflow vector <- Traps.Underflow
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MOVE.L (A0)+,(A1)+ ; &OpError vector <- Traps.OpError
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MOVE.L (A0)+,(A1)+ ; &Overflow vector <- Traps.Overflow
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MOVE.L (A0)+,(A1)+ ; &SigNaN vector <- Traps.SigNaN
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RTS
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; 000000000000 444444 000000000000
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; 00 00 44 44 00 00
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; 00 00 44 44 00 00
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; 00 00 44 44 00 00
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; 00 00 44 44 00 00
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; 00 00 444444444444444 00 00
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; 00 00 44 00 00
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; 00 00 44 00 00
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; 000000000000 44 000000000000
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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FPBSUN_VEC040 EQU $1FCC ; special FP exception vector addresses <12/03/90, JPO>
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FPUNFL_VEC040 EQU $1FD0
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FPOPERR_VEC040 EQU $1FD4
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FPOVFL_VEC040 EQU $1FD8
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FPSNAN_VEC040 EQU $1FDC
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ALIGN 16 ; align on nearest cache line boundary
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EXPORT PrivTrap040 ; needed by SANE / Startup code
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PrivTrap040
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CMP.W #0,D0
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BEQ.S SetExcept040 ; Set the exceptions contained in A0
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CMP.W #1,D0
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BEQ.S GetTrapVec040 ; GetTrapVector code
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CMP.W #2,D0
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BEQ.S SetTrapVec040 ; SetTrapVector code
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_SysBreak ; Error in selector code
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rts ; .. exit <T2>
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GetTrapVec040 ; 040-style
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MOVE.L #$0C4,A1 ; A1 <- &Inexact vector in table
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MOVE.L (FPBSUN_VEC040).W,(A0)+ ; Traps.Unordered <- &Unordered vector
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MOVE.L (A1)+,(A0)+ ; Traps.Inexact <- &Inexact vector
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MOVE.L (A1),(A0)+ ; Traps.DivByZero <- &DivByZero vector
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MOVE.L (FPUNFL_VEC040).W,(A0)+ ; Traps.Underflow <- &Underflow vector
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MOVE.L (FPOPERR_VEC040).W,(A0)+; Traps.OpError <- &OpError vector
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MOVE.L (FPOVFL_VEC040).W,(A0)+ ; Traps.Overflow <- &Overflow vector
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MOVE.L (FPSNAN_VEC040).W,(A0)+ ; Traps.SigNaN <- &SigNaN vector
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RTS
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SetTrapVec040
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MOVE.L #$0C4,A1 ; A1 <- &Inexact vector in table
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MOVE.L (A0)+,(FPBSUN_VEC040).W ; &Unordered vector <- Traps.Unordered
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MOVE.L (A0)+,(A1)+ ; &Inexact vector <- Traps.Inexact
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MOVE.L (A0)+,(A1) ; &DivByZero vector <- Traps.DivByZero
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MOVE.L (A0)+,(FPUNFL_VEC040).W ; &Underflow vector <- Traps.Underflow
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MOVE.L (A0)+,(FPOPERR_VEC040).W; &OpError vector <- Traps.OpError
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MOVE.L (A0)+,(FPOVFL_VEC040).W ; &Overflow vector <- Traps.Overflow
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MOVE.L (A0)+,(FPSNAN_VEC040).W ; &SigNaN vector <- Traps.SigNaN
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RTS
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SetExcept040
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FNOP ; Ensure the 040 FP is idle
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MOVE.L A0,D1 ; Copy exceptions into D1
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FMOVE.L FPSR,D0 ; D0 <- FPSR
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AND.W #$00FF,D0 ; Clear previous op flags <5/12/90-S.McD.>
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OR.W D1,D0 ; Set proper exceptions
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FMOVE.L D0,FPSR ; Move results back to FPSR
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FMOVE.L FPCR,D0 ; D0 <- FPCR
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AND.W D0,D1 ; Find exception intersection
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ANDI.L #$FF00,D1 ; Mask off low byte and high word
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BNE.S @1 ; Force vectoring to highest priority exception handler
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RTS ; Return if none enabled
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@1:
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BTST #15,D1 ; BSUN handler?
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BEQ.S @2 ; No
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FMOVE.S #"$7FFFFFFF",FP1 ; Yes; set NaN condition code
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FBGT.W @done ; BSUN set on unordered branch condition
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FNOP
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RTS
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@2:
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BTST #14,D1 ; SNaN?
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BEQ.S @3 ; No
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FCMP.S #"$7FBFFFFF",FP1 ; Yes; compare FP1 with signaling NaN
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BRA.S @done
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@3:
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BTST #13,D1 ; Operror?
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BEQ.S @4 ; No
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FMOVE.S #"$7F800000",FP1 ; Yes; do INF - INF
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FSUB.X FP1,FP1
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BRA.S @done
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@4:
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BTST #12,D1 ; Overflow?
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BEQ.S @5 ; No
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FMOVE.S #"$7F000000",FP1 ; Yes; load large single-precision value
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FSMUL.X FP1,FP1 ; and square it
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@done:
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FNOP ; Flush pending exceptions
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RTS ; Return
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@5:
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BTST #11,D1 ; Underflow?
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BEQ.S @6 ; No
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FMOVE.S #"$1F000000",FP1 ; Yes; load small single-precision value
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FSMUL.X FP1,FP1 ; and square it (result is subnormal/exact)
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BRA.S @done
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@6:
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BTST #10,D1 ; Divide-by-zero?
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BEQ.S @7 ; No. Inexact
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FMOVE.B #1,FP1 ; Yes; divide 1.0 by 0.0
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FDIV.B #0,FP1
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BRA.S @done
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@7:
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FMOVE.B #1,FP1 ; 040 can trap only on INEX2 condition
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FADD.S #"$00800000",FP1 ; add 1.0 to 2.0**-126
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BRA.S @done
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END |