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433 lines
16 KiB
Plaintext
433 lines
16 KiB
Plaintext
;
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; File: HWElemsControl.a
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;
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; Contains: HW Floating Point ELEMS68K ("PACK 5") that calls MC68881/882 or uses MC68040 FPU
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;
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; Written by: Apple Numerics Group, DSG
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;
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; Copyright: © 1985-1992 by Apple Computer, Inc., all rights reserved.
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;
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; Change History (most recent first):
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;
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; <SM2> 2/3/92 CSS Update from Horror: see mod history from below 06 Apr 92, 08 Apr 92.
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; <2> 11/2/91 DTY Put the End after the EndIf.
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; <1> 10/24/91 SAM/KSM Rolled in Regatta file.
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;
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; Regatta Change History:
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;
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; <2> 5/28/91 SAM Merged from TERROR sources. [<2> Fixed a bug in ANNUITY and
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; COMPOUND that used to allow the possibility of spuriously
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; signaling an invalid exception under reasonable circumstances.
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; <1> 5/15/91 SAM Split off from TERROR Proj.
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;
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; Terror Change History:
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;
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; <1> 01/06/91 BG Added to TERROR/BBS for the time.
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;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; File: 881Elemscontrol.a
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;; Implementation of Elems68K for machines using the Motorola 68881/2
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;; Copyright Apple Computer, Inc. 1985-7,1989-92
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;; All Rights Reserved
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;; Confidential and Proprietary to Apple Computer,Inc.
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;;
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;; Written by Clayton Lewis, from the (unshipped) file ChipElems881.a
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;;
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;; Modification history:
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;; Rev1: 17 May 89 Resurrection from ChipElems881.a begins.
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;; 25 Sep 90 96-bit test for tiny fixed; version updated. -SMcD
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;; 01 Oct 90 made MAIN & END conditional assembly for ROM & INIT ... ali
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;; 01 Oct 90 chnaged the label STICKMAP to STICKYMAP2 to avoid
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;; collision with pack 4's STICKYMAP ... ali
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;; 05 Oct 90 merged SMcDÕs conditional assembly scheme for
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;; ÔMAIN ... ENDÕ pair
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;; 05 Apr 91 for financial functions only, a jump over the first argument
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;; fetch was added. thanks to jon okada for patiently single
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;; stepping to find the problem. ... ali
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;; 06 Apr 92 changed version number to 9, updated copyright dates. ... JPO
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;; 08 Apr 92 used FMOVEM to move result in FP0 to memory. ... JPO
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; The stack looks like:
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;; _______________________________________________
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;; | |
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;; | address of argument 3 (if any) | - Long
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;; |_______________________________________________|
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;; | |
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;; | address of argument 2 (if any) | - Long
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;; |_______________________________________________|
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;; | |
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;; | address of argument 1 | - Long
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;; |_______________________________________________|
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;; | |
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;; | opcode (NOTE: change to bit 7 !!!) | - Word
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;; |_______________________________________________|
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;; | |
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;; | return address | - Long
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;; |_______________________________________________|
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;;
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;; The number of addresses depends on the operation. xpwri and xpwry use 2.
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;; compound and annuity use 3. All the rest use only 1.
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;;
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;; Opcode - If bit 7 is set, all extended data must be in 96-bit format.
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;; If bit 7 is clear, all extended data must be in 80-bit format.
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;;
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;; Save registers D0/D1 & A0/A4 & FP2/FP3, and later save FPSR and FPCR.
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;;
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;; | |
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;; | stack as passed |
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;; |_______________________________________________|
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;; | |
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;; | saved D0/D1 & A0/A4 & FP2/FP3 | - 10 Longs
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;; |_______________________________________________|
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;; | |
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;; | saved FPSR | - Long
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;; |_______________________________________________|
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;; | |
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;; | saved FPCR | - Long
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;; |_______________________________________________|
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;;
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;; Conventions - routines getting control through this file may assume:
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;;
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;; ¥ A0 contains the address of the input argument
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;; ¥ A4 contains the address of the exit routine - to exit, use: JMP (A4)
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;; ¥ FP0 contains the input argument itself
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;; ¥ D0 & D1 are junk from routine dispatch
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;; ¥ FP0 must contain the result value for delivery to common exit routines
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;; ¥ routines must exit with stack unchanged!!!
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;; ¥ xpwri, xpwry, compound, annuity are special cases handling own data and exit
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;; ¥ Preserved registers are listed in HWElemsEqus.a
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;; ¥ Routines which must know whether data is 80-bit or 96-bit can test bit 7
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;; of the opcode which is at Opcode+1(SP) immediately after dispatch.
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;;
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;; Except - no registers are preset for annuity and compound.
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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IF &TYPE('InitMe') = 'UNDEFINED' THEN ; to make ½SANE an INIT, MAIN & END must be
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MAIN ; commented out. they are necessary for the
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ENDIF ; the ROM built. ( and also regular testing )
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BLANKS ON
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STRING ASIS
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; DATA MAIN
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; ORG -$100
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CODE
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PRINT ON
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MACHINE MC68020
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MC68881
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INCLUDE 'HWElemsEqus.a'
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FPState EQU $A4A ; floating point state [6 bytes]
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;This is the sole entry point of the package.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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EXPORT ELEMS881
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ELEMS881
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; IF DebugON THEN
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; DC.W $A9FF
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; ENDIF
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BRA.S Elemsbegin
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DC.W $00 ; MAC SPECIFIC STUFF
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STRING ASIS
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DC.B 'PACK'
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DC.W $5
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DC.W $0009 ; VERSION 9 <4/6/92, JPO>
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Beginning of code.
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;; Reserve space, save registers, execute procentry, and dispatch to called routine
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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Elemsbegin
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MOVEM.L Regs,-(SP) ; save working registers
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FMOVEM FPRegs,-(SP)
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ProcEntry
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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FMOVE.L FPSR,-(SP) ; Save status register (high memory)
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FMOVE.L FPCR,-(SP) ; and control register (low memory)
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MOVEQ #0,D1
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FMOVE.L D1,FPCR ; IEEE default rounding, precision, halts
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FMOVE.L D1,FPSR ; clear exceptions (condition code and Quo)
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Move the (extended) destination value to the chip and select appropriate
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;; exit sequence. If it is a financial function, then skip the first fetch <T2>
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;; since it is going to be a destination for the financials. <T2>
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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MOVEA.L Addr1(SP),A0 ; destination address in A0
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; MOVE.B Opcode+1(SP),D0
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; <T2> thru next <T2>
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;; Added this section to handle financials separately. For these functions the
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;; first argument is a destination and at the start may hold garbage including
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;; SNaN. For the 68040, it may slow down the financials since the garbage may
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;; be an unnormalized number, which will trap to the software... ali
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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MOVE.W Opcode(SP),D0 ; grab the entire opword
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BTST #IsItFinan,D0 ; high byte of opword is $C0 if financial
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BEQ.S @2 ; if not, go get the first operand
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BTST #flag96bit,D0 ; it is a financial, find out if 80 or 96 bit
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BEQ.S @3 ; branch to unpack 80-bit input data
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LEA Out96,A4 ; else just take 96-bit input data
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BRA.S LiftOff
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@3
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LEA Out80,A4
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BRA.S LiftOff
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@2
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BTST #flag96bit,D0 ; if not continue, find out if 80 or 96 bit
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BEQ.S @1 ; branch to unpack 80-bit input data
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; BPL.S @1 ; branch to unpack 80-bit input data
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MOVE.W 4(A0),2(A0) ; replicate significant word into junk word <9/25/90-S.McD>
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LEA Out96,A4 ; else just take 96-bit input data <T2>
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FMOVE.X (A0),FP0
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BRA.S LiftOff
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@1
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LEA Out80,A4
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ADDQ.L #6,A0
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MOVE.L (A0),-(SP)
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MOVE.L -(A0),-(SP)
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SUBQ.L #2,A0
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MOVE.L (A0),-(SP)
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FMOVE.X (SP)+,FP0
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LiftOff
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MOVE.W #OPMASK,D1
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AND.B D0,D1
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MOVE.W ElemsTab(D1),D1
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JMP LiftOff(D1)
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ElemsTab
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DC.W RLnx-LiftOff
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DC.W RLog2x-LiftOff
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DC.W RLn1x-LiftOff
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DC.W RLog21x-LiftOff
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DC.W RExpx-LiftOff
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DC.W RExp2x-LiftOff
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DC.W RExp1x-LiftOff
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DC.W RExp21x-LiftOff
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DC.W RXpwri-LiftOff
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DC.W RXpwry-LiftOff
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DC.W RCompound-LiftOff
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DC.W RAnnuity-LiftOff
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DC.W RSin-LiftOff
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DC.W RCos-LiftOff
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DC.W RTan-LiftOff
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DC.W RAtan-LiftOff
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DC.W RRandom-LiftOff
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Exit code
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;; All one argument routines exit through here
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;; A4 contains the address of the appropriate exit routine (80 or 96-bit extended)
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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Out80
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MOVEA.L Addr1(SP),A0 ; destination address in A0
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; FMOVE.X FP0,-(SP) ; move result to stack - DELETED <4/8/92, JPO>
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FMOVEM.X FP0,-(SP) ; move result to stack <4/8/92, JPO>
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MOVE.W (SP)+,(A0)+ ; move result to memory
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ADDQ.L #2,SP
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MOVE.L (SP)+,(A0)+
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MOVE.L (SP)+,(A0)
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BRA.S Exit
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Out96
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MOVEA.L Addr1(SP),A0 ; destination address in A0
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; FMOVE.X FP0,(A0) ; deliver result - DELETED <4/8/92, JPO>
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FMOVEM.X FP0,(A0) ; deliver result <4/8/92, JPO>
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Adjust the pending exceptions
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;; D0.hi MUST contain set bits for each exception to be set
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;; D0.lo MUST contain set bits for each exception to be cleared
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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Exit
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MOVEQ #-1,D1 ; set mask
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EOR.B D1,D0 ; exception bits to be cleared now in D0.lo
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FMOVE FPSR,D1 ; collect current exceptions
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AND.B D0,D1 ; clear unwanted exceptions
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SWAP D0 ; exceptions to be set now in D0.lo
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OR.B D1,D0 ; set desired exceptions
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*
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* The next step is handled in the Procexit code below, so it is commented out.
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* FMOVE D0,FPSR ; record pending exceptions from this "operation"
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*
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Procexit
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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*
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* This is a private PROCEXIT for ½SANE881's PACK5. Since all
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* elementary function exceptions are triggered by PROCEXIT,
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* PROCEXIT is blamed for all of PACK5's exceptions.
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*
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* This code performs the halt mechanism steps discussed on p.168
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* of the Apple Numerics Manual, Second Edition. Figure 23-1
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* (Stack frame for halt), p.169, is quite helpful.
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*
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* This code was written to be as independent as possible from PACK4.
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* ½SANE881 PACK5 will run stand-alone without ½SANE881 PACK4 being present
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* except because ½SANE881 PACK4 always runs with OPERR trapping enabled,
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* the user's invalid halt enable is stored as (BSUN or SNAN), where BSUN,
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* SNAN, and OPERR are, respectively, the three high bits of the eight FPU
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* trap enables. See Figure 2-2 (MC68881/MC68882 FPCR Exception Enable Byte),
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* p.2-2, in Motorola's 881/2 Manual.
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*
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* That is, halt on invalid is enabled if and only if BSUN or SNAN is set in FPCR.
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*
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* OPERR trapping is assumed enabled so PACK4 can override the FPU's default
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* return behavior for operand errors, i.e. so PACK4 can deliver SANE's style
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* of floating-point and integer NaN codes.
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*
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* BEFORE:
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* STACK: FPCR< FPSR< D0_D1/A0_A4/FP2_FP3< RTS< opcode< &DST< &SRC< &SRC2
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*
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* AFTER:
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* STACK: D0_D1/A0_A4/FP2_FP3< RTS< opcode< &DST< &SRC< &SRC2
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*
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* SIDE-EFFECT: Signals the accrued exceptions currently set on the FPU
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* after restoring the saved FPCR & FPSR values on the stack.
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*
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* SCRATCHED: A0, D0, D1.
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*
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OR.B D0,7(SP) ; 'or' in stickies into saved FPSR on stack
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MOVE.B 2(SP),D1 ; d1.b := saved FPCR trap enables byte
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FMOVEM (SP)+,FPCR/FPSR ; restore saved environment (cc not affected)
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*
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* Since OPERR is always enabled, the following branch will never be taken,
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* so it is commented out.
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* BEQ.S PastHalter ; trap enables all zero? then skip haltcheck
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*
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BCLR #5,D1 ; prepare to map invalid enable onto OPERR bit
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BFTST D1{24:2} ; bsun or snan set? (invalid halt enabled?)
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BEQ.S @1 ; if not, leave OPERR bit clear
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BSET #5,D1 ; otherwise, set OPERR bit
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@1:
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AND #%00111110,D1 ; any halts enabled? (ignores INEX1 for BCD)
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; (note: clears high-byte of d1.w for mask)
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BEQ.S PastHalter ; if none enabled then skip halt check
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LSL.B #2,D1 ; left justify halt enables in byte
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Halt check.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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AND D1,D0 ; d0.b := any halt-enable intersections?
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; (note: clears high-byte of d0.w)
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BEQ.S PastHalter ; if no intersections, skip halt code
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LSR.B #3,D0 ; d0.w := 5 intersection bits right justified
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HaltCode
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Make the FP68K halt stack frame.
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;; Save & restore A0 (end of stack frame ptr).
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;; Set up stack frame:
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;; ------------------
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;; Pending D0 - long
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;; -----------------
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;; Pending CCR - word
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;; ------------------
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;; halts&xcps - word < ----
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;; ------------------ ^
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;; MISC rec ptr ----------->
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;; ------------------
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;; SRC2 addr - long
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;; ------------------
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;; SRC addr - long
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;; ------------------
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;; DST addr - long
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;; ------------------
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;; opcode - word
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;; ------------------
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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CLR.L -(SP) ; push bogus pending D0 for PROCEXIT
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CLR.W -(SP) ; push bogus pending CCR for PROCEXIT
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MOVE.B STICKYMAP2(D0),D0 ; d0.w := halts&xcps mapped to SANE order
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MOVE.W D0,-(SP) ; push Halt exceptions (note: high-byte clear)
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MOVE.L SP,-(SP) ; push pointer to stuff now on stack (MISC REC)
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MOVE.L Addr3-8+4+2+2+4(SP),-(SP) ; push &SRC2
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MOVE.L Addr2-8+4+2+2+4+4(SP),-(SP) ; push &SRC
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MOVE.L Addr1-8+4+2+2+4+4+4(SP),-(SP) ; push &DST
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MOVE.W Opcode-8+4+2+2+4+4+4+4(SP),-(SP) ; push ELEM's Opcode
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BSET #7,(SP) ; make it distinguishable from all FP Opcodes
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MOVEA.L #FPState+2,A0
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MOVEA.L (A0),A0 ; haltvector
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JSR (A0) ; call user's halt routine
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; user pops halt frame
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ADDQ #8,SP ; we pop misc rec
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PastHalter
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Stack cleanup and return
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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FMOVEM (SP)+,FPRegs
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MOVEM.L (SP)+,Regs ; restore registers
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RTD #6 ; return, leaving stack clear
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STICKYMAP2: ; maps FPU's 5 accrued bits to SANE order
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; SANE's bits read backwards with OVFL<-->UNFL
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DC.B 0,16,8,24,2,18,10,26,4,20,12,28,6,22,14,30
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DC.B 1,17,9,25,3,19,11,27,5,21,13,29,7,23,15,31
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Here is an alternative way of producing the random number ( following the ;;
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;; same algorithm ). This method allows the operations to be carried out ;;
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;; all in the integer domain, which is good; that is for now. The bad news ;;
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;; is that the old method is still the more efficient way of computing the ;;
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;; random function on a 68040! sorry. ... ali, received from crl and stu. ;; ;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; seed: d0
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;; d1 <- random
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;; MULU.L #16807,D1:D0
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;; DIVU.L #$7FFFFFFF,D1:D0
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Functions of one argument
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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RRandom
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FMUL.W #16807,FP0 ; 7^5 * x
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MOVEQ #0,D0 ; report no exceptions
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FMOVE.L #RANDMODULUS,FP1 ; 2^31-1
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FREM FP1,FP0 ; (7^5 * x) rem (2^31-1)
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FBGE.W @1 ; branch if positive
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FADD FP1,FP0 ; else add 2^31-1 to make positive
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@1
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JMP (A4)
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INCLUDE 'HWElemsExp.a'
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INCLUDE 'HWElemsFinancial.a'
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INCLUDE 'HWElemsCommon.a'
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INCLUDE 'HWElemsLogs.a'
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INCLUDE 'HWElemsTg.a'
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INCLUDE 'HWElemsArcTg.a'
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INCLUDE 'HWElemsSinCos.a'
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INCLUDE 'HWElemsCoeffs.a'
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IF &TYPE('InitMe') = 'UNDEFINED' THEN ; to make ½SANE an INIT, MAIN & END must be
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; Why include a whole file to execute one pseudo-op? Seems kinda silly, doesn't it?
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; INCLUDE '881ELEMSend.a' ; commented out. they are necessary for the
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ENDIF ; the ROM built. ( and also regular testing )
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END
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