996 lines
46 KiB
Plaintext
996 lines
46 KiB
Plaintext
;
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; File: MMUTables.a
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;
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; Contains: MMU setup and manipulation routines
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;
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; Written by: Bob Herold
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;
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; Copyright: © 1986-1993 by Apple Computer, Inc. All rights reserved.
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;
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; Change History (most recent first):
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;
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; <SM23> 12/13/93 PN Roll in KAOs and Horror changes to support Malcom and AJ
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; machines.
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; <SM22> 11/12/93 SAM Roll in <MC3> from mc900ftjesus.
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; <MC3> 11/12/93 SAM For EMMU machines get the EDisk size from beyond the chunk table
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; (see SizeMem for details).
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; <SM21> 11/10/93 fau Update from SuperMunggio <SMG2>.
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; <SMG2> 8/27/93 fau Added a HHead entry to the table of decoders.
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; <SM20> 11/10/93 SAM Roll in <MC2> from mc900ftjesus.
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; <MC2> 11/10/93 SAM We now enforce the upper limit top the EDisk. Currently its set
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; to 255 MB.
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; <SM19> 3/31/93 chp Synchronize SuperMario with changes from <LW2>. Also modify
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; early universal test for has68kEmulator: the constant for this
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; test must be modulo 8 and it is the individualÕs responsibility
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; to look in the correct byte (TestFor is not available yet).
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; <SM18> 3/11/93 SAM Added a flag to bootGlobs that tell this code whether or not to
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; steal chunks of RAM for the EDisk. Added code to check that
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; flag (sgEDiskStealFlag) instead of sgEDiskSize.
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; <LW2> 2/26/93 fau Removed MMC support and changed all names including MMC to YMCA.
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; <SM17> 2/5/93 SAM Added support for emulated MMUs.
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; <SM16> 12/23/92 RC Added Support for Smurf on Wombat
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; <SM15> 12/18/92 RB Updated the MSC MMUTables from Horror, since it was wrong.
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; <SM14> 12/1/92 EH Added tables and code for Pratt Memory controller.
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; <SM13> 11/13/92 rab Roll in Horror changes. Comments follow:
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; <H32> 10/23/92 BG Changed MinBootGlobs to fix the Quadra 9x0 256MB + RAM Disk
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; problem.
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; <H31> 9/11/92 JC Conditionally add support for an 040 board on Vail.
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; <H30> 8/10/92 NJV Added Double-Exposure support for Sonora 3.0.
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; <H29> 7/24/92 NJV Fixed 2 ReAnimator bugs where addresses were being doubly
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; corrected.
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; <H28> 7/15/92 SWC Put the sound buffer size into the 24- and 32-bit size fields in
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; its entry in the physical space table since VM was getting
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; confused.
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; <H27> 7/13/92 SWC Moved the code to move the RAM chunk table below a sound buffer
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; (SkipSoundBuffer) to SizeMemPatch.a since when it was here, the
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; warmstart flag would get trashed and so would the RAM disk.
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; <H25> 7/6/92 SWC Fixed a couple of bugs in SkipSoundBuffer. If a sound buffer is
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; present, we'll separate it out from other RAM in the physical
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; space table so VM won't use it for paging.
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; <H23> 6/23/92 SWC Modified MSC tables to use full page tables. Modified Dart's MMU
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; tables to use the same setup (needed to tweak things a bit). Use
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; TT0 for DBLite and Dartanian LCD video (we both use the same
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; hardware), and TT1 for DBLite's slot space. Added a new routine,
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; SkipSoundBuffer, to move the RAM chunk table down if there is a
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; sound buffer in high RAM. Use a common equate, b32VidBase, to
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; specify the base of a non-RBV video frame buffer (MSC and Sonora
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; versions went away) since that part of the address space is
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; supposed to be reserved for just that purpose.
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; <H22> 6/3/92 HY Change ROM space for LC/Slice to 4mb. DblX slot space now 64k
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; and the rest of I/O space is now mapped straight thru.
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; Removed all mappings in MMU templates/physical templates for
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; on-board video. Remove routine GetVisaSize (we don't support
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; on-board video, so not needed). Add MMU entry for RAM disk.
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; <H20> 5/28/92 BG Added Wombat memory information. As far as MMUs and memory
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; mapping, it should look exactly the same as Orwell (Q700/9x0).
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; <SM12> 11/10/92 GD Rolled in Niagra (for PowerBook) tables from Horror. Also fixed
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; a "forRomulator" build issue.
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; <SM11> 11/3/92 RB Changed the use of LC930 in the 24 bit mode support test to
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; Supports24Bit
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; <SM10> 10/30/92 RB On the LC930, do not force 32 bit mode, since it supports 24 bit
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; mode.
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; <SM9> 10/22/92 HY Change MMU tables for LC II/930 to support PDS flash. Also
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; remove onboard video support, add EDisk entry, and reduce
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; DblX range from 256k to 64k. Increase ROM size from 2 to 4Mb.
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; <SM8> 10/18/92 CCH Added support for PDM and removed padding at the end.
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; <SM7> 9/30/92 fau Added support for the new Cyclone EVT4 decoder, YMCA. It uses
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; the same tables as the MMC, but it is a new entry in the
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; DecoderKinds record.
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; <SM6> 08/19/92 CSS BootGlobs was changed to StartGlobals by DTY in Reality and this file
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; needs changing, also.
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; <SM5> 08/11/92 jmp Added ReAnimator support for Õ030 machines (taken straight from
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; Horror).
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; <SM4> 8/9/92 CCH Added ReAnimatorª support for HMMU-based machines, and allow
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; Orwell-based machines to have HMMUs.
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; <SM3> 7/13/92 CCH Added conditionalized support for Cub Cards on Quadra 700.
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; <SM1> 5/26/92 CSS Cyclone roll in.;
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; <P13> 5/13/92 KW (HV,H18) Roll-in LC II changes. Add MMU templates for LC II,
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; modify InitMMU routine so that the exception vector table
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; contains logical instead of physical addresses, modify @VISA
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; routine to load up A0 and A1 with MMU templates, and modified
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; routine doPhysROM to build the ROM entries according to the way
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; the physical templates are defined if the ROM physical size is
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; not 256mb.
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; (HJR,H17) Modified Niagra MMU Templates so that part of ROM is
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; mapped to the end of Slot E space. This is in order to fake the
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; Slot Manager into using part of the Main rom as the config ROM.
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; It is necessary that if the location of VSCDeclData moves that
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; the corresponding MMU Tables be updated. Updated physNiagra
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; space table.
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; <P12> 4/24/92 KW (JC,H16) Cleaned up Sonora Physical Space Tables.
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; <P11> 4/16/92 KW (JC, H15) Cleaned up Sonora tables.
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; (SWC, H14) Mucked around a bit more with the MSC tables.
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; <P10> 04/16/92 jmp Replaced some hard-coded values with defined constants.
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; <P9> 04/08/92 jmp Updated the physMMC table entries to more accurate reflect
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; reality (I think).
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; <P8> 03/22/92 jmp Removed the ÒisVoidÓ mappings for Slots A&B for MMC in 24-bit
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; mode.
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; <P7> 2/25/92 RMP Modified the 32-Bit MMC table to map in CIVIC register set and
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; VRAM.
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; <P6> 02/07/92 jmp (SWC,H13) Added entries to the MSC tables for slots C and D,
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; which are available when DBLite is plugged into its docking
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; station.
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; (JC,H12) Add support for optionally using full page tables on
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; 030 machines, modify Sonora Tables, and add support for
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; alternate physical ROM address as defined in Universal Tables.
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; (JC,H11) Change to fix Spike problem on Non Sonora builds.
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; (JC,H10) Add support for Double Exposure for Vail as it was done
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; on Foster Farms, and added support for the alternate ROM
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; physical address defined in Universal Tables.
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; <P5> 1/23/92 RMP Hand map slot 9 for MMC table in 24 bit mode (is 2nd half of
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; 2-Meg ROM).
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; <P4> 1/22/92 RMP Added MMC support. Added MMC tables.
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; <P3> 01/13/92 jmp (SWC,H9) Turned off caching for video space for DB-Lite to get
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; around a bug with the GSC.
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; <P2> 1/4/92 RP Changed ROMMaxSize for 2-Meg ROM
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; <1> 5/17/92 kc first checked in
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; <SM0> 3/26/92 kc Rolled in from Horror. Comments follow.
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;ÊÊÊÊÊÊÊÊÊÊÊÊÊÊÊÊÊÊÊÊÊÊÊÊÊÊÊÊÊÊÊÊÊÊÊForce 32-bit mode. (see <SM7> in MemoryMgr.a)ÊÊÊÊÊÊÊÊÊÊÊÊÊÊÊÊÊÊÊ
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; ¥¥¥¥ This should be backed out as soon as we carve out space for
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; the 2 Meg rom from the slot address space. ¥¥¥¥
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; <H17> 4/24/92 HJR Modified Niagra MMU Templates so that part of ROM is mapped to
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; the end of Slot E space. This is in order to fake the Slot
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; Manager into using part of the Main rom as the config ROM. It
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; is necessary that if the location of VSCDeclData moves that the
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; corresponding MMU Tables be updated. Updated physNiagra space
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; table.
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; <H16> 4/19/92 JC Cleaned up Sonora Physical Space Tables.
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; <H15> 4/13/92 JC Cleaned up Sonora tables.
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; <H14> 4/10/92 SWC Mucked around a bit more with the MSC tables.
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; <H13> 1/31/92 SWC Added entries to the MSC tables for slots C and D, which are
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; available when DBLite is plugged into its docking station.
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; <H12> 1/24/92 JC Add support for optionally using full page tables on 030
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; machines, modify Sonora Tables, and add support for alternate
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; physical ROM address as defined in Universal Tables.
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; <H11> 1/22/92 JC Change to fix Spike problem on Non Sonora builds.
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; <H10> 1/20/92 JC Add support for Double Exposure for Vail as it was done on
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; Foster Farms, and added support for the alternate ROM physical
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; address defined in Universal Tables.
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; <H9> 1/6/92 SWC Turned off caching for video space for DB-Lite to get around a
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; bug with the GSC.
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; <H8> 12/16/91 HJR Added NiagraTables for Dartanian.
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; <H7> 12/13/91 SWC Removed video wrap space from MSC tables since the CPU ID
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; register is directly below the LCD frame buffer so we won't have
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; any QuickDraw gotchas.
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; <H6> 12/12/91 CCH Reverted back to making Edisk space uncacheable when VM is on.
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; <H5> 12/3/91 SWC Added MSCVidWrap to specify the video wrap and display size for
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; DB-Lite since its LCD display supports grayscale (and hence more
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; VRAM).
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; <H4> 11/25/91 CCH Added Sonora support.
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; <H3> 11/14/91 jmp (CCH) Mark EDisk address space as cacheable in physical space
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; table.
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; <H2> 10/15/91 SWC Changed BSR to PRamIO to a BSR.L since PRamIO moved from
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; ClockPatch.a to Clock.a.
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; ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
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; Pre-HORROR ROM comments begin here.
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; ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
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; <25> 7/8/91 CCH Bumped padding size.
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; <24> 6/26/91 CCH Moved RAM disk to slot 7 space.
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; <23> 6/25/91 CCH Fixed a bug in HandleTrailing and WriteTableNode for levels that
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; contain no valid descriptors. Increased Max Ram disk size to 256
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; meg. Added Ram disk support to all machines and changed Ram disk
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; address space to slot 6 space.
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; <22> 6/21/91 BG Swapped the order of the case table in FindInfo to match the
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; (new) order of the DecoderKinds table in UniversalEqu.a.
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; <21> 6/13/91 CCH Moved bRamDisk equate to EDiskEqu.a, and changed RAM disk
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; address location.
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; <20> 6/11/91 CCH Created a nonserialized image of i/o space just above existing
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; space on Orwell-based machines and made slot 9 minor slot space
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; non-serialized.
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; <19> 5/31/91 djw Added jump table entries and MMU tables to support DBLite/MSC.
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; <18> 5/23/91 CCH Fixed a bug in WriteTableNode that wrote out page descriptors in
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; the intermediate table when it encountered an entire level of
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; invalid descriptors. Also modified the Jaws template to take
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; advantage of early termination descriptors.
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; <17> 5/9/91 HJR Set VRAMrealSize to LCDMaxSize in the Jaws case in FindInfo and
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; removed the Slot $E entry in physical space table since make
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; physical set that area to be onboard video.
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; <16> 5/9/91 CCH Removed slot $B mapping from 24-bit Jaws template.
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; <15> 4/21/91 CCH Turned on copyback mode at boot on 68040's. Modified Jaws
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; template to add ramdisk support for Tim. Also fixed a bug in
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; HandlerTrailing which screwed up when all pages in a subtable
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; were invalid.
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; <14> 4/5/91 CCH Added slot 9 minor slot space for Orwell machines as
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; kUsageOnboardVideo in physical space table.
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; <13> 3/29/91 CCH Removed slot 9 entry from Orwell physical space tables.
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; <12> 3/19/91 CCH Turned off full-tables for non-68040 machines.
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; <11> 3/19/91 CCH Added modifications to have the MMU create a seperate ram disk
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; area to allow bootable RAM disks under VM and on machines with
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; non-contiguous memory architectures. Also turned on full page
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; tables on 030 machines.
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; <10> 3/5/91 BG Fixed a typo in Template24RBVe. Slot B was mapped to Slot 9.
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; <9> 2/18/91 HJR Fix commenting error.
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; <8> 2/18/91 HJR Corrected physical space table for physLCD. VM now works on
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; Tim.
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; <7> 2/4/91 CCH Added physical space table for Orwell based machines.
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; <6> 1/14/91 CCH Exported Trans.
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; <5> 12/20/90 CCH Changed stack initialization to used fixed value.
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; <4> 10/25/90 CCH Added support for ReAnimator when forRomulator equate is set.
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; <3> 10/2/90 CCH Added padding at the end of the file.
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; <2> 9/9/90 CCH Moved this file into second half-meg of ROM, and rolled in
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; Eclipse and Tim support.
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; ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
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; Pre-Terror ROM comments begin here.
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; ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
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; <3> 6/12/90 JJ Add support for Apple II emulation video modes. Rolled in
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; changes from main project. Original comments follow.
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; {14} 6/7/90 CCH Ensured that only 24 bits are compared in the 24-bit logical
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; video base address when determining which slot to use for video.
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; <2> 5/14/90 CV Fixed mistake in last rev.
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; <1> 5/14/90 CV This file was originally part of MMU.a. It contains the MMU
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; tables. The files were split because the addition of code to
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; support video in slot E made the file grow beyond the space
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; allocated in MMU.a.
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; To Do:
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;
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; implement lower limits (bell & whistle...)
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PRINT OFF
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LOAD 'StandardEqu.d'
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INCLUDE 'HardwarePrivateEqu.a'
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INCLUDE 'MMUEqu.a'
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INCLUDE 'BootEqu.a'
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INCLUDE 'UniversalEqu.a'
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INCLUDE 'EdiskEqu.a'
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PRINT ON
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MACHINE MC68030
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MMUStuff PROC
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EXPORT InitMMU
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IMPORT BaseOfROM, Critical, PramIO, RamTest
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IMPORT RomLoc
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IMPORT SizeSoundBuffer
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WITH StartGlobals
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WITH MMUConfigInfo
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;-----
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; The following table give MMU setup information for the different memory controllers
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; and their associate memory models (contiguous, split, weird with RBV onboard video).
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; Some extra entries have been provide for future overpatches.
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;
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; The Splitxxmb32 entries are for split memory model machines (such as the MDU without
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; onboard video). The xx is the size of the smallest RAM chunk. We can set up early
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; termination entries to match the smallest RAM chunk size, and thereby make the table
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; smaller when we have larger RAM chunks.
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;
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; Include in each table entry is the TC (translation control register), the two
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; translation register values to use, an offset to a template describing how to map
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; the logical address space, an offset to a special template (see next paragraph) and
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; an offset to a 'physical table' template.
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;
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; The special template can be used to create a huge void in the logical space above low
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; memory and start the system heap right below the ROM. This is useful for stress-testing
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; 32 bit addressing. The special template is used when the appropriate parameter RAM bit
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; is set.
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;---
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MMUSetupInfo RECORD 0,INCR
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newtc ds.l 1 ; translation control register
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newtt0 ds.l 1 ; transparent translation reg 0
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newtt1 ds.l 1 ; transparent translation reg 1
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templOff ds.w 1 ; offset to template
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specialOff ds.w 1 ; offset to special template
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physicalOff ds.w 1 ; offset to template for physical space
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size equ * ; size of each table entry
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ENDR
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WITH MMUSetupInfo
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;-----
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; The template tables describe the logical to physical address mapping.
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;
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; Eech entry has a size of a chunk of the logical space, a suggested physical address for
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; the chunk, a type and a cache inhibit flag. The size and physical address fields are
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; long sized. The suggested physical address often is mostly used for the 24 bit mode case.
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;
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; The type and cache inhibit flags are imbedded in the low order 4 bits of the suggested
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; physical address word, as follows:
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;
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; bits 3,2,1,0 - template type, describes how to map these addresses as follows:
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;
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; 0000 - map the logical address straight thru
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; 0001 - a RAM entry. Map to pages of RAM allocated from the chunks found by Starttest.
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; 0010 - a ROM entry for 32 bit mode. Use either the hardware defined physical
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; address of the ROM, or the base of the ROM image if it is running in RAM.
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; 0011 - a ROM entry for 24 bit mode. Use either a 24 bit compatible version of the
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; hardware address of the ROM, or the base of the ROM image running in RAM.
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; 0100 - hack for a quickdraw bug: map to the end of the onboard video buffer
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; This is used to map addresses immediately below the buffer to someplace
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; that won;t cause bus errors, cuz quickdraw sometimes acceses there.
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; 0101 - a video entry. Map to onboard video buffer (at physical zero for RBV)
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; 0110 - use the specific address specified in the template.
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; 0111 - map the address as invalid - this space will be a void in the middle of
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; real RAM
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; 1000 - 24-bit mode wrap area. This is used on processors that don't have an
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; initial-shift feature (i.e. 68040).
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;
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; bit 5 - cache inhibit flag (1 means inhibit the cache, i.e. uncacheable)
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;
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; bit 4 - 68040 cache mode. This is the second bit in the cache mode for a 68040. Bit 5
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; is the first bit and still indicates if the cache is inhibited. If the cache
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; is on, this bit means 1=CopyBack, 0=Writethrough. If the cache is inhibited, this
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; bit means 1=Non Serialized, 0=Serialized.
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;
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; bit 6 - 0 = use early termination of MMU Tables for this block.
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; 1 = map full pages for this block
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;
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;---
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;-----
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; Equates defining the logical address space
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;---
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k8Size equ $00002000 ; 8K
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k32Size equ $00008000 ; 32K
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k128Size equ k32Size*4 ; 128K
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k512Size equ k128Size*4 ; 512K
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DeclRomSize equ $A0000 ; Fake DeclData Rom size
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DeclRomSz equ k128Size ; Fake DeclDate Rom size for super mario
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ROMMaxSize equ $00200000 ; 2M: size of largest possible ROM <SM1> CSS ; <T7>
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IOMaxSize equ $00040000 ; 256k: max size of memory-mapped I/O space ; <7>
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EDskMaxSize equ $10000000 ; 256M: size of largest possible RAM disk ; <T23>
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VRAMMaxSize equ $00200000 ; 2M: size of largest possible VRAM <SM1> CSS
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VidWrapSize equ k32Size ; size of area before frame buffer to map to
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; start of frame buffer. Fixes a Quickdraw bug.
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; NOTE: must be multiple of page size
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RBVMaxSize equ $F8000 ; maximum frame buffer size for RBV.
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LCDMaxSize equ k32Size ; maximum frame buffer size for Waimea LCD. <9>
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; NOTE: must be multiple of page size
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_AssumeEq $100000, VidWrapSize+RBVMaxSize ; total video area must be 1 mb, or
|
|
; template below must change
|
|
|
|
RBVBase32b equ $FBB08000 ; 32 bit mode base of logical RBV frame buffer in slot B <11>
|
|
RBVWrap32b equ RBVBase32b-VidWrapSize ; 32 bit mode address of wrap area
|
|
RBVEnd32b equ RBVBase32b + RBVMaxSize ; 32 bit mode end frame buffer address
|
|
|
|
_AssumeEq 0, RBVWrap32b<<12 ; RBV Wrap must be on 1MB boundary, or
|
|
; template below must change
|
|
_AssumeEq 0, RBVEnd32b<<12 ; end of frame buffer must be on 1MB boundary, or
|
|
; template below must change
|
|
|
|
RBVBase32e equ $FEE08000 ; 32 bit mode base of logical RBV frame buffer in slot E <11>
|
|
RBVWrap32e equ RBVBase32e-VidWrapSize ; 32 bit mode address of wrap area
|
|
RBVEnd32e equ RBVBase32e + RBVMaxSize ; 32 bit mode end frame buffer address
|
|
|
|
_AssumeEq 0, RBVWrap32e<<12 ; RBV Wrap must be on 1MB boundary, or
|
|
; template below must change
|
|
_AssumeEq 0, RBVEnd32e<<12 ; end of frame buffer must be on 1MB boundary, or
|
|
; template below must change
|
|
|
|
LCDBase32 equ $FEE08000 ; 32 bit mode base of logical video frame buffer <9>
|
|
LCDWrap32 equ LCDBase32-VidWrapSize ; 32 bit mode address of wrap area <9>
|
|
LCDEnd32 equ LCDBase32 + LCDMaxSize ; 32 bit mode end frame buffer address <9>
|
|
|
|
_AssumeEq 0, LCDWrap32<<12 ; LCD Wrap must be on 1MB boundary, or
|
|
; template below must change
|
|
|
|
RBVBase24b equ (RBVBase32b<<8)>>8 ; 24 bit mode base of logical RBV frame buffer in slot B <11>
|
|
RBVWrap24b equ RBVBase24b-VidWrapSize ; 24 bit mode address of wrap area
|
|
RBVEnd24b equ RBVBase24b + RBVMaxSize ; 24 bit mode end frame buffer address
|
|
|
|
RBVBase24e equ (RBVBase32e<<8)>>8 ; 24 bit mode base of logical RBV frame buffer in slot E <11>
|
|
RBVWrap24e equ RBVBase24e-VidWrapSize ; 24 bit mode address of wrap area
|
|
RBVEnd24e equ RBVBase24e + RBVMaxSize ; 24 bit mode end frame buffer address
|
|
|
|
LCDBase24 equ (LCDBase32<<8)>>8 ; 24 bit mode base of logical video frame buffer
|
|
LCDWrap24 equ LCDBase24-VidWrapSize ; 24 bit mode address of wrap area
|
|
LCDEnd24 equ LCDBase24 + LCDMaxSize ; 24 bit mode end frame buffer address
|
|
|
|
MSCVidBase EQU $60000000 ; base of built-in frame buffer (not RBV) <t19>
|
|
MSCVidEnd EQU $70000000 ; end of frame buffer <t19>
|
|
|
|
SonoraVidBase EQU $60000000 ; base of built-in frame buffer (not RBV) <H12>
|
|
SonoraVidEnd EQU $70000000 ; end of frame buffer <H12><H15>
|
|
|
|
|
|
bRam equ $0 ; base of RAM area
|
|
bRom24 equ $00800000 ; base of ROM area (24 bit mode)
|
|
bEyeOh24 equ $00F00000 ; base of I/O area (24 bit mode)
|
|
b24Slot9 equ $00900000 ; base of minor slot 9 (24 bit mode)
|
|
b24SlotA equ $00A00000 ; base of minor slot A (24 bit mode)
|
|
b24SlotB equ $00B00000 ; base of minor slot B (24 bit mode)
|
|
b24SlotC equ $00C00000 ; base of minor slot C (24 bit mode)
|
|
b24SlotD equ $00D00000 ; base of minor slot D (24 bit mode)
|
|
b24SlotE equ $00E00000 ; base of minor slot E (24 bit mode)
|
|
t24SlotE equ $00F00000 ; top of minor slot E (24 bit mode) <SM1> CSS <H18>
|
|
b24DblX equ $00FC0000 ; base of Dbl X 24 bit Slot Space on Sonora <H10>
|
|
bTop24Less1 equ $00FFFFFF ; top of address space, less 1 (24 bit mode)
|
|
|
|
bRom32 equ $40000000 ; base of ROM area (32 bit mode)
|
|
bRealRom32 equ $40800000 ; exact base of ROM area (32 bit mode) <7>
|
|
bEyeOh32 equ $50000000 ; base of I/O area (32 bit mode)
|
|
bVideo32 equ $50036000 ; base of video I/O area (32 bit mode) <SM1> CSS <P7>
|
|
bVRAM32 equ $50100000 ; base of VRAM on Cyclone (32 bit mode) <SM1> CSS <P7>
|
|
bRealEyeOh32 equ $50F00000 ; exact base of I/O area (32 bit mode) <7>
|
|
bNonSerEyeOh equ $50F40000 ; base of non-serialized I/O area (32 bit) <T20>
|
|
bNonSerIO equ $51000000 ; base of non-serialized I/0 area (32 bit)
|
|
b32VidBase equ $60000000 ; base of built-in frame buffer (not RBV) <SM12>
|
|
b32Slot9 equ $F9000000 ; base of minor slot 9 (32 bit mode)
|
|
b32SlotA equ $FA000000 ; base of minor slot A (32 bit mode)
|
|
b32SlotB equ $FB000000 ; base of minor slot B (32 bit mode)
|
|
b32SlotC equ $FC000000 ; base of minor slot C (32 bit mode)
|
|
b32SlotD equ $FD000000 ; base of minor slot D (32 bit mode)
|
|
b32SlotE equ $FE000000 ; base of minor slot E (32 bit mode)
|
|
b32SlotF equ $FF000000 ; base of minor slot F (32 bit mode) DO NOT USE!!!
|
|
bTop32Less1 equ $FFFFFFFF ; top of address space, minus 1 (32 bit mode)
|
|
|
|
|
|
;---
|
|
; Equates for Foster Farms templates <SM1> CSS
|
|
;---
|
|
|
|
FFRomMax equ $400000 ; 4 Mb of ROM space <H18><Begin><SM9>
|
|
FFIOMax equ $C0000 ; Max I/O space
|
|
FFVideoMax equ $10000 ; 64k max for video buffer
|
|
FFbPhysVideo equ $9F0000 ; physical base for on-board video
|
|
DblXSlotMax equ $10000 ; maximum size of double X slot space <SM9>
|
|
|
|
FFbShadow equ $00800000 ; base of shadowed memory <SM13>
|
|
FFtShadow equ $00A00000 ; top of shadowed memory <SM13>
|
|
|
|
FFbRom24 equ $00A00000 ; base of FF ROM (24 bit mode) <SM9>
|
|
FFtRom24 equ FFbRom24+FFRomMax ; end of FF ROM (24 bit mode) <SM9>
|
|
|
|
FFbRom32 equ $40A00000 ; base of FF ROM area (32 bit mode)
|
|
FFtRom32 equ FFbRom32+FFRomMax
|
|
FFbEyeOh24 equ $00F00000 ; Beginning of I/O space (24 bit mode)
|
|
FFtEyeOh24 equ FFbEyeOh24+FFIOMax ; End of I/O space (24 bit mode)
|
|
FFbEyeOh32 equ $50F00000 ; Beginning of I/O space (32 bit mode)
|
|
FFtEyeOh32 equ FFbEyeOh32+FFIOMax ; End of I/O space (32 bit mode)
|
|
|
|
FFtDblxSlot24 equ FFtEyeOh24+DblXSlotMax ; Top of Double Exposure slot space (24 bit) <SM9>
|
|
FFtDblXSlot32 equ FFtEyeOh32+DblXSlotMax ; Top of Double Exposure slot space <H18><End>
|
|
|
|
|
|
;---
|
|
; Equates for building and accessing the template
|
|
;---
|
|
|
|
typeMask equ $0000000F ; mask to get type bits <7>
|
|
cBitMask equ $00000020 ; mask to get cache inhibit bit <7>
|
|
c040ModeMask equ $00000030 ; mask to get cache mode bits for 68040 <7>
|
|
physMask equ $FFFF0000 ; mask to get suggested physical address <7>
|
|
FullTblMask equ $00000040 ; mask to get full vs early termination field <H12>
|
|
|
|
; Values for the 68040 Cache Mode field <16>
|
|
|
|
c040CacheField equ 4 ; lsb of 68040 cache mode bits <16>
|
|
c040WriteThru equ (0 << c040CacheField) ; cacheable, writethrough <16>
|
|
c040CopyBack equ (1 << c040CacheField) ; cacheable, copyback <16>
|
|
c040InhibitSer equ (2 << c040CacheField) ; cache inhibited, serialized writes <16>
|
|
c040InhibitNonSer equ (3 << c040CacheField) ; cache inhibited, non-serialized writes<16>
|
|
|
|
cBitNum equ 5 ; bit number of cache inhibit flag <7>
|
|
cInhibit equ cBitMask ; flag for inhibiting cache
|
|
|
|
isThru equ 0 ; type = 0000: logical address = physical address
|
|
isRam equ 1 ; type = 0001: allocate physical addr from RAM chunks
|
|
isRom32 equ 2 ; type = 0010: use physical address of ROM
|
|
isRom24 equ 3 ; type = 0011: use 24 bit mode physical address of ROM
|
|
isVidWrap equ 4 ; type = 0100: wrap to start of video buffer
|
|
isVideo equ 5 ; type = 0101: allocate physical addr from video buffer
|
|
isMap equ 6 ; type = 0110: use suggested physical addr from template
|
|
isVoid equ 7 ; type = 0111: map as invalid
|
|
isWrap24 equ 8 ; type = 1000: start of 24-bit mode wrap <7>
|
|
isVideoRAM equ 9 ; type = 1001: dedicated onboard video RAM <9>
|
|
isEdisk equ 10 ; type = 1010: ram disk <T11>
|
|
|
|
FullTblBit equ 6 ; bit number of full vs early termination field <H12>
|
|
FullTbl equ FullTblMask ; flag for enabling full MMU tables (no early term) <H12>
|
|
|
|
Template RECORD 0,INCR ; Template Entry:
|
|
span ds.l 1 ; span of the entry
|
|
physNflag ds.l 1 ; suggested physical address, & flags <7>
|
|
tEntrySize equ * ; size of a template entry
|
|
ENDR
|
|
|
|
;-----
|
|
; The physical template tables describe the significant sections of the pysical address space.
|
|
; These templates are used ONLY to generate the 'physical table', which is passed to VM and
|
|
; other foreign operating systems such as Pink/Opus and A/UX. The 'physical table' is not used
|
|
; for the vanilla Mac OS.
|
|
;
|
|
; Each physical template entry describes a chunk of the physical address space. Most of the
|
|
; template entries are just copied to the actual physical table. However, RAM intries are
|
|
; dynamically generated.
|
|
;---
|
|
|
|
IF (&TYPE('kUsageRAM') = 'UNDEFINED') THEN
|
|
|
|
; values for PhysicalSpaceUsage
|
|
|
|
kUsageRAM EQU 1
|
|
kUsageROM EQU 2
|
|
kUsageIO EQU 3
|
|
kUsageMinorSlot EQU 4
|
|
kUsageMajorSlot EQU 5
|
|
kUsageLowMemory equ 6
|
|
kUsageBootGlobals equ 7
|
|
kUsageOnboardVideo equ 8
|
|
kUsageOnboardVideoWrap equ 9
|
|
kUsageEDisk equ 10
|
|
|
|
kUsageEndTable equ $FFFF
|
|
kUsageOther EQU 0
|
|
|
|
; values for PhysicalSpaceAtributes bits
|
|
|
|
kCacheableBit EQU 0 ; MMU cacheable
|
|
kCacheableMask EQU 1 ; MMU cacheable
|
|
|
|
cacheable EQU kCacheableMask
|
|
notCacheable EQU 0
|
|
|
|
; structure to describe a range of addresses
|
|
|
|
AddressRange RECORD 0
|
|
address DS.L 1 ; start of range
|
|
rangeSize DS.L 1 ; size of range
|
|
size EQU *
|
|
ENDR
|
|
|
|
; structure to describe a single block of PhysicalSpace
|
|
|
|
PhysicalSpaceBlock RECORD 0
|
|
usage DS.W 1 ; what kind of block this is
|
|
attributes DS.W 1 ; MMU (and other) attributes
|
|
physical DS.B AddressRange ; physical address range
|
|
logical DS.B AddressRange ; suggested 32-bit address range
|
|
logical24 DS.B AddressRange ; suggested 24-bit address range
|
|
; more can be added here in later versions
|
|
size EQU *
|
|
ENDR
|
|
|
|
; structure to describe an entire PhysicalSpace
|
|
|
|
PhysicalSpace RECORD 0
|
|
numEntries DS.W 1 ; number of entries in table
|
|
entrySize DS.W 1 ; size of each entry in table
|
|
firstEntry DS.B PhysicalSpaceBlock ; first in variable-sized table
|
|
ENDR
|
|
|
|
ENDIF
|
|
|
|
;-----
|
|
; InitMMU 7a20 - sets up the MMU depending on what memory controller we are running and
|
|
; what chunks of RAM were found by StartTest.
|
|
;
|
|
; Entry
|
|
; 'Universal ROM' registers
|
|
; a0 - Pointer to table of base addresses
|
|
; a1 - Pointer to ProductInfo record for this machine
|
|
; d0 - Flags indicating which base addresses are valid
|
|
; d1 - Flags indicating which external features are valid
|
|
; d2 - Bits 15..8, BoxFlag info (possibly unknown)
|
|
; d2 - Bits 7..0, Address Decoder Kind (zero if unknown)
|
|
; d7 - bits 31-16: logic board type
|
|
; d7 - bits 15-0: cpu type (0 = 68000, 1 = 68010, 2 = 68020, 3 = 68030, 4 = 68040, etc.) <2>
|
|
;
|
|
; a6 - points to table of RAM chunks, tucked under the top of memory as follows:
|
|
;
|
|
; ------------ <--- top of highest RAM bank
|
|
; + <diags> + --- 2 longs at top of bank are trashed by diagnostics
|
|
; + <diags> + --- ditto
|
|
; + FFFFFFFF +
|
|
; + <size> +
|
|
; + <addr> +
|
|
; + ... +
|
|
; + <size> +
|
|
; + <addr> +
|
|
; ------------ <--- a6
|
|
;
|
|
; Ench RAM chunk is specified by its physical addess and size. The table of
|
|
; RAM chunks is terminiated by a single longword of $FFFFFFFF. The code
|
|
; depends on the table being sorted by chunk start address, with the lowest
|
|
; addressed chunk pointed to by a6.
|
|
;
|
|
;
|
|
; Exit
|
|
; Universal registers d0-d2/d7,a0-a1 preserved
|
|
; a4 - points to BootGlobs in logical space
|
|
; sp - in the middle of the useable logical space
|
|
;
|
|
; Trashes
|
|
; d3-d5/a2-a7 (a4,sp as documented above)
|
|
;
|
|
; Conventions Used:
|
|
; Routines called by InitMMU assume they can trash d0-d1/a0, and must preserve
|
|
; all other registers they use. Exceptions to this rule should be cleary documented.
|
|
;---
|
|
|
|
|
|
Initframe RECORD {InitLink},DECR
|
|
InitRet ds.l 1 ; return address
|
|
InitLink ds.l 1 ; prev value link register
|
|
prodInfoPtr ds.l 1 ; saved a1 - Pointer to ProductInfo record for this machine
|
|
basesPtr ds.l 1 ; saved a0 - Pointer to table of base addresses
|
|
cpuType ds.w 1 ; saved d7 - bits 15-0: cpu type (0 = 68000, 1 = 68010, etc)
|
|
boxInfo ds.w 1 ; - bits 31-16: logic board type
|
|
decoder ds.b 1 ; saved d2 - Bits 7..0, Address Decoder Kind (zero if unknown)
|
|
boxType ds.b 1 ; - Bits 15..8, BoxFlag info (possibly unknown)
|
|
upperD2 ds.w 1 ; - upper word of d2
|
|
extFeatures ds.l 1 ; saved d1 - Flags indicating which external features are valid
|
|
basesValid ds.l 1 ; saved d0 - Flags indicating which base addresses are valid
|
|
SaveURegs equ BasesValid ; save universal registers here
|
|
globChunks ds.l sgMaxChunks*2;<SM6> CSS space for main RAM chunks (addr/size) (last addr -1)
|
|
eDiskChunks ds.l sgMaxChunks*2;<SM6> CSS space for eDisk chunks (addr/size) (last addr -1) <T11>
|
|
lastPhysRam ds.l 1 ; offset in physical table to last RAM chunk entry
|
|
smallest ds.l 1 ; size of smallest chunk, in megabytes
|
|
VRAMPhysBase ds.l 1 ; base of video buffer, if any <9>
|
|
VRAMrealSize ds.l 1 ; unrounded size of video buffer <9>
|
|
VRAMSize ds.l 1 ; size of video buffer, rounded up to MMU page size multiple <9>
|
|
logVRAMBase24 ds.l 1 ; 24-bit logical base address of video <9>
|
|
logVRAMBase32 ds.l 1 ; 32-bit logical base address of video <9>
|
|
logRomBase ds.l 1 ; logical, 24 bit alias-able addr of ROM
|
|
physRomBase ds.l 1 ; physical ROM addr as the hardware sees it
|
|
soundBufferBase ds.l 1 ; base of sound buffer in high RAM (if any) <H25><SM13>
|
|
soundBufferSize ds.l 1 ; size of sound buffer in high RAM (if any) <H25><SM13>
|
|
InitSize equ * ; size of frame
|
|
ENDR
|
|
|
|
WITH InitFrame
|
|
|
|
UnivRegs REG d0-d2/d7/a0-a1 ; registers to preserve for universality
|
|
|
|
InitMMU link a5,#InitSize ; set up stack frame
|
|
bsr SetupGlobals ; set up stack frame, boot globals
|
|
bsr FindInfo ; get ptr to MMU setup info
|
|
; returns a0 = 32 bit info ptr, a1 = 24 bit ptr
|
|
movem.l SaveURegs(a5),UnivRegs ; restore universal registers
|
|
IF forRomulator THEN ; <T11>
|
|
TestInRAM A2 ; check if running ROM image in RAM |
|
|
beq.s @dontAdj ; IF in RAM v
|
|
biglea BaseOfROM,a4 ; get address base of ROM
|
|
suba.l a6,a4 ; calc offset from BootGlobs
|
|
move.l a4,sgAllocOff(a6) ; save allocation offset <SM6> CSS ^
|
|
@dontAdj ; ENDIF |
|
|
ENDIF ; <T11>
|
|
move.l a6,a4 ; return ptr to BootGlobs
|
|
unlk a5 ; remove stack frame
|
|
rts ; EXITROUTINE
|
|
|
|
;-----
|
|
; SetupGlobals 7a38 - sets up the InitMMU stack frame and the BootGlobals record that is passed
|
|
; back to StartInit.
|
|
;
|
|
; Entry:
|
|
;
|
|
; a0 - Pointer to table of base addresses
|
|
; a1 - Pointer to ProductInfo record for this machine
|
|
; d0 - Flags indicating which base addresses are valid
|
|
; d1 - Flags indicating which external features are valid
|
|
; d2 - Bits 15..8, BoxFlag info (possibly unknown)
|
|
; d2 - Bits 7..0, Address Decoder Kind (zero if unknown)
|
|
; d7 - bits 31-16: logic board type
|
|
; d7 - bits 15-0: cpu type (0 = 68000, 1 = 68010, etc)
|
|
;
|
|
; a6 - points to RAM chunk table
|
|
;
|
|
; Exit
|
|
; InitMMU Stack frame set up
|
|
; BootGlobals set up
|
|
;---
|
|
|
|
WITH DecoderInfo
|
|
|
|
SetupGlobals
|
|
movem.l UnivRegs,SaveURegs(a5) ; save universal regs
|
|
move.l ROMAddr(a0),d0 ; get base address of ROM
|
|
move.l d0,logRomBase(a5) ; save it our globals
|
|
|
|
tst.l ROMPhysAddr(a0) ; Check if there is a defined physical ROM base <H12>
|
|
beq @SavePhys ; IF defined physical ROM base THEN <H12>
|
|
move.l ROMPhysAddr(a0),d0 ; use it instead of computed value <H12>
|
|
|
|
@SavePhys move.l d0,physRomBase(a5) ; save it in our globals
|
|
moveq.l #6,d0 ; figure out what kind of MMU we have
|
|
move.b d0,sgTypeMMU(a6) ; save MMU type in BootGlobs <SM6> CSS
|
|
clr.l VRAMSize(a5) ; assume no onboard video <9>
|
|
clr.l VRAMrealSize(a5) ; assume no onboard video <9>
|
|
clr.l VRAMPhysBase(a5) ; assume no VRAM <9>
|
|
|
|
MOVE.B decoder(A5),D2 ; get the decoder type <H27><SM13>
|
|
LEA @Resume,A2 ; (BSR2) <H27><SM13>
|
|
BRA.L SizeSoundBuffer ; get sound buffer attributes (if any) <H27><SM13>
|
|
@Resume MOVE.L A0,soundBufferBase(A5) ; save the base <H27><SM13>
|
|
MOVE.L D0,soundBufferSize(A5) ; and size of the sound buffer (if any) <H27><SM13>
|
|
|
|
move.l #bRamDisk,sgRamDiskBase(a6) ; init logical base of eDisk <T11><SM6> CSS
|
|
clr.l sgRamDiskSize(a6) ; assume empty ram disk <T11><SM6> CSS
|
|
clr.b sgEDiskStealFlag(a6) ; assume no chunks to steal <SAM>
|
|
move.l #-1,eDiskChunks(a5) ; make eDisk chunk table empty too
|
|
|
|
lea $FFFFFFA4,a0
|
|
move.l a0,sgAllocOff(a6) ; save allocation offset <SM6> CSS
|
|
|
|
clr.l d3 ; clear counter <T23>
|
|
move.l sgTestSpace+24(a6),d1 ; Get the amount of bytes allocated by SizeMem for the EDisk <MC3>
|
|
;
|
|
move.l d1,sgRamDiskSize(a6) ; save size of eDisk in boot globals <T11> <SM6> CSS
|
|
@noEdisk ; ENDIF <T11>
|
|
|
|
lea sgRamTable(a6),a0 ; source = chunk table in BootGlobs <SM6> CSS
|
|
lea globChunks(a5),a1 ; destination = our globals
|
|
bsr CopyChunks ; copy RAM chunks to our globals
|
|
move.l d0,smallest(a5) ; remember smallest chunk size
|
|
move.l d1,sgTotalRAM(a6) ; remember total RAM size in BootGlobs <SM6> CSS
|
|
; a0 = top highest bank, d1 = total RAM
|
|
sub.l a0,d1 ; normal phys-to-log offset = total - top
|
|
|
|
moveq.l #0,d0
|
|
|
|
; IF NOT Supports24Bit THEN ; <SM10> rb <SM11> rb
|
|
|
|
bset #mmFigEnable,d0 ; Force 32-bit mode until we make room for a 2 meg rom <SM3> kc ¥¥¥¥
|
|
bset #MMStartMode,d0 ; Force 32-bit mode until we make room for a 2 meg rom <SM3> kc ¥¥¥¥
|
|
bset #MMMixed,d0 ; Force 32-bit mode until we make room for a 2 meg rom <SM3> kc ¥¥¥¥
|
|
bset #MMSysheap,d0 ; Force 32-bit mode until we make room for a 2 meg rom <SM3> kc ¥¥¥¥
|
|
bset #MMROZheap,d0 ; Force 32-bit mode until we make room for a 2 meg rom <SM3> kc ¥¥¥¥
|
|
|
|
; ENDIF ; <SM10> rb
|
|
|
|
move.b d0,sgMMFlags(a6) ; save memory mgr flags in BootGlobs <SM6> CSS
|
|
move.l d1,sgPhys2Log(a6) ; save physical-to-logical offset <SM6> CSS
|
|
rts
|
|
|
|
ENDWITH ; {DecoderInfo}
|
|
|
|
;_____________________________________________________________________________________________
|
|
; Routine ReadPRAMByte 7ada
|
|
;
|
|
; Inputs: D0 - byte # to read from PRAM
|
|
; A5 - local frame pointer for InitMMU
|
|
;
|
|
; Outputs: D0 - byte read
|
|
;
|
|
; Destroys: ??
|
|
;_____________________________________________________________________________________________
|
|
ReadPRAMByte
|
|
movem.l d1-d6/a0-a3,-(sp) ; save regs that may be trashed
|
|
movea.l basesPtr(a5),a0 ; get ptr to hardware bases <4.0>
|
|
movea.l prodInfoPtr(a5),a1 ; get ptr to product info
|
|
move.l extFeatures(a5),d1 ; get external features <5>
|
|
moveq #1,d3 ; read 1 byte
|
|
swap d3 ; high byte contains count
|
|
move.w d0,d3 ; low word contains byte # to read
|
|
subq #2,sp ; allocate buffer space
|
|
movea.l sp,a3
|
|
bsr.l PramIO ; read it and weep... <5><H2>
|
|
moveq #0,d0
|
|
move.b (sp)+,d0 ; get byte out of buffer
|
|
movem.l (sp)+,d1-d6/a0-a3 ; restore regs
|
|
rts
|
|
|
|
;_____________________________________________________________________________________________
|
|
; CleanupGlobals 7b04
|
|
;
|
|
; Fixes up the RAM entries in the physical space table to account for total space
|
|
; occupied by boot globals and mmu tables. Restores the 'universal' registers that were
|
|
; passed in to InitMMU. Converts the ptr to BootGlobals into a logical address. Stuffs
|
|
; a few last tidbits of useful information into BootGlobs. Figures out logical return
|
|
; address for InitMMU.
|
|
;
|
|
; Entry
|
|
; a5 - points to InitMMU stack frame
|
|
; a6 - physical address of BootGlobs
|
|
;
|
|
; Exit:
|
|
; universal registers d0-d2/d7/a0-a1 restored
|
|
; d3 - ROM physical-2-logical conversion constant
|
|
; a2 - InitMMU's logical return address
|
|
; a3 - points to tc value in the 32 bit mode MMUConfigInfo record in BootGlobs
|
|
; a4 - logical address of BootGlobals
|
|
; sp - halfway through logical useable RAM space, clipped at 8 mb unless 'black hole'
|
|
;---
|
|
|
|
CleanupGlobals
|
|
move.l a6,a0 ; get ptr to BootGlobs
|
|
add.l sgPhysicalTableOff(a6),a0 ; get ptr to start of physical table <SM6> CSS
|
|
add.l lastPhysRam(a5),a0 ; get ptr to entry for last RAM chunk
|
|
move.l sgTopOff(a6),d0 ; get offset to top of boot globals area <SM6> CSS
|
|
sub.l sgAllocOff(a6),d0 ; total size = top offset - bottom offset <SM6> CSS
|
|
|
|
WITH PhysicalSpaceBlock
|
|
move.l soundBufferSize(a5),d1 ; get total RAM taken up by sound buffer <H25><SM13>
|
|
add.l d0,d1 ; and boot globals <H25><SM13>
|
|
sub.l d1,physical.rangeSize(a0) ; adjust size last useable chunk <H25><SM13>
|
|
move.l physical.address(a0),d1 ; get address last useable chunk
|
|
add.l physical.rangeSize(a0),d1 ; address bootglobs chunk = addr last + size
|
|
adda.w #PhysicalSpaceBlock.size,a0 ; point at entry for boot globals
|
|
move.l d1,physical.address(a0) ; set address boot globals chunk
|
|
move.l d0,physical.rangeSize(a0) ; set size boot globals chunk
|
|
move.w #kUsageBootGlobals,usage(a0); set usage field of boot globals chunk
|
|
ENDWITH
|
|
|
|
move.l (sp),d5 ; remember return address
|
|
move.l a6,d0 ; get physical ptr to BootGlobs
|
|
add.l sgPhys2Log(a6),d0 ; convert to logical ptr <SM6> CSS
|
|
move.l d0,a4 ; save logical ptr
|
|
|
|
IF forRomulator THEN ; <T11>
|
|
TestInRAM A2 ; check if running ROM image in RAM |
|
|
beq.s @dontAdj ; IF in RAM v
|
|
biglea BaseOfROM,a0 ; get address base of ROM
|
|
suba.l d0,a0 ; calc offset from BootGlobs
|
|
move.l a0,sgAllocOff(a6) ; save allocation offset <SM6> CSS ^
|
|
@dontAdj ; ENDIF |
|
|
ENDIF ; <T11>
|
|
|
|
add.l sgAllocOff(a6),d0 ; get logical address top useable memory <SM6> CSS
|
|
cmp.l #$200000,d0 ; do we have at least two meg of RAM? <5>
|
|
bge.s @plentyORam ; IF we have less than two meg THEN <5>
|
|
lsr.l #2,d0 ; divide amt useable logical memory by 4 <5>
|
|
mulu.l #3,d0 ; multiply by 3 to get 3/4 of useable memory<5>
|
|
bra.s @stakOk ; go set stack <5>
|
|
@plentyORam ; ELSE <5>
|
|
move.l #defStackAddr,d0 ; use default stack size <5>
|
|
@stakOk ; ENDIF
|
|
move.l d0,sp ; set new stack
|
|
|
|
biglea BaseOfROM,a1 ; get physical base address of ROM
|
|
move.l logRomBase(a5),d3 ; get future logical base addr ROM
|
|
sub.l a1,d3 ; get ROM phys-2-log conversion constant
|
|
|
|
move.l InitRet(a5),a2 ; get InitMMU's return address
|
|
add.l d3,a2 ; convert return addr to logical addr
|
|
lea sg32Info+theTC(a6),a3 ; point at 32 bit mode tc <SM6> CSS
|
|
movem.l SaveURegs(a5),UnivRegs ; restore 'universal' registers
|
|
movea.l d5,a5 ; get return address
|
|
jmp (a5) ; return to caller
|
|
|
|
;-----
|
|
; SaveMMUInfo 7b86 - save tc, tt0, tt1, create and save crp
|
|
;
|
|
; Entry: d0 has 1st longword of crp
|
|
; a0 points to translation table
|
|
; a1 points to MMUConfigInfo record where info should be saved
|
|
; a2 points to layout info
|
|
;-----
|
|
|
|
SaveMMUInfo move.l newtc(a2),theTC(a1) ; move tc
|
|
move.l newtt0(a2),theTT0(a1) ; move tt0
|
|
move.l newtt1(a2),theTT1(a1) ; move tt1
|
|
move.l d0,theCRP(a1) ; save 1st half of crp
|
|
move.l a0,theCRP+4(a1) ; save 2nd half crp on 030, full srp on 040
|
|
cmp.w #cpu68040,d7 ; running on a 68040? <7>
|
|
bne.s @exit ; IF on 68040 <7>
|
|
andi.l #$fffffe00,theSRP(a1) ; bits 0-8 of SRP must be zero <7>
|
|
@exit ; ENDIF <7>
|
|
rts
|
|
|
|
|
|
;-----
|
|
; MMUError 7bac - unrecoverable error discovered while setting up MMU.
|
|
;---
|
|
MMUError move.w #102,d6 ; minor error code = MMU setup error <3.2>
|
|
move.l #$0F,d7 ; major error code = NuMac error <3.2>
|
|
bra.l Critical
|
|
|
|
|
|
;-----
|
|
; CopyChunks 7bb8 - copies a RAM chunk table, skipping zero sized chunks, remembering
|
|
; the smallest one, and accumulating the total size of all the chunks.
|
|
;
|
|
; Entry
|
|
; a0 - points to source table of chunks
|
|
; a1 - points to destination table of chunks
|
|
;
|
|
; Exit
|
|
; d0.l - size of smallest RAM chunk
|
|
; d1.l - total size of all chunks
|
|
; a0.l - ptr to end of last chunk
|
|
;---
|
|
|
|
CopyRegs REG d2-d5
|
|
CopyChunks movem.l CopyRegs,-(sp) ; save work regs
|
|
moveq #0,d1 ; init total RAM size to zero
|
|
moveq #-1,d0 ; init smallest size to huge
|
|
moveq #-1,d5 ; end of table marker
|
|
bra.s @startloop ; start in the middle...
|
|
@copyLoop ; LOOP thru RAM chunks in BootGlobs
|
|
cmp.l d0,d3 ; check chunk size
|
|
bhs.s @smallOK ; If it is the smallest so far
|
|
move.l d3,d0 ; save the new smallest size
|
|
@smallOK ; ENDIF
|
|
add.l d3,d1 ; add bank size to total
|
|
move.l d2,d4 ; get ptr to start of bank
|
|
add.l d3,d4 ; ptr to end = start + size
|
|
@startloop move.l (a0)+,d2 ; get next addr from source
|
|
move.l (a0)+,d3 ; get next size from source
|
|
move.l d2,(a1)+ ; save addr in destination
|
|
move.l d3,(a1)+ ; move size to destination
|
|
bne.s @sizeOK ; IF size is zero
|
|
subq #8,a1 ; back up 1 entry in destination
|
|
@sizeOK ; ENDIF
|
|
cmp.l d5,d2 ; check for end of list marker
|
|
bne.s @copyLoop ; REPEAT till end of list
|
|
move.l d4,a0 ; return ptr to end of bank
|
|
movem.l (sp)+,CopyRegs ; restore regs
|
|
rts
|
|
|
|
|
|
;-----
|
|
; FindInfo - massage RAM chunks based on what type of hardware we are on, and return
|
|
; pointers to the layout tables to use in setting up the MMU.
|
|
;
|
|
; On a machine with RBV onboard video, the video buffer space is removed from the Bank A
|
|
; chunk, and the chunks are rearranged so that Bank B, if present, appears first in the
|
|
; table. This makes logical low memory show up in Bank B's faster RAM once the MMU tables
|
|
; are set up.
|
|
;
|
|
; On machines with a simple split memory architecture, the size of the smallest chunk is
|
|
; used to pick which layout table to use. This allows smaller tables with larger RAM sizes.
|
|
;
|
|
; Entry:
|
|
; a5 - points to InitMMU global stack frame
|
|
; a6 - points to BootGlobs
|
|
;
|
|
; Exit:
|
|
; InitMMU stack frame updated with massaged list of RAM chunks.
|
|
; a0 - points to 32 bit mode layout info
|
|
; a1 - points to 24 bit mode layout info
|
|
;---
|
|
WITH DecoderInfo
|
|
|
|
FindRegs REG d2-d6/a2 ; <3.0>
|
|
FindInfo movem.l FindRegs,-(sp) ; save work registers
|
|
movem.l globChunks(a5),d2-d5; d2-d3, d4-d5 = first two RAM chunks addr/size
|
|
move.l basesPtr(a5),a1 ; get ptr to table of base addresses
|
|
move.l basesValid(a5),d6 ; get mask of valid base addresses
|
|
moveq #0,d0 ; clear a reg
|
|
move.b decoder(a5),d0 ; get controller type
|
|
move.w @casetbl(d0.w*2),d0 ; get offset to controller routine
|
|
jmp @casetbl(d0.w) ; SWITCH(controller type)
|
|
@casetbl dc.w @bad-@casetbl ; .(unknown)
|
|
dc.w @bad-@casetbl ; .(Mac Pal)
|
|
dc.w @bad-@casetbl ; .(BBU)
|
|
dc.w @bad-@casetbl ; .(Normandy)
|
|
dc.w @bad-@casetbl ; .(Mac2Glue)
|
|
dc.w @bad-@casetbl ; .(MDU)
|
|
dc.w @bad-@casetbl ; .(OSS FMC)
|
|
dc.w @bad-@casetbl ; .(VISA has MMU similar to HMMU) <12><T22>
|
|
dc.w @bad-@casetbl ; .(Orwell) <7><T22>
|
|
dc.w @bad-@casetbl ; .(Jaws) <9>
|
|
dc.w @bad-@casetbl ; .(MSC) <T19>
|
|
dc.w @bad-@casetbl ; .(Sonora) <H4>
|
|
dc.w @bad-@casetbl ; .(Niagra) <H8>
|
|
dc.w @bad-@casetbl ; .(YMCA) <SM7> fau <LW2>
|
|
dc.w @bad-@casetbl ; .(djMEMC) <H20><SM13>
|
|
dc.w @exp-@casetbl ; .(HMC) <SM8>
|
|
dc.w @bad-@casetbl ; .(Pratt) <SM14>
|
|
dc.w @exp-@casetbl ; .(HHead)
|
|
dc.w @exp-@casetbl ;
|
|
dc.w @exp-@casetbl ;
|
|
dc.w @exp-@casetbl ;
|
|
dc.w @bad-@casetbl ;
|
|
dc.w @exp-@casetbl ;
|
|
dc.w @exp-@casetbl ;
|
|
dc.w @exp-@casetbl ;
|
|
dc.w @exp-@casetbl ;
|
|
dc.w @exp-@casetbl ;
|
|
dc.w @bad-@casetbl ;
|
|
|
|
Align 4
|
|
@bad ; CASE non-MMU based controller:
|
|
bra MMUError ; we're hosed...
|
|
@exp ; CASE some new controller:
|
|
movem.l (sp)+,FindRegs ; restore work registers
|
|
rts
|
|
|
|
|
|
ENDWITH ; {MMUConfigInfo}
|
|
ENDWITH ; {BootGlobs}
|
|
|
|
|
|
ENDPROC
|
|
END
|
|
|
|
|