2018-07-15 10:22:44 +00:00
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|
VecTbl RECORD 0, INCR ; SPRG3 vector table (looked up by ROM vectors)
|
2018-07-15 10:42:04 +00:00
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ds.l 1 ; 00 ; scratch for IVT
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SystemReset ds.l 1 ; 04 ; from IVT+100
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MachineCheck ds.l 1 ; 08 ; from IVT+200
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DSI ds.l 1 ; 0c ; from IVT+300
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ISI ds.l 1 ; 10 ; from IVT+400
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External ds.l 1 ; 14 ; from IVT+500
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Alignment ds.l 1 ; 18 ; from IVT+600
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Program ds.l 1 ; 1c ; from IVT+700
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FPUnavail ds.l 1 ; 20 ; from IVT+800
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Decrementer ds.l 1 ; 24 ; from IVT+900
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ReservedVector1 ds.l 1 ; 28 ; from IVT+a00
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ReservedVector2 ds.l 1 ; 2c ; from IVT+b00
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Syscall ds.l 1 ; 30 ; from IVT+c00
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Trace ds.l 1 ; 34 ; from IVT+d00
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FPAssist ds.l 1 ; 38 ; from IVT+e00
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PerfMonitor ds.l 1 ; 3c ; from IVT+f00
|
2018-07-15 10:35:32 +00:00
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ds.l 1 ; 40
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ds.l 1 ; 44
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ds.l 1 ; 48
|
2018-07-15 10:10:37 +00:00
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ds.l 1 ; 4c ; Vectors from here downwards are called from
|
2018-07-15 10:42:04 +00:00
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ds.l 1 ; 50 ; odd places in the IVT
|
2018-07-15 10:35:32 +00:00
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ds.l 1 ; 54
|
2018-07-15 10:10:37 +00:00
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ds.l 1 ; 58 ; seems AltiVec-related
|
2018-07-15 10:42:04 +00:00
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ThermalEvent ds.l 1 ; 5c
|
2018-07-15 10:35:32 +00:00
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ds.l 1 ; 60
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ds.l 1 ; 64
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ds.l 1 ; 68
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ds.l 1 ; 6c
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ds.l 1 ; 70
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ds.l 1 ; 74
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ds.l 1 ; 78
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ds.l 1 ; 7c
|
2018-07-15 10:42:04 +00:00
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|
OtherTrace ds.l 1 ; 80
|
2018-07-15 10:35:32 +00:00
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|
ds.l 1 ; 84
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|
ds.l 1 ; 88
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ds.l 1 ; 8c
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ds.l 1 ; 90
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|
ds.l 1 ; 94
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|
ds.l 1 ; 98
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ds.l 1 ; 9c
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ds.l 1 ; a0
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ds.l 1 ; a4
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ds.l 1 ; a8
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ds.l 1 ; ac
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ds.l 1 ; b0
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ds.l 1 ; b4
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ds.l 1 ; b8
|
2018-07-15 10:42:04 +00:00
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ds.l 1 ; bc ; from IVT+0
|
2018-07-15 10:10:37 +00:00
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Size equ *
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ENDR
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########################################################################
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2018-07-15 10:22:44 +00:00
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KCallTbl RECORD 0, INCR ; NanoKernel call table
|
2018-07-15 10:10:37 +00:00
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ReturnFromException ds.l 1 ; 00, trap 0
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RunAlternateContext ds.l 1 ; 04, trap 1
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ResetSystem ds.l 1 ; 08, trap 2 ; 68k RESET
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VMDispatch ds.l 1 ; 0c, trap 3 ; 68k $FE0A
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PrioritizeInterrupts ds.l 1 ; 10, trap 4
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PowerDispatch ds.l 1 ; 14, trap 5 ; 68k $FEOF
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RTASDispatch ds.l 1 ; 18, trap 6
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CacheDispatch ds.l 1 ; 1c, trap 7
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MPDispatch ds.l 1 ; 20, trap 8
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ds.l 1 ; 24, trap 9
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ds.l 1 ; 28, trap 10
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ds.l 1 ; 2c, trap 11
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CallAdapterProcPPC ds.l 1 ; 30, trap 12
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ds.l 1 ; 34, trap 13
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CallAdapterProc68k ds.l 1 ; 38, trap 14
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SystemCrash ds.l 1 ; 3c, trap 15
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Size equ *
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|
ENDR
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########################################################################
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PME RECORD 0, INCR ; PageMap Entry
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LBase ds.w 1 ; 0 ; (base - segment) >> 12
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PageCount ds.w 1 ; 2 ; page count MINUS ONE
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PBaseAndFlags ds.l 1 ; 4 ; PBase page aligned
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PBaseBits equ 20
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FirstFlagBit equ 20
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FirstFlag equ 0x800
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DaddyFlag equ 0x800
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CountingFlag equ 0x400
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PhysicalIsRelativeFlag equ 0x200
|
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; try not to use the equates above; they are dicey
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TopFieldMask equ 0xe00
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Size equ *
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|
ENDR
|
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########################################################################
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|
2018-07-15 10:22:44 +00:00
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|
BAT RECORD 0, INCR
|
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U ds.l 1
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L ds.l 1
|
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|
ENDR
|
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########################################################################
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|
2018-07-24 11:43:17 +00:00
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|
MemMap RECORD 0, INCR
|
2018-07-15 10:22:44 +00:00
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SegMapPtr ds.l 1
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BatMap ds.l 1 ; packed array of 4-bit indices into BATs
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|
ENDR
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########################################################################
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|
2018-07-15 11:59:56 +00:00
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KDP RECORD 0, INCR ; Kernel Data Page
|
2018-07-15 10:10:37 +00:00
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r0 ds.l 1 ; 000 ; used for quick register saves at interrupt time
|
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r1 ds.l 1 ; 004
|
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r2 ds.l 1 ; 008
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r3 ds.l 1 ; 00c
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|
r4 ds.l 1 ; 010
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|
r5 ds.l 1 ; 014
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|
r6 ds.l 1 ; 018
|
|
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|
r7 ds.l 1 ; 01c
|
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|
r8 ds.l 1 ; 020
|
|
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|
r9 ds.l 1 ; 024
|
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|
r10 ds.l 1 ; 028
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|
r11 ds.l 1 ; 02c
|
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|
r12 ds.l 1 ; 030
|
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|
r13 ds.l 1 ; 034
|
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|
r14 ds.l 1 ; 038
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|
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|
r15 ds.l 1 ; 03c
|
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|
r16 ds.l 1 ; 040
|
|
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|
r17 ds.l 1 ; 044
|
|
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|
r18 ds.l 1 ; 048
|
|
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|
r19 ds.l 1 ; 04c
|
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|
r20 ds.l 1 ; 050
|
|
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|
r21 ds.l 1 ; 054
|
|
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|
r22 ds.l 1 ; 058
|
|
|
|
r23 ds.l 1 ; 05c
|
|
|
|
r24 ds.l 1 ; 060
|
|
|
|
r25 ds.l 1 ; 064
|
|
|
|
r26 ds.l 1 ; 068
|
|
|
|
r27 ds.l 1 ; 06c
|
|
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|
r28 ds.l 1 ; 070
|
|
|
|
r29 ds.l 1 ; 074
|
|
|
|
r30 ds.l 1 ; 078
|
|
|
|
r31 ds.l 1 ; 07c
|
|
|
|
|
|
|
|
SegMaps
|
|
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|
SegMap32SupInit ds.l 32 ; 080:100
|
|
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|
SegMap32UsrInit ds.l 32 ; 100:180
|
|
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|
SegMap32CPUInit ds.l 32 ; 180:200
|
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|
SegMap32OvlInit ds.l 32 ; 200:280
|
|
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|
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|
BATs ds.l 32 ; 280:300
|
|
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|
CurIBAT0 ds BAT ; 300:308
|
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|
CurIBAT1 ds BAT ; 308:310
|
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|
CurIBAT2 ds BAT ; 310:318
|
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|
CurIBAT3 ds BAT ; 318:320
|
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|
CurDBAT0 ds BAT ; 320:328
|
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|
CurDBAT1 ds BAT ; 328:330
|
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|
CurDBAT2 ds BAT ; 330:338
|
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|
CurDBAT3 ds BAT ; 338:340
|
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|
NCBPointerCache
|
|
|
|
NCBCacheLA0 ds.l 1 ; 340
|
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|
NCBCachePA0 ds.l 1 ; 344
|
|
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|
NCBCacheLA1 ds.l 1 ; 348
|
|
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|
NCBCachePA1 ds.l 1 ; 34c
|
|
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|
NCBCacheLA2 ds.l 1 ; 350
|
|
|
|
NCBCachePA2 ds.l 1 ; 354
|
|
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|
NCBCacheLA3 ds.l 1 ; 358
|
|
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|
NCBCachePA3 ds.l 1 ; 35c
|
|
|
|
NCBPointerCacheEnd
|
|
|
|
|
|
|
|
VecTblSystem ds VecTbl ; 360:420 ; when 68k emulator is running, *or* any MTask
|
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|
|
VecTblAlternate ds VecTbl ; 420:4e0 ; native PowerPC in blue task
|
|
|
|
VecTblMemRetry ds VecTbl ; 4e0:5a0 ; "FDP" instruction emulation
|
|
|
|
|
2018-07-24 11:43:17 +00:00
|
|
|
FloatScratch ds.d 1 ; 5a0:5a8
|
2018-07-15 10:10:37 +00:00
|
|
|
TopOfFreePages ds.l 1 ; 5a8 ; gotten from the old SPRG0
|
|
|
|
ds.l 1 ; 5ac
|
|
|
|
PARPerSegmentPLEPtrs ds.l 4 ; 5b0:5c0 ; for each PAR segment, a ptr into the PAR PageList
|
|
|
|
FloatingPtTemp1 ds.l 1 ; 5c0
|
|
|
|
FloatingPtTemp2 ds.l 1 ; 5c4
|
|
|
|
|
2018-07-24 11:43:17 +00:00
|
|
|
SupervisorMap ds MemMap ; 5c8:5d0
|
|
|
|
UserMap ds MemMap ; 5d0:5d8
|
|
|
|
CpuMap ds MemMap ; 5d8:5e0
|
|
|
|
OverlayMap ds MemMap ; 5e0:5e8
|
|
|
|
CurMap ds MemMap ; 5e8:5f0
|
2018-07-15 10:10:37 +00:00
|
|
|
|
|
|
|
KCallTbl ds KCallTbl ; 5f0:630
|
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|
|
|
2018-07-15 11:13:45 +00:00
|
|
|
ConfigInfoPtr ds.l 1 ; 630
|
|
|
|
EDPPtr ds.l 1 ; 634
|
2018-07-15 10:10:37 +00:00
|
|
|
KernelMemoryBase ds.l 1 ; 638
|
2018-07-15 11:13:45 +00:00
|
|
|
KernelMemoryEnd ds.l 1 ; 63c
|
|
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|
LowMemPtr ds.l 1 ; 640 ; physical address of PAR Low Memory
|
|
|
|
SharedMemoryAddr ds.l 1 ; 644 ; debug?
|
|
|
|
EmuKCallTblPtrLogical ds.l 1 ; 648
|
2018-07-24 11:43:17 +00:00
|
|
|
CodeBase ds.l 1 ; 64c
|
|
|
|
MRBase ds.l 1 ; 650
|
2018-07-15 11:13:45 +00:00
|
|
|
ECBPtrLogical ds.l 1 ; 654 ; Emulator/System ContextBlock
|
|
|
|
ECBPtr ds.l 1 ; 658
|
2018-07-27 08:41:59 +00:00
|
|
|
ContextPtr ds.l 1 ; 65c ; moved to EWA (per-CPU) in NKv2
|
2018-07-15 10:10:37 +00:00
|
|
|
Flags ds.l 1 ; 660 ; moved to EWA (per-CPU) in NKv2
|
|
|
|
Enables ds.l 1 ; 664 ; moved to EWA (per-CPU) in NKv2
|
2018-07-15 11:13:45 +00:00
|
|
|
OtherContextDEC ds.l 1 ; 668 ; ticks that the *inactive* context has left out of 1s
|
|
|
|
PageMapEndPtr ds.l 1 ; 66c ; et at the same time as PageMapStartPtr below
|
|
|
|
TestIntMaskInit ds.l 1 ; 670
|
|
|
|
PostIntMaskInit ds.l 1 ; 674 ; CR flags to set when posting an interrupt to the Emulator
|
|
|
|
ClearIntMaskInit ds.l 1 ; 678 ; CR flags to clear (as mask) when clearing an interrupt
|
|
|
|
EmuIntLevelPtr ds.l 1 ; 67c ; physical ptr to an Emulator global
|
|
|
|
DebugIntPtr ds.l 1 ; 680 ; within (debug?) shared memory
|
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|
|
PageMapStartPtr ds.l 1 ; 684
|
|
|
|
PageAttributeInit ds.l 1 ; 688 ; defaults for PLE/PTE?
|
|
|
|
HtabTempPage ds.l 1 ; 68c ; a page that lives temporarily in the HTAB (per its PME)
|
|
|
|
HtabTempEntryPtr ds.l 1 ; 690 ; ptr to that PME
|
2018-07-24 04:56:38 +00:00
|
|
|
HtabLastEA ds.l 1 ; 694
|
2018-07-15 10:10:37 +00:00
|
|
|
ApproxCurrentPTEG ds.l 1 ; 698
|
|
|
|
OverflowingPTEG ds.l 1 ; 69c
|
|
|
|
PTEGMask ds.l 1 ; 6a0
|
|
|
|
HTABORG ds.l 1 ; 6a4
|
|
|
|
VMLogicalPages ds.l 1 ; 6a8 ; set at init and changed by VMInit
|
|
|
|
TotalPhysicalPages ds.l 1 ; 6ac ; does not take into acct maximum MacOS memory
|
|
|
|
PARPageListPtr ds.l 1 ; 6b0 ; VM puts this in system heap
|
|
|
|
VMMaxVirtualPages ds.l 1 ; 6b4 ; always 5fffe000, even with VM on
|
|
|
|
|
|
|
|
org 0x700
|
|
|
|
CrashTop
|
|
|
|
CrashR0 ds.l 1 ; 700
|
|
|
|
CrashR1 ds.l 1 ; 704
|
|
|
|
CrashR2 ds.l 1 ; 708
|
|
|
|
CrashR3 ds.l 1 ; 70c
|
|
|
|
CrashR4 ds.l 1 ; 710
|
|
|
|
CrashR5 ds.l 1 ; 714
|
|
|
|
CrashR6 ds.l 1 ; 718
|
|
|
|
CrashR7 ds.l 1 ; 71c
|
|
|
|
CrashR8 ds.l 1 ; 720
|
|
|
|
CrashR9 ds.l 1 ; 724
|
|
|
|
CrashR10 ds.l 1 ; 728
|
|
|
|
CrashR11 ds.l 1 ; 72c
|
|
|
|
CrashR12 ds.l 1 ; 730
|
|
|
|
CrashR13 ds.l 1 ; 734
|
|
|
|
CrashR14 ds.l 1 ; 738
|
|
|
|
CrashR15 ds.l 1 ; 73c
|
|
|
|
CrashR16 ds.l 1 ; 740
|
|
|
|
CrashR17 ds.l 1 ; 744
|
|
|
|
CrashR18 ds.l 1 ; 748
|
|
|
|
CrashR19 ds.l 1 ; 74c
|
|
|
|
CrashR20 ds.l 1 ; 750
|
|
|
|
CrashR21 ds.l 1 ; 754
|
|
|
|
CrashR22 ds.l 1 ; 758
|
|
|
|
CrashR23 ds.l 1 ; 75c
|
|
|
|
CrashR24 ds.l 1 ; 760
|
|
|
|
CrashR25 ds.l 1 ; 764
|
|
|
|
CrashR26 ds.l 1 ; 768
|
|
|
|
CrashR27 ds.l 1 ; 76c
|
|
|
|
CrashR28 ds.l 1 ; 770
|
|
|
|
CrashR29 ds.l 1 ; 774
|
|
|
|
CrashR30 ds.l 1 ; 778
|
|
|
|
CrashR31 ds.l 1 ; 77c
|
|
|
|
CrashCR ds.l 1 ; 780
|
|
|
|
CrashMQ ds.l 1 ; 784
|
|
|
|
CrashXER ds.l 1 ; 788
|
|
|
|
CrashLR ds.l 1 ; 78c
|
|
|
|
CrashCTR ds.l 1 ; 790
|
|
|
|
CrashPVR ds.l 1 ; 794
|
|
|
|
CrashDSISR ds.l 1 ; 798
|
|
|
|
CrashDAR ds.l 1 ; 79c
|
|
|
|
CrashRTCU ds.l 1 ; 7a0
|
|
|
|
CrashRTCL ds.l 1 ; 7a4
|
|
|
|
CrashDEC ds.l 1 ; 7a8
|
|
|
|
CrashHID0 ds.l 1 ; 7ac
|
|
|
|
CrashSDR1 ds.l 1 ; 7b0
|
|
|
|
CrashSRR0 ds.l 1 ; 7b4
|
|
|
|
CrashSRR1 ds.l 1 ; 7b8
|
|
|
|
CrashMSR ds.l 1 ; 7bc
|
|
|
|
CrashSR0 ds.l 1 ; 7c0
|
|
|
|
CrashSR1 ds.l 1 ; 7c4
|
|
|
|
CrashSR2 ds.l 1 ; 7c8
|
|
|
|
CrashSR3 ds.l 1 ; 7cc
|
|
|
|
CrashSR4 ds.l 1 ; 7d0
|
|
|
|
CrashSR5 ds.l 1 ; 7d4
|
|
|
|
CrashSR6 ds.l 1 ; 7d8
|
|
|
|
CrashSR7 ds.l 1 ; 7dc
|
|
|
|
CrashSR8 ds.l 1 ; 7e0
|
|
|
|
CrashSR9 ds.l 1 ; 7e4
|
|
|
|
CrashSR10 ds.l 1 ; 7e8
|
|
|
|
CrashSR11 ds.l 1 ; 7ec
|
|
|
|
CrashSR12 ds.l 1 ; 7f0
|
|
|
|
CrashSR13 ds.l 1 ; 7f4
|
|
|
|
CrashSR14 ds.l 1 ; 7f8
|
|
|
|
CrashSR15 ds.l 1 ; 7fc
|
|
|
|
CrashF0 ds.d 1 ; 800
|
|
|
|
CrashF1 ds.d 1 ; 808
|
|
|
|
CrashF2 ds.d 1 ; 810
|
|
|
|
CrashF3 ds.d 1 ; 818
|
|
|
|
CrashF4 ds.d 1 ; 820
|
|
|
|
CrashF5 ds.d 1 ; 828
|
|
|
|
CrashF6 ds.d 1 ; 830
|
|
|
|
CrashF7 ds.d 1 ; 838
|
|
|
|
CrashF8 ds.d 1 ; 840
|
|
|
|
CrashF9 ds.d 1 ; 848
|
|
|
|
CrashF10 ds.d 1 ; 850
|
|
|
|
CrashF11 ds.d 1 ; 858
|
|
|
|
CrashF12 ds.d 1 ; 860
|
|
|
|
CrashF13 ds.d 1 ; 868
|
|
|
|
CrashF14 ds.d 1 ; 870
|
|
|
|
CrashF15 ds.d 1 ; 878
|
|
|
|
CrashF16 ds.d 1 ; 880
|
|
|
|
CrashF17 ds.d 1 ; 888
|
|
|
|
CrashF18 ds.d 1 ; 890
|
|
|
|
CrashF19 ds.d 1 ; 898
|
|
|
|
CrashF20 ds.d 1 ; 8a0
|
|
|
|
CrashF21 ds.d 1 ; 8a8
|
|
|
|
CrashF22 ds.d 1 ; 8b0
|
|
|
|
CrashF23 ds.d 1 ; 8b8
|
|
|
|
CrashF24 ds.d 1 ; 8c0
|
|
|
|
CrashF25 ds.d 1 ; 8c8
|
|
|
|
CrashF26 ds.d 1 ; 8d0
|
|
|
|
CrashF27 ds.d 1 ; 8d8
|
|
|
|
CrashF28 ds.d 1 ; 8e0
|
|
|
|
CrashF29 ds.d 1 ; 8e8
|
|
|
|
CrashF30 ds.d 1 ; 8f0
|
|
|
|
CrashF31 ds.d 1 ; 8f8
|
|
|
|
CrashFPSCR ds.l 1 ; 900
|
|
|
|
CrashKernReturn ds.l 1 ; 904
|
2018-07-15 11:29:31 +00:00
|
|
|
CrashUnknown1 ds.l 1 ; 908
|
|
|
|
CrashUnknown2 ds.l 1 ; 90c
|
2018-07-15 10:10:37 +00:00
|
|
|
CrashBtm
|
|
|
|
|
2018-07-15 11:29:31 +00:00
|
|
|
PageMap ds.b 0x1a8 ; 910:ab8
|
|
|
|
|
2018-07-15 10:10:37 +00:00
|
|
|
org 0xCC0
|
|
|
|
SysInfo ds NKSystemInfo ; cc0:d80
|
|
|
|
DiagInfo ds NKDiagInfo ; d80:e80
|
|
|
|
NKInfo ds NKNanoKernelInfo ; e80:f80
|
|
|
|
ProcInfo ds NKProcessorInfo ; f80:fc0
|
|
|
|
|
|
|
|
InfoRecBlk ds.b 64 ; fc0:1000 ; Access using ptr equates in InfoRecords
|
|
|
|
ENDR
|
2018-07-15 10:22:44 +00:00
|
|
|
|
|
|
|
########################################################################
|
|
|
|
|
2018-07-27 08:41:59 +00:00
|
|
|
KernelState RECORD 0,INCR
|
|
|
|
Flags ds.l 1 ; 00
|
|
|
|
Enables ds.l 1 ; 04
|
|
|
|
|
|
|
|
Handler ds.d 1 ; 08
|
|
|
|
HandlerArg ds.d 1 ; 10
|
|
|
|
HandlerReturn ds.d 1 ; 18
|
|
|
|
|
|
|
|
MemRet17 ds.d 1 ; 20 ; MemRetry state
|
|
|
|
MemRetData ds.d 1 ; 28
|
|
|
|
MemRet19 ds.d 1 ; 30
|
|
|
|
MemRet18 ds.d 1 ; 38
|
|
|
|
ENDR
|
|
|
|
|
|
|
|
########################################################################
|
|
|
|
|
2018-07-15 10:22:44 +00:00
|
|
|
CB RECORD 0,INCR ; ContextBlock (Emulator/System or Native/Alternate)
|
2018-07-27 08:41:59 +00:00
|
|
|
|
|
|
|
InterState ds KernelState ; 000:040 ; for switching between contexts
|
|
|
|
IntraState ds KernelState ; 040:080 ; for raising/disposing exceptions within a context
|
|
|
|
|
|
|
|
FaultSrcPC ds.d 1 ; 080 ; saved when starting an exception handler
|
|
|
|
FaultSrcLR ds.d 1 ; 088
|
|
|
|
FaultSrcR3 ds.d 1 ; 090
|
|
|
|
FaultSrcR4 ds.d 1 ; 098
|
|
|
|
|
|
|
|
MSR ds.d 1 ; 0a0
|
|
|
|
ds.d 1 ; 0a8
|
|
|
|
ds.d 1 ; 0b0
|
|
|
|
ds.d 1 ; 0b8
|
|
|
|
MQ ds.d 1 ; 0c0 ; 601 only
|
|
|
|
ds.d 1 ; 0c8
|
|
|
|
XER ds.d 1 ; 0d0
|
|
|
|
CR ds.d 1 ; 0d8
|
|
|
|
FPSCR ds.d 1 ; 0e0 ; unsure, mffs/mtfs?
|
|
|
|
LR ds.d 1 ; 0e8
|
|
|
|
CTR ds.d 1 ; 0f0
|
|
|
|
PC ds.d 1 ; 0f8
|
|
|
|
|
|
|
|
r0 ds.d 1 ; 100 ; big-endian, so 32-bit value stored in second word
|
|
|
|
r1 ds.d 1 ; 108
|
|
|
|
r2 ds.d 1 ; 110
|
|
|
|
r3 ds.d 1 ; 118
|
|
|
|
r4 ds.d 1 ; 120
|
|
|
|
r5 ds.d 1 ; 128
|
|
|
|
r6 ds.d 1 ; 130
|
|
|
|
r7 ds.d 1 ; 138
|
|
|
|
r8 ds.d 1 ; 140
|
|
|
|
r9 ds.d 1 ; 148
|
|
|
|
r10 ds.d 1 ; 150
|
|
|
|
r11 ds.d 1 ; 158
|
|
|
|
r12 ds.d 1 ; 160
|
|
|
|
r13 ds.d 1 ; 168
|
|
|
|
r14 ds.d 1 ; 170
|
|
|
|
r15 ds.d 1 ; 178
|
|
|
|
r16 ds.d 1 ; 180
|
|
|
|
r17 ds.d 1 ; 188
|
|
|
|
r18 ds.d 1 ; 190
|
|
|
|
r19 ds.d 1 ; 198
|
|
|
|
r20 ds.d 1 ; 1a0
|
|
|
|
r21 ds.d 1 ; 1a8
|
|
|
|
r22 ds.d 1 ; 1b0
|
|
|
|
r23 ds.d 1 ; 1b8
|
|
|
|
r24 ds.d 1 ; 1c0
|
|
|
|
r25 ds.d 1 ; 1c8
|
|
|
|
r26 ds.d 1 ; 1d0
|
|
|
|
r27 ds.d 1 ; 1d8
|
|
|
|
r28 ds.d 1 ; 1e0
|
|
|
|
r29 ds.d 1 ; 1e8
|
|
|
|
r30 ds.d 1 ; 1f0
|
|
|
|
r31 ds.d 1 ; 1f8
|
|
|
|
|
|
|
|
f0 ds.d 1 ; 200
|
|
|
|
f1 ds.d 1 ; 208
|
|
|
|
f2 ds.d 1 ; 210
|
|
|
|
f3 ds.d 1 ; 218
|
|
|
|
f4 ds.d 1 ; 220
|
|
|
|
f5 ds.d 1 ; 228
|
|
|
|
f6 ds.d 1 ; 230
|
|
|
|
f7 ds.d 1 ; 238
|
|
|
|
f8 ds.d 1 ; 240
|
|
|
|
f9 ds.d 1 ; 248
|
|
|
|
f10 ds.d 1 ; 250
|
|
|
|
f11 ds.d 1 ; 258
|
|
|
|
f12 ds.d 1 ; 260
|
|
|
|
f13 ds.d 1 ; 268
|
|
|
|
f14 ds.d 1 ; 270
|
|
|
|
f15 ds.d 1 ; 278
|
|
|
|
f16 ds.d 1 ; 280
|
|
|
|
f17 ds.d 1 ; 288
|
|
|
|
f18 ds.d 1 ; 290
|
|
|
|
f19 ds.d 1 ; 298
|
|
|
|
f20 ds.d 1 ; 2a0
|
|
|
|
f21 ds.d 1 ; 2a8
|
|
|
|
f22 ds.d 1 ; 2b0
|
|
|
|
f23 ds.d 1 ; 2b8
|
|
|
|
f24 ds.d 1 ; 2c0
|
|
|
|
f25 ds.d 1 ; 2c8
|
|
|
|
f26 ds.d 1 ; 2d0
|
|
|
|
f27 ds.d 1 ; 2d8
|
|
|
|
f28 ds.d 1 ; 2e0
|
|
|
|
f29 ds.d 1 ; 2e8
|
|
|
|
f30 ds.d 1 ; 2f0
|
|
|
|
f31 ds.d 1 ; 2f8
|
2018-07-15 12:05:16 +00:00
|
|
|
ENDR
|