2018-07-14 17:31:15 +00:00
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; Registers passed in by HardwareInit
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rCI set r3 ; NKConfigurationInfo
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rPI set r4 ; NKProcessorInfo
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rSI set r5 ; NKSystemInfo
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rDI set r6 ; NKDiagInfo
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; Other registers we use
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rED set r8 ; Emulator Data Page
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########################################################################
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li r0, 0 ; Zero lots of fields
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########################################################################
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ClearSPRs
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mtsr 0, r0
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mtsr 1, r0
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mtsr 2, r0
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mtsr 3, r0
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mtsr 4, r0
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mtsr 5, r0
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mtsr 6, r0
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mtsr 7, r0
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mtsr 8, r0
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mtsr 9, r0
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mtsr 10, r0
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mtsr 11, r0
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mtsr 12, r0
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mtsr 13, r0
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mtsr 14, r0
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mtsr 15, r0
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mtspr rtcl, r0
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mtspr rtcu, r0
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########################################################################
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AlignFirstBankToPAR
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lwz r12, NKConfigurationInfo.PA_RelocatedLowMemInit(rCI) ; Scoop the ram before this ptr out of banks
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; so that PAR starts at PA_RelocatedLowMemInit
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lwz r11, NKSystemInfo.Bank0Start(rSI)
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add r11, r11, r12
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stw r11, NKSystemInfo.Bank0Start(rSI)
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lwz r11, NKSystemInfo.Bank0Size(rSI)
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subf r11, r12, r11
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stw r11, NKSystemInfo.Bank0Size(rSI)
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lwz r11, NKSystemInfo.PhysicalMemorySize(rSI)
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subf r11, r12, r11
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stw r11, NKSystemInfo.PhysicalMemorySize(rSI)
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########################################################################
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InitKernelMemory
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lwz r15, NKSystemInfo.PhysicalMemorySize(rSI) ; Size the HTAB for 2 entries per page
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subi r15, r15, 1
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cntlzw r12, r15
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lis r14, 0x01ff ; r14 = size-1
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srw r14, r14, r12
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ori r14, r14, 0xffff ; Obey architecture min and max size
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clrlwi r14, r14, 9
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addis r15, r15, 0x40 ; Size the PageList
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rlwinm r15, r15, 32-10, 10, 19 ; (4b entry per page, total rounded to nearest page)
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add r15, r15, r14 ; Total = PageList + KDP/EDP (2 pages) + HTAB
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addi r15, r15, 0x2001
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addi r10, rSI, NKSystemInfo.EndOfBanks ; Choose which bank of physical RAM to use
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@nextbank ; (no need to edit the bank table)
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lwz r11, -4(r10)
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lwzu r12, -8(r10)
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add r11, r12, r11 ; r12 = bank start, r11 = bank end
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andc r13, r11, r14 ; Check if HTAB fits in this bank,
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subf r13, r15, r13 ; while remaining aligned to its own size
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cmplw r13, r12
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blt @nextbank
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cmplw r13, r11
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bgt @nextbank
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add r12, r13, r15 ; base of address range we will use
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subf r12, r14, r12 ; r12 = ptr to HTAB (inside address range)
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inslwi r12, r14, 16, 16 ; SDR1 = HTABORG || HTABMASK (16b each)
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mtspr sdr1, r12
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clrrwi r11, r12, 16 ; Init KDP, 2 pages below HTAB
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subi r1, r11, 0x2000
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lwz r11, KDP.ThudSavedSDR1(r1)
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mtsprg 0, r1
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cmpw r12, r11
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lis r11, 0x7fff
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bne @did_not_panic
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subf r11, r13, r1
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addi r11, r11, KDP.StartOfPanicArea
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@did_not_panic
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subf r12, r14, r15 ; Erase all of kernel globals, except crash data
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subi r12, r12, 1
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@eraseloop
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subic. r12, r12, 4
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subf r10, r11, r12
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cmplwi cr7, r10, KDP.EndOfPanicArea - KDP.StartOfPanicArea - 4
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ble cr7, @skipwrite
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stwx r0, r13, r12
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@skipwrite
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bne @eraseloop
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########################################################################
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CopyInfoRecords
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addi r11, r1, KDP.ProcInfo
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li r10, 64
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@loop_procinfo
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subic. r10, r10, 4
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lwzx r12, rPI, r10
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stwx r12, r11, r10
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bgt @loop_procinfo
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addi r11, r1, KDP.SysInfo
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li r10, 160
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@loop_sysinfo
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subic. r10, r10, 4
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lwzx r12, rSI, r10
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stwx r12, r11, r10
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bgt @loop_sysinfo
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addi r11, r1, KDP.DiagInfo
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li r10, 256
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@loop_diaginfo
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subic. r10, r10, 4
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lwzx r12, rDI, r10
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stwx r12, r11, r10
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bgt @loop_diaginfo
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########################################################################
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InitKernelGlobals
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stw rCI, KDP.PA_ConfigInfo(r1)
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addi r12, r14, 1
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stw r12, KDP.SysInfo.HashTableSize(r11)
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addi rED, r1, 0x1000
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stw rED, KDP.PA_EmulatorData(r1)
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stw r13, KDP.KernelMemoryBase(r1)
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add r12, r13, r15
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stw r12, KDP.KernelMemoryEnd(r1)
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lwz r12, NKConfigurationInfo.PA_RelocatedLowMemInit(rCI)
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stw r12, KDP.PA_RelocatedLowMemInit(r1)
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lwz r12, NKConfigurationInfo.SharedMemoryAddr(rCI)
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stw r12, KDP.SharedMemoryAddr(r1)
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lwz r12, NKConfigurationInfo.LA_EmulatorCode(rCI)
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lwz r11, NKConfigurationInfo.KernelTrapTableOffset(rCI)
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add r12, r12, r11
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stw r12, KDP.LA_EmulatorKernelTrapTable(r1)
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bl * + 4
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mflr r12
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addi r12, r12, 4 - *
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stw r12, KDP.PA_NanoKernelCode(r1)
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_kaddr r12, r12, FDP
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stw r12, KDP.PA_FDP(r1)
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lwz r12, NKConfigurationInfo.LA_EmulatorData(rCI)
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lwz r11, NKConfigurationInfo.ECBOffset(rCI)
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add r12, r12, r11
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stw r12, KDP.LA_ECB(r1)
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add r12, rED, r11
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stw r12, KDP.PA_ECB(r1)
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stw r12, KDP.PA_ContextBlock(r1)
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lwz r12, NKConfigurationInfo.TestIntMaskInit(rCI)
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stw r12, KDP.TestIntMaskInit(r1)
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lwz r12, NKConfigurationInfo.ClearIntMaskInit(rCI)
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stw r12, KDP.ClearIntMaskInit(r1)
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lwz r12, NKConfigurationInfo.PostIntMaskInit(rCI)
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stw r12, KDP.PostIntMaskInit(r1)
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lwz r12, NKConfigurationInfo.IplValueOffset(rCI)
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add r12, rED, r12
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stw r12, KDP.PA_EmulatorIplValue(r1)
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lwz r12, NKConfigurationInfo.SharedMemoryAddr(rCI)
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addi r12, r12, 0x7c
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2018-07-15 09:20:35 +00:00
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stw r12, KDP.DebugIntPtr(r1)
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2018-07-14 17:31:15 +00:00
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lwz r12, NKConfigurationInfo.PageAttributeInit(rCI)
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stw r12, KDP.PageAttributeInit(r1)
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addi r13, r1, KDP.PageMap
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lwz r12, NKConfigurationInfo.PageMapInitSize(rCI)
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stw r13, KDP.PA_PageMapStart(r1)
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add r13, r13, r12
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stw r13, KDP.PA_PageMapEnd(r1)
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########################################################################
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InitInfoRecords
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lwz r11, NKConfigurationInfo.LA_KernelData(rCI)
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addi r12, r11, 0xFC0
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stw r12, 0xFC0(r1)
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stw r0, 0xFC4(r1)
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addi r12, r11, 0xFC8
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stw r12, 0xFC8(r1)
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stw r0, 0xFCC(r1)
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addi r12, r11, 0xFD0
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stw r12, 0xFD0(r1)
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stw r0, 0xFD4(r1)
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addi r12, r11, NKProcessorInfoPtr & 0xFFF
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stw r12, NKProcessorInfoPtr & 0xFFF(r1)
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li r12, 0x100
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sth r12, NKProcessorInfoVer & 0xFFF(r1)
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li r12, 64
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sth r12, NKProcessorInfoLen & 0xFFF(r1)
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addi r12, r11, NKNanoKernelInfoPtr & 0xFFF
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stw r12, NKNanoKernelInfoPtr & 0xFFF(r1)
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li r12, kNanoKernelVersion
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sth r12, NKNanoKernelInfoVer & 0xFFF(r1)
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li r12, 256
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sth r12, NKNanoKernelInfoLen & 0xFFF(r1)
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addi r12, r11, NKDiagInfoPtr & 0xFFF
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stw r12, NKDiagInfoPtr & 0xFFF(r1)
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li r12, 0x100
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sth r12, NKDiagInfoVer & 0xFFF(r1)
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li r12, 256
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sth r12, NKDiagInfoLen & 0xFFF(r1)
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addi r12, r11, NKSystemInfoPtr & 0xFFF
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stw r12, NKSystemInfoPtr & 0xFFF(r1)
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li r12, 0x102
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sth r12, NKSystemInfoVer & 0xFFF(r1)
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li r12, 160
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sth r12, NKSystemInfoLen & 0xFFF(r1)
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addi r12, r11, NKProcessorInfoPtr & 0xFFF
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stw r12, 0xFF8(r1)
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li r12, 0x100
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sth r12, 0xFFC(r1)
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li r12, 64
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sth r12, 0xFFE(r1)
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########################################################################
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2018-07-15 09:20:35 +00:00
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InitProcessorInfo
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2018-07-14 17:31:15 +00:00
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mfpvr r12
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stw r12, KDP.ProcInfo.ProcessorVersionReg(r1)
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srwi r12, r12, 16
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lwz r11, KDP.PA_NanoKernelCode(r1)
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addi r10, r1, KDP.ProcInfo.Ovr
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li r9, NKProcessorInfo.OvrEnd - NKProcessorInfo.Ovr
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_kaddr r11, r11, ProcessorInfoTable
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cmpwi r12, 1 ; 601
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addi r11, r11, NKProcessorInfo.OvrEnd - NKProcessorInfo.Ovr
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beq CopyProcessorInfo
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cmpwi r12, 3 ; 603
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addi r11, r11, NKProcessorInfo.OvrEnd - NKProcessorInfo.Ovr
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beq CopyProcessorInfo
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cmpwi r12, 4 ; 604
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addi r11, r11, NKProcessorInfo.OvrEnd - NKProcessorInfo.Ovr
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beq CopyProcessorInfo
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subi r11, r11, NKProcessorInfo.OvrEnd - NKProcessorInfo.Ovr
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b CopyProcessorInfo
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ProcessorInfoTable
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; 601
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dc.l 0x1000 ; PageSize
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dc.l 0x8000 ; DataCacheTotalSize
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dc.l 0x8000 ; InstCacheTotalSize
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dc.w 0x20 ; CoherencyBlockSize
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dc.w 0x20 ; ReservationGranuleSize
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dc.w 1 ; CombinedCaches
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dc.w 0x40 ; InstCacheLineSize
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dc.w 0x40 ; DataCacheLineSize
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dc.w 0x20 ; DataCacheBlockSizeTouch
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dc.w 0x20 ; InstCacheBlockSize
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dc.w 0x20 ; DataCacheBlockSize
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dc.w 8 ; InstCacheAssociativity
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dc.w 8 ; DataCacheAssociativity
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dc.w 0x100 ; TransCacheTotalSize
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dc.w 2 ; TransCacheAssociativity
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; 603
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dc.l 0x1000 ; PageSize
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dc.l 0x2000 ; DataCacheTotalSize
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dc.l 0x2000 ; InstCacheTotalSize
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dc.w 0x20 ; CoherencyBlockSize
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dc.w 0x20 ; ReservationGranuleSize
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dc.w 0 ; CombinedCaches
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dc.w 0x20 ; InstCacheLineSize
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dc.w 0x20 ; DataCacheLineSize
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dc.w 0x20 ; DataCacheBlockSizeTouch
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dc.w 0x20 ; InstCacheBlockSize
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dc.w 0x20 ; DataCacheBlockSize
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dc.w 2 ; InstCacheAssociativity
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dc.w 2 ; DataCacheAssociativity
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dc.w 0x40 ; TransCacheTotalSize
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dc.w 2 ; TransCacheAssociativity
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; 604
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dc.l 0x1000 ; PageSize
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dc.l 0x4000 ; DataCacheTotalSize
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dc.l 0x4000 ; InstCacheTotalSize
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dc.w 0x20 ; CoherencyBlockSize
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dc.w 0x20 ; ReservationGranuleSize
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dc.w 0 ; CombinedCaches
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dc.w 0x20 ; InstCacheLineSize
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dc.w 0x20 ; DataCacheLineSize
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dc.w 0x20 ; DataCacheBlockSizeTouch
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dc.w 0x20 ; InstCacheBlockSize
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dc.w 0x20 ; DataCacheBlockSize
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dc.w 4 ; InstCacheAssociativity
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dc.w 4 ; DataCacheAssociativity
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dc.w 0x40 ; TransCacheTotalSize
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dc.w 2 ; TransCacheAssociativity
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CopyProcessorInfo
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@loop
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subic. r9, r9, 4
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lwzx r12, r11, r9
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stwx r12, r10, r9
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bgt @loop
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2017-11-19 04:11:07 +00:00
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2018-07-14 17:31:15 +00:00
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########################################################################
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2017-11-19 04:11:07 +00:00
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2018-07-14 17:31:15 +00:00
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InitEmulator
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lwz r11, NKConfigurationInfo.BootVersionOffset(rCI) ; Copy 16b boot ver string
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lwz r12, NKConfigurationInfo.BootstrapVersion(rCI) ; ("Boot PDM 601 1.0")
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stwux r12, r11, rED ; into emulator data area
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lwz r12, NKConfigurationInfo.BootstrapVersion + 4(rCI)
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stw r12, 4(r11)
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lwz r12, NKConfigurationInfo.BootstrapVersion + 8(rCI)
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stw r12, 8(r11)
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lwz r12, NKConfigurationInfo.BootstrapVersion + 12(rCI)
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stw r12, 12(r11)
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2017-11-19 04:11:07 +00:00
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2018-07-14 17:31:15 +00:00
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lwz r12, NKConfigurationInfo.LA_EmulatorCode(rCI) ; Prepare the System ContextBlock
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lwz r11, NKConfigurationInfo.EmulatorEntryOffset(rCI)
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add r12, r11, r12
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lwz r11, NKConfigurationInfo.ECBOffset(rCI) ; address of declared Emu entry point
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add r11, r11, rED
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stw r12, CB.ExceptionOriginAddr(r11)
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2017-11-19 04:11:07 +00:00
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2018-07-14 17:31:15 +00:00
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lwz r12, NKConfigurationInfo.LA_EmulatorData(rCI) ; address of Emu global page
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stw r12, CB.ExceptionOriginR3(r11)
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2017-11-19 04:11:07 +00:00
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2018-07-14 17:31:15 +00:00
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lwz r12, NKConfigurationInfo.LA_DispatchTable(rCI) ; address of 512kb Emu dispatch table
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stw r12, CB.ExceptionOriginR4(r11)
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2017-11-19 04:11:07 +00:00
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2018-07-14 17:31:15 +00:00
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lwz r12, KDP.LA_EmulatorKernelTrapTable(r1) ; address of KCallReturnFromException trap
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stw r12, CB.ExceptionHandlerRetAddr(r11)
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2017-11-19 04:11:07 +00:00
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2018-07-14 17:31:15 +00:00
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lwz r10, KDP.PA_RelocatedLowMemInit(r1) ; Zero out bottom 8k of Low Memory
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li r9, 0x2000
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@zeroloop
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subic. r9, r9, 4
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stwx r0, r10, r9
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bne @zeroloop
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2017-11-19 04:11:07 +00:00
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2018-07-14 17:31:15 +00:00
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lwz r11, NKConfigurationInfo.MacLowMemInitOffset(rCI) ; Read address/value pairs from ConfigInfo
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lwz r10, KDP.PA_RelocatedLowMemInit(r1) ; and apply them to Low Memory
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lwzux r9, r11, rCI
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@setloop
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mr. r9, r9
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beq @donelm
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lwzu r12, 4(r11)
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stwx r12, r10, r9
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lwzu r9, 4(r11)
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b @setloop
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@donelm
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2017-11-19 04:11:07 +00:00
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2018-07-14 17:31:15 +00:00
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mfpvr r7 ; Calculate Flags:
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srwi r7, r7, 16
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cmpwi r7, 1
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lis r7, FlagEmu >> 16 ; we will enter System Context (all CPUs)
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bne @not_601
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ori r7, r7, FlagHasMQ ; but only 601 has MQ register
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@not_601
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stw r7, KDP.Flags(r1)
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2017-11-19 04:11:07 +00:00
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2018-07-14 17:31:15 +00:00
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lwz r10, KDP.LA_EmulatorKernelTrapTable(r1) ; Start at KCallReturnFromException trap
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2017-11-19 04:11:07 +00:00
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2018-07-14 17:31:15 +00:00
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mfmsr r14 ; Calculate the user space MSR
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andi. r14, r14, MsrIP ; (not sure why the dot)
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ori r15, r14, MsrME | MsrDR | MsrRI ; does r15 even get used?
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ori r11, r14, MsrEE | MsrPR | MsrME | MsrIR | MsrDR | MsrRI ; <- this is the real one
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2017-11-19 04:11:07 +00:00
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2018-07-14 17:31:15 +00:00
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li r13, 0 ; Zero important registers (r13=CR, r12=LR)
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2017-11-19 04:11:07 +00:00
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li r12, 0
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li r0, 0
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li r2, 0
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li r3, 0
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li r4, 0
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2018-07-14 17:31:15 +00:00
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########################################################################
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2017-11-19 04:11:07 +00:00
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2018-07-14 17:31:15 +00:00
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ResetContextClock
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lwz r8, KDP.ProcInfo.DecClockRateHz
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stw r8, KDP.OtherContextDEC(r1)
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mtdec r8
|
2017-11-19 04:11:07 +00:00
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2018-07-14 17:31:15 +00:00
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########################################################################
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2017-11-19 04:11:07 +00:00
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2018-07-14 17:31:15 +00:00
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b Reset
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