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https://github.com/elliotnunn/powermac-rom.git
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lots of architectural work
This commit is contained in:
Elliot Nunn
parent
dbf0af7ab9
commit
2194a99638
@ -32,13 +32,13 @@ MRDataStorageInt ; Consult DSISR and the page table to decide what to do
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@access_exception
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@access_exception
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andi. r28, r31, 3
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andi. r28, r31, 3
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li r8, ecDataSupAccessViolation
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li r8, ecDataSupAccessViolation
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beq ExceptionAfterRetry
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beq MRException
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cmpwi r28, 3
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cmpwi r28, 3
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li r8, ecDataWriteViolation
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li r8, ecDataWriteViolation
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beq ExceptionAfterRetry ; Nobody allowed to write => Exception
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beq MRException ; Nobody allowed to write => Exception
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li r8, ecDataSupWriteViolation
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li r8, ecDataSupWriteViolation
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b ExceptionAfterRetry ; Supervisor allowed to write => Exception
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b MRException ; Supervisor allowed to write => Exception
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@possible_htab_miss
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@possible_htab_miss
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andis. r28, r31, 0x8010 ; Check for DataAccess Interrupt or ec[io]wx
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andis. r28, r31, 0x8010 ; Check for DataAccess Interrupt or ec[io]wx
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@ -49,9 +49,9 @@ MRDataStorageInt ; Consult DSISR and the page table to decide what to do
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mtlr r28
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mtlr r28
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beq @return ; HTAB success => RFI
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beq @return ; HTAB success => RFI
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li r8, ecDataPageFault
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li r8, ecDataPageFault
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blt ExceptionAfterRetry ; Fault => Exception
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blt MRException ; Fault => Exception
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li r8, ecDataInvalidAddress
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li r8, ecDataInvalidAddress
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b ExceptionAfterRetry ; Bad address => Exception
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b MRException ; Bad address => Exception
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MRMachineCheckInt ; Always gives HW fault
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MRMachineCheckInt ; Always gives HW fault
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mfsprg r1, 1
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mfsprg r1, 1
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@ -77,7 +77,7 @@ MRMachineCheckInt ; Always gives HW fault
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MRHardwareFault ; Can come from a DSI or a Machine Check
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MRHardwareFault ; Can come from a DSI or a Machine Check
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cmplw r10, r19
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cmplw r10, r19
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li r8, ecDataHardwareFault
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li r8, ecDataHardwareFault
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bne ExceptionAfterRetry
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bne MRException
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mtsprg 3, r24
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mtsprg 3, r24
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lmw r14, KDP.r14(r1)
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lmw r14, KDP.r14(r1)
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@ -1,12 +1,12 @@
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; Each routine accepts:
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; Each routine accepts:
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; r17 = pretend inst with (byteCount-1) in bits 28-30 (will be decremented)
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; r17 = pretend inst with accessLen (range 1-8) in bits 27-30 (will be decremented)
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; r19 = address of byte to the right of the string to be loaded/saved
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; r19 = address of byte to the right of the string to be loaded/saved
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; r23 as a scratch register
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; r23 as a scratch register
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; r20/r21 = right-justified data (stores only)
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; r20/r21 = right-justified data (stores only)
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; Before jumping to MRDoSecondary or one of the MRFast paths, each routine sets:
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; Before jumping to MRDoSecondary or one of the MRFast paths, each routine sets:
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; r20/r21 = right-justified data (loads only)
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; r20/r21 = right-justified data (loads only)
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; r17 has byteCount field decremented
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; r17 has len field decremented
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; r23 = junk, not to be trusted
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; r23 = junk, not to be trusted
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########################################################################
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########################################################################
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@ -1,6 +1,25 @@
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MACRO
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MACRO
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optabRow &upperSix, &lowerSix, &flags, &primLabel, &secLabel
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optabRow &upperSix, &lowerSix, &flags, &primLabel, &secLabel
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DC.W ((&lowerSix) << 10) | (&upperSix << 4) | &flags ; 0-5 lowerSix, 6-11 upperSix, 12-15 flags
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IF &TYPE('&upperSix') = 'UNDEFINED' ; 0-5 lowerSix
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orUpperSix set 63
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ELSE
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orUpperSix set &upperSix
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ENDIF
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IF &TYPE('&lowerSix') = 'UNDEFINED' ; 6-11 upperSix
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orLowerSix set 1
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ELSE
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orLowerSix set &lowerSix
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ENDIF
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IF &TYPE('&flags') = 'UNDEFINED' ; 12-15 flags
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orFlags set 1
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ELSE
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orFlags set &flags
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ENDIF
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DC.W (orLowerSix << 10) | (orUpperSix << 4) | orFlags
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IF &TYPE('&primLabel') = 'UNDEFINED' ; 16-23 primary routine
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IF &TYPE('&primLabel') = 'UNDEFINED' ; 16-23 primary routine
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DC.B (MRPriCrash - MRBase) >> 2
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DC.B (MRPriCrash - MRBase) >> 2
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ELSE
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ELSE
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@ -13,144 +32,145 @@
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ENDIF
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ENDIF
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ENDM
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ENDM
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; LEGEND .. top 6 bits of r17
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; LEGEND .. metatab index (r17 bits 0-5, dflt=63)
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; .. bottom 6 bits of r17
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; .... access size (r17 bits 27-30) and (L)oad/(S)tore (r17 bit 31)
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; . mrOpflag1
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; . mrOpflag2
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; . mrOpflag3
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; . mrFlagDidLoad
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;
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;
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; primary routine secondary routine
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; . mrOpflag1 }
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; (dflt=MRPriCrash) (dflt=MRSecException)
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; . mrOpflag2 } cr3 flags,
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; ................ ................
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; . mrOpflag3 } all unset by default
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; . mrFlagDidLoad }
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;
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; primary routine secondary routine X-form extended opcode D-form opcode
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; (dflt=MRPriCrash) (dflt=MRSecExc'n)
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; ................ ................ ....................... .................
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MROptabX
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MROptabX
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optabRow 20, 9, %0000, MRPriPlainLoad, MRSecLWARX ; Xopcd=00000(101)00=020=LWARX
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optabRow 20, 4,L, %0000, MRPriPlainLoad, MRSecLWARX ; 00000(101)00=020=LWARX metatabLine %0001, MRSecLWARX ; 20
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optabRow 21, 17, %0000, , ; Xopcd=00010(101)00=084
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optabRow 21, 8,L, %0000, MRPriCrash, MRSecException ; 00010(101)00=084=LDARX metatabLine %0001, MRSecException ; 21
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optabRow 63, 1, %0000, , ; Xopcd=00100(101)00=148
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optabRow , ,, , , ; 00100(101)00=148
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optabRow 63, 1, %0000, , ; Xopcd=00110(101)00=212
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optabRow , ,, , , ; 00110(101)00=212
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optabRow 63, 1, %0000, , ; Xopcd=01000(101)00=276
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optabRow , ,, , , ; 01000(101)00=276
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optabRow 63, 1, %0000, , ; Xopcd=01010(101)00=340
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optabRow , ,, , , ; 01010(101)00=340
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optabRow 63, 1, %0000, , ; Xopcd=01100(101)00=404
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optabRow , ,, , , ; 01100(101)00=404
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optabRow 63, 1, %0000, , ; Xopcd=01110(101)00=468
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optabRow , ,, , , ; 01110(101)00=468
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optabRow 63, 1, %0000, , ; Xopcd=10000(101)00=532
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optabRow , ,, , , ; 10000(101)00=532
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optabRow 63, 1, %0000, , ; Xopcd=10010(101)00=596
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optabRow , ,, , , ; 10010(101)00=596
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optabRow 63, 1, %0000, , ; Xopcd=10100(101)00=660
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optabRow , ,, , , ; 10100(101)00=660
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optabRow 63, 1, %0000, , ; Xopcd=10110(101)00=724
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optabRow , ,, , , ; 10110(101)00=724
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optabRow 3, 17, %0000, MRPriPlainLoad, MRSecLoad ; Xopcd=11000(101)00=788
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optabRow 3, 8,L, %0000, MRPriPlainLoad, MRSecLoad ; 11000(101)00=788 metatabLine %0001, MRSecLoad ; 3
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optabRow 6, 9, %0000, MRPriPlainLoad, MRSecLoad ; Xopcd=11010(101)00=852
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optabRow 6, 4,L, %0000, MRPriPlainLoad, MRSecLoad ; 11010(101)00=852 metatabLine %0001, MRSecLoad ; 6
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optabRow 19, 16, %0000, MRPriPlainStore, MRSecDone ; Xopcd=11100(101)00=916
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optabRow 19, 8,S, %0000, MRPriPlainStore, MRSecDone ; 11100(101)00=916 metatabLine %0001, MRSecDone ; 19
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optabRow 63, 1, %0000, , ; Xopcd=11110(101)00=980
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optabRow , ,, , , ; 11110(101)00=980
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optabRow 63, 1, %0000, , ; Xopcd=00001(101)00=052
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optabRow , ,, , , ; 00001(101)00=052
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optabRow 63, 1, %0000, , ; Xopcd=00011(101)00=116
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optabRow , ,, , , ; 00011(101)00=116
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optabRow 63, 1, %0000, , ; Xopcd=00101(101)00=180
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optabRow , ,, , , ; 00101(101)00=180
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optabRow 63, 1, %0000, , ; Xopcd=00111(101)00=244
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optabRow , ,, , , ; 00111(101)00=244
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optabRow 63, 1, %0000, , ; Xopcd=01001(101)00=308
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optabRow , ,, , , ; 01001(101)00=308
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optabRow 63, 1, %0000, , ; Xopcd=01011(101)00=372
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optabRow , ,, , , ; 01011(101)00=372
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optabRow 63, 1, %0000, , ; Xopcd=01101(101)00=436
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optabRow , ,, , , ; 01101(101)00=436
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optabRow 63, 1, %0000, , ; Xopcd=01111(101)00=500
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optabRow , ,, , , ; 01111(101)00=500
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optabRow 63, 1, %0000, , ; Xopcd=10001(101)00=564
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optabRow , ,, , , ; 10001(101)00=564
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optabRow 63, 1, %0000, , ; Xopcd=10011(101)00=628
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optabRow , ,, , , ; 10011(101)00=628
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optabRow 63, 1, %0000, , ; Xopcd=10101(101)00=692
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optabRow , ,, , , ; 10101(101)00=692
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optabRow 63, 1, %0000, , ; Xopcd=10111(101)00=756
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optabRow , ,, , , ; 10111(101)00=756
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optabRow 3, 17, %0000, MRPriUpdLoad, MRSecLoad ; Xopcd=11001(101)00=820
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optabRow 3, 8,L, %0000, MRPriUpdLoad, MRSecLoad ; 11001(101)00=820 metatabLine %0001, MRSecLoad ; 3
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optabRow 27, 17, %0011, , ; Xopcd=11011(101)00=884
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optabRow 27, 8,L, %0011, MRPriCrash, MRSecException ; 11011(101)00=884 metatabLine %0011, MRSecException ; 27
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optabRow 19, 16, %0000, MRPriUpdStore, MRSecDone ; Xopcd=11101(101)00=948
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optabRow 19, 8,S, %0000, MRPriUpdStore, MRSecDone ; 11101(101)00=948 metatabLine %0001, MRSecDone ; 19
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optabRow 31, 16, %0010, , ; Xopcd=11111(101)00=1012
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optabRow 31, 8,S, %0010, MRPriCrash, MRSecException ; 11111(101)00=1012 metatabLine %0011, MRSecException ; 31
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optabRow 3, 17, %0000, MRPriPlainLoad, MRSecLoad ; Xopcd=00000(101)01=021=LDX
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optabRow 3, 8,L, %0000, MRPriPlainLoad, MRSecLoad ; 00000(101)01=021=LDX metatabLine %0001, MRSecLoad ; 3
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optabRow 63, 1, %0000, , ; Xopcd=00010(101)01=085
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optabRow , ,, , , ; 00010(101)01=085
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optabRow 19, 16, %0000, MRPriPlainStore, MRSecDone ; Xopcd=00100(101)01=149=STDX
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optabRow 19, 8,S, %0000, MRPriPlainStore, MRSecDone ; 00100(101)01=149=STDX metatabLine %0001, MRSecDone ; 19
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optabRow 63, 1, %0000, , ; Xopcd=00110(101)01=213
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optabRow , ,, , , ; 00110(101)01=213
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optabRow 40, 9, %1011, MRPriUnknown, MRSecUnknown ; Xopcd=01000(101)01=277
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optabRow 40, 4,L, %1011, MRPriLSCBX, MRSecLSCBX ; 01000(101)01=277=LSCBX (POWER) metatabLine %0011, MRSecLSCBX ; 40
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optabRow 6, 9, %0000, MRPriPlainLoad, MRSecLoad ; Xopcd=01010(101)01=341
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optabRow 6, 4,L, %0000, MRPriPlainLoad, MRSecLoad ; 01010(101)01=341=LWAX metatabLine %0001, MRSecLoad ; 6
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optabRow 63, 1, %0000, , ; Xopcd=01100(101)01=405
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optabRow , ,, , , ; 01100(101)01=405
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optabRow 63, 1, %0000, , ; Xopcd=01110(101)01=469
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optabRow , ,, , , ; 01110(101)01=469
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optabRow 32, 9, %1011, MRPriLSWX, MRSecLSWix ; Xopcd=10000(101)01=533=LSWX
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optabRow 32, 4,L, %1011, MRPriLSWX, MRSecLSWix ; 10000(101)01=533=LSWX metatabLine %0011, MRSecLSWix ; 32
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optabRow 32, 9, %1111, MRPriLSWI, MRSecLSWix ; Xopcd=10010(101)01=597=LSWI
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optabRow 32, 4,L, %1111, MRPriLSWI, MRSecLSWix ; 10010(101)01=597=LSWI metatabLine %0011, MRSecLSWix ; 32
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optabRow 36, 8, %0010, MRPriSTSWX, MRSecStrStore ; Xopcd=10100(101)01=661=STSWX
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optabRow 36, 4,S, %0010, MRPriSTSWX, MRSecStrStore ; 10100(101)01=661=STSWX metatabLine %0011, MRSecStrStore ; 36
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optabRow 36, 8, %1110, MRPriSTSWI, MRSecStrStore ; Xopcd=10110(101)01=725=STSWI
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optabRow 36, 4,S, %1110, MRPriSTSWI, MRSecStrStore ; 10110(101)01=725=STSWI metatabLine %0011, MRSecStrStore ; 36
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optabRow 63, 1, %0000, , ; Xopcd=11000(101)01=789
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optabRow , ,, , , ; 11000(101)01=789
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optabRow 63, 1, %0000, , ; Xopcd=11010(101)01=853
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optabRow , ,, , , ; 11010(101)01=853
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optabRow 63, 1, %0000, , ; Xopcd=11100(101)01=917
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optabRow , ,, , , ; 11100(101)01=917
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optabRow 63, 1, %0000, , ; Xopcd=11110(101)01=981
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optabRow , ,, , , ; 11110(101)01=981
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optabRow 3, 17, %0000, MRPriUpdLoad, MRSecLoad ; Xopcd=00001(101)01=053=LDUX
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optabRow 3, 8,L, %0000, MRPriUpdLoad, MRSecLoad ; 00001(101)01=053=LDUX metatabLine %0001, MRSecLoad ; 3
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optabRow 63, 1, %0000, , ; Xopcd=00011(101)01=117
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optabRow , ,, , , ; 00011(101)01=117
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optabRow 19, 16, %0000, MRPriUpdStore, MRSecDone ; Xopcd=00101(101)01=181=STDUX
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optabRow 19, 8,S, %0000, MRPriUpdStore, MRSecDone ; 00101(101)01=181=STDUX metatabLine %0001, MRSecDone ; 19
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optabRow 63, 1, %0000, , ; Xopcd=00111(101)01=245
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optabRow , ,, , , ; 00111(101)01=245
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optabRow 63, 1, %0000, , ; Xopcd=01001(101)01=309
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optabRow , ,, , , ; 01001(101)01=309
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optabRow 6, 9, %0000, MRPriUpdLoad, MRSecDone ; Xopcd=01011(101)01=373=LWAUX
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optabRow 6, 4,L, %0000, MRPriUpdLoad, MRSecDone ; 01011(101)01=373=LWAUX metatabLine %0001, MRSecLoad ; 6
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optabRow 63, 1, %0000, , ; Xopcd=01101(101)01=437
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optabRow , ,, , , ; 01101(101)01=437
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optabRow 63, 1, %0000, , ; Xopcd=01111(101)01=501
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optabRow , ,, , , ; 01111(101)01=501
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optabRow 63, 1, %0000, , ; Xopcd=10001(101)01=565
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optabRow , ,, , , ; 10001(101)01=565
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optabRow 63, 1, %0000, , ; Xopcd=10011(101)01=629
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optabRow , ,, , , ; 10011(101)01=629
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optabRow 63, 1, %0000, , ; Xopcd=10101(101)01=693
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optabRow , ,, , , ; 10101(101)01=693
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optabRow 63, 1, %0000, , ; Xopcd=10111(101)01=757
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optabRow , ,, , , ; 10111(101)01=757
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optabRow 63, 1, %0000, , ; Xopcd=11001(101)01=821
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optabRow , ,, , , ; 11001(101)01=821
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optabRow 63, 1, %0000, , ; Xopcd=11011(101)01=885
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optabRow , ,, , , ; 11011(101)01=885
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optabRow 63, 1, %0000, , ; Xopcd=11101(101)01=949
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optabRow , ,, , , ; 11101(101)01=949
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optabRow 63, 1, %0000, , ; Xopcd=11111(101)01=1013
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optabRow , ,, , , ; 11111(101)01=1013
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optabRow 63, 1, %0000, , ; Xopcd=00000(101)10=022
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optabRow , ,, , , ; 00000(101)10=022
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optabRow 62, 3, %0010, MRPriUpdLoad, MRSecCacheWang ; Xopcd=00010(101)10=086
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optabRow 62, 1,L, %0010, MRPriUpdLoad, MRSecRedoNoTrace ; 00010(101)10=086 metatabLine %0011, MRSecRedoNoTrace ; 62
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optabRow 22, 9, %0000, MRPriPlainStore, MRSecSTWCX ; Xopcd=00100(101)10=150=STWCX.
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optabRow 22, 4,L, %0000, MRPriPlainStore, MRSecSTWCX ; 00100(101)10=150=STWCX. metatabLine %0001, MRSecSTWCX ; 22
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optabRow 23, 16, %0000, , ; Xopcd=00110(101)10=214
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optabRow 23, 8,S, %0000, MRPriCrash, MRSecException ; 00110(101)10=214=STDCX. metatabLine %0001, MRSecException ; 23
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optabRow 62, 3, %0010, MRPriUpdLoad, MRSecCacheWang ; Xopcd=01000(101)10=278=DCBT
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optabRow 62, 1,L, %0010, MRPriUpdLoad, MRSecRedoNoTrace ; 01000(101)10=278=DCBT metatabLine %0011, MRSecRedoNoTrace ; 62
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optabRow 63, 1, %0000, , ; Xopcd=01010(101)10=342
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optabRow , ,, , , ; 01010(101)10=342
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optabRow 63, 1, %0000, , ; Xopcd=01100(101)10=406
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optabRow , ,, , , ; 01100(101)10=406
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optabRow 63, 1, %0000, , ; Xopcd=01110(101)10=470
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optabRow , ,, , , ; 01110(101)10=470
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optabRow 10, 9, %0010, MRPriUpdLoad, MRSecLWBRX ; Xopcd=10000(101)10=534=LWBRX
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optabRow 10, 4,L, %0010, MRPriUpdLoad, MRSecLWBRX ; 10000(101)10=534=LWBRX metatabLine %0011, MRSecLWBRX ; 10
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optabRow 63, 1, %0000, , ; Xopcd=10010(101)10=598
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optabRow , ,, , , ; 10010(101)10=598
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optabRow 18, 8, %0000, MRPriSTWBRX, MRSecDone ; Xopcd=10100(101)10=662=STWBRX
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optabRow 18, 4,S, %0000, MRPriSTWBRX, MRSecDone ; 10100(101)10=662=STWBRX metatabLine %0001, MRSecDone ; 18
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optabRow 63, 1, %0000, , ; Xopcd=10110(101)10=726
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optabRow , ,, , , ; 10110(101)10=726
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optabRow 9, 5, %0010, MRPriUpdLoad, MRSecLHBRX ; Xopcd=11000(101)10=790=LHBRX
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optabRow 9, 2,L, %0010, MRPriUpdLoad, MRSecLHBRX ; 11000(101)10=790=LHBRX metatabLine %0011, MRSecLHBRX ; 9
|
||||||
optabRow 63, 1, %0000, , ; Xopcd=11010(101)10=854
|
optabRow , ,, , , ; 11010(101)10=854
|
||||||
optabRow 17, 4, %0000, MRPriSTHBRX, MRSecDone ; Xopcd=11100(101)10=918=STHBRX
|
optabRow 17, 2,S, %0000, MRPriSTHBRX, MRSecDone ; 11100(101)10=918=STHBRX metatabLine %0001, MRSecDone ; 17
|
||||||
optabRow 62, 3, %0010, MRPriUpdLoad, MRSecCacheWang ; Xopcd=11110(101)10=982=ICBI
|
optabRow 62, 1,L, %0010, MRPriUpdLoad, MRSecRedoNoTrace ; 11110(101)10=982=ICBI metatabLine %0011, MRSecRedoNoTrace ; 62
|
||||||
optabRow 62, 3, %0010, MRPriUpdLoad, MRSecCacheWang ; Xopcd=00001(101)10=054=DCBST
|
optabRow 62, 1,L, %0010, MRPriUpdLoad, MRSecRedoNoTrace ; 00001(101)10=054=DCBST metatabLine %0011, MRSecRedoNoTrace ; 62
|
||||||
optabRow 63, 1, %0000, , ; Xopcd=00011(101)10=118
|
optabRow , ,, , , ; 00011(101)10=118
|
||||||
optabRow 63, 1, %0000, , ; Xopcd=00101(101)10=182
|
optabRow , ,, , , ; 00101(101)10=182
|
||||||
optabRow 62, 3, %0010, MRPriUpdLoad, MRSecCacheWang ; Xopcd=00111(101)10=246=DCBTST
|
optabRow 62, 1,L, %0010, MRPriUpdLoad, MRSecRedoNoTrace ; 00111(101)10=246=DCBTST metatabLine %0011, MRSecRedoNoTrace ; 62
|
||||||
optabRow 63, 1, %0000, MRPriPlainLoad, MRSecIOInstFail ; Xopcd=01001(101)10=310=ECIWX
|
optabRow 63, 0,L, %0000, MRPriPlainLoad, MRSecException2 ; 01001(101)10=310=ECIWX metatabLine %0001, MRSecException2 ; 63
|
||||||
optabRow 63, 1, %0000, , ; Xopcd=01011(101)10=374
|
optabRow , ,, , , ; 01011(101)10=374
|
||||||
optabRow 63, 0, %0000, MRPriPlainStore, MRSecIOInstFail ; Xopcd=01101(101)10=438=ECOWX
|
optabRow 63, 0,S, %0000, MRPriPlainStore, MRSecException2 ; 01101(101)10=438=ECOWX metatabLine %0001, MRSecException2 ; 63
|
||||||
optabRow 63, 1, %0000, , ; Xopcd=01111(101)10=502
|
optabRow , ,, , , ; 01111(101)10=502
|
||||||
optabRow 63, 1, %0000, , ; Xopcd=10001(101)10=566
|
optabRow , ,, , , ; 10001(101)10=566
|
||||||
optabRow 63, 1, %0000, , ; Xopcd=10011(101)10=630
|
optabRow , ,, , , ; 10011(101)10=630
|
||||||
optabRow 63, 1, %0000, , ; Xopcd=10101(101)10=694
|
optabRow , ,, , , ; 10101(101)10=694
|
||||||
optabRow 63, 1, %0000, , ; Xopcd=10111(101)10=758
|
optabRow , ,, , , ; 10111(101)10=758
|
||||||
optabRow 63, 1, %0000, , ; Xopcd=11001(101)10=822
|
optabRow , ,, , , ; 11001(101)10=822
|
||||||
optabRow 63, 1, %0000, , ; Xopcd=11011(101)10=886
|
optabRow , ,, , , ; 11011(101)10=886
|
||||||
optabRow 63, 1, %0000, , ; Xopcd=11101(101)10=950
|
optabRow , ,, , , ; 11101(101)10=950
|
||||||
optabRow 48, 16, %0010, MRPriDCBZ, MRSecDCBZ ; Xopcd=11111(101)10=1014=DCBZ
|
optabRow 48, 8,S, %0010, MRPriDCBZ, MRSecDCBZ ; 11111(101)10=1014=DCBZ metatabLine %0011, MRSecDCBZ ; 48
|
||||||
MROptabD
|
MROptabD
|
||||||
optabRow 2, 9, %0000, MRPriPlainLoad, MRSecLoad ; Xopcd=00000(101)11=023=LWZX Dopcd=(1)00000=32=LWZ
|
optabRow 2, 4,L, %0000, MRPriPlainLoad, MRSecLoad ; 00000(101)11=023=LWZX (1)00000=32=LWZ metatabLine %0001, MRSecLoad ; 2
|
||||||
optabRow 0, 3, %0000, MRPriPlainLoad, MRSecLoad ; Xopcd=00010(101)11=087=LBZX Dopcd=(1)00010=34=LBZ
|
optabRow 0, 1,L, %0000, MRPriPlainLoad, MRSecLoad ; 00010(101)11=087=LBZX (1)00010=34=LBZ metatabLine %0001, MRSecLoad ; 0
|
||||||
optabRow 18, 8, %0000, MRPriPlainStore, MRSecDone ; Xopcd=00100(101)11=151=STWX Dopcd=(1)00100=36=STW
|
optabRow 18, 4,S, %0000, MRPriPlainStore, MRSecDone ; 00100(101)11=151=STWX (1)00100=36=STW metatabLine %0001, MRSecDone ; 18
|
||||||
optabRow 16, 2, %0000, MRPriPlainStore, MRSecDone ; Xopcd=00110(101)11=215=STBX Dopcd=(1)00110=38=STB
|
optabRow 16, 1,S, %0000, MRPriPlainStore, MRSecDone ; 00110(101)11=215=STBX (1)00110=38=STB metatabLine %0001, MRSecDone ; 16
|
||||||
optabRow 1, 5, %0000, MRPriPlainLoad, MRSecLoad ; Xopcd=01000(101)11=279=LHZX Dopcd=(1)01000=40=LHZ
|
optabRow 1, 2,L, %0000, MRPriPlainLoad, MRSecLoad ; 01000(101)11=279=LHZX (1)01000=40=LHZ metatabLine %0001, MRSecLoad ; 1
|
||||||
optabRow 5, 5, %0000, MRPriPlainLoad, MRSecLoadExt ; Xopcd=01010(101)11=343=LHAX Dopcd=(1)01010=42=LHA
|
optabRow 5, 2,L, %0000, MRPriPlainLoad, MRSecLoadExt ; 01010(101)11=343=LHAX (1)01010=42=LHA metatabLine %0001, MRSecLoadExt ; 5
|
||||||
optabRow 17, 4, %0000, MRPriPlainStore, MRSecDone ; Xopcd=01100(101)11=407=STHX Dopcd=(1)01100=44=STH
|
optabRow 17, 2,S, %0000, MRPriPlainStore, MRSecDone ; 01100(101)11=407=STHX (1)01100=44=STH metatabLine %0001, MRSecDone ; 17
|
||||||
optabRow 26, 9, %0011, MRPriUpdLoad, MRSecLMW ; Xopcd=01110(101)11=471 Dopcd=(1)01110=46=LMW
|
optabRow 26, 4,L, %0011, MRPriUpdLoad, MRSecLMW ; 01110(101)11=471 (1)01110=46=LMW metatabLine %0011, MRSecLMW ; 26
|
||||||
optabRow 14, 9, %0000, MRPriPlainLoad, MRSecLFSu ; Xopcd=10000(101)11=535=LFSX Dopcd=(1)10000=48=LFS
|
optabRow 14, 4,L, %0000, MRPriPlainLoad, MRSecLFSu ; 10000(101)11=535=LFSX (1)10000=48=LFS metatabLine %0001, MRSecLFSu ; 14
|
||||||
optabRow 15, 17, %0000, MRPriPlainLoad, MRSecLFDu ; Xopcd=10010(101)11=599=LFDX Dopcd=(1)10010=50=LFD
|
optabRow 15, 8,L, %0000, MRPriPlainLoad, MRSecLFDu ; 10010(101)11=599=LFDX (1)10010=50=LFD metatabLine %0001, MRSecLFDu ; 15
|
||||||
optabRow 18, 8, %0000, MRPriSTFSx, MRSecDone ; Xopcd=10100(101)11=663=STFSX Dopcd=(1)10100=52=STFS
|
optabRow 18, 4,S, %0000, MRPriSTFSx, MRSecDone ; 10100(101)11=663=STFSX (1)10100=52=STFS metatabLine %0001, MRSecDone ; 18
|
||||||
optabRow 19, 16, %0000, MRPriSTFDx, MRSecDone ; Xopcd=10110(101)11=727=STFDX Dopcd=(1)10110=54=STFD
|
optabRow 19, 8,S, %0000, MRPriSTFDx, MRSecDone ; 10110(101)11=727=STFDX (1)10110=54=STFD metatabLine %0001, MRSecDone ; 19
|
||||||
optabRow 63, 1, %0000, , ; Xopcd=11000(101)11=791 Dopcd=(1)11000=56
|
optabRow , ,, , , ; 11000(101)11=791 (1)11000=56
|
||||||
optabRow 63, 1, %0000, , ; Xopcd=11010(101)11=855 Dopcd=(1)11010=58
|
optabRow , ,, , , ; 11010(101)11=855 (1)11010=58
|
||||||
optabRow 63, 1, %0000, , ; Xopcd=11100(101)11=919 Dopcd=(1)11100=60
|
optabRow , ,, , , ; 11100(101)11=919 (1)11100=60
|
||||||
optabRow 18, 8, %0000, MRPriSTFDx, MRSecDone ; Xopcd=11110(101)11=983=STFIWX Dopcd=(1)11110=62
|
optabRow 18, 4,S, %0000, MRPriSTFDx, MRSecDone ; 11110(101)11=983=STFIWX (1)11110=62 metatabLine %0001, MRSecDone ; 18
|
||||||
optabRow 2, 9, %0000, MRPriUpdLoad, MRSecLoad ; Xopcd=00001(101)11=055=LWZUX Dopcd=(1)00001=33=LWZU
|
optabRow 2, 4,L, %0000, MRPriUpdLoad, MRSecLoad ; 00001(101)11=055=LWZUX (1)00001=33=LWZU metatabLine %0001, MRSecLoad ; 2
|
||||||
optabRow 0, 3, %0000, MRPriUpdLoad, MRSecLoad ; Xopcd=00011(101)11=119=LBZUX Dopcd=(1)00011=35=LBZU
|
optabRow 0, 1,L, %0000, MRPriUpdLoad, MRSecLoad ; 00011(101)11=119=LBZUX (1)00011=35=LBZU metatabLine %0001, MRSecLoad ; 0
|
||||||
optabRow 18, 8, %0000, MRPriUpdStore, MRSecDone ; Xopcd=00101(101)11=183=STWUX Dopcd=(1)00101=37=STWU
|
optabRow 18, 4,S, %0000, MRPriUpdStore, MRSecDone ; 00101(101)11=183=STWUX (1)00101=37=STWU metatabLine %0001, MRSecDone ; 18
|
||||||
optabRow 16, 2, %0000, MRPriUpdStore, MRSecDone ; Xopcd=00111(101)11=247=STBUX Dopcd=(1)00111=39=STBU
|
optabRow 16, 1,S, %0000, MRPriUpdStore, MRSecDone ; 00111(101)11=247=STBUX (1)00111=39=STBU metatabLine %0001, MRSecDone ; 16
|
||||||
optabRow 1, 5, %0000, MRPriUpdLoad, MRSecLoad ; Xopcd=01001(101)11=311=LHZUX Dopcd=(1)01001=41=LHZU
|
optabRow 1, 2,L, %0000, MRPriUpdLoad, MRSecLoad ; 01001(101)11=311=LHZUX (1)01001=41=LHZU metatabLine %0001, MRSecLoad ; 1
|
||||||
optabRow 5, 5, %0000, MRPriUpdLoad, MRSecLoadExt ; Xopcd=01011(101)11=375=LHAUX Dopcd=(1)01011=43=LHAU
|
optabRow 5, 2,L, %0000, MRPriUpdLoad, MRSecLoadExt ; 01011(101)11=375=LHAUX (1)01011=43=LHAU metatabLine %0001, MRSecLoadExt ; 5
|
||||||
optabRow 17, 4, %0000, MRPriUpdStore, MRSecDone ; Xopcd=01101(101)11=439=STHUX Dopcd=(1)01101=45=STHU
|
optabRow 17, 2,S, %0000, MRPriUpdStore, MRSecDone ; 01101(101)11=439=STHUX (1)01101=45=STHU metatabLine %0001, MRSecDone ; 17
|
||||||
optabRow 30, 8, %0010, MRPriUpdStore, MRSecSTMW ; Xopcd=01111(101)11=503 Dopcd=(1)01111=47=STMW
|
optabRow 30, 4,S, %0010, MRPriUpdStore, MRSecSTMW ; 01111(101)11=503 (1)01111=47=STMW metatabLine %0011, MRSecSTMW ; 30
|
||||||
optabRow 14, 9, %0000, MRPriUpdLoad, MRSecLFSu ; Xopcd=10001(101)11=567=LFSUX Dopcd=(1)10001=49=LFSU
|
optabRow 14, 4,L, %0000, MRPriUpdLoad, MRSecLFSu ; 10001(101)11=567=LFSUX (1)10001=49=LFSU metatabLine %0001, MRSecLFSu ; 14
|
||||||
optabRow 15, 17, %0000, MRPriUpdLoad, MRSecLFDu ; Xopcd=10011(101)11=631=LFDUX Dopcd=(1)10011=51=LFDU
|
optabRow 15, 8,L, %0000, MRPriUpdLoad, MRSecLFDu ; 10011(101)11=631=LFDUX (1)10011=51=LFDU metatabLine %0001, MRSecLFDu ; 15
|
||||||
optabRow 18, 8, %0000, MRPriSTFSUx, MRSecDone ; Xopcd=10101(101)11=695=STFSUX Dopcd=(1)10101=53=STFSU
|
optabRow 18, 4,S, %0000, MRPriSTFSUx, MRSecDone ; 10101(101)11=695=STFSUX (1)10101=53=STFSU metatabLine %0001, MRSecDone ; 18
|
||||||
optabRow 19, 16, %0000, MRPriSTFDUx, MRSecDone ; Xopcd=10111(101)11=759=STFDUX Dopcd=(1)10111=55=STFDU
|
optabRow 19, 8,S, %0000, MRPriSTFDUx, MRSecDone ; 10111(101)11=759=STFDUX (1)10111=55=STFDU metatabLine %0001, MRSecDone ; 19
|
||||||
optabRow 63, 1, %0000, , ; Xopcd=11001(101)11=823 Dopcd=(1)11001=57
|
optabRow , ,, , , ; 11001(101)11=823 (1)11001=57
|
||||||
optabRow 63, 1, %0000, , ; Xopcd=11011(101)11=887 Dopcd=(1)11011=59
|
optabRow , ,, , , ; 11011(101)11=887 (1)11011=59
|
||||||
optabRow 63, 1, %0000, , ; Xopcd=11101(101)11=951 Dopcd=(1)11101=61
|
optabRow , ,, , , ; 11101(101)11=951 (1)11101=61
|
||||||
optabRow 63, 1, %0000, , ; Xopcd=11111(101)11=1015 Dopcd=(1)11111=63
|
optabRow , ,, , , ; 11111(101)11=1015 (1)11111=63
|
||||||
|
|||||||
@ -1,7 +1,7 @@
|
|||||||
MRPriCrash ; C00
|
MRPriCrash ; C00
|
||||||
bl SystemCrash
|
bl SystemCrash
|
||||||
MRSecException ; C04
|
MRSecException ; C04
|
||||||
b MRSecIOInstFail
|
b MRSecException2
|
||||||
|
|
||||||
########################################################################
|
########################################################################
|
||||||
|
|
||||||
@ -139,30 +139,30 @@ MRSecLoad ; D44
|
|||||||
|
|
||||||
########################################################################
|
########################################################################
|
||||||
|
|
||||||
MRSecDone ; D50
|
MRSecDone
|
||||||
andi. r23, r16, FlagTrace
|
andi. r23, r16, ContextFlagTraceWhenDone ; Time to return from interrupt
|
||||||
addi r10, r10, 4
|
addi r10, r10, 4
|
||||||
mtsrr0 r10
|
mtsrr0 r10
|
||||||
mtsrr1 r11
|
mtsrr1 r11
|
||||||
bne @trace
|
bne @trace ; Is a Trace flagged?
|
||||||
mtlr r12
|
mtlr r12
|
||||||
|
|
||||||
bc BO_IF_NOT, mrFlagDidLoad, @otherway
|
bc BO_IF_NOT, mrFlagDidLoad, @load_ewa_registers
|
||||||
mtcr r13
|
mtcr r13
|
||||||
lmw r2, KDP.r2(r1)
|
lmw r2, KDP.r2(r1)
|
||||||
lwz r0, KDP.r0(r1)
|
lwz r0, KDP.r0(r1)
|
||||||
lwz r1, KDP.r1(r1)
|
lwz r1, KDP.r1(r1)
|
||||||
rfi
|
rfi
|
||||||
@otherway
|
@load_ewa_registers ; Only load changed registers
|
||||||
mtcr r13
|
mtcr r13
|
||||||
lmw r10, KDP.r10(r1)
|
lmw r10, KDP.r10(r1)
|
||||||
lwz r1, KDP.r1(r1)
|
lwz r1, KDP.r1(r1)
|
||||||
rfi
|
rfi
|
||||||
|
|
||||||
@trace
|
@trace ; Jump to Trace int handler
|
||||||
mfsprg r24, 3
|
mfsprg r24, 3
|
||||||
mtsprg 2, r12
|
mtsprg 2, r12
|
||||||
_bclr r16, r16, bitFlagTrace
|
_clear r16, r16, bitContextFlagTraceWhenDone
|
||||||
lwz r12, VecTbl.Trace(r24)
|
lwz r12, VecTbl.Trace(r24)
|
||||||
stw r16, KDP.Flags(r1)
|
stw r16, KDP.Flags(r1)
|
||||||
mtcr r13
|
mtcr r13
|
||||||
@ -292,17 +292,17 @@ MRSecSTWCX ; EE4
|
|||||||
|
|
||||||
########################################################################
|
########################################################################
|
||||||
|
|
||||||
MRSecCacheWang ; EF8
|
MRSecRedoNoTrace ; Rerun the (cache) instruction, but not its Trace Exception
|
||||||
rlwinm r16, r16, 0, ~(FlagTrace | FlagLowSaves)
|
rlwinm r16, r16, 0, ~(ContextFlagTraceWhenDone | ContextFlagMemRetryErr)
|
||||||
addi r10, r10, -4
|
subi r10, r10, 4
|
||||||
stw r16, KDP.Flags(r1)
|
stw r16, KDP.Flags(r1)
|
||||||
b MRSecDone
|
b MRSecDone
|
||||||
|
|
||||||
########################################################################
|
########################################################################
|
||||||
|
|
||||||
MRSecIOInstFail ; F08
|
MRSecException2 ; F08
|
||||||
li r8, ecDataInvalidAddress
|
li r8, ecDataInvalidAddress
|
||||||
b ExceptionAfterRetry
|
b MRException
|
||||||
|
|
||||||
########################################################################
|
########################################################################
|
||||||
|
|
||||||
@ -368,7 +368,7 @@ MRSecLSWix ; FA0
|
|||||||
|
|
||||||
########################################################################
|
########################################################################
|
||||||
|
|
||||||
MRPriUnknown ; FB8
|
MRPriLSCBX ; FB8
|
||||||
mfxer r22
|
mfxer r22
|
||||||
andi. r22, r22, 0x7F
|
andi. r22, r22, 0x7F
|
||||||
rlwimi r17, r27, 0,16,20
|
rlwimi r17, r27, 0,16,20
|
||||||
@ -384,16 +384,16 @@ MRPriUnknown ; FB8
|
|||||||
rlwimi r17, r17, 5,11,15
|
rlwimi r17, r17, 5,11,15
|
||||||
b loc_10C8
|
b loc_10C8
|
||||||
|
|
||||||
MRSecUnknown ; FF0
|
MRSecLSCBX ; FF0
|
||||||
rlwinm. r22, r17, 28,25,29
|
rlwinm. r22, r17, 28,25,29
|
||||||
rlwinm r28, r17, 13,25,29
|
rlwinm r28, r17, 13,25,29
|
||||||
bne loc_109C
|
bne loc_109C
|
||||||
rlwinm r23, r17, 9,27,28
|
rlwinm r23, r17, 9,27,28
|
||||||
|
|
||||||
loc_1000 ; 1000
|
|
||||||
slw r21, r21, r23
|
slw r21, r21, r23
|
||||||
b loc_109C
|
b loc_109C
|
||||||
|
|
||||||
|
########################################################################
|
||||||
|
|
||||||
loc_1008 ; 1008
|
loc_1008 ; 1008
|
||||||
andi. r23, r17, 0x7C0
|
andi. r23, r17, 0x7C0
|
||||||
rlwinm r28, r17, 13,25,29
|
rlwinm r28, r17, 13,25,29
|
||||||
|
|||||||
@ -103,39 +103,33 @@ ecDataSupWriteViolation equ 23
|
|||||||
ecUnknown24 equ 24
|
ecUnknown24 equ 24
|
||||||
|
|
||||||
|
|
||||||
; Runtime Flag equates
|
; FLAGS r7/cr
|
||||||
_bitEqu 0, Flag0
|
|
||||||
_bitEqu 1, Flag1
|
crMaskAll equ %11111111
|
||||||
_bitEqu 2, Flag2
|
|
||||||
_bitEqu 3, Flag3
|
; Bits 0-7 (CR0-CR1): Exception Cause Number (see equates)
|
||||||
_bitEqu 4, Flag4
|
crMaskExceptionNum equ %11000000
|
||||||
_bitEqu 5, Flag5
|
maskExceptionNum equ 0xFF000000
|
||||||
_bitEqu 6, Flag6
|
|
||||||
_bitEqu 7, Flag7
|
crMaskFlags equ %00111111
|
||||||
_bitEqu 8, FlagEmu
|
maskFlags equ 0x00FFFFFF
|
||||||
_bitEqu 9, Flag9
|
|
||||||
_bitEqu 10, FlagBlue
|
; Bits 8-15 (CR2-CR3) Global Flags
|
||||||
_bitEqu 11, Flag11
|
crMaskGlobalFlags equ %00110000
|
||||||
_bitEqu 12, FlagVec
|
maskGlobalFlags equ 0x00FF0000
|
||||||
_bitEqu 13, FlagHasMQ
|
_bitEqu 8, GlobalFlagSystem ; raised when System (Emulator) Context is running
|
||||||
_bitEqu 14, Flag14
|
_bitEqu 13, GlobalFlagMQReg ; raised when POWER "Multiply-Quotient" register is present
|
||||||
_bitEqu 15, Flag15
|
|
||||||
_bitEqu 16, FlagSIGP
|
; Bits 24-31 (CR6-CR7) Context Flags
|
||||||
_bitEqu 17, Flag17
|
crMaskContextFlags equ %00001111
|
||||||
_bitEqu 18, Flag18
|
maskContextFlags equ 0x0000FFFF
|
||||||
_bitEqu 19, Flag19
|
; Bits 20-23 (CR5) MSR Flags FE0/SE/BE/FE1:
|
||||||
_bitEqu 20, FlagFE0
|
crMaskMsrFlags equ %000001000
|
||||||
_bitEqu 21, FlagSE
|
maskMsrFlags equ 0x00000F000
|
||||||
_bitEqu 22, FlagBE
|
; Bits 24-31 (CR6-CR7) Other Context Flags:
|
||||||
_bitEqu 23, FlagFE1
|
_bitEqu 26, ContextFlagTraceWhenDone ; raised when MSR[SE] is up but we get an unrelated interrupt
|
||||||
_bitEqu 24, Flag24
|
_bitEqu 27, ContextFlagMemRetryErr ; raised when an exception is raised during MemRetry
|
||||||
_bitEqu 25, Flag25
|
_bitEqu 31, ContextFlagResumeMemRetry ; allows MemRetry to be resumed (raised by userspace?)
|
||||||
_bitEqu 26, FlagTrace
|
|
||||||
_bitEqu 27, FlagLowSaves
|
|
||||||
_bitEqu 28, Flag28
|
|
||||||
_bitEqu 29, Flag29
|
|
||||||
_bitEqu 30, Flag30
|
|
||||||
_bitEqu 31, Flag31
|
|
||||||
|
|
||||||
|
|
||||||
mrOpflag1 equ cr3_lt
|
mrOpflag1 equ cr3_lt
|
||||||
|
|||||||
@ -2,23 +2,21 @@
|
|||||||
|
|
||||||
########################################################################
|
########################################################################
|
||||||
|
|
||||||
ExceptionAfterRetry
|
MRException
|
||||||
mtsprg 3, r24
|
mtsprg 3, r24
|
||||||
|
|
||||||
lwz r9, KDP.Enables(r1)
|
lwz r9, KDP.Enables(r1)
|
||||||
rlwinm r23, r17, (32-1), 27, 31
|
extrwi r23, r17, 5, 25 ; extract accessLen field
|
||||||
rlwnm. r9, r9, r8, 0, 0 ; BGE taken if exception disabled
|
rlwnm. r9, r9, r8, 0, 0 ; BGE taken if exception disabled
|
||||||
|
|
||||||
bcl BO_IF, bitFlag15, major_0x02980_0x100
|
bcl BO_IF, mrFlagDidLoad, LoadExtraMRRegs
|
||||||
|
|
||||||
lwz r6, KDP.CurCBPtr(r1)
|
lwz r6, KDP.ContextPtr(r1)
|
||||||
|
|
||||||
_bset r7, r16, 27
|
|
||||||
|
|
||||||
|
_set r7, r16, bitContextFlagMemRetryErr
|
||||||
neg r23, r23
|
neg r23, r23
|
||||||
mtcrf 0x3f, r7
|
mtcrf crMaskFlags, r7
|
||||||
add r19, r19, r23
|
add r19, r19, r23 ; convert r19 from end address back to start address??
|
||||||
|
|
||||||
insrwi r7, r8, 8, 0 ; ec code -> high byte of flags
|
insrwi r7, r8, 8, 0 ; ec code -> high byte of flags
|
||||||
|
|
||||||
slwi r8, r8, 2 ; increment counter
|
slwi r8, r8, 2 ; increment counter
|
||||||
@ -29,19 +27,19 @@ ExceptionAfterRetry
|
|||||||
|
|
||||||
; Move regs from KDP to ContextBlock
|
; Move regs from KDP to ContextBlock
|
||||||
lwz r8, KDP.r7(r1)
|
lwz r8, KDP.r7(r1)
|
||||||
stw r8, CB.r7(r6)
|
stw r8, CB.r7+4(r6)
|
||||||
lwz r8, KDP.r8(r1)
|
lwz r8, KDP.r8(r1)
|
||||||
stw r8, CB.r8(r6)
|
stw r8, CB.r8+4(r6)
|
||||||
lwz r8, KDP.r9(r1)
|
lwz r8, KDP.r9(r1)
|
||||||
stw r8, CB.r9(r6)
|
stw r8, CB.r9+4(r6)
|
||||||
lwz r8, KDP.r10(r1)
|
lwz r8, KDP.r10(r1)
|
||||||
stw r8, CB.r10(r6)
|
stw r8, CB.r10+4(r6)
|
||||||
lwz r8, KDP.r11(r1)
|
lwz r8, KDP.r11(r1)
|
||||||
stw r8, CB.r11(r6)
|
stw r8, CB.r11+4(r6)
|
||||||
lwz r8, KDP.r12(r1)
|
lwz r8, KDP.r12(r1)
|
||||||
stw r8, CB.r12(r6)
|
stw r8, CB.r12+4(r6)
|
||||||
lwz r8, KDP.r13(r1)
|
lwz r8, KDP.r13(r1)
|
||||||
stw r8, CB.r13(r6)
|
stw r8, CB.r13+4(r6)
|
||||||
|
|
||||||
bge RunSystemContext ; Alt Context has left exception disabled => Sys Context
|
bge RunSystemContext ; Alt Context has left exception disabled => Sys Context
|
||||||
;fall through ; exception enabled => run userspace handler
|
;fall through ; exception enabled => run userspace handler
|
||||||
@ -49,36 +47,36 @@ ExceptionAfterRetry
|
|||||||
########################################################################
|
########################################################################
|
||||||
|
|
||||||
RunExceptionHandler
|
RunExceptionHandler
|
||||||
stw r10, CB.ExceptionOriginAddr(r6) ; Save r10/SRR0, r12/LR, r3, r4
|
stw r10, CB.FaultSrcPC+4(r6) ; Save r10/SRR0, r12/LR, r3, r4
|
||||||
stw r12, CB.ExceptionOriginLR(r6)
|
stw r12, CB.FaultSrcLR+4(r6)
|
||||||
stw r3, CB.ExceptionOriginR3(r6)
|
stw r3, CB.FaultSrcR3+4(r6)
|
||||||
stw r4, CB.ExceptionOriginR4(r6)
|
stw r4, CB.FaultSrcR4+4(r6)
|
||||||
|
|
||||||
lwz r8, KDP.Enables(r1) ; Save Enables & Flags
|
lwz r8, KDP.Enables(r1) ; Save Enables & Flags, inc ContextFlagMemRetryErr
|
||||||
stw r7, CB.ExceptionOriginFlags(r6)
|
stw r7, CB.IntraState.Flags(r6)
|
||||||
stw r8, CB.ExceptionOriginEnables(r6)
|
stw r8, CB.IntraState.Enables(r6)
|
||||||
|
|
||||||
; Set up the Exception Handler context
|
; Set up the Exception Handler context
|
||||||
li r8, 0 ; r8/Enables = 0 (handler must not throw exception)
|
li r8, 0 ; r8/Enables = 0 (handler must not throw exception)
|
||||||
lwz r10, CB.ExceptionHandler(r6) ; r10/SRR0 = handler addr
|
lwz r10, CB.IntraState.Handler+4(r6) ; r10/SRR0 = handler addr
|
||||||
lwz r4, CB.ExceptionHandlerR4(r6) ; r4 = arbitrary second argument
|
lwz r4, CB.IntraState.HandlerArg+4(r6) ; r4 = arbitrary second argument
|
||||||
lwz r3, KDP.ECBPtrLogical(r1) ; r3 = ContextBlock ptr
|
lwz r3, KDP.ECBPtrLogical(r1) ; r3 = ContextBlock ptr
|
||||||
bc BO_IF, bitFlagEmu, @sys
|
bc BO_IF, bitGlobalFlagSystem, @sys
|
||||||
lwz r3, KDP.NCBCacheLA0(r1)
|
lwz r3, KDP.NCBCacheLA0(r1)
|
||||||
@sys
|
@sys
|
||||||
lwz r12, KDP.EmuKCallTblPtrLogical(r1) ; r12/LR = address of KCallReturnFromException trap
|
lwz r12, KDP.EmuKCallTblPtrLogical(r1) ; r12/LR = address of KCallReturnFromException trap
|
||||||
|
|
||||||
bcl BO_IF, bitFlagLowSaves, PreferRegistersFromKDPSavingContextBlock ; ???
|
bcl BO_IF, bitContextFlagMemRetryErr, SaveFailingMemRetryState
|
||||||
|
|
||||||
rlwinm r7, r7, 0, 29, 15 ; unset flags 16-28
|
rlwinm r7, r7, 0, 29, 15 ; unset flags 16-28
|
||||||
stw r8, KDP.Enables(r1)
|
stw r8, KDP.Enables(r1)
|
||||||
rlwimi r11, r7, 0, 20, 23 ; threfore unset MSR[FE0/SE/BE/FE1]
|
rlwimi r11, r7, 0, 20, 23 ; threfore unset MSR[FE0/SE/BE/FE1]
|
||||||
|
|
||||||
b IntReturn
|
b ReturnFromInt
|
||||||
|
|
||||||
########################################################################
|
########################################################################
|
||||||
|
|
||||||
major_0x02980_0x100
|
LoadExtraMRRegs
|
||||||
lwz r0, KDP.r0(r1)
|
lwz r0, KDP.r0(r1)
|
||||||
lwz r2, KDP.r2(r1)
|
lwz r2, KDP.r2(r1)
|
||||||
lwz r3, KDP.r3(r1)
|
lwz r3, KDP.r3(r1)
|
||||||
@ -86,12 +84,12 @@ major_0x02980_0x100
|
|||||||
lwz r5, KDP.r5(r1)
|
lwz r5, KDP.r5(r1)
|
||||||
blr
|
blr
|
||||||
|
|
||||||
PreferRegistersFromKDPSavingContextBlock
|
SaveFailingMemRetryState
|
||||||
stw r17, CB.PropagateR17(r6)
|
stw r17, CB.IntraState.MemRet17+4(r6)
|
||||||
stw r20, CB.PropagateR20(r6)
|
stw r20, CB.IntraState.MemRetData(r6)
|
||||||
stw r21, CB.PropagateR21(r6)
|
stw r21, CB.IntraState.MemRetData+4(r6)
|
||||||
stw r19, CB.PropagateR19(r6)
|
stw r19, CB.IntraState.MemRet19+4(r6)
|
||||||
stw r18, CB.PropagateR18(r6)
|
stw r18, CB.IntraState.MemRet18+4(r6)
|
||||||
lmw r14, KDP.r14(r1)
|
lmw r14, KDP.r14(r1)
|
||||||
blr
|
blr
|
||||||
|
|
||||||
@ -104,68 +102,70 @@ KCallReturnFromExceptionFastPath
|
|||||||
addi r11, r11, 1
|
addi r11, r11, 1
|
||||||
stw r11, KDP.NKInfo.NanoKernelCallCounts(r1)
|
stw r11, KDP.NKInfo.NanoKernelCallCounts(r1)
|
||||||
mfsrr1 r11
|
mfsrr1 r11
|
||||||
rlwimi r7, r7, 27, 26, 26 ; ?re-enable single stepping
|
rlwimi r7, r7, 32+bitMsrSE-bitContextFlagTraceWhenDone, ContextFlagTraceWhenDone
|
||||||
|
|
||||||
KCallReturnFromException
|
KCallReturnFromException
|
||||||
cmplwi cr1, r3, 1 ; exception handler return value
|
cmplwi cr1, r3, 1 ; exception handler return value
|
||||||
blt cr1, @dispose
|
blt cr1, @dispose
|
||||||
mtcrf 0x3f, r7
|
mtcrf crMaskFlags, r7
|
||||||
beq cr1, @propagate
|
beq cr1, @propagate
|
||||||
|
|
||||||
;force to system context ; Handler returned >= 1
|
; If handler returns an exception cause code 2-255, "force" this exception to the System Context.
|
||||||
subi r8, r3, 32
|
subi r8, r3, 32
|
||||||
lwz r9, KDP.NKInfo.ExceptionForcedCount(r1)
|
lwz r9, KDP.NKInfo.ExceptionForcedCount(r1)
|
||||||
cmplwi r8, 256-32
|
cmplwi r8, 256-32
|
||||||
addi r9, r9, 1
|
addi r9, r9, 1
|
||||||
stw r9, KDP.NKInfo.ExceptionForcedCount(r1)
|
stw r9, KDP.NKInfo.ExceptionForcedCount(r1)
|
||||||
insrwi r7, r3, 8, 0
|
insrwi r7, r3, 8, 0
|
||||||
blt RunSystemContext ; Handler returned 1-255: force that exception number to System
|
blt RunSystemContext
|
||||||
li r8, ecTrapInstr
|
li r8, ecTrapInstr
|
||||||
b Exception ; Handler returned >= 256: fail!
|
b Exception ; (error if number is > max exception number)
|
||||||
|
|
||||||
@dispose ; Handler returned 0: return to the code that threw the exception
|
; If handler returns 0 (System Context must always do this), return to userspace.
|
||||||
lwz r8, CB.ExceptionOriginFlags(r6)
|
@dispose
|
||||||
lwz r10, CB.ExceptionOriginAddr(r6)
|
lwz r8, CB.IntraState.Flags(r6) ; Restore Context flags (inc exception number?)
|
||||||
rlwimi r7, r8, 0, 0xFF00FFFF ; restore most Flags to pre-exception state
|
lwz r10, CB.FaultSrcPC+4(r6)
|
||||||
lwz r8, CB.ExceptionOriginEnables(r6)
|
rlwimi r7, r8, 0, maskExceptionNum | maskContextFlags ; preserve global flags
|
||||||
rlwimi r11, r7, 0, 20, 23 ; MSR[FE0/SE/BE/FE1] <- Flags
|
lwz r8, CB.IntraState.Enables(r6)
|
||||||
|
rlwimi r11, r7, 0, maskMsrFlags
|
||||||
stw r8, KDP.Enables(r1)
|
stw r8, KDP.Enables(r1)
|
||||||
|
andi. r8, r11, MsrFE0 + MsrFE1 ; check: are floating-pt exceptions enabled?
|
||||||
|
|
||||||
andi. r8, r11, MsrFE0 + MsrFE1 ; check: are floating-pt exceptions enabled?
|
lwz r12, CB.FaultSrcLR+4(r6) ; restore LR/r3/r4
|
||||||
|
lwz r3, CB.FaultSrcR3+4(r6)
|
||||||
|
lwz r4, CB.FaultSrcR4+4(r6)
|
||||||
|
|
||||||
lwz r12, CB.ExceptionOriginLR(r6) ; restore LR/r3/r4
|
bnel EnableFPU
|
||||||
lwz r3, CB.ExceptionOriginR3(r6)
|
|
||||||
lwz r4, CB.ExceptionOriginR4(r6)
|
|
||||||
|
|
||||||
bnel EnableFPU ; if FP exceptions are enabled, make sure the FPU is enabled
|
addi r9, r6, CB.IntraState ; If MemRetry was interrupted, resume it.
|
||||||
|
|
||||||
addi r9, r6, CB.ExceptionOriginFlags ; never gets used... points to exception part of ContextBlock?
|
b ReturnFromInt
|
||||||
|
|
||||||
b IntReturn
|
; If handler returns 1, "propagate" this exception to the System Context
|
||||||
|
; (When we get back to the Alternate Context, it will be as if the exception was disposed.)
|
||||||
@propagate ; Handler returned 1: propagate exception
|
@propagate
|
||||||
lwz r9, KDP.NKInfo.ExceptionPropagateCount(r1)
|
lwz r9, KDP.NKInfo.ExceptionPropagateCount(r1)
|
||||||
lwz r8, CB.ExceptionOriginFlags(r6)
|
lwz r8, CB.IntraState.Flags(r6)
|
||||||
addi r9, r9, 1
|
addi r9, r9, 1
|
||||||
stw r9, KDP.NKInfo.ExceptionPropagateCount(r1)
|
stw r9, KDP.NKInfo.ExceptionPropagateCount(r1)
|
||||||
lwz r10, CB.ExceptionOriginAddr(r6)
|
lwz r10, CB.FaultSrcPC+4(r6)
|
||||||
rlwimi r7, r8, 0, 0xFF00FFFF ; restore most Flags to pre-exception state
|
rlwimi r7, r8, 0, maskExceptionNum | maskContextFlags ; preserve global flags
|
||||||
lwz r8, CB.ExceptionOriginEnables(r6)
|
lwz r8, CB.IntraState.Enables(r6)
|
||||||
mtcrf 0x0f, r7
|
mtcrf crMaskContextFlags, r7
|
||||||
rlwimi r11, r7, 0, 20, 23 ; MSR[FE0/SE/BE/FE1] <- Flags
|
rlwimi r11, r7, 0, maskMsrFlags
|
||||||
stw r8, KDP.Enables(r1)
|
stw r8, KDP.Enables(r1)
|
||||||
|
|
||||||
lwz r12, CB.ExceptionOriginLR(r6) ; restore LR/r3/r4
|
lwz r12, CB.FaultSrcLR+4(r6) ; restore LR/r3/r4
|
||||||
lwz r3, CB.ExceptionOriginR3(r6)
|
lwz r3, CB.FaultSrcR3+4(r6)
|
||||||
lwz r4, CB.ExceptionOriginR4(r6)
|
lwz r4, CB.FaultSrcR4+4(r6)
|
||||||
|
|
||||||
bc BO_IF_NOT, bitFlagLowSaves, RunSystemContext
|
bc BO_IF_NOT, bitContextFlagMemRetryErr, RunSystemContext
|
||||||
stmw r14, KDP.r14(r1)
|
stmw r14, KDP.r14(r1) ; When we *do* get back to this context,
|
||||||
lwz r17, CB.PropagateR17(r6)
|
lwz r17, CB.IntraState.MemRet17+4(r6) ; make sure MemRetry state can be resumed
|
||||||
lwz r20, CB.PropagateR20(r6)
|
lwz r20, CB.IntraState.MemRetData(r6) ; from InterState
|
||||||
lwz r21, CB.PropagateR21(r6)
|
lwz r21, CB.IntraState.MemRetData+4(r6)
|
||||||
lwz r19, CB.PropagateR19(r6)
|
lwz r19, CB.IntraState.MemRet19+4(r6)
|
||||||
lwz r18, CB.PropagateR18(r6)
|
lwz r18, CB.IntraState.MemRet18+4(r6)
|
||||||
b RunSystemContext
|
b RunSystemContext
|
||||||
|
|
||||||
########################################################################
|
########################################################################
|
||||||
@ -198,14 +198,14 @@ LoadInterruptRegisters
|
|||||||
stw r6, KDP.r6(r1)
|
stw r6, KDP.r6(r1)
|
||||||
mfsprg r6, 1
|
mfsprg r6, 1
|
||||||
stw r6, KDP.r1(r1)
|
stw r6, KDP.r1(r1)
|
||||||
lwz r6, KDP.CurCBPtr(r1)
|
lwz r6, KDP.ContextPtr(r1)
|
||||||
stw r7, CB.r7(r6)
|
stw r7, CB.r7+4(r6)
|
||||||
stw r8, CB.r8(r6)
|
stw r8, CB.r8+4(r6)
|
||||||
stw r9, CB.r9(r6)
|
stw r9, CB.r9+4(r6)
|
||||||
stw r10, CB.r10(r6)
|
stw r10, CB.r10+4(r6)
|
||||||
stw r11, CB.r11(r6)
|
stw r11, CB.r11+4(r6)
|
||||||
stw r12, CB.r12(r6)
|
stw r12, CB.r12+4(r6)
|
||||||
stw r13, CB.r13(r6)
|
stw r13, CB.r13+4(r6)
|
||||||
mfsrr0 r10
|
mfsrr0 r10
|
||||||
mfcr r13
|
mfcr r13
|
||||||
lwz r7, KDP.Flags(r1)
|
lwz r7, KDP.Flags(r1)
|
||||||
@ -217,7 +217,7 @@ LoadInterruptRegisters
|
|||||||
|
|
||||||
Exception
|
Exception
|
||||||
lwz r9, KDP.Enables(r1)
|
lwz r9, KDP.Enables(r1)
|
||||||
mtcrf 0x3f, r7
|
mtcrf crMaskFlags, r7
|
||||||
|
|
||||||
rlwnm. r9, r9, r8, 0, 0 ; BLT taken if exception enabled
|
rlwnm. r9, r9, r8, 0, 0 ; BLT taken if exception enabled
|
||||||
|
|
||||||
@ -240,7 +240,7 @@ RunSystemContext
|
|||||||
addi r8, r1, KDP.VecTblSystem ; System VecTbl
|
addi r8, r1, KDP.VecTblSystem ; System VecTbl
|
||||||
mtsprg 3, r8
|
mtsprg 3, r8
|
||||||
|
|
||||||
bcl BO_IF, bitFlagEmu, SystemCrash ; System Context already running!
|
bcl BO_IF, bitGlobalFlagSystem, SystemCrash ; System Context already running!
|
||||||
|
|
||||||
; Fallthru (new CB in r9, old CB in r6)
|
; Fallthru (new CB in r9, old CB in r6)
|
||||||
|
|
||||||
@ -249,61 +249,61 @@ RunSystemContext
|
|||||||
SwitchContext ; OldCB *r6, NewCB *r9
|
SwitchContext ; OldCB *r6, NewCB *r9
|
||||||
; Run the System or Alternate Context
|
; Run the System or Alternate Context
|
||||||
lwz r8, KDP.Enables(r1)
|
lwz r8, KDP.Enables(r1)
|
||||||
stw r7, CB.Flags(r6)
|
stw r7, CB.InterState.Flags(r6)
|
||||||
stw r8, CB.Enables(r6)
|
stw r8, CB.InterState.Enables(r6)
|
||||||
|
|
||||||
bc BO_IF_NOT, bitFlagLowSaves, @not_low_saves
|
bc BO_IF_NOT, bitContextFlagMemRetryErr, @can_dispose_mr_state
|
||||||
stw r17, CB.LowSave17(r6)
|
stw r17, CB.InterState.MemRet17+4(r6)
|
||||||
stw r20, CB.LowSave20(r6)
|
stw r20, CB.InterState.MemRetData(r6)
|
||||||
stw r21, CB.LowSave21(r6)
|
stw r21, CB.InterState.MemRetData+4(r6)
|
||||||
stw r19, CB.LowSave19(r6)
|
stw r19, CB.InterState.MemRet19+4(r6)
|
||||||
stw r18, CB.LowSave18(r6)
|
stw r18, CB.InterState.MemRet18+4(r6)
|
||||||
lmw r14, KDP.r14(r1)
|
lmw r14, KDP.r14(r1)
|
||||||
@not_low_saves
|
@can_dispose_mr_state
|
||||||
|
|
||||||
mfxer r8
|
mfxer r8
|
||||||
stw r13, CB.CR(r6)
|
stw r13, CB.CR+4(r6)
|
||||||
stw r8, CB.XER(r6)
|
stw r8, CB.XER+4(r6)
|
||||||
stw r12, CB.LR(r6)
|
stw r12, CB.LR+4(r6)
|
||||||
mfctr r8
|
mfctr r8
|
||||||
stw r10, CB.SRR0(r6)
|
stw r10, CB.PC+4(r6)
|
||||||
stw r8, CB.CTR(r6)
|
stw r8, CB.CTR+4(r6)
|
||||||
|
|
||||||
bc BO_IF_NOT, bitFlagHasMQ, @no_mq
|
bc BO_IF_NOT, bitGlobalFlagMQReg, @no_mq
|
||||||
lwz r8, CB.MQ(r9)
|
lwz r8, CB.MQ+4(r9)
|
||||||
mfspr r12, mq
|
mfspr r12, mq
|
||||||
mtspr mq, r8
|
mtspr mq, r8
|
||||||
stw r12, CB.MQ(r6)
|
stw r12, CB.MQ+4(r6)
|
||||||
@no_mq
|
@no_mq
|
||||||
|
|
||||||
lwz r8, KDP.r1(r1)
|
lwz r8, KDP.r1(r1)
|
||||||
stw r0, CB.r0(r6)
|
stw r0, CB.r0+4(r6)
|
||||||
stw r8, 0x010c(r6)
|
stw r8, CB.r1+4(r6)
|
||||||
stw r2, 0x0114(r6)
|
stw r2, CB.r2+4(r6)
|
||||||
stw r3, 0x011c(r6)
|
stw r3, CB.r3+4(r6)
|
||||||
stw r4, 0x0124(r6)
|
stw r4, CB.r4+4(r6)
|
||||||
lwz r8, 0x0018(r1)
|
lwz r8, KDP.r6(r1)
|
||||||
stw r5, 0x012c(r6)
|
stw r5, CB.r5+4(r6)
|
||||||
stw r8, 0x0134(r6)
|
stw r8, CB.r6+4(r6)
|
||||||
_band. r8, r11, bitMsrFP
|
_band. r8, r11, bitMsrFP
|
||||||
stw r14, 0x0174(r6)
|
stw r14, CB.r14+4(r6)
|
||||||
stw r15, 0x017c(r6)
|
stw r15, CB.r15+4(r6)
|
||||||
stw r16, 0x0184(r6)
|
stw r16, CB.r16+4(r6)
|
||||||
stw r17, 0x018c(r6)
|
stw r17, CB.r17+4(r6)
|
||||||
stw r18, 0x0194(r6)
|
stw r18, CB.r18+4(r6)
|
||||||
stw r19, 0x019c(r6)
|
stw r19, CB.r19+4(r6)
|
||||||
stw r20, 0x01a4(r6)
|
stw r20, CB.r20+4(r6)
|
||||||
stw r21, 0x01ac(r6)
|
stw r21, CB.r21+4(r6)
|
||||||
stw r22, 0x01b4(r6)
|
stw r22, CB.r22+4(r6)
|
||||||
stw r23, 0x01bc(r6)
|
stw r23, CB.r23+4(r6)
|
||||||
stw r24, 0x01c4(r6)
|
stw r24, CB.r24+4(r6)
|
||||||
stw r25, 0x01cc(r6)
|
stw r25, CB.r25+4(r6)
|
||||||
stw r26, 0x01d4(r6)
|
stw r26, CB.r26+4(r6)
|
||||||
stw r27, 0x01dc(r6)
|
stw r27, CB.r27+4(r6)
|
||||||
stw r28, 0x01e4(r6)
|
stw r28, CB.r28+4(r6)
|
||||||
stw r29, 0x01ec(r6)
|
stw r29, CB.r29+4(r6)
|
||||||
stw r30, 0x01f4(r6)
|
stw r30, CB.r30+4(r6)
|
||||||
stw r31, 0x01fc(r6)
|
stw r31, CB.r31+4(r6)
|
||||||
bnel DisableFPU
|
bnel DisableFPU
|
||||||
|
|
||||||
lwz r8, KDP.OtherContextDEC(r1)
|
lwz r8, KDP.OtherContextDEC(r1)
|
||||||
@ -313,144 +313,140 @@ SwitchContext ; OldCB *r6, NewCB *r9
|
|||||||
mtdec r8
|
mtdec r8
|
||||||
blel ResetDEC ; to r8
|
blel ResetDEC ; to r8
|
||||||
|
|
||||||
lwz r8, CB.Flags(r9) ; r8 is the new Flags variable
|
lwz r8, CB.InterState.Flags(r9) ; r8 is the new Flags variable
|
||||||
stw r9, KDP.CurCBPtr(r1)
|
stw r9, KDP.ContextPtr(r1)
|
||||||
xoris r7, r7, 1 << (15 - bitFlagEmu) ; flip Emulator flag
|
xoris r7, r7, GlobalFlagSystem >> 16 ; flip Emulator flag
|
||||||
rlwimi r11, r8, 0, 20, 23 ; "enact" MSR[FE0/SE/BE/FE1]
|
rlwimi r11, r8, 0, maskMsrFlags
|
||||||
mr r6, r9 ; change the magic ContextBlock register
|
mr r6, r9 ; change the magic ContextBlock register
|
||||||
rlwimi r7, r8, 0, 0x0000FFFF ; change bottom half of flags only
|
rlwimi r7, r8, 0, maskContextFlags ; change bottom half of flags only
|
||||||
|
|
||||||
andi. r8, r11, MsrFE0 + MsrFE1 ; FP exceptions enabled in new context?
|
andi. r8, r11, MsrFE0 + MsrFE1 ; FP exceptions enabled in new context?
|
||||||
|
|
||||||
lwz r8, CB.Enables(r6)
|
lwz r8, CB.InterState.Enables(r6)
|
||||||
lwz r13, CB.CR(r6)
|
lwz r13, CB.CR+4(r6)
|
||||||
stw r8, KDP.Enables(r1)
|
stw r8, KDP.Enables(r1)
|
||||||
lwz r8, CB.XER(r6)
|
lwz r8, CB.XER+4(r6)
|
||||||
lwz r12, CB.LR(r6)
|
lwz r12, CB.LR+4(r6)
|
||||||
mtxer r8
|
mtxer r8
|
||||||
lwz r8, CB.CTR(r6)
|
lwz r8, CB.CTR+4(r6)
|
||||||
lwz r10, CB.SRR0(r6)
|
lwz r10, CB.PC+4(r6)
|
||||||
mtctr r8
|
mtctr r8
|
||||||
|
|
||||||
bnel ReloadFPU ; FP exceptions enabled, so load FPU
|
bnel ReloadFPU ; FP exceptions enabled, so load FPU
|
||||||
|
|
||||||
stwcx. r0, 0, r1
|
stwcx. r0, 0, r1
|
||||||
|
|
||||||
lwz r8, CB.r1(r6)
|
lwz r8, CB.r1+4(r6)
|
||||||
lwz r0, CB.r0(r6)
|
lwz r0, CB.r0+4(r6)
|
||||||
stw r8, KDP.r1(r1)
|
stw r8, KDP.r1(r1)
|
||||||
lwz r2, 0x0114(r6)
|
lwz r2, CB.r2+4(r6)
|
||||||
lwz r3, 0x011c(r6)
|
lwz r3, CB.r3+4(r6)
|
||||||
lwz r4, 0x0124(r6)
|
lwz r4, CB.r4+4(r6)
|
||||||
lwz r8, 0x0134(r6)
|
lwz r8, CB.r6+4(r6)
|
||||||
lwz r5, 0x012c(r6)
|
lwz r5, CB.r5+4(r6)
|
||||||
stw r8, 0x0018(r1)
|
stw r8, KDP.r6(r1)
|
||||||
lwz r14, 0x0174(r6)
|
lwz r14, CB.r14+4(r6)
|
||||||
lwz r15, 0x017c(r6)
|
lwz r15, CB.r15+4(r6)
|
||||||
lwz r16, 0x0184(r6)
|
lwz r16, CB.r16+4(r6)
|
||||||
lwz r17, 0x018c(r6)
|
lwz r17, CB.r17+4(r6)
|
||||||
lwz r18, 0x0194(r6)
|
lwz r18, CB.r18+4(r6)
|
||||||
lwz r19, 0x019c(r6)
|
lwz r19, CB.r19+4(r6)
|
||||||
lwz r20, 0x01a4(r6)
|
lwz r20, CB.r20+4(r6)
|
||||||
lwz r21, 0x01ac(r6)
|
lwz r21, CB.r21+4(r6)
|
||||||
lwz r22, 0x01b4(r6)
|
lwz r22, CB.r22+4(r6)
|
||||||
lwz r23, 0x01bc(r6)
|
lwz r23, CB.r23+4(r6)
|
||||||
lwz r24, 0x01c4(r6)
|
lwz r24, CB.r24+4(r6)
|
||||||
lwz r25, 0x01cc(r6)
|
lwz r25, CB.r25+4(r6)
|
||||||
lwz r26, 0x01d4(r6)
|
lwz r26, CB.r26+4(r6)
|
||||||
lwz r27, 0x01dc(r6)
|
lwz r27, CB.r27+4(r6)
|
||||||
lwz r28, 0x01e4(r6)
|
lwz r28, CB.r28+4(r6)
|
||||||
lwz r29, 0x01ec(r6)
|
lwz r29, CB.r29+4(r6)
|
||||||
lwz r30, 0x01f4(r6)
|
lwz r30, CB.r30+4(r6)
|
||||||
lwz r31, 0x01fc(r6)
|
lwz r31, CB.r31+4(r6)
|
||||||
|
|
||||||
########################################################################
|
########################################################################
|
||||||
|
|
||||||
IntReturn
|
ReturnFromInt ; If ContextFlagMemRetryErr && ContextFlagResumeMemRetry, please pass KernelState ptr in r9
|
||||||
andi. r8, r7, FlagTrace | FlagLowSaves
|
andi. r8, r7, ContextFlagTraceWhenDone | ContextFlagMemRetryErr
|
||||||
bnel @do_trace
|
bnel @special_cases ; Keep rare cases out of the hot path
|
||||||
|
|
||||||
stw r7, KDP.Flags(r1) ; Save kernel flags for next interrupt
|
stw r7, KDP.Flags(r1) ; Save kernel flags for next interrupt
|
||||||
mtlr r12 ; Restore user SPRs from kernel GPRs
|
mtlr r12 ; Restore user SPRs from kernel GPRs
|
||||||
mtsrr0 r10
|
mtsrr0 r10
|
||||||
mtsrr1 r11
|
mtsrr1 r11
|
||||||
mtcr r13
|
mtcr r13
|
||||||
lwz r10, CB.r10(r6) ; Restore user GPRs from ContextBlock
|
lwz r10, CB.r10+4(r6) ; Restore user GPRs from ContextBlock
|
||||||
lwz r11, CB.r11(r6)
|
lwz r11, CB.r11+4(r6)
|
||||||
lwz r12, CB.r12(r6)
|
lwz r12, CB.r12+4(r6)
|
||||||
lwz r13, CB.r13(r6)
|
lwz r13, CB.r13+4(r6)
|
||||||
lwz r7, CB.r7(r6)
|
lwz r7, CB.r7+4(r6)
|
||||||
lwz r8, CB.r8(r6)
|
lwz r8, CB.r8+4(r6)
|
||||||
lwz r9, CB.r9(r6)
|
lwz r9, CB.r9+4(r6)
|
||||||
lwz r6, KDP.r6(r1) ; Restore last two registers from EWA
|
lwz r6, KDP.r6(r1) ; Restore last two registers from EWA
|
||||||
lwz r1, KDP.r1(r1)
|
lwz r1, KDP.r1(r1)
|
||||||
|
rfi ; Go
|
||||||
|
|
||||||
rfi ; Return from interrupt
|
@special_cases
|
||||||
|
mtcrf crMaskFlags, r7
|
||||||
|
bc BO_IF_NOT, bitContextFlagMemRetryErr, @no_memretry ; If MemRetry had to be paused for an exception
|
||||||
|
_clear r7, r7, bitContextFlagMemRetryErr ; which is now finished, finish MemRetry.
|
||||||
|
bc BO_IF, bitContextFlagResumeMemRetry, @resume_memretry
|
||||||
|
_clear r7, r7, bitContextFlagTraceWhenDone
|
||||||
|
b @justreturn
|
||||||
|
|
||||||
|
@no_memretry
|
||||||
@do_trace
|
bc BO_IF_NOT, bitContextFlagTraceWhenDone, @justreturn ; If this current interrupt was raised when
|
||||||
mtcrf 0x3f, r7
|
_clear r7, r7, bitContextFlagTraceWhenDone ; every instruction should be followed by a
|
||||||
|
stw r7, KDP.Flags(r1) ; Trace exception, then raise one.
|
||||||
bc BO_IF_NOT, bitFlagLowSaves, @no_low_saves
|
|
||||||
|
|
||||||
_bclr r7, r7, bitFlagLowSaves ; LowSaves set with flag 31 -> unset and do some emulation
|
|
||||||
bc BO_IF, bitFlag31, @last_minute_memretry
|
|
||||||
|
|
||||||
_bclr r7, r7, bitFlagTrace ; But if flag 31 is unset, disable tracing and go home
|
|
||||||
b @return
|
|
||||||
|
|
||||||
@no_low_saves
|
|
||||||
bc BO_IF_NOT, bitFlagTrace, @return
|
|
||||||
|
|
||||||
_bclr r7, r7, bitFlagTrace ; Trace flag set with no LowSaves -> unset that flag, and do Trace Exception
|
|
||||||
stw r7, KDP.Flags(r1)
|
|
||||||
li r8, ecInstTrace
|
li r8, ecInstTrace
|
||||||
b Exception
|
b Exception
|
||||||
|
|
||||||
@return
|
@justreturn
|
||||||
blr
|
blr
|
||||||
|
|
||||||
@last_minute_memretry
|
@resume_memretry ; Pick up where an MRException left off, now that the Exception has been disposed.
|
||||||
stw r7, KDP.Flags(r1)
|
stw r7, KDP.Flags(r1)
|
||||||
stw r0, 0x0000(r1)
|
|
||||||
stw r2, 0x0008(r1)
|
stw r0, KDP.r0(r1)
|
||||||
stw r3, 0x000c(r1)
|
stw r2, KDP.r2(r1)
|
||||||
stw r4, 0x0010(r1)
|
stw r3, KDP.r3(r1)
|
||||||
stw r5, 0x0014(r1)
|
stw r4, KDP.r4(r1)
|
||||||
lwz r8, 0x013c(r6)
|
stw r5, KDP.r5(r1)
|
||||||
stw r8, 0x001c(r1)
|
|
||||||
lwz r8, 0x0144(r6)
|
lwz r8, CB.r7+7(r6)
|
||||||
stw r8, 0x0020(r1)
|
stw r8, KDP.r7(r1)
|
||||||
lwz r8, 0x014c(r6)
|
lwz r8, CB.r8+7(r6)
|
||||||
stw r8, 0x0024(r1)
|
stw r8, KDP.r8(r1)
|
||||||
lwz r8, 0x0154(r6)
|
lwz r8, CB.r9+7(r6)
|
||||||
stw r8, 0x0028(r1)
|
stw r8, KDP.r9(r1)
|
||||||
lwz r8, 0x015c(r6)
|
lwz r8, CB.r10+7(r6)
|
||||||
stw r8, 0x002c(r1)
|
stw r8, KDP.r10(r1)
|
||||||
lwz r8, 0x0164(r6)
|
lwz r8, CB.r11+7(r6)
|
||||||
stw r8, 0x0030(r1)
|
stw r8, KDP.r11(r1)
|
||||||
lwz r8, 0x016c(r6)
|
lwz r8, CB.r12+7(r6)
|
||||||
stw r8, 0x0034(r1)
|
stw r8, KDP.r12(r1)
|
||||||
|
lwz r8, CB.r13+7(r6)
|
||||||
|
stw r8, KDP.r13(r1)
|
||||||
|
|
||||||
stmw r14, KDP.r14(r1)
|
stmw r14, KDP.r14(r1)
|
||||||
|
|
||||||
lwz r17, CB.LowSave17(r9) ; LowSave means "MemRetry in ContextBlock"
|
lwz r17, KernelState.MemRet17+4(r9) ; Get the MR state from IntraState (if context was never switched)
|
||||||
lwz r20, CB.LowSave20(r9)
|
lwz r20, KernelState.MemRetData(r9) ; or InterState (if exception was propagated to System Context and
|
||||||
lwz r21, CB.LowSave21(r9)
|
lwz r21, KernelState.MemRetData+4(r9) ; we are now switching back to Alternate Context).
|
||||||
lwz r19, CB.LowSave19(r9)
|
lwz r19, KernelState.MemRet19+4(r9)
|
||||||
lwz r18, CB.LowSave18(r9)
|
lwz r18, KernelState.MemRet18+4(r9)
|
||||||
_bclr r16, r7, bitFlagLowSaves
|
_clear r16, r7, bitContextFlagMemRetryErr
|
||||||
|
|
||||||
lwz r25, KDP.MRBase(r1) ; MRUnknown is indexed by the first arg of MROptab?
|
lwz r25, KDP.MRBase(r1) ; MRUnknown is indexed by the first arg of MROptab?
|
||||||
extrwi. r22, r17, 4, 27 ;
|
extrwi. r22, r17, 4, 27 ;
|
||||||
add r19, r19, r22 ; Correct r19 (EA) by adding byteCount from r17
|
add r19, r19, r22 ; Correct r19 (EA) by adding len from r17
|
||||||
rlwimi r25, r17, 7, 25, 30 ; The top of MRUnknown is... mysterious!
|
rlwimi r25, r17, 7, 25, 30 ; The top of MRUnknown is... mysterious!
|
||||||
lhz r26, MRUnknown-MRBase(r25) ; leaving this incorrect as a reminder!
|
lhz r26, MRUnknown-MRBase(r25) ; leaving this incorrect as a reminder!
|
||||||
|
|
||||||
insrwi r25, r19, 3, 28 ; Set Memtab alignment modulus
|
insrwi r25, r19, 3, 28 ; Set Memtab alignment modulus
|
||||||
stw r16, KDP.Flags(r1)
|
stw r16, KDP.Flags(r1)
|
||||||
rlwimi r26, r26, 8, 8, 15 ; First byte of MRUnknown is for cr3/cr4
|
rlwimi r26, r26, 8, 8, 15 ; First byte of MRUnknown is for cr3/cr4
|
||||||
insrwi r25, r17, 4, 24 ; byteCount and load/store from second arg of MROptab?
|
insrwi r25, r17, 4, 24 ; len and load/store from second arg of MROptab?
|
||||||
mtcrf 0x10, r26 ; Set CR3
|
mtcrf 0x10, r26 ; Set CR3
|
||||||
lha r22, MRMemtab-MRBase(r25) ; Jump to MRMemtab...
|
lha r22, MRMemtab-MRBase(r25) ; Jump to MRMemtab...
|
||||||
|
|
||||||
@ -460,9 +456,9 @@ IntReturn
|
|||||||
mtlr r22
|
mtlr r22
|
||||||
mtsprg 3, r23
|
mtsprg 3, r23
|
||||||
mfmsr r14
|
mfmsr r14
|
||||||
_bset r15, r14, bitMsrDR
|
_set r15, r14, bitMsrDR
|
||||||
mtmsr r15
|
mtmsr r15
|
||||||
rlwimi r25, r26, 2, 22, 29 ; Second byte of MRUnknown is
|
rlwimi r25, r26, 2, 22, 29 ; Second byte of MRUnknown is a secondary routine
|
||||||
bnelr
|
bnelr
|
||||||
b MRDoSecondary
|
b MRDoSecondary
|
||||||
|
|
||||||
|
|||||||
@ -14,12 +14,12 @@ FPUnavailInt
|
|||||||
stw r11, KDP.NKInfo.FPUReloadCount(r1)
|
stw r11, KDP.NKInfo.FPUReloadCount(r1)
|
||||||
|
|
||||||
mfsrr1 r11
|
mfsrr1 r11
|
||||||
_bset r11, r11, bitMsrFP
|
_set r11, r11, bitMsrFP
|
||||||
mtsrr1 r11
|
mtsrr1 r11
|
||||||
|
|
||||||
mfmsr r11 ; need this to access float registers
|
mfmsr r11 ; need this to access float registers
|
||||||
_bset r11, r11, bitMsrFP
|
_set r11, r11, bitMsrFP
|
||||||
lwz r6, KDP.CurCBPtr(r1)
|
lwz r6, KDP.ContextPtr(r1)
|
||||||
mtmsr r11
|
mtmsr r11
|
||||||
|
|
||||||
bl LoadFloats
|
bl LoadFloats
|
||||||
@ -40,53 +40,53 @@ EnableFPU
|
|||||||
bnelr
|
bnelr
|
||||||
|
|
||||||
ReloadFPU
|
ReloadFPU
|
||||||
lwz r8, 0xe4(r6) ; ???
|
lwz r8, CB.FPSCR+4(r6)
|
||||||
rlwinm. r8, r8, 1, 0, 0
|
rlwinm. r8, r8, 1, 0, 0
|
||||||
|
|
||||||
mfmsr r8
|
mfmsr r8
|
||||||
_bset r8, r8, bitMsrFP
|
_set r8, r8, bitMsrFP
|
||||||
beqlr
|
beqlr
|
||||||
mtmsr r8
|
mtmsr r8
|
||||||
|
|
||||||
_bset r11, r11, bitMsrFP
|
_set r11, r11, bitMsrFP
|
||||||
|
|
||||||
########################################################################
|
########################################################################
|
||||||
|
|
||||||
LoadFloats
|
LoadFloats
|
||||||
lfd f31, 0xe0(r6)
|
lfd f31, CB.FPSCR(r6)
|
||||||
lfd f0, 0x200(r6)
|
lfd f0, CB.f0(r6)
|
||||||
lfd f1, 0x208(r6)
|
lfd f1, CB.f1(r6)
|
||||||
lfd f2, 0x210(r6)
|
lfd f2, CB.f2(r6)
|
||||||
lfd f3, 0x218(r6)
|
lfd f3, CB.f3(r6)
|
||||||
lfd f4, 0x220(r6)
|
lfd f4, CB.f4(r6)
|
||||||
lfd f5, 0x228(r6)
|
lfd f5, CB.f5(r6)
|
||||||
lfd f6, 0x230(r6)
|
lfd f6, CB.f6(r6)
|
||||||
lfd f7, 0x238(r6)
|
lfd f7, CB.f7(r6)
|
||||||
mtfsf 0xff, f31
|
mtfs f31
|
||||||
lfd f8, 0x240(r6)
|
lfd f8, CB.f8(r6)
|
||||||
lfd f9, 0x248(r6)
|
lfd f9, CB.f9(r6)
|
||||||
lfd f10, 0x250(r6)
|
lfd f10, CB.f10(r6)
|
||||||
lfd f11, 0x258(r6)
|
lfd f11, CB.f11(r6)
|
||||||
lfd f12, 0x260(r6)
|
lfd f12, CB.f12(r6)
|
||||||
lfd f13, 0x268(r6)
|
lfd f13, CB.f13(r6)
|
||||||
lfd f14, 0x270(r6)
|
lfd f14, CB.f14(r6)
|
||||||
lfd f15, 0x278(r6)
|
lfd f15, CB.f15(r6)
|
||||||
lfd f16, 0x280(r6)
|
lfd f16, CB.f16(r6)
|
||||||
lfd f17, 0x288(r6)
|
lfd f17, CB.f17(r6)
|
||||||
lfd f18, 0x290(r6)
|
lfd f18, CB.f18(r6)
|
||||||
lfd f19, 0x298(r6)
|
lfd f19, CB.f19(r6)
|
||||||
lfd f20, 0x2a0(r6)
|
lfd f20, CB.f20(r6)
|
||||||
lfd f21, 0x2a8(r6)
|
lfd f21, CB.f21(r6)
|
||||||
lfd f22, 0x2b0(r6)
|
lfd f22, CB.f22(r6)
|
||||||
lfd f23, 0x2b8(r6)
|
lfd f23, CB.f23(r6)
|
||||||
lfd f24, 0x2c0(r6)
|
lfd f24, CB.f24(r6)
|
||||||
lfd f25, 0x2c8(r6)
|
lfd f25, CB.f25(r6)
|
||||||
lfd f26, 0x2d0(r6)
|
lfd f26, CB.f26(r6)
|
||||||
lfd f27, 0x2d8(r6)
|
lfd f27, CB.f27(r6)
|
||||||
lfd f28, 0x2e0(r6)
|
lfd f28, CB.f28(r6)
|
||||||
lfd f29, 0x2e8(r6)
|
lfd f29, CB.f29(r6)
|
||||||
lfd f30, 0x2f0(r6)
|
lfd f30, CB.f30(r6)
|
||||||
lfd f31, 0x2f8(r6)
|
lfd f31, CB.f31(r6)
|
||||||
|
|
||||||
blr
|
blr
|
||||||
|
|
||||||
@ -94,45 +94,45 @@ LoadFloats
|
|||||||
|
|
||||||
DisableFPU
|
DisableFPU
|
||||||
mfmsr r8
|
mfmsr r8
|
||||||
_bset r8, r8, bitMsrFP
|
_set r8, r8, bitMsrFP
|
||||||
mtmsr r8
|
mtmsr r8
|
||||||
|
|
||||||
_bclr r11, r11, bitMsrFP
|
_clear r11, r11, bitMsrFP
|
||||||
|
|
||||||
stfd f0, 0x200(r6)
|
stfd f0, CB.f0(r6)
|
||||||
stfd f1, 0x208(r6)
|
stfd f1, CB.f1(r6)
|
||||||
stfd f2, 0x210(r6)
|
stfd f2, CB.f2(r6)
|
||||||
stfd f3, 0x218(r6)
|
stfd f3, CB.f3(r6)
|
||||||
stfd f4, 0x220(r6)
|
stfd f4, CB.f4(r6)
|
||||||
stfd f5, 0x228(r6)
|
stfd f5, CB.f5(r6)
|
||||||
stfd f6, 0x230(r6)
|
stfd f6, CB.f6(r6)
|
||||||
stfd f7, 0x238(r6)
|
stfd f7, CB.f7(r6)
|
||||||
stfd f8, 0x240(r6)
|
stfd f8, CB.f8(r6)
|
||||||
stfd f9, 0x248(r6)
|
stfd f9, CB.f9(r6)
|
||||||
stfd f10, 0x250(r6)
|
stfd f10, CB.f10(r6)
|
||||||
stfd f11, 0x258(r6)
|
stfd f11, CB.f11(r6)
|
||||||
stfd f12, 0x260(r6)
|
stfd f12, CB.f12(r6)
|
||||||
stfd f13, 0x268(r6)
|
stfd f13, CB.f13(r6)
|
||||||
stfd f14, 0x270(r6)
|
stfd f14, CB.f14(r6)
|
||||||
stfd f15, 0x278(r6)
|
stfd f15, CB.f15(r6)
|
||||||
stfd f16, 0x280(r6)
|
stfd f16, CB.f16(r6)
|
||||||
stfd f17, 0x288(r6)
|
stfd f17, CB.f17(r6)
|
||||||
stfd f18, 0x290(r6)
|
stfd f18, CB.f18(r6)
|
||||||
stfd f19, 0x298(r6)
|
stfd f19, CB.f19(r6)
|
||||||
stfd f20, 0x2a0(r6)
|
stfd f20, CB.f20(r6)
|
||||||
stfd f21, 0x2a8(r6)
|
stfd f21, CB.f21(r6)
|
||||||
stfd f22, 0x2b0(r6)
|
stfd f22, CB.f22(r6)
|
||||||
stfd f23, 0x2b8(r6)
|
stfd f23, CB.f23(r6)
|
||||||
mffs f0
|
mffs f0
|
||||||
stfd f24, 0x2c0(r6)
|
stfd f24, CB.f24(r6)
|
||||||
stfd f25, 0x2c8(r6)
|
stfd f25, CB.f25(r6)
|
||||||
stfd f26, 0x2d0(r6)
|
stfd f26, CB.f26(r6)
|
||||||
stfd f27, 0x2d8(r6)
|
stfd f27, CB.f27(r6)
|
||||||
stfd f28, 0x2e0(r6)
|
stfd f28, CB.f28(r6)
|
||||||
stfd f29, 0x2e8(r6)
|
stfd f29, CB.f29(r6)
|
||||||
stfd f30, 0x2f0(r6)
|
stfd f30, CB.f30(r6)
|
||||||
stfd f31, 0x2f8(r6)
|
stfd f31, CB.f31(r6)
|
||||||
stfd f0, 0xe0(r6)
|
stfd f0, CB.FPSCR(r6)
|
||||||
|
|
||||||
blr
|
blr
|
||||||
|
|
||||||
|
|||||||
@ -181,7 +181,7 @@ InitKernelGlobals
|
|||||||
|
|
||||||
add r12, rED, r11
|
add r12, rED, r11
|
||||||
stw r12, KDP.ECBPtr(r1)
|
stw r12, KDP.ECBPtr(r1)
|
||||||
stw r12, KDP.CurCBPtr(r1)
|
stw r12, KDP.ContextPtr(r1)
|
||||||
|
|
||||||
lwz r12, NKConfigurationInfo.TestIntMaskInit(rCI)
|
lwz r12, NKConfigurationInfo.TestIntMaskInit(rCI)
|
||||||
stw r12, KDP.TestIntMaskInit(r1)
|
stw r12, KDP.TestIntMaskInit(r1)
|
||||||
@ -362,16 +362,16 @@ InitEmulator
|
|||||||
add r12, r11, r12
|
add r12, r11, r12
|
||||||
lwz r11, NKConfigurationInfo.ECBOffset(rCI) ; address of declared Emu entry point
|
lwz r11, NKConfigurationInfo.ECBOffset(rCI) ; address of declared Emu entry point
|
||||||
add r11, r11, rED
|
add r11, r11, rED
|
||||||
stw r12, CB.ExceptionOriginAddr(r11)
|
stw r12, CB.FaultSrcPC+4(r11)
|
||||||
|
|
||||||
lwz r12, NKConfigurationInfo.LA_EmulatorData(rCI) ; address of Emu global page
|
lwz r12, NKConfigurationInfo.LA_EmulatorData(rCI) ; address of Emu global page
|
||||||
stw r12, CB.ExceptionOriginR3(r11)
|
stw r12, CB.FaultSrcR3+4(r11)
|
||||||
|
|
||||||
lwz r12, NKConfigurationInfo.LA_DispatchTable(rCI) ; address of 512kb Emu dispatch table
|
lwz r12, NKConfigurationInfo.LA_DispatchTable(rCI) ; address of 512kb Emu dispatch table
|
||||||
stw r12, CB.ExceptionOriginR4(r11)
|
stw r12, CB.FaultSrcR4+4(r11)
|
||||||
|
|
||||||
lwz r12, KDP.EmuKCallTblPtrLogical(r1) ; address of KCallReturnFromException trap
|
lwz r12, KDP.EmuKCallTblPtrLogical(r1) ; address of KCallReturnFromException trap
|
||||||
stw r12, CB.ExceptionHandlerRetAddr(r11)
|
stw r12, CB.IntraState.HandlerReturn+4(r11)
|
||||||
|
|
||||||
|
|
||||||
lwz r10, KDP.LowMemPtr(r1) ; Zero out bottom 8k of Low Memory
|
lwz r10, KDP.LowMemPtr(r1) ; Zero out bottom 8k of Low Memory
|
||||||
@ -398,9 +398,9 @@ InitEmulator
|
|||||||
mfpvr r7 ; Calculate Flags:
|
mfpvr r7 ; Calculate Flags:
|
||||||
srwi r7, r7, 16
|
srwi r7, r7, 16
|
||||||
cmpwi r7, 1
|
cmpwi r7, 1
|
||||||
lis r7, FlagEmu >> 16 ; we will enter System Context (all CPUs)
|
lis r7, GlobalFlagSystem >> 16 ; we will enter System Context (all CPUs)
|
||||||
bne @not_601
|
bne @not_601
|
||||||
_bset r7, r7, bitFlagHasMQ ; but only 601 has MQ register
|
_set r7, r7, bitGlobalFlagMQReg ; but only 601 has MQ register
|
||||||
@not_601
|
@not_601
|
||||||
stw r7, KDP.Flags(r1)
|
stw r7, KDP.Flags(r1)
|
||||||
|
|
||||||
|
|||||||
@ -14,7 +14,7 @@ ExternalInt0
|
|||||||
|
|
||||||
mfmsr r2 ; Save a self-ptr to FF880000... why?
|
mfmsr r2 ; Save a self-ptr to FF880000... why?
|
||||||
lis r3, 0xFF88
|
lis r3, 0xFF88
|
||||||
_bset r0, r2, bitMsrDR
|
_set r0, r2, bitMsrDR
|
||||||
stw r4, KDP.r4(r1)
|
stw r4, KDP.r4(r1)
|
||||||
stw r5, KDP.r5(r1)
|
stw r5, KDP.r5(r1)
|
||||||
mfsrr0 r4
|
mfsrr0 r4
|
||||||
@ -81,7 +81,7 @@ ExternalInt1
|
|||||||
|
|
||||||
lis r2, 0x50F3 ; Query OpenPIC at 50F2A000
|
lis r2, 0x50F3 ; Query OpenPIC at 50F2A000
|
||||||
mfmsr r3
|
mfmsr r3
|
||||||
_bset r0, r3, bitMsrDR
|
_set r0, r3, bitMsrDR
|
||||||
stw r4, KDP.r4(r1)
|
stw r4, KDP.r4(r1)
|
||||||
stw r5, KDP.r5(r1)
|
stw r5, KDP.r5(r1)
|
||||||
mfsrr0 r4
|
mfsrr0 r4
|
||||||
@ -139,7 +139,7 @@ ExternalInt2
|
|||||||
|
|
||||||
lis r2, 0xF300 ; Query OpenPIC at F3000028/C
|
lis r2, 0xF300 ; Query OpenPIC at F3000028/C
|
||||||
mfmsr r0
|
mfmsr r0
|
||||||
_bset r3, r0, bitMsrDR
|
_set r3, r0, bitMsrDR
|
||||||
stw r4, KDP.r4(r1)
|
stw r4, KDP.r4(r1)
|
||||||
stw r5, KDP.r5(r1)
|
stw r5, KDP.r5(r1)
|
||||||
mfsrr0 r4
|
mfsrr0 r4
|
||||||
@ -275,7 +275,7 @@ DataStorageInt
|
|||||||
mfcr r13
|
mfcr r13
|
||||||
|
|
||||||
mfmsr r14
|
mfmsr r14
|
||||||
_bset r15, r14, bitMsrDR
|
_set r15, r14, bitMsrDR
|
||||||
mtmsr r15
|
mtmsr r15
|
||||||
lwz r27, 0(r10) ; r27 = INSTRUCTION
|
lwz r27, 0(r10) ; r27 = INSTRUCTION
|
||||||
mtmsr r14
|
mtmsr r14
|
||||||
@ -291,7 +291,7 @@ EmulateDataAccess
|
|||||||
lwz r16, KDP.Flags(r1)
|
lwz r16, KDP.Flags(r1)
|
||||||
mfsprg r24, 3
|
mfsprg r24, 3
|
||||||
rlwinm r17, r27, 0, 6, 15 ; r17 = rS/D and rA fields
|
rlwinm r17, r27, 0, 6, 15 ; r17 = rS/D and rA fields
|
||||||
rlwimi r16, r16, 27, 26, 26
|
rlwimi r16, r16, 27, 26, 26 ; ContextFlagTraceWhenDone = MsrSE
|
||||||
bge @xform
|
bge @xform
|
||||||
|
|
||||||
;dform
|
;dform
|
||||||
@ -351,7 +351,7 @@ AlignmentInt
|
|||||||
rlwinm r17, r27, 16, 0x03FF0000
|
rlwinm r17, r27, 16, 0x03FF0000
|
||||||
lwz r16, KDP.Flags(r1)
|
lwz r16, KDP.Flags(r1)
|
||||||
rlwimi r25, r27, 24, 23, 29 ; add constant fields from dsisr (*4) to FDP
|
rlwimi r25, r27, 24, 23, 29 ; add constant fields from dsisr (*4) to FDP
|
||||||
rlwimi r16, r16, 27, 26, 26 ; copy FlagSE to FlagTrace
|
rlwimi r16, r16, 27, 26, 26 ; ContextFlagTraceWhenDone = MsrSE
|
||||||
bne @X_form
|
bne @X_form
|
||||||
|
|
||||||
; D- or DS-form (immediate-indexed) instruction
|
; D- or DS-form (immediate-indexed) instruction
|
||||||
@ -359,7 +359,7 @@ AlignmentInt
|
|||||||
mfmsr r14
|
mfmsr r14
|
||||||
rlwimi r25, r26, 26, 22, 29 ; third byte of lookup value is a /4 code offset in FDP
|
rlwimi r25, r26, 26, 22, 29 ; third byte of lookup value is a /4 code offset in FDP
|
||||||
mtlr r25 ; so get ready to go there
|
mtlr r25 ; so get ready to go there
|
||||||
_bset r15, r14, bitMsrDR
|
_set r15, r14, bitMsrDR
|
||||||
mtcr r26
|
mtcr r26
|
||||||
rlwimi r17, r26, 6, 26, 5 ; wrap some shite around the register values
|
rlwimi r17, r26, 6, 26, 5 ; wrap some shite around the register values
|
||||||
blr
|
blr
|
||||||
@ -370,7 +370,7 @@ AlignmentInt
|
|||||||
mfmsr r14
|
mfmsr r14
|
||||||
rlwimi r25, r26, 26, 22, 29
|
rlwimi r25, r26, 26, 22, 29
|
||||||
mtlr r25
|
mtlr r25
|
||||||
_bset r15, r14, bitMsrDR
|
_set r15, r14, bitMsrDR
|
||||||
mtcr r26
|
mtcr r26
|
||||||
rlwimi r17, r26, 6, 26, 5
|
rlwimi r17, r26, 6, 26, 5
|
||||||
bclr BO_IF_NOT, mrOpflag1
|
bclr BO_IF_NOT, mrOpflag1
|
||||||
@ -398,7 +398,7 @@ InstStorageInt
|
|||||||
|
|
||||||
mfsprg r24, 3
|
mfsprg r24, 3
|
||||||
mfmsr r14
|
mfmsr r14
|
||||||
_bset r15, r14, bitMsrDR
|
_set r15, r14, bitMsrDR
|
||||||
addi r23, r1, KDP.VecTblMemRetry
|
addi r23, r1, KDP.VecTblMemRetry
|
||||||
mtsprg 3, r23
|
mtsprg 3, r23
|
||||||
mr r19, r10
|
mr r19, r10
|
||||||
@ -408,7 +408,7 @@ InstStorageInt
|
|||||||
mtmsr r14
|
mtmsr r14
|
||||||
mtsprg 3, r24
|
mtsprg 3, r24
|
||||||
lmw r14, KDP.r14(r1)
|
lmw r14, KDP.r14(r1)
|
||||||
b IntReturn
|
b ReturnFromInt
|
||||||
|
|
||||||
@not_in_htab
|
@not_in_htab
|
||||||
lmw r14, KDP.r14(r1)
|
lmw r14, KDP.r14(r1)
|
||||||
|
|||||||
@ -1,7 +1,7 @@
|
|||||||
; AUTO-GENERATED SYMBOL LIST
|
; AUTO-GENERATED SYMBOL LIST
|
||||||
; IMPORTS:
|
; IMPORTS:
|
||||||
; NKExceptions
|
; NKExceptions
|
||||||
; IntReturn
|
; ReturnFromInt
|
||||||
; NKPaging
|
; NKPaging
|
||||||
; PutPTE
|
; PutPTE
|
||||||
; EXPORTS:
|
; EXPORTS:
|
||||||
@ -114,8 +114,8 @@ VMReturn ; OUTSIDE REFERER
|
|||||||
lwz r15, KDP.r15(r1)
|
lwz r15, KDP.r15(r1)
|
||||||
lwz r16, KDP.r16(r1)
|
lwz r16, KDP.r16(r1)
|
||||||
lwz r7, KDP.Flags(r1)
|
lwz r7, KDP.Flags(r1)
|
||||||
lwz r6, KDP.CurCBPtr(r1)
|
lwz r6, KDP.ContextPtr(r1)
|
||||||
b IntReturn
|
b ReturnFromInt
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
@ -176,7 +176,7 @@ HalfLoadedReg set (®)
|
|||||||
ENDM
|
ENDM
|
||||||
|
|
||||||
MACRO
|
MACRO
|
||||||
_bset &dest, &src, &bit
|
_set &dest, &src, &bit
|
||||||
|
|
||||||
IF &bit < 16
|
IF &bit < 16
|
||||||
oris&dot &dest, &src, 1 << (15 - (&bit))
|
oris&dot &dest, &src, 1 << (15 - (&bit))
|
||||||
@ -187,19 +187,19 @@ HalfLoadedReg set (®)
|
|||||||
ENDM
|
ENDM
|
||||||
|
|
||||||
MACRO
|
MACRO
|
||||||
_bclr &dest, &src, &bit
|
_clear &dest, &src, &bit
|
||||||
|
|
||||||
_bclr_rbit set &bit+1
|
_clear_rbit set &bit+1
|
||||||
if _bclr_rbit > 31
|
if _clear_rbit > 31
|
||||||
_bclr_rbit set 0
|
_clear_rbit set 0
|
||||||
endif
|
endif
|
||||||
|
|
||||||
_bclr_lbit set &bit-1
|
_clear_lbit set &bit-1
|
||||||
if _bclr_lbit < 0
|
if _clear_lbit < 0
|
||||||
_bclr_lbit set 31
|
_clear_lbit set 31
|
||||||
endif
|
endif
|
||||||
|
|
||||||
rlwinm&dot &dest, &src, 0, _bclr_rbit, _bclr_lbit
|
rlwinm&dot &dest, &src, 0, _clear_rbit, _clear_lbit
|
||||||
|
|
||||||
ENDM
|
ENDM
|
||||||
|
|
||||||
|
|||||||
@ -14,7 +14,7 @@
|
|||||||
|
|
||||||
; LOOP until SECONDARY ROUTINE calls, or is, an exit routine
|
; LOOP until SECONDARY ROUTINE calls, or is, an exit routine
|
||||||
; MRPriDone accepts:
|
; MRPriDone accepts:
|
||||||
; r17 = pretend inst: 0-5 from optab || 6-10 rS/rD || 11-15 rA || 21-27 ?? || 28-30 byteCount-1 || 31 isLoad (NB: what about bottom 6 bits??)
|
; r17 = pretend inst: 0-5 from optab || 6-10 rS/rD || 11-15 rA || 21-26 ?? || 27-30 accessLen || 31 isLoad (NB: what about bottom 6 bits??)
|
||||||
; r19 = address first byte *after* the string to be accessed
|
; r19 = address first byte *after* the string to be accessed
|
||||||
; r25 = dirty MRBase ptr
|
; r25 = dirty MRBase ptr
|
||||||
; r26 = the original OpTab entry
|
; r26 = the original OpTab entry
|
||||||
@ -32,7 +32,7 @@
|
|||||||
; r20/r21 = right-justified data (stores only)
|
; r20/r21 = right-justified data (stores only)
|
||||||
|
|
||||||
; MemAccess routine sets:
|
; MemAccess routine sets:
|
||||||
; r17 = same but with byteCount field decremented
|
; r17 = same but with len field decremented
|
||||||
; r20/r21 = right-justified data (loads only)
|
; r20/r21 = right-justified data (loads only)
|
||||||
; r26 = scratch
|
; r26 = scratch
|
||||||
|
|
||||||
@ -47,6 +47,19 @@
|
|||||||
|
|
||||||
; EXIT ROUTINE
|
; EXIT ROUTINE
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
; registers in broad terms:
|
||||||
|
; r16 Flags (why not r7?)
|
||||||
|
;*r17 Status
|
||||||
|
;*r18 effective address
|
||||||
|
;*r19 end address
|
||||||
|
;*r20/r21 data
|
||||||
|
; r25 MemRetry pointer (often dirty)
|
||||||
|
; r26 OpTab entry
|
||||||
|
; r27 instruction
|
||||||
|
|
||||||
|
|
||||||
_align 10
|
_align 10
|
||||||
MRBase
|
MRBase
|
||||||
INCLUDE 'MROptabCode.s' ; c00:1154
|
INCLUDE 'MROptabCode.s' ; c00:1154
|
||||||
@ -54,6 +67,84 @@ MRBase
|
|||||||
INCLUDE 'MRInterrupts.s' ; 13f4:14f4
|
INCLUDE 'MRInterrupts.s' ; 13f4:14f4
|
||||||
INCLUDE 'MROptab.s' ; 14f4:16f4
|
INCLUDE 'MROptab.s' ; 14f4:16f4
|
||||||
INCLUDE 'MRMemtab.s' ; 16f4:17f4
|
INCLUDE 'MRMemtab.s' ; 16f4:17f4
|
||||||
; INCLUDE 'MRUnknown.s' ; 17f4:1874
|
; INCLUDE 'MRUnknown.s' ; 17f4:1874
|
||||||
MRUnknown
|
MRUnknown
|
||||||
dcb.b 128, 0
|
dcb.b 128, 0
|
||||||
|
|
||||||
|
END
|
||||||
|
|
||||||
|
; There is definitely some structure here -- but what does it mean?? Crack the bastard...
|
||||||
|
|
||||||
|
; metatabLine %0001, MRSecLoad ; 0
|
||||||
|
; metatabLine %0001, MRSecLoad ; 1
|
||||||
|
; metatabLine %0001, MRSecLoad ; 2
|
||||||
|
; metatabLine %0001, MRSecLoad ; 3
|
||||||
|
|
||||||
|
metatabLine %0001, MRSecException ; 4
|
||||||
|
; metatabLine %0001, MRSecLoadExt ; 5
|
||||||
|
; metatabLine %0001, MRSecLoad ; 6
|
||||||
|
metatabLine %0001, MRSecException ; 7
|
||||||
|
metatabLine %0001, MRSecException ; 8
|
||||||
|
; metatabLine %0011, MRSecLHBRX ; 9
|
||||||
|
; metatabLine %0011, MRSecLWBRX ; 10
|
||||||
|
metatabLine %0001, MRSecException ; 11
|
||||||
|
metatabLine %0001, MRSecException ; 12
|
||||||
|
metatabLine %0001, MRSecException ; 13
|
||||||
|
; metatabLine %0001, MRSecLFSu ; 14
|
||||||
|
; metatabLine %0001, MRSecLFDu ; 15
|
||||||
|
|
||||||
|
; metatabLine %0001, MRSecDone ; 16
|
||||||
|
; metatabLine %0001, MRSecDone ; 17
|
||||||
|
; metatabLine %0001, MRSecDone ; 18
|
||||||
|
; metatabLine %0001, MRSecDone ; 19
|
||||||
|
|
||||||
|
; metatabLine %0001, MRSecLWARX ; 20 ; MRSecLoad
|
||||||
|
; metatabLine %0001, MRSecException ; 21
|
||||||
|
; metatabLine %0001, MRSecSTWCX ; 22 ; MRSecDone
|
||||||
|
; metatabLine %0001, MRSecException ; 23
|
||||||
|
|
||||||
|
metatabLine %0001, MRSecException ; 24
|
||||||
|
metatabLine %0001, MRSecException ; 25
|
||||||
|
; metatabLine %0011, MRSecLMW ; 26
|
||||||
|
; metatabLine %0011, MRSecException ; 27
|
||||||
|
metatabLine %0001, MRSecException ; 28
|
||||||
|
metatabLine %0001, MRSecException ; 29
|
||||||
|
; metatabLine %0011, MRSecSTMW ; 30
|
||||||
|
; metatabLine %0011, MRSecException ; 31
|
||||||
|
|
||||||
|
|
||||||
|
; metatabLine %0011, MRSecLSWix ; 32
|
||||||
|
metatabLine %0011, MRSecLSWix ; 33
|
||||||
|
metatabLine %0011, MRSecLSWix ; 34
|
||||||
|
metatabLine %0011, MRSecLSWix ; 35
|
||||||
|
|
||||||
|
; metatabLine %0011, MRSecStrStore ; 36
|
||||||
|
metatabLine %0011, MRSecStrStore ; 37
|
||||||
|
metatabLine %0011, MRSecStrStore ; 38
|
||||||
|
metatabLine %0011, MRSecStrStore ; 39
|
||||||
|
|
||||||
|
; metatabLine %0011, MRSecLSCBX ; 40
|
||||||
|
metatabLine %0011, MRSecLSCBX ; 41
|
||||||
|
metatabLine %0011, MRSecLSCBX ; 42
|
||||||
|
metatabLine %0011, MRSecLSCBX ; 43
|
||||||
|
metatabLine %0011, MRSecLSCBX ; 44
|
||||||
|
metatabLine %0011, MRSecLSCBX ; 45
|
||||||
|
metatabLine %0011, MRSecLSCBX ; 46
|
||||||
|
metatabLine %0011, MRSecLSCBX ; 47
|
||||||
|
|
||||||
|
; metatabLine %0011, MRSecDCBZ ; 48
|
||||||
|
metatabLine %0001, MRSecException ; 49
|
||||||
|
metatabLine %0001, MRSecException ; 50
|
||||||
|
metatabLine %0001, MRSecException ; 51
|
||||||
|
metatabLine %0001, MRSecException ; 52 ; MRSecDone
|
||||||
|
metatabLine %0001, MRSecException ; 53 ; FDP_0370
|
||||||
|
metatabLine %0001, MRSecException ; 54 ; FDP_0384
|
||||||
|
metatabLine %0001, MRSecException ; 55 ; FDP_0398
|
||||||
|
metatabLine %0001, MRSecException ; 56 ; MRSecDone
|
||||||
|
metatabLine %0001, MRSecException ; 57 ; MRSecDone
|
||||||
|
metatabLine %0001, MRSecException ; 58 ; MRSecDone
|
||||||
|
metatabLine %0001, MRSecException ; 59 ; MRSecDone
|
||||||
|
metatabLine %0001, MRSecException ; 60
|
||||||
|
metatabLine %0001, MRSecException ; 61
|
||||||
|
; metatabLine %0011, MRSecRedoNoTrace ; 62
|
||||||
|
; metatabLine %0001, MRSecException2 ; 63
|
||||||
|
|||||||
@ -213,7 +213,7 @@ PutPTE ; EA r27 // PTE r30/r31, EQ=Success, GT=Invalid, LT=Fault
|
|||||||
cmpwi cr7, r28, 0
|
cmpwi cr7, r28, 0
|
||||||
clrrwi r28, r31, 12
|
clrrwi r28, r31, 12
|
||||||
cmpw r28, r1
|
cmpw r28, r1
|
||||||
lwz r30, KDP.CurCBPtr(r1)
|
lwz r30, KDP.ContextPtr(r1)
|
||||||
|
|
||||||
beq cr7, @rethink_pte_search
|
beq cr7, @rethink_pte_search
|
||||||
addi r31, r30, 768-1
|
addi r31, r30, 768-1
|
||||||
|
|||||||
@ -259,7 +259,7 @@ CopyBATRangeInit
|
|||||||
lwzu r21, 4(r9) ; grab LBAT
|
lwzu r21, 4(r9) ; grab LBAT
|
||||||
stwu r20, 4(r8) ; store UBAT
|
stwu r20, 4(r8) ; store UBAT
|
||||||
|
|
||||||
_bclr r23, r21, 22 ; if LBAT[22] (reserved) is set:
|
_clear r23, r21, 22 ; if LBAT[22] (reserved) is set:
|
||||||
cmpw r21, r23
|
cmpw r21, r23
|
||||||
beq @bitnotset
|
beq @bitnotset
|
||||||
add r21, r23, rCI ; then LBAT[BRPN] is relative to ConfigInfo struct
|
add r21, r23, rCI ; then LBAT[BRPN] is relative to ConfigInfo struct
|
||||||
|
|||||||
@ -4,7 +4,7 @@
|
|||||||
|
|
||||||
IllegalInstruction
|
IllegalInstruction
|
||||||
mfmsr r9
|
mfmsr r9
|
||||||
_bset r8, r9, bitMsrDR
|
_set r8, r9, bitMsrDR
|
||||||
mtmsr r8
|
mtmsr r8
|
||||||
lwz r8, 0(r10)
|
lwz r8, 0(r10)
|
||||||
mtmsr r9
|
mtmsr r9
|
||||||
@ -14,19 +14,19 @@ IllegalInstruction
|
|||||||
stw r3, KDP.r3(r1)
|
stw r3, KDP.r3(r1)
|
||||||
stw r4, KDP.r4(r1)
|
stw r4, KDP.r4(r1)
|
||||||
stw r5, KDP.r5(r1)
|
stw r5, KDP.r5(r1)
|
||||||
lwz r9, CB.r7(r6)
|
lwz r9, CB.r7+4(r6)
|
||||||
stw r9, KDP.r7(r1)
|
stw r9, KDP.r7(r1)
|
||||||
lwz r9, CB.r8(r6)
|
lwz r9, CB.r8+4(r6)
|
||||||
stw r9, KDP.r8(r1)
|
stw r9, KDP.r8(r1)
|
||||||
lwz r9, CB.r9(r6)
|
lwz r9, CB.r9+4(r6)
|
||||||
stw r9, KDP.r9(r1)
|
stw r9, KDP.r9(r1)
|
||||||
lwz r9, CB.r10(r6)
|
lwz r9, CB.r10+4(r6)
|
||||||
stw r9, KDP.r10(r1)
|
stw r9, KDP.r10(r1)
|
||||||
lwz r9, CB.r11(r6)
|
lwz r9, CB.r11+4(r6)
|
||||||
stw r9, KDP.r11(r1)
|
stw r9, KDP.r11(r1)
|
||||||
lwz r9, CB.r12(r6)
|
lwz r9, CB.r12+4(r6)
|
||||||
stw r9, KDP.r12(r1)
|
stw r9, KDP.r12(r1)
|
||||||
lwz r9, CB.r13(r6)
|
lwz r9, CB.r13+4(r6)
|
||||||
stw r9, KDP.r13(r1)
|
stw r9, KDP.r13(r1)
|
||||||
stmw r14, KDP.r14(r1)
|
stmw r14, KDP.r14(r1)
|
||||||
|
|
||||||
@ -69,15 +69,15 @@ IllegalInstruction
|
|||||||
addze r20, r20
|
addze r20, r20
|
||||||
mtxer r23
|
mtxer r23
|
||||||
lwz r23, KDP.NKInfo.EmulatedUnimpInstCount(r1)
|
lwz r23, KDP.NKInfo.EmulatedUnimpInstCount(r1)
|
||||||
rlwimi r7, r7, 27, 26, 26
|
rlwimi r7, r7, 27, 26, 26 ; ContextFlagTraceWhenDone = MsrSE
|
||||||
addi r23, r23, 1
|
addi r23, r23, 1
|
||||||
stw r23, KDP.NKInfo.EmulatedUnimpInstCount(r1)
|
stw r23, KDP.NKInfo.EmulatedUnimpInstCount(r1)
|
||||||
|
|
||||||
stwx r21, r1, r28 ; save register into EWA
|
stwx r21, r1, r28 ; save register into EWA
|
||||||
mr r16, r7
|
mr r16, r7
|
||||||
beq cr7, MRSecDone ; TBL
|
beq cr7, MRSecDone ; TBL
|
||||||
stwx r20, r1, r28
|
stwx r20, r1, r28
|
||||||
b MRSecDone ; TBU
|
b MRSecDone ; TBU
|
||||||
|
|
||||||
|
|
||||||
@STFIWX
|
@STFIWX
|
||||||
@ -86,7 +86,7 @@ IllegalInstruction
|
|||||||
addi r23, r23, 1
|
addi r23, r23, 1
|
||||||
stw r23, KDP.NKInfo.EmulatedUnimpInstCount(r1)
|
stw r23, KDP.NKInfo.EmulatedUnimpInstCount(r1)
|
||||||
mfmsr r14
|
mfmsr r14
|
||||||
_bset r15, r14, bitMsrDR
|
_set r15, r14, bitMsrDR
|
||||||
b EmulateDataAccess
|
b EmulateDataAccess
|
||||||
|
|
||||||
########################################################################
|
########################################################################
|
||||||
@ -103,7 +103,7 @@ KCallRunAlternateContext
|
|||||||
lwz r9, KDP.NCBCacheLA0(r1)
|
lwz r9, KDP.NCBCacheLA0(r1)
|
||||||
rlwinm r8, r3, 0, 0, 25
|
rlwinm r8, r3, 0, 0, 25
|
||||||
cmpw cr1, r8, r9
|
cmpw cr1, r8, r9
|
||||||
bne IntReturn
|
bne ReturnFromInt
|
||||||
lwz r9, KDP.NCBCachePA0(r1)
|
lwz r9, KDP.NCBCachePA0(r1)
|
||||||
bne cr1, @search_cache
|
bne cr1, @search_cache
|
||||||
|
|
||||||
@ -114,11 +114,11 @@ KCallRunAlternateContext
|
|||||||
mtsprg 3, r8
|
mtsprg 3, r8
|
||||||
|
|
||||||
lwz r8, KDP.EmuKCallTblPtrLogical(r1)
|
lwz r8, KDP.EmuKCallTblPtrLogical(r1)
|
||||||
mtcrf 0x3f, r7
|
mtcrf crMaskFlags, r7
|
||||||
clrlwi r7, r7, 8
|
clrlwi r7, r7, 8
|
||||||
stw r8, CB.ExceptionHandlerRetAddr(r9)
|
stw r8, CB.IntraState.HandlerReturn+4(r9)
|
||||||
|
|
||||||
stw r9, KDP.CurCBPtr(r1)
|
stw r9, KDP.ContextPtr(r1)
|
||||||
|
|
||||||
b SwitchContext ; OldCB *r6, NewCB *r9
|
b SwitchContext ; OldCB *r6, NewCB *r9
|
||||||
|
|
||||||
@ -252,9 +252,9 @@ KCallResetSystem
|
|||||||
|
|
||||||
; Gary Davidian skeleton key: r5/D0 = MSR bits to unset, r7/D2 = MSR bits to set
|
; Gary Davidian skeleton key: r5/D0 = MSR bits to unset, r7/D2 = MSR bits to set
|
||||||
andc r11, r11, r5
|
andc r11, r11, r5
|
||||||
lwz r8, CB.r7(r6)
|
lwz r8, CB.r7+4(r6)
|
||||||
or r11, r11, r8
|
or r11, r11, r8
|
||||||
b IntReturn
|
b ReturnFromInt
|
||||||
|
|
||||||
Reset
|
Reset
|
||||||
include 'NKReset.s'
|
include 'NKReset.s'
|
||||||
@ -272,18 +272,18 @@ KCallPrioritizeInterrupts
|
|||||||
mtsrr0 r10
|
mtsrr0 r10
|
||||||
mtsrr1 r11
|
mtsrr1 r11
|
||||||
mtcr r13
|
mtcr r13
|
||||||
lwz r10, CB.r10(r6)
|
lwz r10, CB.r10+4(r6)
|
||||||
lwz r11, CB.r11(r6)
|
lwz r11, CB.r11+4(r6)
|
||||||
lwz r12, CB.r12(r6)
|
lwz r12, CB.r12+4(r6)
|
||||||
lwz r13, CB.r13(r6)
|
lwz r13, CB.r13+4(r6)
|
||||||
lwz r7, CB.r7(r6)
|
lwz r7, CB.r7+4(r6)
|
||||||
lwz r8, KDP.r1(r1)
|
lwz r8, KDP.r1(r1)
|
||||||
mfsprg r9, 3
|
mfsprg r9, 3
|
||||||
lwz r9, VecTbl.External(r9)
|
lwz r9, VecTbl.External(r9)
|
||||||
mtsprg 1, r8
|
mtsprg 1, r8
|
||||||
mtlr r9
|
mtlr r9
|
||||||
lwz r8, CB.r8(r6)
|
lwz r8, CB.r8+4(r6)
|
||||||
lwz r9, CB.r9(r6)
|
lwz r9, CB.r9+4(r6)
|
||||||
lwz r6, KDP.r6(r1)
|
lwz r6, KDP.r6(r1)
|
||||||
blrl ; (could this ever fall though to KCallSystemCrash?)
|
blrl ; (could this ever fall though to KCallSystemCrash?)
|
||||||
|
|
||||||
@ -296,22 +296,22 @@ KCallSystemCrash
|
|||||||
stw r4, KDP.r4(r1)
|
stw r4, KDP.r4(r1)
|
||||||
stw r5, KDP.r5(r1)
|
stw r5, KDP.r5(r1)
|
||||||
|
|
||||||
lwz r8, CB.r7(r6)
|
lwz r8, CB.r7+4(r6)
|
||||||
lwz r9, CB.r8(r6)
|
lwz r9, CB.r8+4(r6)
|
||||||
stw r8, KDP.r7(r1)
|
stw r8, KDP.r7(r1)
|
||||||
stw r9, KDP.r8(r1)
|
stw r9, KDP.r8(r1)
|
||||||
|
|
||||||
lwz r8, CB.r9(r6)
|
lwz r8, CB.r9+4(r6)
|
||||||
lwz r9, CB.r10(r6)
|
lwz r9, CB.r10+4(r6)
|
||||||
stw r8, KDP.r9(r1)
|
stw r8, KDP.r9(r1)
|
||||||
stw r9, KDP.r10(r1)
|
stw r9, KDP.r10(r1)
|
||||||
|
|
||||||
lwz r8, CB.r11(r6)
|
lwz r8, CB.r11+4(r6)
|
||||||
lwz r9, CB.r12(r6)
|
lwz r9, CB.r12+4(r6)
|
||||||
stw r8, KDP.r11(r1)
|
stw r8, KDP.r11(r1)
|
||||||
stw r9, KDP.r12(r1)
|
stw r9, KDP.r12(r1)
|
||||||
|
|
||||||
lwz r8, CB.r13(r6)
|
lwz r8, CB.r13+4(r6)
|
||||||
stw r8, KDP.r13(r1)
|
stw r8, KDP.r13(r1)
|
||||||
|
|
||||||
stmw r14, KDP.r14(r1)
|
stmw r14, KDP.r14(r1)
|
||||||
@ -329,14 +329,14 @@ ProgramInt
|
|||||||
stw r6, KDP.r6(r1)
|
stw r6, KDP.r6(r1)
|
||||||
mfsprg r6, 1
|
mfsprg r6, 1
|
||||||
stw r6, KDP.r1(r1)
|
stw r6, KDP.r1(r1)
|
||||||
lwz r6, KDP.CurCBPtr(r1)
|
lwz r6, KDP.ContextPtr(r1)
|
||||||
stw r7, CB.r7(r6)
|
stw r7, CB.r7+4(r6)
|
||||||
stw r8, CB.r8(r6)
|
stw r8, CB.r8+4(r6)
|
||||||
stw r9, CB.r9(r6)
|
stw r9, CB.r9+4(r6)
|
||||||
stw r10, CB.r10(r6)
|
stw r10, CB.r10+4(r6)
|
||||||
stw r11, CB.r11(r6)
|
stw r11, CB.r11+4(r6)
|
||||||
stw r12, CB.r12(r6)
|
stw r12, CB.r12+4(r6)
|
||||||
stw r13, CB.r13(r6)
|
stw r13, CB.r13+4(r6)
|
||||||
|
|
||||||
; Compare SRR0 with address of Emulator's KCall trap table
|
; Compare SRR0 with address of Emulator's KCall trap table
|
||||||
lwz r8, KDP.EmuKCallTblPtrLogical(r1)
|
lwz r8, KDP.EmuKCallTblPtrLogical(r1)
|
||||||
@ -346,7 +346,7 @@ ProgramInt
|
|||||||
lwz r7, KDP.Flags(r1)
|
lwz r7, KDP.Flags(r1)
|
||||||
mfsprg r12, 2
|
mfsprg r12, 2
|
||||||
beq KCallReturnFromExceptionFastPath ; KCall in Emulator table => fast path
|
beq KCallReturnFromExceptionFastPath ; KCall in Emulator table => fast path
|
||||||
rlwimi. r7, r7, bitFlagEmu, 0, 0
|
rlwimi. r7, r7, bitGlobalFlagSystem, 0, 0
|
||||||
cmplwi cr7, r8, 16 * 4
|
cmplwi cr7, r8, 16 * 4
|
||||||
bge cr0, @fromAltContext ; Alt Context cannot make KCalls; this might be an External Int
|
bge cr0, @fromAltContext ; Alt Context cannot make KCalls; this might be an External Int
|
||||||
bge cr7, @notFromEmulatorTrapTable ; from Emulator but not from its KCall table => do more checks
|
bge cr7, @notFromEmulatorTrapTable ; from Emulator but not from its KCall table => do more checks
|
||||||
@ -370,7 +370,7 @@ ProgramInt
|
|||||||
bc BO_IF_NOT, 14, @notTrap
|
bc BO_IF_NOT, 14, @notTrap
|
||||||
|
|
||||||
mfmsr r9 ; fetch the instruction to get the "trap number"
|
mfmsr r9 ; fetch the instruction to get the "trap number"
|
||||||
_bset r8, r9, bitMsrDR
|
_set r8, r9, bitMsrDR
|
||||||
mtmsr r8
|
mtmsr r8
|
||||||
lwz r8, 0(r10)
|
lwz r8, 0(r10)
|
||||||
mtmsr r9
|
mtmsr r9
|
||||||
@ -431,7 +431,7 @@ SyscallInt
|
|||||||
########################################################################
|
########################################################################
|
||||||
|
|
||||||
_alignToCacheBlock
|
_alignToCacheBlock
|
||||||
TraceInt
|
TraceInt ; here because of MSR[SE/BE], possibly thanks to ContextFlagTraceWhenDone
|
||||||
bl LoadInterruptRegisters
|
bl LoadInterruptRegisters
|
||||||
li r8, ecInstTrace
|
li r8, ecInstTrace
|
||||||
b Exception
|
b Exception
|
||||||
|
|||||||
@ -201,7 +201,7 @@ CodeBase ds.l 1 ; 64c
|
|||||||
MRBase ds.l 1 ; 650
|
MRBase ds.l 1 ; 650
|
||||||
ECBPtrLogical ds.l 1 ; 654 ; Emulator/System ContextBlock
|
ECBPtrLogical ds.l 1 ; 654 ; Emulator/System ContextBlock
|
||||||
ECBPtr ds.l 1 ; 658
|
ECBPtr ds.l 1 ; 658
|
||||||
CurCBPtr ds.l 1 ; 65c ; moved to EWA (per-CPU) in NKv2
|
ContextPtr ds.l 1 ; 65c ; moved to EWA (per-CPU) in NKv2
|
||||||
Flags ds.l 1 ; 660 ; moved to EWA (per-CPU) in NKv2
|
Flags ds.l 1 ; 660 ; moved to EWA (per-CPU) in NKv2
|
||||||
Enables ds.l 1 ; 664 ; moved to EWA (per-CPU) in NKv2
|
Enables ds.l 1 ; 664 ; moved to EWA (per-CPU) in NKv2
|
||||||
OtherContextDEC ds.l 1 ; 668 ; ticks that the *inactive* context has left out of 1s
|
OtherContextDEC ds.l 1 ; 668 ; ticks that the *inactive* context has left out of 1s
|
||||||
@ -342,136 +342,108 @@ InfoRecBlk ds.b 64 ; fc0:1000 ; Access using ptr equates in InfoRecords
|
|||||||
|
|
||||||
########################################################################
|
########################################################################
|
||||||
|
|
||||||
CB RECORD 0,INCR ; ContextBlock (Emulator/System or Native/Alternate)
|
KernelState RECORD 0,INCR
|
||||||
Flags ds.l 1 ; 000
|
Flags ds.l 1 ; 00
|
||||||
Enables ds.l 1 ; 004
|
Enables ds.l 1 ; 04
|
||||||
ds.l 1 ; 008
|
|
||||||
ds.l 1 ; 00c
|
|
||||||
ds.l 1 ; 010
|
|
||||||
ds.l 1 ; 014
|
|
||||||
ds.l 1 ; 018
|
|
||||||
ds.l 1 ; 01c
|
|
||||||
ds.l 1 ; 020
|
|
||||||
LowSave17 ds.l 1 ; 024
|
|
||||||
LowSave20 ds.l 1 ; 028
|
|
||||||
LowSave21 ds.l 1 ; 02c
|
|
||||||
ds.l 1 ; 030
|
|
||||||
LowSave19 ds.l 1 ; 034
|
|
||||||
ds.l 1 ; 038
|
|
||||||
LowSave18 ds.l 1 ; 03c
|
|
||||||
|
|
||||||
ExceptionOriginFlags ds.l 1 ; 040 ; from before exception
|
Handler ds.d 1 ; 08
|
||||||
ExceptionOriginEnables ds.l 1 ; 044 ; from before exception
|
HandlerArg ds.d 1 ; 10
|
||||||
ds.l 1 ; 048
|
HandlerReturn ds.d 1 ; 18
|
||||||
ExceptionHandler ds.l 1 ; 04c
|
|
||||||
ds.l 1 ; 050
|
|
||||||
ExceptionHandlerR4 ds.l 1 ; 054
|
|
||||||
ds.l 1 ; 058
|
|
||||||
ExceptionHandlerRetAddr ds.l 1 ; 05c
|
|
||||||
ds.l 1 ; 060
|
|
||||||
PropagateR17 ds.l 1 ; 064
|
|
||||||
PropagateR20 ds.l 1 ; 068
|
|
||||||
PropagateR21 ds.l 1 ; 06c
|
|
||||||
ds.l 1 ; 070
|
|
||||||
PropagateR19 ds.l 1 ; 074
|
|
||||||
ds.l 1 ; 078
|
|
||||||
PropagateR18 ds.l 1 ; 07c
|
|
||||||
|
|
||||||
ds.l 1 ; 080
|
MemRet17 ds.d 1 ; 20 ; MemRetry state
|
||||||
ExceptionOriginAddr ds.l 1 ; 084
|
MemRetData ds.d 1 ; 28
|
||||||
ds.l 1 ; 088
|
MemRet19 ds.d 1 ; 30
|
||||||
ExceptionOriginLR ds.l 1 ; 08c
|
MemRet18 ds.d 1 ; 38
|
||||||
ds.l 1 ; 090
|
ENDR
|
||||||
ExceptionOriginR3 ds.l 1 ; 094
|
|
||||||
ds.l 1 ; 098
|
########################################################################
|
||||||
ExceptionOriginR4 ds.l 1 ; 09c
|
|
||||||
ds.l 1 ; 0a0
|
CB RECORD 0,INCR ; ContextBlock (Emulator/System or Native/Alternate)
|
||||||
MSR ds.l 1 ; 0a4
|
|
||||||
ds.l 1 ; 0a8
|
InterState ds KernelState ; 000:040 ; for switching between contexts
|
||||||
ds.l 1 ; 0ac
|
IntraState ds KernelState ; 040:080 ; for raising/disposing exceptions within a context
|
||||||
ds.l 1 ; 0b0
|
|
||||||
ds.l 1 ; 0b4
|
FaultSrcPC ds.d 1 ; 080 ; saved when starting an exception handler
|
||||||
ds.l 1 ; 0b8
|
FaultSrcLR ds.d 1 ; 088
|
||||||
ds.l 1 ; 0bc
|
FaultSrcR3 ds.d 1 ; 090
|
||||||
ds.l 1 ; 0c0
|
FaultSrcR4 ds.d 1 ; 098
|
||||||
MQ ds.l 1 ; 0c4 ; 601 only
|
|
||||||
ds.l 1 ; 0c8
|
MSR ds.d 1 ; 0a0
|
||||||
ds.l 1 ; 0cc
|
ds.d 1 ; 0a8
|
||||||
ds.l 1 ; 0d0
|
ds.d 1 ; 0b0
|
||||||
XER ds.l 1 ; 0d4
|
ds.d 1 ; 0b8
|
||||||
ds.l 1 ; 0d8
|
MQ ds.d 1 ; 0c0 ; 601 only
|
||||||
CR ds.l 1 ; 0dc
|
ds.d 1 ; 0c8
|
||||||
ds.l 1 ; 0e0
|
XER ds.d 1 ; 0d0
|
||||||
ds.l 1 ; 0e4
|
CR ds.d 1 ; 0d8
|
||||||
ds.l 1 ; 0e8
|
FPSCR ds.d 1 ; 0e0 ; unsure, mffs/mtfs?
|
||||||
LR ds.l 1 ; 0ec
|
LR ds.d 1 ; 0e8
|
||||||
ds.l 1 ; 0f0
|
CTR ds.d 1 ; 0f0
|
||||||
CTR ds.l 1 ; 0f4
|
PC ds.d 1 ; 0f8
|
||||||
ds.l 1 ; 0f8
|
|
||||||
SRR0 ds.l 1 ; 0fc
|
r0 ds.d 1 ; 100 ; big-endian, so 32-bit value stored in second word
|
||||||
ds.l 1
|
r1 ds.d 1 ; 108
|
||||||
r0 ds.l 1 ; 104
|
r2 ds.d 1 ; 110
|
||||||
ds.l 1
|
r3 ds.d 1 ; 118
|
||||||
r1 ds.l 1 ; 10c
|
r4 ds.d 1 ; 120
|
||||||
ds.l 1
|
r5 ds.d 1 ; 128
|
||||||
r2 ds.l 1 ; 114
|
r6 ds.d 1 ; 130
|
||||||
ds.l 1
|
r7 ds.d 1 ; 138
|
||||||
r3 ds.l 1 ; 11c
|
r8 ds.d 1 ; 140
|
||||||
ds.l 1
|
r9 ds.d 1 ; 148
|
||||||
r4 ds.l 1 ; 124
|
r10 ds.d 1 ; 150
|
||||||
ds.l 1
|
r11 ds.d 1 ; 158
|
||||||
r5 ds.l 1 ; 12c
|
r12 ds.d 1 ; 160
|
||||||
ds.l 1
|
r13 ds.d 1 ; 168
|
||||||
r6 ds.l 1 ; 134
|
r14 ds.d 1 ; 170
|
||||||
ds.l 1
|
r15 ds.d 1 ; 178
|
||||||
r7 ds.l 1 ; 13c
|
r16 ds.d 1 ; 180
|
||||||
ds.l 1
|
r17 ds.d 1 ; 188
|
||||||
r8 ds.l 1 ; 144
|
r18 ds.d 1 ; 190
|
||||||
ds.l 1
|
r19 ds.d 1 ; 198
|
||||||
r9 ds.l 1 ; 14c
|
r20 ds.d 1 ; 1a0
|
||||||
ds.l 1
|
r21 ds.d 1 ; 1a8
|
||||||
r10 ds.l 1 ; 154
|
r22 ds.d 1 ; 1b0
|
||||||
ds.l 1
|
r23 ds.d 1 ; 1b8
|
||||||
r11 ds.l 1 ; 15c
|
r24 ds.d 1 ; 1c0
|
||||||
ds.l 1
|
r25 ds.d 1 ; 1c8
|
||||||
r12 ds.l 1 ; 164
|
r26 ds.d 1 ; 1d0
|
||||||
ds.l 1
|
r27 ds.d 1 ; 1d8
|
||||||
r13 ds.l 1 ; 16c
|
r28 ds.d 1 ; 1e0
|
||||||
ds.l 1
|
r29 ds.d 1 ; 1e8
|
||||||
r14 ds.l 1 ; 174
|
r30 ds.d 1 ; 1f0
|
||||||
ds.l 1
|
r31 ds.d 1 ; 1f8
|
||||||
r15 ds.l 1 ; 17c
|
|
||||||
ds.l 1
|
f0 ds.d 1 ; 200
|
||||||
r16 ds.l 1 ; 184
|
f1 ds.d 1 ; 208
|
||||||
ds.l 1
|
f2 ds.d 1 ; 210
|
||||||
r17 ds.l 1 ; 18c
|
f3 ds.d 1 ; 218
|
||||||
ds.l 1
|
f4 ds.d 1 ; 220
|
||||||
r18 ds.l 1 ; 194
|
f5 ds.d 1 ; 228
|
||||||
ds.l 1
|
f6 ds.d 1 ; 230
|
||||||
r19 ds.l 1 ; 19c
|
f7 ds.d 1 ; 238
|
||||||
ds.l 1
|
f8 ds.d 1 ; 240
|
||||||
r20 ds.l 1 ; 1a4
|
f9 ds.d 1 ; 248
|
||||||
ds.l 1
|
f10 ds.d 1 ; 250
|
||||||
r21 ds.l 1 ; 1ac
|
f11 ds.d 1 ; 258
|
||||||
ds.l 1
|
f12 ds.d 1 ; 260
|
||||||
r22 ds.l 1 ; 1b4
|
f13 ds.d 1 ; 268
|
||||||
ds.l 1
|
f14 ds.d 1 ; 270
|
||||||
r23 ds.l 1 ; 1bc
|
f15 ds.d 1 ; 278
|
||||||
ds.l 1
|
f16 ds.d 1 ; 280
|
||||||
r24 ds.l 1 ; 1c4
|
f17 ds.d 1 ; 288
|
||||||
ds.l 1
|
f18 ds.d 1 ; 290
|
||||||
r25 ds.l 1 ; 1cc
|
f19 ds.d 1 ; 298
|
||||||
ds.l 1
|
f20 ds.d 1 ; 2a0
|
||||||
r26 ds.l 1 ; 1d4
|
f21 ds.d 1 ; 2a8
|
||||||
ds.l 1
|
f22 ds.d 1 ; 2b0
|
||||||
r27 ds.l 1 ; 1dc
|
f23 ds.d 1 ; 2b8
|
||||||
ds.l 1
|
f24 ds.d 1 ; 2c0
|
||||||
r28 ds.l 1 ; 1e4
|
f25 ds.d 1 ; 2c8
|
||||||
ds.l 1
|
f26 ds.d 1 ; 2d0
|
||||||
r29 ds.l 1 ; 1ec
|
f27 ds.d 1 ; 2d8
|
||||||
ds.l 1
|
f28 ds.d 1 ; 2e0
|
||||||
r30 ds.l 1 ; 1f4
|
f29 ds.d 1 ; 2e8
|
||||||
ds.l 1
|
f30 ds.d 1 ; 2f0
|
||||||
r31 ds.l 1 ; 1fc
|
f31 ds.d 1 ; 2f8
|
||||||
FloatRegisters ds.d 32 ; 200:300
|
|
||||||
ENDR
|
ENDR
|
||||||
|
|||||||
@ -86,7 +86,7 @@ SystemCrash
|
|||||||
stw r0, KDP.CrashSR15(r1)
|
stw r0, KDP.CrashSR15(r1)
|
||||||
|
|
||||||
mfmsr r0
|
mfmsr r0
|
||||||
_bset r0, r0, bitMsrFP
|
_set r0, r0, bitMsrFP
|
||||||
mtmsr r0
|
mtmsr r0
|
||||||
stfd f0, KDP.CrashF0(r1)
|
stfd f0, KDP.CrashF0(r1)
|
||||||
stfd f1, KDP.CrashF1(r1)
|
stfd f1, KDP.CrashF1(r1)
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user