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intelligent structures

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Elliot Nunn 2018-07-09 16:13:00 +08:00
parent 87797ccff0
commit 4d3f6fe0b2
23 changed files with 115 additions and 212 deletions
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99
Internal/InfoRecords.a
View File

@ -171,46 +171,8 @@ Bank16Start ds.l 1 ; 0b0, irp+e70 ; Starting address of RAM bank 16
Bank16Size ds.l 1 ; 0b4, irp+e74 ; Number of bytes in RAM bank 16 Bank16Size ds.l 1 ; 0b4, irp+e74 ; Number of bytes in RAM bank 16
Bank17Start ds.l 1 ; 0b8, irp+e78 ; Starting address of RAM bank 17 Bank17Start ds.l 1 ; 0b8, irp+e78 ; Starting address of RAM bank 17
Bank17Size ds.l 1 ; 0bc, irp+e7c ; Number of bytes in RAM bank 17 Bank17Size ds.l 1 ; 0bc, irp+e7c ; Number of bytes in RAM bank 17
Bank18Start ds.l 1 ; 0c0, irp+e80 ; Starting address of RAM bank 18
Bank18Size ds.l 1 ; 0c4, irp+e84 ; Number of bytes in RAM bank 18
Bank19Start ds.l 1 ; 0c8, irp+e88 ; Starting address of RAM bank 19
Bank19Size ds.l 1 ; 0cc, irp+e8c ; Number of bytes in RAM bank 19
Bank20Start ds.l 1 ; 0d0, irp+e90 ; Starting address of RAM bank 20
Bank20Size ds.l 1 ; 0d4, irp+e94 ; Number of bytes in RAM bank 20
Bank21Start ds.l 1 ; 0d8, irp+e98 ; Starting address of RAM bank 21
Bank21Size ds.l 1 ; 0dc, irp+e9c ; Number of bytes in RAM bank 21
Bank22Start ds.l 1 ; 0e0, irp+ea0 ; Starting address of RAM bank 22
Bank22Size ds.l 1 ; 0e4, irp+ea4 ; Number of bytes in RAM bank 22
Bank23Start ds.l 1 ; 0e8, irp+ea8 ; Starting address of RAM bank 23
Bank23Size ds.l 1 ; 0ec, irp+eac ; Number of bytes in RAM bank 23
Bank24Start ds.l 1 ; 0f0, irp+eb0 ; Starting address of RAM bank 24
Bank24Size ds.l 1 ; 0f4, irp+eb4 ; Number of bytes in RAM bank 24
Bank25Start ds.l 1 ; 0f8, irp+eb8 ; Starting address of RAM bank 25
Bank25Size ds.l 1 ; 0fc, irp+ebc ; Number of bytes in RAM bank 25
EndOfBanks EndOfBanks
MaxBanks equ 16 ; Pads out to old struct len (cache block), more to come... MaxBanks equ 16 ; Pads out to old struct len (cache block), more to come...
; Interrupt Support Data
IntCntrBaseAddr ds.l 1 ; 100, irp+ec0 ; Interrupt Controller Base Address (variable is used since this is a PCI Dev and address is relocatable)
IntPendingReg ds.l 2 ; 104, irp+ec4 ; Data of current interrupts pending register
; These fields were added to report information about tightly-coupled L2 caches.
; The inline L2 information should be used in situations where there is a CPU
; card L2 cache that can coexist with a motherboard L2.
InlineL2DSize ds.l 1 ; 10c, irp+ecc ; Size of in-line L2 Dcache
InlineL2ISize ds.l 1 ; 110, irp+ed0 ; Size of in-line L2 Icache
InlineL2Combined ds.w 1 ; 114, irp+ed4 ; 1 <- combined or no cache, 0 <- split cache
InlineL2IBlockSize ds.w 1 ; 116, irp+ed6 ; Block size of in-line I L2 cache
InlineL2DBlockSize ds.w 1 ; 118, irp+ed8 ; Block size of in-line D L2 cache
InlineL2IAssoc ds.w 1 ; 11a, irp+eda ; Associativity of L2 I
InlineL2DAssoc ds.w 1 ; 11c, irp+edc ; Associativity of L2 D
ds.w 1 ; 11e, irp+ede ; pad
; More Interrupt Support Data
IntsCompleted ds.l 2 ; 120, irp+ee0 ; completed interrupts
align 5 ; pad to nice cache block alignment
endr endr
@ -301,37 +263,6 @@ ExceptionPropagateCount ds.l 1 ; 0e8, kdp+ea8 ; count of Exceptions propagated
ExceptionForcedCount ds.l 1 ; 0ec, kdp+eac ; count of Exceptions forced to system ExceptionForcedCount ds.l 1 ; 0ec, kdp+eac ; count of Exceptions forced to system
SysContextCpuTime ds.l 2 ; 0f0, kdp+eb0 ; CPU Time used by System Context SysContextCpuTime ds.l 2 ; 0f0, kdp+eb0 ; CPU Time used by System Context
AltContextCpuTime ds.l 2 ; 0f8, kdp+eb4 ; CPU Time used by Alternate Context AltContextCpuTime ds.l 2 ; 0f8, kdp+eb4 ; CPU Time used by Alternate Context
; This stuff is new (starts at 0x100)
blueProcessID ds.l 1 ; 100, kdp+ec0 ; ID of the blue process.
blueTaskID ds.l 1 ; 104, kdp+ec4 ; ID of the blue task.
pageQueueID ds.l 1 ; 108, kdp+ec8 ; ID of the page fault queue.
TaskCount ds.l 1 ; 10c, kdp+ecc ; Number of tasks.
FreePoolExtendCount ds.l 1 ; 110, kdp+ed0 ; Number of pages given to the nanokernel.
;rsrv1 ds.l 3 ; 114, kdp+ed4 ; reserved???
; My additions
org 0x11c
ConfigFlags ds.l 1 ; 11c, kdp+edc ; includes ScreenConsole ... TODO put flag equs here
NanodbgrFlagShift equ 1
NanodbgrFlagBit equ 31 - NanodbgrFlagShift
LogFlagShift equ 3
LogFlagBit equ 31 - LogFlagShift
; bit 31 always set on replacement, bit 27 set on replacement with ROM 2.7f3 or later
AlertCount ds.l 1 ; 120, kdp+ee0 ; interprocessor alerts
SchEvalCount ds.l 1 ; 124, kdp+ee4
VMDispatchCountTblPtr ds.l 1 ; 128, kdp+ee8
ds.l 1
ds.l 1
MPDispatchCountTblPtr ds.l 1 ; 134, kdp+ef4 ; ???????
AddrSpcSetCtr ds.l 1 ; 138, kdp+ef8 ; incremented by SchSwitchSpace
IDCtr ds.l 1 ; 13c, kdp+efc
org 0x160
endr endr
@ -372,35 +303,7 @@ DataCacheAssociativity ds.w 1 ; 02e, kdp+f4e ; Associativity of the Data Cache
TransCacheTotalSize ds.w 1 ; 030, kdp+f50 ; number of entries in the Translation Cache TransCacheTotalSize ds.w 1 ; 030, kdp+f50 ; number of entries in the Translation Cache
TransCacheAssociativity ds.w 1 ; 032, kdp+f52 ; Associativity of the Translation Cache TransCacheAssociativity ds.w 1 ; 032, kdp+f52 ; Associativity of the Translation Cache
OvrEnd OvrEnd
org 0x40
; These fields were added to report information about back-side L2 caches
ProcessorL2DSize ds.l 1 ; 034, kdp+f54 ; Size of back-side L2 Dcache
ProcessorL2ISize ds.l 1 ; 038, kdp+f58 ; Size of back-side L2 Icache
ProcessorL2Combined ds.w 1 ; 03c, kdp+f5c ; 1 <- combined or no cache, 0 <- split cache
ProcessorL2IBlockSize ds.w 1 ; 03e, kdp+f5e ; Block size of back-side I L2 cache
ProcessorL2DBlockSize ds.w 1 ; 040, kdp+f60 ; Block size of back-side D L2 cache
ProcessorL2IAssoc ds.w 1 ; 042, kdp+f62 ; Associativity of L2 I
ProcessorL2DAssoc ds.w 1 ; 044, kdp+f64 ; Associativity of L2 D
filler1 ds.w 1 ; 046, kdp+f66 ; align to long
; ProcessorFlags - Definitions for the processor flags field. These are bit positions,
; as in 1 << hasVMX, and not masks.
hasL2CR equ 0
hasPLRUL1 equ 1
hasTAU equ 2
hasVMX equ 3
hasMSSregs equ 4
hasExtraBATs equ 5
ProcessorFlags ds.l 1 ; 048, kdp+f68 ; flags to specify processor features
align 5 ; pad to nice cache block alignment
org 0x05e
SetToZero ds.w 1 ; 05e, kdp+f7e ; by same code that sets below
ClockRates ds.b 16*4 ; 060:0a0, kdp:f80:fc0 ; 16b blks of cpu/bus/dec/?? speeds (Hz)
endr endr

8
Internal/NKPublic.a
View File

@ -704,10 +704,10 @@ ZeroWord ds.l 1 ; 910 ; Only NewWorld and Unknown PIHes touch this
ds.l 1 ; 918 ds.l 1 ; 918
ds.l 1 ; 91c ds.l 1 ; 91c
ds.b 0x3a0 ; 920:cc0 ds.b 0x3a0 ; 920:cc0
SystemInfo ds.b 192 ; cc0:d80 SysInfo ds NKSystemInfo ; cc0:d80
DiagnosticInfo ds.b 256 ; d80:e80 DiagInfo ds NKDiagInfo ; d80:e80
NanoKernelInfo ds.b 256 ; e80:f80 ; see NKNanoKernelInfo in PPCInfoRecordsPriv NKInfo ds NKNanoKernelInfo; e80:f80 ; see NKNanoKernelInfo in PPCInfoRecordsPriv
ProcessorInfo ds.b 64 ; f80:fc0 ProcInfo ds NKProcessorInfo ; f80:fc0
InfoRecord ds.b 64 ; fc0:1000 ; was main copy in NKv1, now vestigial? InfoRecord ds.b 64 ; fc0:1000 ; was main copy in NKv1, now vestigial?
endr endr

6
NanoKernel/NKAddressSpaces.s
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@ -288,7 +288,7 @@ CreateAreasFromPageMap
add r15, r15, r26 ; add a page, I think add r15, r15, r26 ; add a page, I think
slwi r16, r16, 12 slwi r16, r16, 12
lwz r8, KDP.NanoKernelInfo + NKNanoKernelInfo.blueProcessID(r1) lwz r8, KDP.NKInfo.blueProcessID(r1)
stw r8, Area.ProcessID(r31) stw r8, Area.ProcessID(r31)
lwz r8, EWA.PA_CurAddressSpace(r1) lwz r8, EWA.PA_CurAddressSpace(r1)
@ -526,7 +526,7 @@ MPGetPageSize
cmpwi r3, 1 cmpwi r3, 1
bne ReturnParamErrFromMPCall bne ReturnParamErrFromMPCall
lwz r3, KDP.ProcessorInfo + NKProcessorInfo.PageSize(r1) lwz r3, KDP.ProcInfo.PageSize(r1)
b CommonMPCallReturnPath b CommonMPCallReturnPath
@ -4646,7 +4646,7 @@ DeletePTE ; PTE *r18, PLE *r30
_InvalNCBPointerCache scratch=r16 _InvalNCBPointerCache scratch=r16
foo set KDP.NanoKernelInfo + NKNanoKernelInfo.HashTableDeleteCount foo set KDP.NKInfo.HashTableDeleteCount
lwz r16, foo(r1) lwz r16, foo(r1)
_bclr r14, r14, Area.kPLEFlagIsInHTAB _bclr r14, r14, Area.kPLEFlagIsInHTAB
addi r16, r16, 1 addi r16, r16, 1

10
NanoKernel/NKBuiltinInit.s
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@ -422,13 +422,13 @@ InitBuiltin
; If CI.Debug >= 257 && CI.DebugFlags & 2 ... ; If CI.Debug >= 257 && CI.DebugFlags & 2 ...
cmplwi r8, NKConfigurationInfo.DebugThreshold cmplwi r8, NKConfigurationInfo.DebugThreshold
lwz r8, KDP.NanoKernelInfo + NKNanoKernelInfo.ConfigFlags(r1) lwz r8, KDP.NKInfo.ConfigFlags(r1)
if &TYPE('NKShowLog') = 'UNDEFINED' if &TYPE('NKShowLog') = 'UNDEFINED'
blt @no_screen_log blt @no_screen_log
lwz r8, NKConfigurationInfo.DebugFlags(r9) lwz r8, NKConfigurationInfo.DebugFlags(r9)
rlwinm. r8, r8, 0, NKConfigurationInfo.LogFlagBit, NKConfigurationInfo.LogFlagBit rlwinm. r8, r8, 0, NKConfigurationInfo.LogFlagBit, NKConfigurationInfo.LogFlagBit
lwz r8, KDP.NanoKernelInfo + NKNanoKernelInfo.ConfigFlags(r1) lwz r8, KDP.NKInfo.ConfigFlags(r1)
beq @no_screen_log beq @no_screen_log
endif endif
@ -439,7 +439,7 @@ InitBuiltin
; Switch on two other flags ; Switch on two other flags
ori r8, r8, 1<< 0 ; not sure ori r8, r8, 1<< 0 ; not sure
ori r8, r8, 1<< 4 ; to do with interrupts ori r8, r8, 1<< 4 ; to do with interrupts
stw r8, KDP.NanoKernelInfo + NKNanoKernelInfo.ConfigFlags(r1) stw r8, KDP.NKInfo.ConfigFlags(r1)
@ -800,10 +800,10 @@ InitBuiltin
; ProcessorInfoTable.s ; ProcessorInfoTable.s
mfpvr r12 mfpvr r12
stw r12, KDP.ProcessorInfo + NKProcessorInfo.ProcessorVersionReg(r1) stw r12, KDP.ProcInfo.ProcessorVersionReg(r1)
srwi r12, r12, 16 srwi r12, r12, 16
lwz r11, KDP.PA_NanoKernelCode(r1) lwz r11, KDP.PA_NanoKernelCode(r1)
addi r10, r1, KDP.ProcessorInfo + NKProcessorInfo.Ovr addi r10, r1, KDP.ProcInfo.Ovr
li r9, NKProcessorInfo.OvrEnd - NKProcessorInfo.Ovr li r9, NKProcessorInfo.OvrEnd - NKProcessorInfo.Ovr
; check for several (some unknown) pre-7410 CPUs, and load their info ; check for several (some unknown) pre-7410 CPUs, and load their info

20
NanoKernel/NKCache.s
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@ -63,7 +63,7 @@ kcCacheDispatch
cmplwi r8, 2 cmplwi r8, 2
bgt @fail_bad_selector bgt @fail_bad_selector
lwz r8, KDP.ProcessorInfo + NKProcessorInfo.ProcessorFlags(r1) lwz r8, KDP.ProcInfo.ProcessorFlags(r1)
andi. r8, r8, 1 << NKProcessorInfo.hasL2CR andi. r8, r8, 1 << NKProcessorInfo.hasL2CR
beq CacheCallFailNoL2 ; no L2CR => fail (what about 601?) beq CacheCallFailNoL2 ; no L2CR => fail (what about 601?)
@ -186,7 +186,7 @@ CacheCallL2EnableSelected
andis. r21, r21, 0x8000 andis. r21, r21, 0x8000
bne CacheCallReturn bne CacheCallReturn
lwz r8, KDP.ProcessorInfo + NKProcessorInfo.ProcessorL2DSize(r1) lwz r8, KDP.ProcInfo.ProcessorL2DSize(r1)
and. r8, r8, r8 and. r8, r8, r8
beq CacheCallFailNoL2 ; fail if zero-sized cache reported beq CacheCallFailNoL2 ; fail if zero-sized cache reported
@ -323,7 +323,7 @@ CacheCallGetInfoForReturnValue
blr blr
@level2 @level2
lwz r8, KDP.ProcessorInfo + NKProcessorInfo.ProcessorL2DSize(r1) lwz r8, KDP.ProcInfo.ProcessorL2DSize(r1)
and. r8, r8, r8 and. r8, r8, r8
beq CacheCallFailNoL2 beq CacheCallFailNoL2
@ -375,17 +375,17 @@ FlushCaches
; Flush level 1 ; Flush level 1
lhz r25, KDP.ProcessorInfo + NKProcessorInfo.DataCacheLineSize(r1) lhz r25, KDP.ProcInfo.DataCacheLineSize(r1)
and. r25, r25, r25 ; r25 = L1-D line size and. r25, r25, r25 ; r25 = L1-D line size
cntlzw r8, r25 cntlzw r8, r25
beq @return beq @return
subfic r9, r8, 31 ; r9 = logb(L1-D line size) subfic r9, r8, 31 ; r9 = logb(L1-D line size)
lwz r8, KDP.ProcessorInfo + NKProcessorInfo.DataCacheTotalSize(r1) lwz r8, KDP.ProcInfo.DataCacheTotalSize(r1)
and. r8, r8, r8 ; r8 = L1-D size and. r8, r8, r8 ; r8 = L1-D size
beq @return beq @return
lwz r24, KDP.ProcessorInfo + NKProcessorInfo.ProcessorFlags(r1) lwz r24, KDP.ProcInfo.ProcessorFlags(r1)
mtcr r24 mtcr r24
bc BO_IF, 31 - NKProcessorInfo.hasMSSregs, @use_SPRs_to_invalidate bc BO_IF, 31 - NKProcessorInfo.hasMSSregs, @use_SPRs_to_invalidate
@ -411,7 +411,7 @@ FlushCaches
; Flush level 2 (very similar to above) ; Flush level 2 (very similar to above)
lwz r24, KDP.ProcessorInfo + NKProcessorInfo.ProcessorFlags(r1) lwz r24, KDP.ProcInfo.ProcessorFlags(r1)
andi. r24, r24, 1 << NKProcessorInfo.hasL2CR andi. r24, r24, 1 << NKProcessorInfo.hasL2CR
beq @return ; return if L2CR unavailable beq @return ; return if L2CR unavailable
@ -419,13 +419,13 @@ FlushCaches
andis. r24, r24, 0x8000 andis. r24, r24, 0x8000
beq @return ; return if L2 off (per L2CR[L2E]) beq @return ; return if L2 off (per L2CR[L2E])
lhz r25, KDP.ProcessorInfo + NKProcessorInfo.ProcessorL2DBlockSize(r1) lhz r25, KDP.ProcInfo.ProcessorL2DBlockSize(r1)
and. r25, r25, r25 ; r25 = L2-D line size and. r25, r25, r25 ; r25 = L2-D line size
cntlzw r8, r25 cntlzw r8, r25
beq @return beq @return
subfic r9, r8, 31 ; r9 = logb(L2-D line size) subfic r9, r8, 31 ; r9 = logb(L2-D line size)
lwz r8, KDP.ProcessorInfo + NKProcessorInfo.ProcessorL2DSize(r1) lwz r8, KDP.ProcInfo.ProcessorL2DSize(r1)
and. r8, r8, r8 ; r8 = L2-D size and. r8, r8, r8 ; r8 = L2-D size
beq @return beq @return
@ -515,7 +515,7 @@ FlushL1CacheUsingMSSCR0
; Return if MSSCR0 unavailable ; Return if MSSCR0 unavailable
lwz r8, KDP.ProcessorInfo + NKProcessorInfo.ProcessorFlags(r1) lwz r8, KDP.ProcInfo.ProcessorFlags(r1)
mtcr r8 mtcr r8
bclr BO_IF_NOT, 31-NKProcessorInfo.hasMSSregs bclr BO_IF_NOT, 31-NKProcessorInfo.hasMSSregs

20
NanoKernel/NKExceptions.s
View File

@ -23,9 +23,9 @@ ExceptionAfterRetry
slwi r8, r8, 2 ; increment counter slwi r8, r8, 2 ; increment counter
add r8, r8, r1 add r8, r8, r1
lwz r9, KDP.NanoKernelInfo + NKNanoKernelInfo.ExceptionCauseCounts(r8) lwz r9, KDP.NKInfo.ExceptionCauseCounts(r8)
addi r9, r9, 1 addi r9, r9, 1
stw r9, KDP.NanoKernelInfo + NKNanoKernelInfo.ExceptionCauseCounts(r8) stw r9, KDP.NKInfo.ExceptionCauseCounts(r8)
; Move regs from KDP to ContextBlock ; Move regs from KDP to ContextBlock
lwz r8, EWA.r7(r1) lwz r8, EWA.r7(r1)
@ -100,10 +100,10 @@ PreferRegistersFromKDPSavingContextBlock
_alignToCacheBlock _alignToCacheBlock
KCallReturnFromExceptionFastPath KCallReturnFromExceptionFastPath
lwz r11, KDP.NanoKernelInfo + NKNanoKernelInfo.NanoKernelCallCounts(r1) lwz r11, KDP.NKInfo.NanoKernelCallCounts(r1)
mr r10, r12 mr r10, r12
addi r11, r11, 1 addi r11, r11, 1
stw r11, KDP.NanoKernelInfo + NKNanoKernelInfo.NanoKernelCallCounts(r1) stw r11, KDP.NKInfo.NanoKernelCallCounts(r1)
mfsrr1 r11 mfsrr1 r11
rlwimi r7, r7, 27, 26, 26 ; ?re-enable single stepping rlwimi r7, r7, 27, 26, 26 ; ?re-enable single stepping
@ -115,10 +115,10 @@ KCallReturnFromException
;force to system context ; Handler returned >= 1 ;force to system context ; Handler returned >= 1
subi r8, r3, 32 subi r8, r3, 32
lwz r9, KDP.NanoKernelInfo + NKNanoKernelInfo.ExceptionForcedCount(r1) lwz r9, KDP.NKInfo.ExceptionForcedCount(r1)
cmplwi r8, 256-32 cmplwi r8, 256-32
addi r9, r9, 1 addi r9, r9, 1
stw r9, KDP.NanoKernelInfo + NKNanoKernelInfo.ExceptionForcedCount(r1) stw r9, KDP.NKInfo.ExceptionForcedCount(r1)
insrwi r7, r3, 8, 0 insrwi r7, r3, 8, 0
blt RunSystemContext ; Handler returned 1-255: force that exception number to System blt RunSystemContext ; Handler returned 1-255: force that exception number to System
li r8, ecTrapInstr li r8, ecTrapInstr
@ -145,10 +145,10 @@ KCallReturnFromException
b IntReturn b IntReturn
@propagate ; Handler returned 1: propagate exception @propagate ; Handler returned 1: propagate exception
lwz r9, KDP.NanoKernelInfo + NKNanoKernelInfo.ExceptionPropagateCount(r1) lwz r9, KDP.NKInfo.ExceptionPropagateCount(r1)
lwz r8, CB.ExceptionOriginFlags(r6) lwz r8, CB.ExceptionOriginFlags(r6)
addi r9, r9, 1 addi r9, r9, 1
stw r9, KDP.NanoKernelInfo + NKNanoKernelInfo.ExceptionPropagateCount(r1) stw r9, KDP.NKInfo.ExceptionPropagateCount(r1)
lwz r10, CB.ExceptionOriginAddr(r6) lwz r10, CB.ExceptionOriginAddr(r6)
rlwimi r7, r8, 0, 0xFF00FFFF ; restore most Flags to pre-exception state rlwimi r7, r8, 0, 0xFF00FFFF ; restore most Flags to pre-exception state
lwz r8, CB.ExceptionOriginEnables(r6) lwz r8, CB.ExceptionOriginEnables(r6)
@ -226,9 +226,9 @@ Exception
slwi r8, r8, 2 ; Increment counter, easy enough slwi r8, r8, 2 ; Increment counter, easy enough
add r8, r8, r1 add r8, r8, r1
lwz r9, KDP.NanoKernelInfo + NKNanoKernelInfo.ExceptionCauseCounts(r8) lwz r9, KDP.NKInfo.ExceptionCauseCounts(r8)
addi r9, r9, 1 addi r9, r9, 1
stw r9, KDP.NanoKernelInfo + NKNanoKernelInfo.ExceptionCauseCounts(r8) stw r9, KDP.NKInfo.ExceptionCauseCounts(r8)
blt RunExceptionHandler ; exception enabled => run userspace handler blt RunExceptionHandler ; exception enabled => run userspace handler
;fall through ; Alt Context has left exception disabled => Sys Context ;fall through ; Alt Context has left exception disabled => Sys Context

4
NanoKernel/NKFloatingPt.s
View File

@ -8,10 +8,10 @@ IntFPUnavail
mfsprg r1, 0 mfsprg r1, 0
stw r11, KDP.FloatingPtTemp1(r1) stw r11, KDP.FloatingPtTemp1(r1)
lwz r11, KDP.NanoKernelInfo + NKNanoKernelInfo.FPUReloadCount(r1) lwz r11, KDP.NKInfo.FPUReloadCount(r1)
stw r6, KDP.FloatingPtTemp2(r1) stw r6, KDP.FloatingPtTemp2(r1)
addi r11, r11, 1 addi r11, r11, 1
stw r11, KDP.NanoKernelInfo + NKNanoKernelInfo.FPUReloadCount(r1) stw r11, KDP.NKInfo.FPUReloadCount(r1)
mfsrr1 r11 mfsrr1 r11
_bset r11, r11, bitMsrFP _bset r11, r11, bitMsrFP

10
NanoKernel/NKIndex.s
View File

@ -48,7 +48,7 @@ InitIDIndex
beq Local_Panic beq Local_Panic
li r9, 0 li r9, 0
stw r9, KDP.NanoKernelInfo + NKNanoKernelInfo.IDCtr(r1) stw r9, KDP.NKInfo.IDCtr(r1)
sth r9, Index.HalfOne(r22) sth r9, Index.HalfOne(r22)
sth r9, Index.HalfTwo(r22) sth r9, Index.HalfTwo(r22)
@ -158,9 +158,9 @@ MakeID
@_f0 @_f0
stw r8, 0x0004(r22) stw r8, 0x0004(r22)
stb r9, 0x0000(r22) stb r9, 0x0000(r22)
lwz r9, KDP.NanoKernelInfo + NKNanoKernelInfo.IDCtr(r1) lwz r9, KDP.NKInfo.IDCtr(r1)
addi r9, r9, 0x01 addi r9, r9, 0x01
stw r9, KDP.NanoKernelInfo + NKNanoKernelInfo.IDCtr(r1) stw r9, KDP.NKInfo.IDCtr(r1)
lhz r20, 0x0000(r18) lhz r20, 0x0000(r18)
lhz r8, 0x0002(r22) lhz r8, 0x0002(r22)
lwz r21, PSA.IndexPtr(r1) lwz r21, PSA.IndexPtr(r1)
@ -206,9 +206,9 @@ DeleteID
cmpw cr1, r23, r20 cmpw cr1, r23, r20
beqlr beqlr
bnelr cr1 bnelr cr1
lwz r9, KDP.NanoKernelInfo + NKNanoKernelInfo.IDCtr(r1) lwz r9, KDP.NKInfo.IDCtr(r1)
addi r9, r9, -0x01 addi r9, r9, -0x01
stw r9, KDP.NanoKernelInfo + NKNanoKernelInfo.IDCtr(r1) stw r9, KDP.NKInfo.IDCtr(r1)
lhz r20, 0x0002(r18) lhz r20, 0x0002(r18)
stb r8, 0x0000(r22) stb r8, 0x0000(r22)
addi r20, r20, 0x01 addi r20, r20, 0x01

26
NanoKernel/NKInit.s
View File

@ -273,19 +273,19 @@ FinishInitBuiltin
; Copy some choice values out of KDP's copy of NKProcessorInfo ; Copy some choice values out of KDP's copy of NKProcessorInfo
lwz r9, KDP.ProcessorInfo + NKProcessorInfo.DecClockRateHz(r1) lwz r9, KDP.ProcInfo.DecClockRateHz(r1)
stw r9, KDP.ProcessorInfo + NKProcessorInfo.ClockRates + 8(r1) stw r9, KDP.ProcInfo.ClockRates + 8(r1)
lwz r9, KDP.ProcessorInfo + NKProcessorInfo.BusClockRateHz(r1) lwz r9, KDP.ProcInfo.BusClockRateHz(r1)
stw r9, KDP.ProcessorInfo + NKProcessorInfo.ClockRates + 4(r1) stw r9, KDP.ProcInfo.ClockRates + 4(r1)
lwz r9, KDP.ProcessorInfo + NKProcessorInfo.CpuClockRateHz(r1) lwz r9, KDP.ProcInfo.CpuClockRateHz(r1)
stw r9, KDP.ProcessorInfo + NKProcessorInfo.ClockRates + 0(r1) stw r9, KDP.ProcInfo.ClockRates + 0(r1)
li r9, 0 li r9, 0
sth r9, KDP.ProcessorInfo + NKProcessorInfo.SetToZero(r1) sth r9, KDP.ProcInfo.SetToZero(r1)
lwz r8, KDP.ProcessorInfo + NKProcessorInfo.DecClockRateHz(r1) lwz r8, KDP.ProcInfo.DecClockRateHz(r1)
stw r8, PSA.DecClockRateHzCopy(r1) stw r8, PSA.DecClockRateHzCopy(r1)
@ -757,7 +757,7 @@ SetProcessorFlags
slwi r23, r23, 2 slwi r23, r23, 2
add r8, r25, r23 add r8, r25, r23
lwz r23, ProcessorFlagsTable - NKTop + 64(r8) lwz r23, ProcessorFlagsTable - NKTop + 64(r8)
stw r23, KDP.ProcessorInfo + NKProcessorInfo.ProcessorFlags(r1) stw r23, KDP.ProcInfo.ProcessorFlags(r1)
b @done b @done
@pvr_has_high_bit_set @pvr_has_high_bit_set
@ -779,7 +779,7 @@ SetProcessorFlags
slwi r23, r23, 2 slwi r23, r23, 2
add r8, r25, r23 add r8, r25, r23
lwz r23, ProcessorFlagsTable - NKTop + 128(r8) lwz r23, ProcessorFlagsTable - NKTop + 128(r8)
stw r23, KDP.ProcessorInfo + NKProcessorInfo.ProcessorFlags(r1) stw r23, KDP.ProcInfo.ProcessorFlags(r1)
b @done b @done
@done @done
@ -870,7 +870,7 @@ SetProcessorFlags
; Save ID in self and KDP ; Save ID in self and KDP
stw r8, Process.ID(r31) stw r8, Process.ID(r31)
stw r8, KDP.NanoKernelInfo + NKNanoKernelInfo.blueProcessID(r1) stw r8, KDP.NKInfo.blueProcessID(r1)
; Sign it ; Sign it
lisori r8, Process.kSignature lisori r8, Process.kSignature
@ -1164,7 +1164,7 @@ SetProcessorFlags
stw r8, LLL.Freeform(r9) stw r8, LLL.Freeform(r9)
; ...which the blue task will probably want to know about ; ...which the blue task will probably want to know about
stw r8, KDP.NanoKernelInfo + NKNanoKernelInfo.pageQueueID(r1) stw r8, KDP.NKInfo.pageQueueID(r1)
InitList r9, 'PAGQ', scratch=r16 InitList r9, 'PAGQ', scratch=r16
@ -1215,7 +1215,7 @@ SetProcessorFlags
beq Init_Panic beq Init_Panic
lwz r8, Task.ID(r31) lwz r8, Task.ID(r31)
stw r8, KDP.NanoKernelInfo + NKNanoKernelInfo.blueTaskID(r1) stw r8, KDP.NKInfo.blueTaskID(r1)
; Can equal -1 or a 68k interrupt number. PIHes touch it. ; Can equal -1 or a 68k interrupt number. PIHes touch it.

4
NanoKernel/NKIntHandlers.s
View File

@ -138,9 +138,9 @@ IntAlignment
mfsprg r1, 0 mfsprg r1, 0
stmw r2, EWA.r2(r1) stmw r2, EWA.r2(r1)
lwz r11, KDP.NanoKernelInfo + NKNanoKernelInfo.MisalignmentCount(r1) lwz r11, KDP.NKInfo.MisalignmentCount(r1)
addi r11, r11, 1 addi r11, r11, 1
stw r11, KDP.NanoKernelInfo + NKNanoKernelInfo.MisalignmentCount(r1) stw r11, KDP.NKInfo.MisalignmentCount(r1)
mfsprg r11, 1 mfsprg r11, 1
stw r0, EWA.r0(r1) stw r0, EWA.r0(r1)

14
NanoKernel/NKLegacyVM.s
View File

@ -243,7 +243,7 @@ VMInit_0x110
stw r4, KDP.VMLogicalPages(r1) stw r4, KDP.VMLogicalPages(r1)
slwi r7, r4, 12 slwi r7, r4, 12
stw r7, KDP.SystemInfo + NKSystemInfo.LogicalMemorySize(r1) ; bug in NKv2?? stw r7, KDP.SysInfo.LogicalMemorySize(r1) ; bug in NKv2??
slwi r7, r4, 2 slwi r7, r4, 2
li r8, 0x00 li r8, 0x00
@ -873,8 +873,8 @@ VMAllocateMemory_0xf4
stw r7, KDP.TotalPhysicalPages(r1) stw r7, KDP.TotalPhysicalPages(r1)
stw r7, KDP.VMLogicalPages(r1) stw r7, KDP.VMLogicalPages(r1)
slwi r8, r7, 12 slwi r8, r7, 12
stw r8, KDP.SystemInfo + NKSystemInfo.UsableMemorySize(r1) stw r8, KDP.SysInfo.UsableMemorySize(r1)
stw r8, KDP.SystemInfo + NKSystemInfo.LogicalMemorySize(r1) stw r8, KDP.SysInfo.LogicalMemorySize(r1)
addi r14, r1, 120 addi r14, r1, 120
lwz r15, KDP.PARPageListPtr(r1) lwz r15, KDP.PARPageListPtr(r1)
@ -1040,10 +1040,10 @@ EditPTEOnlyInHTAB ; OUTSIDE REFERER
;r15 is address of stored PTE ;r15 is address of stored PTE
;r16 is PTE value ;r16 is PTE value
RemovePTEFromHTAB ; OUTSIDE REFERER RemovePTEFromHTAB ; OUTSIDE REFERER
lwz r8, KDP.NanoKernelInfo + NKNanoKernelInfo.HashTableDeleteCount(r1);update a value in NanoKernelInfo lwz r8, KDP.NKInfo.HashTableDeleteCount(r1);update a value in NanoKernelInfo
rlwinm r16, r16, 0, 21, 19 ;update PTE flags to indicate not in HTAB rlwinm r16, r16, 0, 21, 19 ;update PTE flags to indicate not in HTAB
addi r8, r8, 0x01 addi r8, r8, 0x01
stw r8, KDP.NanoKernelInfo + NKNanoKernelInfo.HashTableDeleteCount(r1) stw r8, KDP.NKInfo.HashTableDeleteCount(r1)
rlwimi r16, r9, 0, 0, 19 ;move page# back into PTE rlwimi r16, r9, 0, 0, 19 ;move page# back into PTE
_InvalNCBPointerCache scratch=r8 _InvalNCBPointerCache scratch=r8
@ -1102,10 +1102,10 @@ VMLastExportedFunc_0x83
addi r14, r14, 0x08 addi r14, r14, 0x08
VMLastExportedFunc_0x87 VMLastExportedFunc_0x87
lwz r9, KDP.NanoKernelInfo + NKNanoKernelInfo.HashTableCreateCount(r1) lwz r9, KDP.NKInfo.HashTableCreateCount(r1)
rlwinm r8, r6, 7, 1, 24 rlwinm r8, r6, 7, 1, 24
addi r9, r9, 0x01 addi r9, r9, 0x01
stw r9, KDP.NanoKernelInfo + NKNanoKernelInfo.HashTableCreateCount(r1) stw r9, KDP.NKInfo.HashTableCreateCount(r1)
rlwimi r8, r4, 22, 26, 31 rlwimi r8, r4, 22, 26, 31
lwz r9, KDP.PageAttributeInit(r1) lwz r9, KDP.PageAttributeInit(r1)
oris r8, r8, 0x8000 oris r8, r8, 0x8000

8
NanoKernel/NKMPCalls.s
View File

@ -179,7 +179,7 @@ MPCallTableEnd
; Not sure where this counter table is? ; Not sure where this counter table is?
lwz r16, KDP.NanoKernelInfo + NKNanoKernelInfo.MPDispatchCountTblPtr(r1) lwz r16, KDP.NKInfo.MPDispatchCountTblPtr(r1)
rlwinm r17, r15, 2, 20, 29 rlwinm r17, r15, 2, 20, 29
cmplwi r16, 0 cmplwi r16, 0
beq @no_count beq @no_count
@ -816,7 +816,7 @@ MPDelayUntil
MPDelayUntilSys MPDelayUntilSys
rlwinm. r8, r7, 0, EWA.kFlagBlue, EWA.kFlagBlue rlwinm. r8, r7, 0, EWA.kFlagBlue, EWA.kFlagBlue
lwz r16, KDP.NanoKernelInfo + NKNanoKernelInfo.ExternalIntCount(r1) lwz r16, KDP.NKInfo.ExternalIntCount(r1)
beq _MPDelayUntilCommon beq _MPDelayUntilCommon
; Why the hell are we counting interrupts? ; Why the hell are we counting interrupts?
@ -1796,7 +1796,7 @@ NKSetPrInfoClockRates
bge ReturnParamErrFromMPCall bge ReturnParamErrFromMPCall
mulli r17, r3, 16 mulli r17, r3, 16
addi r18, r1, KDP.ProcessorInfo + NKProcessorInfo.ClockRates addi r18, r1, KDP.ProcInfo.ClockRates
add r18, r17, r18 add r18, r17, r18
lwz r16, ContextBlock.r6(r6) lwz r16, ContextBlock.r6(r6)
@ -2114,7 +2114,7 @@ MPCall_133 ; OUTSIDE REFERER
_Lock PSA.SchLock, scratch1=r16, scratch2=r17 _Lock PSA.SchLock, scratch1=r16, scratch2=r17
cmpw r3, r0 cmpw r3, r0
lwz r16, KDP.NanoKernelInfo + NKNanoKernelInfo.ConfigFlags(r1) lwz r16, KDP.NKInfo.ConfigFlags(r1)
li r17, 0x0b li r17, 0x0b
blt MPCall_133_0x34 blt MPCall_133_0x34
and r3, r3, r17 and r3, r3, r17

18
NanoKernel/NKMemory.s
View File

@ -90,10 +90,10 @@ PopulateHTAB ; LogicalAddress r28 // Success cr0.eq
sync ; because we just wanged the page table sync ; because we just wanged the page table
stwu r30, -24(r29) ; PTE[hi] = r30 stwu r30, -24(r29) ; PTE[hi] = r30
lwz r28, KDP.NanoKernelInfo + NKNanoKernelInfo.HashTableCreateCount(r1) lwz r28, KDP.NKInfo.HashTableCreateCount(r1)
stw r29, KDP.ApproxCurrentPTEG(r1) stw r29, KDP.ApproxCurrentPTEG(r1)
addi r28, r28, 1 addi r28, r28, 1
stw r28, KDP.NanoKernelInfo + NKNanoKernelInfo.HashTableCreateCount(r1) stw r28, KDP.NKInfo.HashTableCreateCount(r1)
beqlr ; >>>>> RETURN "BEQ" if we got to "Case 1" directly beqlr ; >>>>> RETURN "BEQ" if we got to "Case 1" directly
cmpwi r26, 0x5A5A ; Special value set so that we take note of this new temporary PTE? cmpwi r26, 0x5A5A ; Special value set so that we take note of this new temporary PTE?
@ -115,10 +115,10 @@ PopulateHTAB ; LogicalAddress r28 // Success cr0.eq
######################################################################## ########################################################################
; Helpful code that jumps back to roughly where it started ; Helpful code that jumps back to roughly where it started
@remove_temp_pte @remove_temp_pte
lwz r28, KDP.NanoKernelInfo + NKNanoKernelInfo.HashTableDeleteCount(r1) lwz r28, KDP.NKInfo.HashTableDeleteCount(r1)
lwz r29, KDP.HtabTempEntryPtr(r1) lwz r29, KDP.HtabTempEntryPtr(r1)
addi r28, r28, 1 addi r28, r28, 1
stw r28, KDP.NanoKernelInfo + NKNanoKernelInfo.HashTableDeleteCount(r1) stw r28, KDP.NKInfo.HashTableDeleteCount(r1)
li r28, 0 li r28, 0
stw r28, 0(r29) stw r28, 0(r29)
lwz r29, KDP.HtabTempPage(r1) lwz r29, KDP.HtabTempPage(r1)
@ -257,14 +257,14 @@ PopulateHTAB ; LogicalAddress r28 // Success cr0.eq
extrwi r31, r26, 2, 20 extrwi r31, r26, 2, 20
cmpwi cr7, r31, 3 ; not a DaddyFlag + CountingFlag? Try again! cmpwi cr7, r31, 3 ; not a DaddyFlag + CountingFlag? Try again!
lwz r31, KDP.NanoKernelInfo + NKNanoKernelInfo.HashTableOverflowCount(r1) lwz r31, KDP.NKInfo.HashTableOverflowCount(r1)
stw r29, KDP.OverflowingPTEG(r1) stw r29, KDP.OverflowingPTEG(r1)
addi r31, r31, 1 addi r31, r31, 1
stw r31, KDP.NanoKernelInfo + NKNanoKernelInfo.HashTableOverflowCount(r1) stw r31, KDP.NKInfo.HashTableOverflowCount(r1)
lwz r31, KDP.NanoKernelInfo + NKNanoKernelInfo.HashTableDeleteCount(r1) lwz r31, KDP.NKInfo.HashTableDeleteCount(r1)
stw r30, 0(r29) stw r30, 0(r29)
addi r31, r31, 1 addi r31, r31, 1
stw r31, KDP.NanoKernelInfo + NKNanoKernelInfo.HashTableDeleteCount(r1) stw r31, KDP.NKInfo.HashTableDeleteCount(r1)
sync sync
tlbie r28 tlbie r28
@ -530,7 +530,7 @@ nobats
######################################################################## ########################################################################
FlushTLB FlushTLB
lhz r29, KDP.ProcessorInfo + NKProcessorInfo.TransCacheTotalSize(r1) lhz r29, KDP.ProcInfo.TransCacheTotalSize(r1)
slwi r29, r29, 11 slwi r29, r29, 11
@loop @loop
subi r29, r29, 4096 subi r29, r29, 4096

4
NanoKernel/NKPoolAllocator.s
View File

@ -457,9 +457,9 @@ _pool_page_seg equ 0x1000
; Counter can be viewed from Apple System Profiler ; Counter can be viewed from Apple System Profiler
lwz r16, KDP.NanoKernelInfo + NKNanoKernelInfo.FreePoolExtendCount(r1) lwz r16, KDP.NKInfo.FreePoolExtendCount(r1)
addi r16, r16, 1 addi r16, r16, 1
stw r16, KDP.NanoKernelInfo + NKNanoKernelInfo.FreePoolExtendCount(r1) stw r16, KDP.NKInfo.FreePoolExtendCount(r1)
; Bit of palaver ; Bit of palaver

6
NanoKernel/NKPowerCalls.s
View File

@ -290,7 +290,7 @@ PwrSuspendSystem
; Disable L2 cache (via L2CR, if present) ; Disable L2 cache (via L2CR, if present)
lwz r26, KDP.ProcessorInfo + NKProcessorInfo.ProcessorFlags(r1) lwz r26, KDP.ProcInfo.ProcessorFlags(r1)
andi. r26, r26, 1 << NKProcessorInfo.hasL2CR andi. r26, r26, 1 << NKProcessorInfo.hasL2CR
beq @no_need_to_deactivate_l2 beq @no_need_to_deactivate_l2
mfspr r9, l2cr mfspr r9, l2cr
@ -459,10 +459,10 @@ PwrSuspendSystem
; Reactivate L2 cache ; Reactivate L2 cache
lwz r26, KDP.ProcessorInfo + NKProcessorInfo.ProcessorFlags(r1) lwz r26, KDP.ProcInfo.ProcessorFlags(r1)
andi. r26, r26, 1 << NKProcessorInfo.hasL2CR andi. r26, r26, 1 << NKProcessorInfo.hasL2CR
beq @no_need_to_reactivate_l2 beq @no_need_to_reactivate_l2
lwz r8, KDP.ProcessorInfo + NKProcessorInfo.ProcessorL2DSize(r1) lwz r8, KDP.ProcInfo.ProcessorL2DSize(r1)
mr. r8, r8 mr. r8, r8
beq @no_need_to_reactivate_l2 beq @no_need_to_reactivate_l2

6
NanoKernel/NKPrimaryIntHandlers.s
View File

@ -199,7 +199,7 @@ CommonPIHPath_0xc ; OUTSIDE REFERER
addi r8, r31, Task.Timer addi r8, r31, Task.Timer
bl DequeueTimer bl DequeueTimer
@task_timer_not_in_use @task_timer_not_in_use
lwz r16, KDP.NanoKernelInfo + NKNanoKernelInfo.ExternalIntCount(r1) lwz r16, KDP.NKInfo.ExternalIntCount(r1)
stw r16, PSA.OtherSystemContextPtr(r1) stw r16, PSA.OtherSystemContextPtr(r1)
@now_reschedule_task @now_reschedule_task
@ -327,9 +327,9 @@ PDM_PIH
mfsprg r30, 3 mfsprg r30, 3
bne @nocount bne @nocount
lwz r21, KDP.NanoKernelInfo + NKNanoKernelInfo.ExternalIntCount(r1) lwz r21, KDP.NKInfo.ExternalIntCount(r1)
addi r21, r21, 0x01 addi r21, r21, 0x01
stw r21, KDP.NanoKernelInfo + NKNanoKernelInfo.ExternalIntCount(r1) stw r21, KDP.NKInfo.ExternalIntCount(r1)
@nocount @nocount
; Switch to Blue vector table ; Switch to Blue vector table

6
NanoKernel/NKReplacementInit.s
View File

@ -362,14 +362,14 @@ replace_old_kernel_0x198
sth r12, KDP.InfoRecord + InfoRecord.NKNanoKernelInfoVer(r1) sth r12, KDP.InfoRecord + InfoRecord.NKNanoKernelInfoVer(r1)
lwz r8, KDP.ProcessorInfo + NKProcessorInfo.DecClockRateHz(r1) lwz r8, KDP.ProcInfo.DecClockRateHz(r1)
stw r8, PSA.DecClockRateHzCopy(r1) stw r8, PSA.DecClockRateHzCopy(r1)
; Play with ConfigFlags ; Play with ConfigFlags
lwz r8, KDP.NanoKernelInfo + NKNanoKernelInfo.ConfigFlags(r1) lwz r8, KDP.NKInfo.ConfigFlags(r1)
_bset r8, r8, 31 ; always set bit 31 _bset r8, r8, 31 ; always set bit 31
@ -382,7 +382,7 @@ replace_old_kernel_0x198
_bset r8, r8, 27 _bset r8, r8, 27
@oldrom @oldrom
stw r8, KDP.NanoKernelInfo + NKNanoKernelInfo.ConfigFlags(r1) stw r8, KDP.NKInfo.ConfigFlags(r1)

6
NanoKernel/NKReset.s
View File

@ -338,7 +338,7 @@ CreatePageList
lwz r20, KDP.KernelMemoryEnd(r1) lwz r20, KDP.KernelMemoryEnd(r1)
subi r29, r21, 4 ; ptr to last added entry subi r29, r21, 4 ; ptr to last added entry
addi r19, r1, KDP.SystemInfo + NKSystemInfo.Bank0Start - 8 addi r19, r1, KDP.SysInfo.Bank0Start - 8
lwz r23, KDP.PageAttributeInit(r1) ; default WIMG/PP settings in PTEs lwz r23, KDP.PageAttributeInit(r1) ; default WIMG/PP settings in PTEs
@ -394,9 +394,9 @@ CreatePARInPageMap
addi r19, r22, 4 addi r19, r22, 4
slwi r19, r19, 10 slwi r19, r19, 10
ori r30, r30, 0xffff ori r30, r30, 0xffff
stw r19, KDP.SystemInfo + NKSystemInfo.UsableMemorySize(r1) stw r19, KDP.SysInfo.UsableMemorySize(r1)
srwi r22, r22, 2 srwi r22, r22, 2
stw r19, KDP.SystemInfo + NKSystemInfo.LogicalMemorySize(r1) stw r19, KDP.SysInfo.LogicalMemorySize(r1)
; convert r19 to pages, and save in some places ; convert r19 to pages, and save in some places
srwi r19, r19, 12 srwi r19, r19, 12

16
NanoKernel/NKScheduler.s
View File

@ -69,7 +69,7 @@ Local_Panic set *
SchInit SchInit
li r16, 0 li r16, 0
stw r16, KDP.NanoKernelInfo + NKNanoKernelInfo.TaskCount(r1) stw r16, KDP.NKInfo.TaskCount(r1)
mflr r20 mflr r20
@ -883,9 +883,9 @@ _SchRdyTaskCommon
SchSwitchSpace SchSwitchSpace
; This is the only function that hits this counter ; This is the only function that hits this counter
lwz r17, KDP.NanoKernelInfo + NKNanoKernelInfo.AddrSpcSetCtr(r1) lwz r17, KDP.NKInfo.AddrSpcSetCtr(r1)
addi r17, r17, 1 addi r17, r17, 1
stw r17, KDP.NanoKernelInfo + NKNanoKernelInfo.AddrSpcSetCtr(r1) stw r17, KDP.NKInfo.AddrSpcSetCtr(r1)
; Check that we have the right guy (a 'SPAC') ; Check that we have the right guy (a 'SPAC')
lwz r16, AddressSpace.Signature(r8) lwz r16, AddressSpace.Signature(r8)
@ -1026,7 +1026,7 @@ SchSwitchSpace
; This is weird. If the hasExtraBATs flag (my name) is set in ProcessorInfo, ; This is weird. If the hasExtraBATs flag (my name) is set in ProcessorInfo,
; populate a second (undocumented?) set of BATs from the same struct. ; populate a second (undocumented?) set of BATs from the same struct.
lwz r17, KDP.ProcessorInfo + NKProcessorInfo.ProcessorFlags(r1) lwz r17, KDP.ProcInfo.ProcessorFlags(r1)
lwz r16, AddressSpace.ExtraBAT0U(r8) lwz r16, AddressSpace.ExtraBAT0U(r8)
rlwinm. r17, r17, 0, 31-NKProcessorInfo.hasExtraBATs, 31-NKProcessorInfo.hasExtraBATs rlwinm. r17, r17, 0, 31-NKProcessorInfo.hasExtraBATs, 31-NKProcessorInfo.hasExtraBATs
lwz r17, AddressSpace.ExtraBAT0U(r9) lwz r17, AddressSpace.ExtraBAT0U(r9)
@ -1199,9 +1199,9 @@ SchEval
lwz r31, EWA.PA_CurTask(r14) lwz r31, EWA.PA_CurTask(r14)
lwz r1, EWA.PA_KDP(r14) lwz r1, EWA.PA_KDP(r14)
lwz r9, KDP.NanoKernelInfo + NKNanoKernelInfo.SchEvalCount(r1) lwz r9, KDP.NKInfo.SchEvalCount(r1)
addi r9, r9, 1 addi r9, r9, 1
stw r9, KDP.NanoKernelInfo + NKNanoKernelInfo.SchEvalCount(r1) stw r9, KDP.NKInfo.SchEvalCount(r1)
bl SchFiddlePriorityShifty bl SchFiddlePriorityShifty
lbz r27, 0x0019(r31) lbz r27, 0x0019(r31)
@ -2006,9 +2006,9 @@ FlagSchEval
; To force a scheduler evaluation to run on *another* CPU, we interrupt it ; To force a scheduler evaluation to run on *another* CPU, we interrupt it
AlertSchEvalOnOtherCPU AlertSchEvalOnOtherCPU
lwz r9, KDP.NanoKernelInfo + NKNanoKernelInfo.AlertCount(r1) lwz r9, KDP.NKInfo.AlertCount(r1)
addi r9, r9, 1 addi r9, r9, 1
stw r9, KDP.NanoKernelInfo + NKNanoKernelInfo.AlertCount(r1) stw r9, KDP.NKInfo.AlertCount(r1)
li r16, kAlert li r16, kAlert
stw r16, EWA.SIGPSelector(r15) stw r16, EWA.SIGPSelector(r15)

20
NanoKernel/NKSoftInt.s
View File

@ -71,10 +71,10 @@ IllegalInstruction
addc r21, r21, r8 addc r21, r21, r8
addze r20, r20 addze r20, r20
mtxer r23 mtxer r23
lwz r23, KDP.NanoKernelInfo + NKNanoKernelInfo.EmulatedUnimpInstCount(r1) lwz r23, KDP.NKInfo.EmulatedUnimpInstCount(r1)
rlwimi r7, r7, 27, 26, 26 rlwimi r7, r7, 27, 26, 26
addi r23, r23, 1 addi r23, r23, 1
stw r23, KDP.NanoKernelInfo + NKNanoKernelInfo.EmulatedUnimpInstCount(r1) stw r23, KDP.NKInfo.EmulatedUnimpInstCount(r1)
stwx r21, r1, r28 ; save register into EWA stwx r21, r1, r28 ; save register into EWA
mr r16, r7 mr r16, r7
@ -84,10 +84,10 @@ IllegalInstruction
@STFIWX @STFIWX
lwz r23, KDP.NanoKernelInfo + NKNanoKernelInfo.EmulatedUnimpInstCount(r1) lwz r23, KDP.NKInfo.EmulatedUnimpInstCount(r1)
mr r27, r8 mr r27, r8
addi r23, r23, 1 addi r23, r23, 1
stw r23, KDP.NanoKernelInfo + NKNanoKernelInfo.EmulatedUnimpInstCount(r1) stw r23, KDP.NKInfo.EmulatedUnimpInstCount(r1)
mfmsr r14 mfmsr r14
_bset r15, r14, bitMsrDR _bset r15, r14, bitMsrDR
b loc_A38 b loc_A38
@ -178,9 +178,9 @@ KCallRunAlternateContext
; Found a non-cached physical address for this NCB! ; Found a non-cached physical address for this NCB!
lwz r23, KDP.NanoKernelInfo + NKNanoKernelInfo.NCBPtrCacheMissCount(r1) lwz r23, KDP.NKInfo.NCBPtrCacheMissCount(r1)
addi r23, r23, 1 addi r23, r23, 1
stw r23, KDP.NanoKernelInfo + NKNanoKernelInfo.NCBPtrCacheMissCount(r1) stw r23, KDP.NKInfo.NCBPtrCacheMissCount(r1)
; Stick it in cache slot 3 ; Stick it in cache slot 3
@ -358,10 +358,10 @@ IntProgram
; SUCCESSFUL TRAP from emulator KCall table ; SUCCESSFUL TRAP from emulator KCall table
; => Service call then return to link register ; => Service call then return to link register
add r8, r8, r1 add r8, r8, r1
lwz r11, KDP.NanoKernelInfo + NKNanoKernelInfo.NanoKernelCallCounts(r8) lwz r11, KDP.NKInfo.NanoKernelCallCounts(r8)
lwz r10, KDP.NanoKernelCallTable(r8) lwz r10, KDP.NanoKernelCallTable(r8)
addi r11, r11, 1 addi r11, r11, 1
stw r11, KDP.NanoKernelInfo + NKNanoKernelInfo.NanoKernelCallCounts(r8) stw r11, KDP.NKInfo.NanoKernelCallCounts(r8)
mtlr r10 mtlr r10
mr r10, r12 ; ret addr: LR was saved to SPRG2, SPRG2 to r12 above, r12 to r10 now, r10 to SRR0 to program ctr later mr r10, r12 ; ret addr: LR was saved to SPRG2, SPRG2 to r12 above, r12 to r10 now, r10 to SRR0 to program ctr later
mfsrr1 r11 mfsrr1 r11
@ -386,9 +386,9 @@ IntProgram
; SUCCESSFUL TRAP from outside emulator KCall table ; SUCCESSFUL TRAP from outside emulator KCall table
; => Service call then return to following instruction ; => Service call then return to following instruction
add r8, r8, r1 add r8, r8, r1
lwz r10, KDP.NanoKernelInfo + NKNanoKernelInfo.NanoKernelCallCounts(r8) lwz r10, KDP.NKInfo.NanoKernelCallCounts(r8)
addi r10, r10, 1 addi r10, r10, 1
stw r10, KDP.NanoKernelInfo + NKNanoKernelInfo.NanoKernelCallCounts(r8) stw r10, KDP.NKInfo.NanoKernelCallCounts(r8)
lwz r8, KDP.NanoKernelCallTable(r8) lwz r8, KDP.NanoKernelCallTable(r8)
mtlr r8 mtlr r8
addi r10, r10, 4 ; continue executing the next instruction addi r10, r10, 4 ; continue executing the next instruction

4
NanoKernel/NKTasks.s
View File

@ -298,9 +298,9 @@ CreateTask
stw r8, Task.CreateTime3(r28) stw r8, Task.CreateTime3(r28)
stw r9, Task.CreateTime3 + 4(r28) stw r9, Task.CreateTime3 + 4(r28)
lwz r16, KDP.NanoKernelInfo + NKNanoKernelInfo.TaskCount(r1) lwz r16, KDP.NKInfo.TaskCount(r1)
addi r16, r16, 1 addi r16, r16, 1
stw r16, KDP.NanoKernelInfo + NKNanoKernelInfo.TaskCount(r1) stw r16, KDP.NKInfo.TaskCount(r1)
; Squeeze some info (including my owning process) out of the passed PROC ptr ; Squeeze some info (including my owning process) out of the passed PROC ptr
stw r27, Task.OwningProcessPtr(r28) stw r27, Task.OwningProcessPtr(r28)

10
NanoKernel/NKTimers.s
View File

@ -115,9 +115,9 @@ InitTMRQs_0xb4
rlwinm. r8, r31, 0, NKConfigurationInfo.NanodbgrFlagBit, NKConfigurationInfo.NanodbgrFlagBit rlwinm. r8, r31, 0, NKConfigurationInfo.NanodbgrFlagBit, NKConfigurationInfo.NanodbgrFlagBit
beq @nodebug beq @nodebug
lwz r8, KDP.NanoKernelInfo + NKNanoKernelInfo.ConfigFlags(r1) lwz r8, KDP.NKInfo.ConfigFlags(r1)
_bset r8, r8, NKNanoKernelInfo.NanodbgrFlagBit _bset r8, r8, NKNanoKernelInfo.NanodbgrFlagBit
stw r8, KDP.NanoKernelInfo + NKNanoKernelInfo.ConfigFlags(r1) stw r8, KDP.NKInfo.ConfigFlags(r1)
mflr r30 mflr r30
@ -587,12 +587,12 @@ TimerFire5_0x8 ; OUTSIDE REFERER
; Dead code -- probably removed from TimerTable ; Dead code -- probably removed from TimerTable
_log 'Heartbeat: Ext ' _log 'Heartbeat: Ext '
lwz r16, KDP.NanoKernelInfo + NKNanoKernelInfo.ExternalIntCount(r1) lwz r16, KDP.NKInfo.ExternalIntCount(r1)
mr r8, r16 mr r8, r16
bl printd bl printd
_log 'Alerts ' _log 'Alerts '
lwz r16, KDP.NanoKernelInfo + NKNanoKernelInfo.AlertCount(r1) lwz r16, KDP.NKInfo.AlertCount(r1)
mr r8, r16 mr r8, r16
bl printd bl printd
@ -886,7 +886,7 @@ DequeueTimer
TimebaseTicksPerPeriod TimebaseTicksPerPeriod
mr. r17, r8 mr. r17, r8
li r19, 250 li r19, 250
lwz r9, KDP.ProcessorInfo + NKProcessorInfo.DecClockRateHz(r1) lwz r9, KDP.ProcInfo.DecClockRateHz(r1)
bgt+ @period_positive bgt+ @period_positive
blt+ @period_negative blt+ @period_negative

2
NanoKernel/NKTranslation.s
View File

@ -2243,7 +2243,7 @@ ProbePerfMonitor ; OUTSIDE REFERER
lisori r21, 0xd62611e3 lisori r21, 0xd62611e3
; Left-justify the decrementer clock rate ; Left-justify the decrementer clock rate
lwz r19, KDP.ProcessorInfo + NKProcessorInfo.DecClockRateHz(r1) lwz r19, KDP.ProcInfo.DecClockRateHz(r1)
cntlzw r23, r19 cntlzw r23, r19
slw r19, r19, r23 slw r19, r19, r23