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memretry fixup

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This commit is contained in:
Elliot Nunn 2018-08-13 20:51:15 +08:00
parent cdbe4d6d96
commit 79465405d2
4 changed files with 19 additions and 19 deletions
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8
NanoKernel/MROptab.s
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@ -84,10 +84,10 @@ _S set 0
; LEGEND .... access size (r17 bits 27-30) and 0=Store/1=Load (r17 bit 31)
; ................ MRRestab entry (r17 bits 0-5)
;
; . mrOpflag1 }
; . mrOpflag2 } cr3 flags
; . mrOpflag3 }
; . mrFlagDidLoad }
; . mrSkipInstLoad }
; . mrXformIgnoreIdxReg } cr3 flags
; . mrSuppressUpdate }
; . mrChangedRegInEWA }
;
; primary routine secondary routine X-form extended opcode D-form opcode
; ................ ................ ....................... .................

18
NanoKernel/MROptabCode.s
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@ -165,20 +165,20 @@ MRStore22 ; Fast return paths from MemAccess code
MRLoad22
lhz r23, -4(r19)
addi r17, r17, -4
insrwi r21, r23, 16,0
insrwi r21, r23, 16, 0
MRLoad2
lhz r23, -2(r19)
insrwi r21, r23, 16,16
insrwi r21, r23, 16, 16
MRDoSecondary
sync
rlwinm. r28, r17, 18,25,29
rlwinm. r28, r17, 18,25,29 ; get the block-offset of rA
mtlr r25
cror cr0_eq, cr0_eq, mrOpflag3
cror cr0_eq, cr0_eq, mrSuppressUpdate
mtmsr r14
mtsprg 3, r24
beqlr
crset mrFlagDidLoad
crset mrChangedRegInEWA ; do this only if it's a non-zero register and we aren't suppressing update
stwx r18, r1, r28
blr
@ -189,7 +189,7 @@ MRSecLoadExt
MRSecLoad
rlwinm r28, r17, 13,25,29
crset mrFlagDidLoad
crset mrChangedRegInEWA
stwx r21, r1, r28
########################################################################
@ -202,7 +202,7 @@ MRSecDone
bne @trace ; Is a Trace flagged?
mtlr r12
bc BO_IF_NOT, mrFlagDidLoad, @load_ewa_registers
bc BO_IF_NOT, mrChangedRegInEWA, @load_ewa_registers
mtcr r13
lmw r2, KDP.r2(r1)
lwz r0, KDP.r0(r1)
@ -235,7 +235,7 @@ MRSecLHBRX
MRSecLWBRX
rlwinm r28, r17, 13,25,29
crset mrFlagDidLoad
crset mrChangedRegInEWA
stwbrx r21, r1, r28
b MRSecDone
@ -333,7 +333,7 @@ MRComDCBZ
MRSecLWARX
rlwinm r28, r17, 13,25,29
crset mrFlagDidLoad
crset mrChangedRegInEWA
stwx r21, r1, r28
stwcx. r21, r1, r28
b MRSecDone

8
NanoKernel/NKEquates.s
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@ -80,10 +80,10 @@ maskMsrFlags equ 0x00000F00
########################################################################
; MemRetry flags in CR3
mrOpflag1 equ cr3_lt
mrOpflag2 equ cr3_gt
mrOpflag3 equ cr3_eq
mrFlagDidLoad equ cr3_so
_bitequate cr3_lt, mrSkipInstLoad ; misalignment handler need not read the instruction
_bitequate cr3_gt, mrXformIgnoreIdxReg ; instruction is X-form but without an rB field
_bitequate cr3_eq, mrSuppressUpdate ; instruction may not update base reg in-place
_bitequate cr3_so, mrChangedRegInEWA ; have "loaded" a new reg value (i.e. saved into EWA)
########################################################################

4
NanoKernel/NKHotInts.s
View File

@ -331,7 +331,7 @@ EmulateDataAccess
lwzx r23, r1, r23 ; get rB from saved registers
rlwimi r17, r26, 6, 26, 5 ; r17 = pretend X-form inst with: maj opcode (from tbl), rS/D and RA (from inst), min opcode (from tbl)
add r18, r18, r23 ; r18 = effective address attempted by instruction
bclr BO_IF_NOT, mrOpflag2
bclr BO_IF_NOT, mrXformIgnoreIdxReg
neg r23, r23
add r18, r18, r23
blr
@ -385,7 +385,7 @@ AlignmentInt
_ori r15, r14, MsrDR
mtcr r26
rlwimi r17, r26, 6, 26, 5
bclr BO_IF_NOT, mrOpflag1
bclr BO_IF_NOT, mrSkipInstLoad
mtmsr r15
lwz r27, 0(r10)
mtmsr r14