commit c5c5b784cbb319a21409fe57574379ae302a3334 Author: Elliot Nunn Date: Sun Nov 19 12:11:07 2017 +0800 Initial commit diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..a02b845 --- /dev/null +++ b/.gitignore @@ -0,0 +1,6 @@ +.DS_Store +BuildResults/ +*.NJ +*.tool +RomMondo.bin.x +*.dmg diff --git a/BuildResults/ThisFolderMustExist b/BuildResults/ThisFolderMustExist new file mode 100644 index 0000000..e69de29 diff --git a/ConfigInfo.s b/ConfigInfo.s new file mode 100644 index 0000000..6dd5486 --- /dev/null +++ b/ConfigInfo.s @@ -0,0 +1,160 @@ +; ROM version of NKConfigurationInfo struct, based on Mac OS ROM 8=9=10. +; Lives at ROM + 0x30d000 (and other addresses on OldWorld). + +; From start of ConfigInfo to end of LoMemInit = 4k: + + + +; Auto-align fields + + aligning on + + + + import RomTop, RomBtm + import Mac68kRomTop, Mac68kRomBtm + import ExTblTop + import NKTop + import EmTop, EmBtm, EmEntry, EmKernelTrapTable + import OpcodeTblTop, OpcodeTblBtm + + + +ConfigInfo + +; These sums are not checked on NewWorld, but :Tools:ToolSource:RiscLayout.c calcs them anyway + dcb.l 8, 0 ; 000 ; ROMByteCheckSums ; ROM Checksums - one word for each of 8 byte lanes + dcb.l 2, 0 ; 020 ; ROMCheckSum64 ; ROM Checksum - 64 bit sum of doublewords + + dc.l RomTop-ConfigInfo ; 028 ; ROMImageBaseOffset ; Offset of Base of total ROM image + dc.l RomBtm-RomTop ; 02c ; ROMImageSize ; Number of bytes in ROM image + dc.l 0 ; 030 ; ROMImageVersion ; ROM Version number for entire ROM + +; ROM component Info (offsets are from base of ConfigInfo page) + dc.l Mac68kRomTop-ConfigInfo ; 034 ; Mac68KROMOffset ; Offset of base of Macintosh 68K ROM + dc.l Mac68kRomBtm-Mac68kRomTop ; 038 ; Mac68KROMSize ; Number of bytes in Macintosh 68K ROM + + dc.l ExTblTop-ConfigInfo ; 03c ; ExceptionTableOffset ; Offset of base of PowerPC Exception Table Code + dc.l 0xc000 ; 040 ; ExceptionTableSize ; Number of bytes in PowerPC Exception Table Code (generous) + + dc.l RomTop+0x320000-ConfigInfo ; 044 ; HWInitCodeOffset ; Offset of base of Hardware Init Code (no longer exists) + dc.l 0x10000 ; 048 ; HWInitCodeSize ; Number of bytes in Hardware Init Code + + dc.l NKTop-ConfigInfo ; 04c ; KernelCodeOffset ; Offset of base of NanoKernel Code + dc.l 0x10000 ; 050 ; KernelCodeSize ; Number of bytes in NanoKernel Code (too small) + + dc.l EmTop-ConfigInfo ; 054 ; EmulatorCodeOffset ; Offset of base of Emulator Code + dc.l EmBtm-EmTop ; 058 ; EmulatorCodeSize ; Number of bytes in Emulator Code + + dc.l OpcodeTblTop-ConfigInfo ; 05c ; OpcodeTableOffset ; Offset of base of Opcode Table + dc.l OpcodeTblBtm-OpcodeTblTop ; 060 ; OpcodeTableSize ; Number of bytes in Opcode Table + +; Offsets within the Emulator Data Page. + string AsIs +@s dc.b 'NewWorld v1.0' ; 064 ; BootstrapVersion ; Bootstrap loader version info + org @s + 16 + + dc.l 0xf00 ; 074 ; BootVersionOffset ; offset within EmulatorData of BootstrapVersion + dc.l 0x100 ; 078 ; ECBOffset ; offset within EmulatorData of ECB + dc.l 0x070 ; 07c ; IplValueOffset ; offset within EmulatorData of IplValue + +; Offsets within the Emulator Code. + dc.l EmEntry-EmTop ; 080 ; EmulatorEntryOffset ; offset within Emulator Code of entry point + dc.l EmKernelTrapTable-EmTop ; 084 ; KernelTrapTableOffset ; offset within Emulator Code of KernelTrapTable + +; Interrupt Passing Masks. + dc.l 0x00200000 ; 088 ; TestIntMaskInit ; initial value for test interrupt mask + dc.l 0xff9fffff ; 08c ; ClearIntMaskInit ; initial value for clear interrupt mask + dc.l 0x00e00000 ; 090 ; PostIntMaskInit ; initial value for post interrupt mask + dc.l 0x808e0000 ; 094 ; LA_InterruptCtl ; logical address of Interrupt Control I/O page + dc.b 6 ; 098 ; InterruptHandlerKind ; kind of handler to use + + dc.l 0x5fffe000 ; 09c ; LA_InfoRecord ; logical address of InfoRecord page + dc.l 0x68ffe000 ; 0a0 ; LA_KernelData ; logical address of KernelData page + dc.l 0x68fff000 ; 0a4 ; LA_EmulatorData ; logical address of EmulatorData page + dc.l 0x68080000 ; 0a8 ; LA_DispatchTable ; logical address of Dispatch Table + dc.l 0x68060000 ; 0ac ; LA_EmulatorCode ; logical address of Emulator Code + + dc.l LowMemVals-ConfigInfo ; 0b0 ; MacLowMemInitOffset ; offset to list of LowMem addr/data values + + +; +; Then the pagemap init stuff is filled by the trampoline at boot +; + + +; Address Space Mapping + dc.l 0 ; 0b4 ; PageAttributeInit ; default WIMG, PP settings for PTE creation + dc.l 0 ; 0b8 ; PageMapInitSize ; size of page mapping info + dc.l 0 ; 0bc ; PageMapInitOffset ; offset to page mapping info (from base of ConfigInfo) + dc.l 0 ; 0c0 ; PageMapIRPOffset ; offset of InfoRecord map info (from base of PageMap) + dc.l 0 ; 0c4 ; PageMapKDPOffset ; offset of KernelData map info (from base of PageMap) + dc.l 0 ; 0c8 ; PageMapEDPOffset ; offset of EmulatorData map info (from base of PageMap) + + dcb.l 32, 0 ; 0cc ; SegMap32SupInit ; 32 bit mode Segment Map Supervisor space + dcb.l 32, 0 ; 14c ; SegMap32UsrInit ; 32 bit mode Segment Map User space + dcb.l 32, 0 ; 1cc ; SegMap32CPUInit ; 32 bit mode Segment Map CPU space + dcb.l 32, 0 ; 24c ; SegMap32OvlInit ; 32 bit mode Segment Map Overlay mode + + dcb.l 32, 0 ; 2cc ; BATRangeInit ; BAT mapping ranges + + dc.l 0 ; 34c ; BatMap32SupInit ; 32 bit mode BAT Map Supervisor space + dc.l 0 ; 350 ; BatMap32UsrInit ; 32 bit mode BAT Map User space + dc.l 0 ; 354 ; BatMap32CPUInit ; 32 bit mode BAT Map CPU space + dc.l 0 ; 358 ; BatMap32OvlInit ; 32 bit mode BAT Map Overlay mode + +; Only needed for Smurf + dc.l 0 ; 35c ; SharedMemoryAddr ; physical address of Mac/Smurf shared message mem + + dc.l -1 ; 360 ; PA_RelocatedLowMemInit ; physical address of RelocatedLowMem + + dc.l 0x330000 - 0x30d000 ; 364 ; OpenFWBundleOffset ; Offset of base of OpenFirmware PEF Bundle + dc.l 0x20000 ; 368 ; OpenFWBundleSize ; Number of bytes in OpenFirmware PEF Bundle + + dc.l 0xff800000 ; 36c ; LA_OpenFirmware ; logical address of Open Firmware + dc.l 0x00400000 ; 370 ; PA_OpenFirmware ; physical address of Open Firmware + dc.l 0xfff0c000 ; 374 ; LA_HardwarePriv ; logical address of HardwarePriv callback + +; There are still some fixed-location fields here that the Trampoline will populate, +; but the ROM we are building contains just zeros. + + + +; +; Key/value pairs for initializing Low Memory Globals. +; (at the end of ConfigInfo's 4k max size) +; + +; A wee little macro to write LoMem key/value pairs *below* the asm location counter + + macro + LowMem &addr, &val +@b + org @b - 4 + dc.l &val + org @b - 8 + dc.l &addr + org @b - 8 + endm + + +; Sentinel zero at end (late address) of list + + org 4096 - 4 + dc.l 0 + org 4096 - 4 + + +; The table (older RISC versions have more in here.) + + ; The 68k emulator's cold-start vector, points to a "JMP StartBoot" + ; instruction in the 68k ROM header. (Normally this value would be + ; read from the ROM while it was overlaid on RAM at cold start, but + ; why emulate that on a PowerPC?) + + ; SheepShaver patches the 68k reset vector around this location, + ; but assumed offset 0xfd8. + + LowMem 0x00000004, 0xffc0002a + +LowMemVals diff --git a/EasyBuild b/EasyBuild new file mode 100644 index 0000000..0d2a1bc --- /dev/null +++ b/EasyBuild @@ -0,0 +1,5 @@ +Set Parent "`Files -f "{0}" | StreamEdit -d -e '/((Å:)*)¨1([Â:]*)/ Print ¨1'`" +SetDirectory "{Parent}" # too easy + +Make -w > :BuildResults:BuildOut +:BuildResults:BuildOut diff --git a/Emulator.x b/Emulator.x new file mode 100644 index 0000000..06b429a Binary files /dev/null and b/Emulator.x differ diff --git a/Internal/EmulatorPublic.a b/Internal/EmulatorPublic.a new file mode 100644 index 0000000..8765625 --- /dev/null +++ b/Internal/EmulatorPublic.a @@ -0,0 +1,125 @@ +EDP record 0,INCR + + org 0x70 +IplValue ds.w 1 ; 070 ; 68k int level or -1 + + org 0x100 +ContextBlock ds.b 768 ; 100:300 ; Emulator Context Block, ECB; NKv2 ties this to blue task + + org 0xf00 +BootstrapVersion ds.b 16 ; f00:f10 ; Bootstrap loader version info, from ConfigInfo + + endr + + + + + +; Lives in EDP. Keeping a separate record to EDP makes the code nicer. +; Gets called the "system context" +ContextBlock record 0,INCR + +EmpiricalCpuFeatures ds.l 1 ; 000 ; (SPAC) copied from kdp by CreateTask + + org 0x5c +LA_EmulatorKernelTrapTable ds.l 1 + + org 0x84 +LA_EmulatorEntry ds.l 1 ; 084 ; Entry pt of emulator; set by NK Init.s + + org 0x94 +LA_EmulatorData ds.l 1 + + org 0x9c +LA_DispatchTable ds.l 1 + + org 0xa4 +MSR ds.l 1 ; 0a4 ; (SPAC) copied from kdp by CreateTask + + org 0xc4 +MQ ds.l 1 ; 0c4 ; 601 only + ds.l 1 +PriorityShifty ds.l 1 ; 0cc ; if low nybble is empty, InitRDYQs sets this to 2 + + org 0xd4 +XER ds.l 1 +VectorSaveArea ds.l 1 ; 0d8 ; AltiVec hack: vector registers don't fit in CB! + + org 0xe0 +PageInSystemHeap ds.l 1 ; 0e0 ; these are set by StartInit.a:FiddleWithEmulator +OtherPageInSystemHeap ds.l 1 ; 0e4 +FE000000 ds.l 1 ; 0e8 +Zero ds.l 1 ; 0ec + + org 0xfc +CodePtr ds.l 1 ; 0fc ; probably goes in SRR0? + + org 0x100 + ds.l 1 +r0 ds.l 1 ; 104 + ds.l 1 +r1 ds.l 1 ; 10c + ds.l 1 +r2 ds.l 1 ; 114 + ds.l 1 +r3 ds.l 1 ; 11c + ds.l 1 +r4 ds.l 1 ; 124 + ds.l 1 +r5 ds.l 1 ; 12c + ds.l 1 +r6 ds.l 1 ; 134 + ds.l 1 +r7 ds.l 1 ; 13c + ds.l 1 +r8 ds.l 1 ; 144 + ds.l 1 +r9 ds.l 1 ; 14c + ds.l 1 +r10 ds.l 1 ; 154 + ds.l 1 +r11 ds.l 1 ; 15c + ds.l 1 +r12 ds.l 1 ; 164 + ds.l 1 +r13 ds.l 1 ; 16c + ds.l 1 +r14 ds.l 1 ; 174 + ds.l 1 +r15 ds.l 1 ; 17c + ds.l 1 +r16 ds.l 1 ; 184 + ds.l 1 +r17 ds.l 1 ; 18c + ds.l 1 +r18 ds.l 1 ; 194 + ds.l 1 +r19 ds.l 1 ; 19c + ds.l 1 +r20 ds.l 1 ; 1a4 + ds.l 1 +r21 ds.l 1 ; 1ac + ds.l 1 +r22 ds.l 1 ; 1b4 + ds.l 1 +r23 ds.l 1 ; 1bc + ds.l 1 +r24 ds.l 1 ; 1c4 + ds.l 1 +r25 ds.l 1 ; 1cc + ds.l 1 +r26 ds.l 1 ; 1d4 + ds.l 1 +r27 ds.l 1 ; 1dc + ds.l 1 +r28 ds.l 1 ; 1e4 + ds.l 1 +r29 ds.l 1 ; 1ec + ds.l 1 +r30 ds.l 1 ; 1f4 + ds.l 1 +r31 ds.l 1 ; 1fc + +FloatRegisters ds.d 32 ; 200:300 + + endr diff --git a/Internal/InfoRecords.a b/Internal/InfoRecords.a new file mode 100644 index 0000000..35f776b --- /dev/null +++ b/Internal/InfoRecords.a @@ -0,0 +1,553 @@ +;_______________________________________________________________________ +; Configuration Info Record +; Used to pass Configuration information from the Boot Program to the +; NanoKernel for data structure and address mapping initialization. +;_______________________________________________________________________ + +NKConfigurationInfo record 0,increment +ROMByteCheckSums ds.l 8 ; 000 ; ROM Checksums - one word for each of 8 byte lanes +ROMCheckSum64 ds.l 2 ; 020 ; ROM Checksum - 64 bit sum of doublewords + +ROMImageBaseOffset ds.l 1 ; 028 ; Offset of Base of total ROM image +ROMImageSize ds.l 1 ; 02c ; Number of bytes in ROM image +ROMImageVersion ds.l 1 ; 030 ; ROM Version number for entire ROM + +Mac68KROMOffset ds.l 1 ; 034 ; Offset of base of Macintosh 68K ROM +Mac68KROMSize ds.l 1 ; 038 ; Number of bytes in Macintosh 68K ROM + +ExceptionTableOffset ds.l 1 ; 03c ; Offset of base of PowerPC Exception Table Code +ExceptionTableSize ds.l 1 ; 040 ; Number of bytes in PowerPC Exception Table Code + +HWInitCodeOffset ds.l 1 ; 044 ; Offset of base of Hardware Init Code (field moved!) +HWInitCodeSize ds.l 1 ; 048 ; Number of bytes in Hardware Init Code + +KernelCodeOffset ds.l 1 ; 04c ; Offset of base of NanoKernel Code +KernelCodeSize ds.l 1 ; 050 ; Number of bytes in NanoKernel Code + +EmulatorCodeOffset ds.l 1 ; 054 ; Offset of base of Emulator Code +EmulatorCodeSize ds.l 1 ; 058 ; Number of bytes in Emulator Code + +OpcodeTableOffset ds.l 1 ; 05c ; Offset of base of Opcode Table +OpcodeTableSize ds.l 1 ; 060 ; Number of bytes in Opcode Table + +BootstrapVersion ds.b 16 ; 064 ; Bootstrap loader version info +BootVersionOffset ds.l 1 ; 074 ; offset within EmulatorData of BootstrapVersion +ECBOffset ds.l 1 ; 078 ; offset within EmulatorData of ECB +IplValueOffset ds.l 1 ; 07c ; offset within EmulatorData of IplValue + +EmulatorEntryOffset ds.l 1 ; 080 ; offset within Emulator Code of entry point +KernelTrapTableOffset ds.l 1 ; 084 ; offset within Emulator Code of KernelTrapTable + +TestIntMaskInit ds.l 1 ; 088 ; initial value for test interrupt mask +ClearIntMaskInit ds.l 1 ; 08c ; initial value for clear interrupt mask +PostIntMaskInit ds.l 1 ; 090 ; initial value for post interrupt mask +LA_InterruptCtl ds.l 1 ; 094 ; logical address of Interrupt Control I/O page +InterruptHandlerKind ds.b 1 ; 098 ; kind of handler to use + ds.b 3 ; 099 ; filler + +LA_InfoRecord ds.l 1 ; 09c ; logical address of InfoRecord page +LA_KernelData ds.l 1 ; 0a0 ; logical address of KernelData page +LA_EmulatorData ds.l 1 ; 0a4 ; logical address of EmulatorData page +LA_DispatchTable ds.l 1 ; 0a8 ; logical address of Dispatch Table +LA_EmulatorCode ds.l 1 ; 0ac ; logical address of Emulator Code + +MacLowMemInitOffset ds.l 1 ; 0b0 ; offset to list of LowMem addr/data values + +PageAttributeInit ds.l 1 ; 0b4 ; default WIMG/PP settings for PTE creation +PageMapInitSize ds.l 1 ; 0b8 ; size of page mapping info +PageMapInitOffset ds.l 1 ; 0bc ; offset to page mapping info (from base of ConfigInfo) +PageMapIRPOffset ds.l 1 ; 0c0 ; offset of InfoRecord map info (from base of PageMap) +PageMapKDPOffset ds.l 1 ; 0c4 ; offset of KernelData map info (from base of PageMap) +PageMapEDPOffset ds.l 1 ; 0c8 ; offset of EmulatorData map info (from base of PageMap) + +SegMaps +SegMap32SupInit ds.l 32 ; 0cc ; 32 bit mode Segment Map Supervisor space +SegMap32UsrInit ds.l 32 ; 14c ; 32 bit mode Segment Map User space +SegMap32CPUInit ds.l 32 ; 1cc ; 32 bit mode Segment Map CPU space +SegMap32OvlInit ds.l 32 ; 24c ; 32 bit mode Segment Map Overlay mode + +BATRangeInit ds.l 32 ; 2cc ; BAT mapping ranges + +BatMap32SupInit ds.l 1 ; 34c ; 32 bit mode BAT Map Supervisor space +BatMap32UsrInit ds.l 1 ; 350 ; 32 bit mode BAT Map User space +BatMap32CPUInit ds.l 1 ; 354 ; 32 bit mode BAT Map CPU space +BatMap32OvlInit ds.l 1 ; 358 ; 32 bit mode BAT Map Overlay mode + +SharedMemoryAddr ds.l 1 ; 35c ; physical address of Mac/Smurf shared message mem + +PA_RelocatedLowMemInit ds.l 1 ; 360 ; physical address of RelocatedLowMem + +OpenFWBundleOffset ds.l 1 ; 364 ; Offset of base of OpenFirmware PEF Bundle +OpenFWBundleSize ds.l 1 ; 368 ; Number of bytes in OpenFirmware PEF Bundle + +LA_OpenFirmware ds.l 1 ; 36c ; logical address of Open Firmware +PA_OpenFirmware ds.l 1 ; 370 ; physical address of Open Firmware +LA_HardwarePriv ds.l 1 ; 374 ; logical address of HardwarePriv callback + +; Used to stop here, plus 8 bytes for cache block alignment (0x380 bytes). +; Now there be more! + +Debug ds.w 1 ; 378 ; > 256 required for screen log +DebugThreshold equ 257 + + org 0x388 +DebugFlags ds.l 1 ; 388 ; bit 1<< 1 required for screen log +NanodbgrFlagShift equ 0 +NanodbgrFlagBit equ 31 - NanodbgrFlagShift +LogFlagShift equ 1 +LogFlagBit equ 31 - LogFlagShift + + + endr + + + + +;_______________________________________________________________________ +; System Info Record +; +; Used to pass System information from the NanoKernel to user mode +; software. +;_______________________________________________________________________ + +NKSystemInfoPtr equ $5FFFEFF0 ; logical address of NKSystemInfo record +NKSystemInfoVer equ $5FFFEFF4 ; version number of NKSystemInfo record +NKSystemInfoLen equ $5FFFEFF6 ; length of NKSystemInfo record + +NKSystemInfo record 0,increment +PhysicalMemorySize ds.l 1 ; 000, irp+dc0 ; Number of bytes in Physical RAM +UsableMemorySize ds.l 1 ; 004, irp+dc4 ; Number of bytes in Usable RAM +LogicalMemorySize ds.l 1 ; 008, irp+dc8 ; Number of bytes in Logical RAM +HashTableSize ds.l 1 ; 00c, irp+dcc ; Number of bytes in Memory Hash Table + +L2DataCacheTotalSize ds.l 1 ; 010, irp+dd0 ; number of bytes in the L2 Data Cache +L2InstCacheTotalSize ds.l 1 ; 014, irp+dd4 ; number of bytes in the L2 Instruction Cache +L2CombinedCaches ds.w 1 ; 018, irp+dd8 ; 1 <- combined or no cache, 0 <- split cache +L2InstCacheBlockSize ds.w 1 ; 01a, irp+dda ; number of bytes in a Block of the L2 Instruction Cache +L2DataCacheBlockSize ds.w 1 ; 01c, irp+ddc ; number of bytes in a Block of the L2 Data Cache +L2InstCacheAssociativity ds.w 1 ; 01e, irp+dde ; Associativity of the L2 Instruction Cache +L2DataCacheAssociativity ds.w 1 ; 020, irp+de0 ; Associativity of the L2 Data Cache + ds.b 2 ; 022, irp+de2 ; unused + + ds.b 2 ; 024, irp+de4 ; unused +FlashManufacturerCode ds.b 1 ; 026, irp+de6 ; Flash ROM Manufacturer code +FlashDeviceCode ds.b 1 ; 027, irp+de7 ; Flash ROM Device code +FlashStart ds.l 1 ; 028, irp+de8 ; Starting address of Flash ROM +FlashSize ds.l 1 ; 02c, irp+dec ; Number of bytes in Flash ROM + +Bank0Start ds.l 1 ; 030, irp+df0 ; Starting address of RAM bank 0 +Bank0Size ds.l 1 ; 034, irp+df4 ; Number of bytes in RAM bank 0 +Bank1Start ds.l 1 ; 038, irp+df8 ; Starting address of RAM bank 1 +Bank1Size ds.l 1 ; 03c, irp+dfc ; Number of bytes in RAM bank 1 +Bank2Start ds.l 1 ; 040, irp+e00 ; Starting address of RAM bank 2 +Bank2Size ds.l 1 ; 044, irp+e04 ; Number of bytes in RAM bank 2 +Bank3Start ds.l 1 ; 048, irp+e08 ; Starting address of RAM bank 3 +Bank3Size ds.l 1 ; 04c, irp+e0c ; Number of bytes in RAM bank 3 +Bank4Start ds.l 1 ; 050, irp+e10 ; Starting address of RAM bank 4 +Bank4Size ds.l 1 ; 054, irp+e14 ; Number of bytes in RAM bank 4 +Bank5Start ds.l 1 ; 058, irp+e18 ; Starting address of RAM bank 5 +Bank5Size ds.l 1 ; 05c, irp+e1c ; Number of bytes in RAM bank 5 +Bank6Start ds.l 1 ; 060, irp+e20 ; Starting address of RAM bank 6 +Bank6Size ds.l 1 ; 064, irp+e24 ; Number of bytes in RAM bank 6 +Bank7Start ds.l 1 ; 068, irp+e28 ; Starting address of RAM bank 7 +Bank7Size ds.l 1 ; 06c, irp+e2c ; Number of bytes in RAM bank 7 +Bank8Start ds.l 1 ; 070, irp+e30 ; Starting address of RAM bank 8 +Bank8Size ds.l 1 ; 074, irp+e34 ; Number of bytes in RAM bank 8 +Bank9Start ds.l 1 ; 078, irp+e38 ; Starting address of RAM bank 9 +Bank9Size ds.l 1 ; 07c, irp+e3c ; Number of bytes in RAM bank 9 +Bank10Start ds.l 1 ; 080, irp+e40 ; Starting address of RAM bank 10 +Bank10Size ds.l 1 ; 084, irp+e44 ; Number of bytes in RAM bank 10 +Bank11Start ds.l 1 ; 088, irp+e48 ; Starting address of RAM bank 11 +Bank11Size ds.l 1 ; 08c, irp+e4c ; Number of bytes in RAM bank 11 +Bank12Start ds.l 1 ; 090, irp+e50 ; Starting address of RAM bank 12 +Bank12Size ds.l 1 ; 094, irp+e54 ; Number of bytes in RAM bank 12 +Bank13Start ds.l 1 ; 098, irp+e58 ; Starting address of RAM bank 13 +Bank13Size ds.l 1 ; 09c, irp+e5c ; Number of bytes in RAM bank 13 +Bank14Start ds.l 1 ; 0a0, irp+e60 ; Starting address of RAM bank 14 +Bank14Size ds.l 1 ; 0a4, irp+e64 ; Number of bytes in RAM bank 14 +Bank15Start ds.l 1 ; 0a8, irp+e68 ; Starting address of RAM bank 15 +Bank15Size ds.l 1 ; 0ac, irp+e6c ; Number of bytes in RAM bank 15 +Bank16Start ds.l 1 ; 0b0, irp+e70 ; Starting address of RAM bank 16 +Bank16Size ds.l 1 ; 0b4, irp+e74 ; Number of bytes in RAM bank 16 +Bank17Start ds.l 1 ; 0b8, irp+e78 ; Starting address of RAM bank 17 +Bank17Size ds.l 1 ; 0bc, irp+e7c ; Number of bytes in RAM bank 17 +Bank18Start ds.l 1 ; 0c0, irp+e80 ; Starting address of RAM bank 18 +Bank18Size ds.l 1 ; 0c4, irp+e84 ; Number of bytes in RAM bank 18 +Bank19Start ds.l 1 ; 0c8, irp+e88 ; Starting address of RAM bank 19 +Bank19Size ds.l 1 ; 0cc, irp+e8c ; Number of bytes in RAM bank 19 +Bank20Start ds.l 1 ; 0d0, irp+e90 ; Starting address of RAM bank 20 +Bank20Size ds.l 1 ; 0d4, irp+e94 ; Number of bytes in RAM bank 20 +Bank21Start ds.l 1 ; 0d8, irp+e98 ; Starting address of RAM bank 21 +Bank21Size ds.l 1 ; 0dc, irp+e9c ; Number of bytes in RAM bank 21 +Bank22Start ds.l 1 ; 0e0, irp+ea0 ; Starting address of RAM bank 22 +Bank22Size ds.l 1 ; 0e4, irp+ea4 ; Number of bytes in RAM bank 22 +Bank23Start ds.l 1 ; 0e8, irp+ea8 ; Starting address of RAM bank 23 +Bank23Size ds.l 1 ; 0ec, irp+eac ; Number of bytes in RAM bank 23 +Bank24Start ds.l 1 ; 0f0, irp+eb0 ; Starting address of RAM bank 24 +Bank24Size ds.l 1 ; 0f4, irp+eb4 ; Number of bytes in RAM bank 24 +Bank25Start ds.l 1 ; 0f8, irp+eb8 ; Starting address of RAM bank 25 +Bank25Size ds.l 1 ; 0fc, irp+ebc ; Number of bytes in RAM bank 25 +EndOfBanks +MaxBanks equ 26 ; Pads out to old struct len (cache block), more to come... + + ; Interrupt Support Data +IntCntrBaseAddr ds.l 1 ; 100, irp+ec0 ; Interrupt Controller Base Address (variable is used since this is a PCI Dev and address is relocatable) +IntPendingReg ds.l 2 ; 104, irp+ec4 ; Data of current interrupts pending register + + ; These fields were added to report information about tightly-coupled L2 caches. + ; The inline L2 information should be used in situations where there is a CPU + ; card L2 cache that can coexist with a motherboard L2. + +InlineL2DSize ds.l 1 ; 10c, irp+ecc ; Size of in-line L2 Dcache +InlineL2ISize ds.l 1 ; 110, irp+ed0 ; Size of in-line L2 Icache +InlineL2Combined ds.w 1 ; 114, irp+ed4 ; 1 <- combined or no cache, 0 <- split cache +InlineL2IBlockSize ds.w 1 ; 116, irp+ed6 ; Block size of in-line I L2 cache +InlineL2DBlockSize ds.w 1 ; 118, irp+ed8 ; Block size of in-line D L2 cache +InlineL2IAssoc ds.w 1 ; 11a, irp+eda ; Associativity of L2 I +InlineL2DAssoc ds.w 1 ; 11c, irp+edc ; Associativity of L2 D + ds.w 1 ; 11e, irp+ede ; pad + + ; More Interrupt Support Data +IntsCompleted ds.l 2 ; 120, irp+ee0 ; completed interrupts + + align 5 ; pad to nice cache block alignment + endr + + + + +;_______________________________________________________________________ +; Diagnostic Info Record +; +; Used to pass Diagnostic information from the power on Diagnostics to +; the NanoKernel, and from the NanoKernel to user mode software. +;_______________________________________________________________________ + +NKDiagInfoPtr equ $5FFFEFE8 ; logical address of DiagnosticInfo record +NKDiagInfoVer equ $5FFFEFEC ; version number of DiagnosticInfo record +NKDiagInfoLen equ $5FFFEFEE ; length of DiagnosticInfo record + +NKDiagInfo record 0,increment +BankMBFailOffset ds.l 1 ; 000 ; Mother Board RAM failure code +BankAFailOffset ds.l 1 ; 004 ; Bank A RAM failure code +BankBFailOffset ds.l 1 ; 008 ; Bank B RAM failure code +BankCFailOffset ds.l 1 ; 00c ; Bank C RAM failure code + +BankDFailOffset ds.l 1 ; 010 ; Bank D RAM failure code +BankEFailOffset ds.l 1 ; 014 ; Bank E RAM failure code +BankFFailOffset ds.l 1 ; 018 ; Bank F RAM failure code +BankGFailOffset ds.l 1 ; 01c ; Bank G RAM failure code + +BankHFailOffset ds.l 1 ; 020 ; Bank H RAM failure code +CacheFailOffset ds.l 1 ; 024 ; cache failure code +LongBootParamOffset ds.l 1 ; 028 ; on longBoot this is where the params will be +POSTTraceOffset ds.l 1 ; 02c ; this tells us what route the POST took + +POSTOldWarmOffset ds.l 1 ; 030 ; logged address of old warmstart flag +POSTOldLongOffset ds.l 1 ; 034 ; logged address of old long boot flag +POSTOldGlobbOffset ds.l 1 ; 038 ; logged address of old Diagnostic Info Record +POSTOldParamOffset ds.l 1 ; 03c ; the params from the old diag globb + +POSTStartRTCUOffset ds.l 1 ; 040 ; PPC Real Time Clock Upper at start of POST +POSTStartRTCLOffset ds.l 1 ; 044 ; PPC Real Time Clock Lower at start of POST +POSTEndRTCUOffset ds.l 1 ; 048 ; PPC Real Time Clock Upper at end of POST +POSTEndRTCLOffset ds.l 1 ; 04c ; PPC Real Time Clock Lower at end of POST + +POSTTestTypeOffset ds.l 1 ; 050 ; when long RAM tests fail test type which failed is put here +POSTError2Offset ds.l 1 ; 054 ; result codes from tests +POSTError3Offset ds.l 1 ; 058 ; result codes from tests +POSTError4Offset ds.l 1 ; 05c ; result codes from tests + +RegistersStore ds.b 140 ; 060 ; store all 60x registers here, still fit into 256 bytes size. + +; Everything BEFORE here is new (hence the funny-sized register store) + +DiagPOSTResult2 ds.l 1 ; 0ec ; POST results +DiagPOSTResult1 ds.l 1 ; 0f0 ; POST results +DiagLongBootSig ds.l 1 ; 0f4 ; Burn in restart flag +DiagWarmStartHigh ds.l 1 ; 0f8 ; First long of native warm start (WLSC) +DiagWarmStartLow ds.l 1 ; 0fc ; Second long of native warm start (SamB) + align 5 ; pad to nice cache block alignment + endr + + + + +;_______________________________________________________________________ +; NanoKernel Info Record +; +; Used to pass NanoKernel statistics from the NanoKernel to user mode +; software. +;_______________________________________________________________________ + +NKNanoKernelInfoPtr equ $5FFFEFE0 ; logical address of NanoKernelInfo record +NKNanoKernelInfoVer equ $5FFFEFE4 ; version number of NanoKernelInfo record +NKNanoKernelInfoLen equ $5FFFEFE6 ; length of NanoKernelInfo record + +NKNanoKernelInfo record 0,increment +ExceptionCauseCounts ds.l 32 ; 000, kdp+dc0 ; counters per exception cause +NanoKernelCallCounts ds.l 16 ; 080, kdp+e40 ; counters per NanoKernel call +ExternalIntCount ds.l 1 ; 0c0, kdp+e80 ; count of External Interrupts +MisalignmentCount ds.l 1 ; 0c4, kdp+e84 ; count of Misalignment Interrupts +FPUReloadCount ds.l 1 ; 0c8, kdp+e88 ; count of FPU reloads on demand +DecrementerIntCount ds.l 1 ; 0cc, kdp+e8c ; count of Decrementer Interrupts +QuietWriteCount ds.l 1 ; 0d0, kdp+e90 ; count of Writes to Quiet Read-Only memory +HashTableCreateCount ds.l 1 ; 0d4, kdp+e94 ; count of Hash Table Entry creations +HashTableDeleteCount ds.l 1 ; 0d8, kdp+e98 ; count of Hash Table Entry deletions +HashTableOverflowCount ds.l 1 ; 0dc, kdp+e9c ; count of Hash Table Entry overflows +EmulatedUnimpInstCount ds.l 1 ; 0e0, kdp+ea0 ; count of Emulated unimplemented instructions +NCBPtrCacheMissCount ds.l 1 ; 0e4, kdp+ea4 ; count of NCB Pointer cache misses +ExceptionPropagateCount ds.l 1 ; 0e8, kdp+ea8 ; count of Exceptions propagated to system +ExceptionForcedCount ds.l 1 ; 0ec, kdp+eac ; count of Exceptions forced to system +SysContextCpuTime ds.l 2 ; 0f0, kdp+eb0 ; CPU Time used by System Context +AltContextCpuTime ds.l 2 ; 0f8, kdp+eb4 ; CPU Time used by Alternate Context + +; This stuff is new (starts at 0x100) + +blueProcessID ds.l 1 ; 100, kdp+ec0 ; ID of the blue process. +blueTaskID ds.l 1 ; 104, kdp+ec4 ; ID of the blue task. +pageQueueID ds.l 1 ; 108, kdp+ec8 ; ID of the page fault queue. +TaskCount ds.l 1 ; 10c, kdp+ecc ; Number of tasks. +FreePoolExtendCount ds.l 1 ; 110, kdp+ed0 ; Number of pages given to the nanokernel. + +;rsrv1 ds.l 3 ; 114, kdp+ed4 ; reserved??? + +; My additions + + org 0x11c +ConfigFlags ds.l 1 ; 11c, kdp+edc ; includes ScreenConsole ... TODO put flag equs here +NanodbgrFlagShift equ 1 +NanodbgrFlagBit equ 31 - NanodbgrFlagShift +LogFlagShift equ 3 +LogFlagBit equ 31 - LogFlagShift +; bit 31 always set on replacement, bit 27 set on replacement with ROM 2.7f3 or later + + org 0x128 +VMDispatchCountTblPtr ds.l 1 ; 128, kdp+ee8 + ds.l 1 + ds.l 1 +MPDispatchCountTblPtr ds.l 1 ; 134, kdp+ef4 ; ??????? +AddrSpcSetCtr ds.l 1 ; 138, kdp+ef8 ; incremented by SetAddrSpcRegisters +IDCtr ds.l 1 ; 13c, kdp+efc + + org 0x160 + endr + + + + +;_______________________________________________________________________ +; Processor Info Record +; +; Used to pass Processor information from the NanoKernel to user mode +; software. +;_______________________________________________________________________ + +NKProcessorInfoPtr equ $5FFFEFD8 ; logical address of ProcessorInfo record +NKProcessorInfoVer equ $5FFFEFDC ; version number of ProcessorInfo record +NKProcessorInfoLen equ $5FFFEFDE ; length of ProcessorInfo record + +NKProcessorInfo record 0,increment +ProcessorVersionReg ds.l 1 ; 000, kdp+f20 ; contents of the PVR special purpose register +CpuClockRateHz ds.l 1 ; 004, kdp+f24 ; CPU Clock frequency +BusClockRateHz ds.l 1 ; 008, kdp+f28 ; Bus Clock frequency +DecClockRateHz ds.l 1 ; 00c, kdp+f2c ; Decrementer Clock frequency + +Ovr +PageSize ds.l 1 ; 010, kdp+f30 ; number of bytes in a memory page +DataCacheTotalSize ds.l 1 ; 014, kdp+f34 ; number of bytes in the Data Cache +InstCacheTotalSize ds.l 1 ; 018, kdp+f38 ; number of bytes in the Instruction Cache +CoherencyBlockSize ds.w 1 ; 01c, kdp+f3c ; number of bytes in a Coherency Block +ReservationGranuleSize ds.w 1 ; 01e, kdp+f3e ; number of bytes in a Reservation Granule +CombinedCaches ds.w 1 ; 020, kdp+f40 ; 1 <- combined or no cache, 0 <- split cache +InstCacheLineSize ds.w 1 ; 022, kdp+f42 ; number of bytes in a Line of the Instruction Cache +DataCacheLineSize ds.w 1 ; 024, kdp+f44 ; number of bytes in a Line of the Data Cache +DataCacheBlockSizeTouch ds.w 1 ; 026, kdp+f46 ; number of bytes in a Block for DCBT DCBTST +InstCacheBlockSize ds.w 1 ; 028, kdp+f48 ; number of bytes in a Block of the Instruction Cache +DataCacheBlockSize ds.w 1 ; 02a, kdp+f4a ; number of bytes in a Block of the Data Cache +InstCacheAssociativity ds.w 1 ; 02c, kdp+f4c ; Associativity of the Instruction Cache +DataCacheAssociativity ds.w 1 ; 02e, kdp+f4e ; Associativity of the Data Cache + +TransCacheTotalSize ds.w 1 ; 030, kdp+f50 ; number of entries in the Translation Cache +TransCacheAssociativity ds.w 1 ; 032, kdp+f52 ; Associativity of the Translation Cache +OvrEnd + +; These fields were added to report information about back-side L2 caches + +ProcessorL2DSize ds.l 1 ; 034, kdp+f54 ; Size of back-side L2 Dcache +ProcessorL2ISize ds.l 1 ; 038, kdp+f58 ; Size of back-side L2 Icache +ProcessorL2Combined ds.w 1 ; 03c, kdp+f5c ; 1 <- combined or no cache, 0 <- split cache +ProcessorL2IBlockSize ds.w 1 ; 03e, kdp+f5e ; Block size of back-side I L2 cache +ProcessorL2DBlockSize ds.w 1 ; 040, kdp+f60 ; Block size of back-side D L2 cache +ProcessorL2IAssoc ds.w 1 ; 042, kdp+f62 ; Associativity of L2 I +ProcessorL2DAssoc ds.w 1 ; 044, kdp+f64 ; Associativity of L2 D + +filler1 ds.w 1 ; 046, kdp+f66 ; align to long + +; ProcessorFlags - Definitions for the processor flags field. These are bit positions, +; as in 1 << hasVMX, and not masks. +hasL2CR equ 0 +hasPLRUL1 equ 1 +hasTAU equ 2 +hasVMX equ 3 +unknownFlag equ 4 +hasExtraBATs equ 5 +ProcessorFlags ds.l 1 ; 048, kdp+f68 ; flags to specify processor features + + align 5 ; pad to nice cache block alignment + + org 0x05e +SetToZero ds.w 1 ; 05e, kdp+f7e ; by same code that sets below +CpuClockRateHzCopy ds.l 1 ; 060, kdp+f80 ; copies by Init.s +BusClockRateHzCopy ds.l 1 ; 064, kdp+f84 ; copies by Init.s +DecClockRateHzCopy ds.l 1 ; 068, kdp+f88 ; copies by Init.s + + endr + + + + +;_______________________________________________________________________ +; Hardware Info Record +; +; Used to pass hardware information from the NanoKernel to user mode +; software. +;_______________________________________________________________________ + +NKHWInfoPtr equ $5FFFEFD0 ; logical address of HWInfo record +NKHWInfoVer equ $5FFFEFD4 ; version number of HWInfo record +NKHWInfoLen equ $5FFFEFD6 ; length of HWInfo record + +NKHWInfo record 0,increment +MacROM_Base ds.l 1 ; 000, irp+f00 ; base address (physical) of Mac ROM +DeviceTreeBase ds.l 1 ; 004, irp+f04 ; base address of the copied device tree properties +UniversalInfoTableBase ds.l 1 ; 008, irp+f08 ; base address of the Universal Info Table +ConfigInfoTableBase ds.l 1 ; 00c, irp+f0c ; base address of the Config Info Table +VectorLookupTable ds.l 1 ; 010, irp+f10 ; base address of the interrupt vector lookup table (short *) +VectorMaskTable ds.l 1 ; 014, irp+f14 ; base address of the interrupt vector mask table (long *) + +OpenPICBaseAddr ds.l 1 ; 018, irp+f18 ; OpenPIC base address + +ISAMaster8259 ds.l 1 ; 01c, irp+f1c ; ISA Master 8259 ports (char *) +ISASlave8259 ds.l 1 ; 020, irp+f20 ; ISA Slave 8259 ports (char *) +InterruptAck8259 ds.l 1 ; 024, irp+f24 ; address to read to ack 8259 interrupt (long *) + + ; interrupt pending bits (actively changing) + +PendingInts ds.l 2 ; 028, irp+f28 ; 64 bits of pending interrupts + + ; some Mac I/O device base addresses + +ADB_Base ds.l 1 ; 030, irp+f30 ; base address of ADB +SCSI_DMA_Base ds.l 1 ; 034, irp+f34 ; base address of SCSI DMA registers + + ; RTAS related stuff + +RTAS_PrivDataArea ds.l 1 ; 038, irp+f38 ; RTAS private data area +MacOS_NVRAM_Offset ds.l 1 ; 03c, irp+f3c ; offset into nvram to MacOS data + +RTAS_NVRAM_Fetch ds.l 1 ; 040, irp+f40 ; token for RTAS NVRAM fetch +RTAS_NVRAM_Store ds.l 1 ; 044, irp+f44 ; token for RTAS NVRAM store +RTAS_Get_Clock ds.l 1 ; 048, irp+f48 ; token for RTAS clock get +RTAS_Set_Clock ds.l 1 ; 04c, irp+f4c ; token for RTAS clock set +RTAS_Restart ds.l 1 ; 050, irp+f50 ; token for RTAS Restart +RTAS_Shutdown ds.l 1 ; 054, irp+f54 ; token for RTAS Shutdown +RTAS_Restart_At ds.l 1 ; 058, irp+f58 ; token for RTAS system startup at specified time +RTAS_EventScan ds.l 1 ; 05c, irp+f5c ; token for RTAS event scan +RTAS_Check_Exception ds.l 1 ; 060, irp+f60 ; token for RTAS check exception +RTAS_Read_PCI_Config ds.l 1 ; 064, irp+f64 ; token for RTAS read PCI config +RTAS_Write_PCI_Config ds.l 1 ; 068, irp+f68 ; token for RTAS write PCI config + + ; SIO interrupt source numbers for the MPIC + +SIOIntVect ds.w 1 ; 06c, irp+f6c ; SIO (8259 cascade vector) vector number +SIOIntBit ds.w 1 ; 06e, irp+f6e ; SIO (8259 cascade vector) bit number + +Signature ds.l 1 ; 070, irp+f70 ; signature for this record ('Hnfo') + + ; more interrupt source numbers + +SpuriousIntVect ds.w 1 ; 074, irp+f74 ; spurious vector number + +CPU_ID ds.w 1 ; 076, irp+f76 ; the ID of this CPU (universal-tables-related) + +SCCAIntVect ds.w 1 ; 078, irp+f78 ; SCC A (non-DMA) vector number +SCCBIntVect ds.w 1 ; 07a, irp+f7a ; SCC B (non-DMA) vector number +SCSIIntVect ds.w 1 ; 07c, irp+f7c ; SCSI vector number +SCSIDMAIntVect ds.w 1 ; 07e, irp+f7e ; SCSI DMA vector number +VIAIntVect ds.w 1 ; 080, irp+f80 ; VIA vector number +VIAIntBit ds.w 1 ; 082, irp+f82 ; VIA bit number +ADBIntVect ds.w 1 ; 084, irp+f84 ; vector number +NMIIntVect ds.w 1 ; 086, irp+f86 ; NMI vector number +NMIIntBit ds.w 1 ; 088, irp+f88 ; NMI bit number + + ; current (actively changing) interrupt handling variables + +ISAPendingInt ds.w 1 ; 08a, irp+f8a ; currently pending ISA/8259 interrupt +CompletedInts ds.b 8 ; 08c, irp+f8c ; completed interrupts + +nkHWInfoFlagSlowMESH equ 1 ; set if fast MESH doesn't work on this box +nkHWInfoFlagAsynchMESH equ 2 ; set if Synchronous MESH doesn't work on this box +nkHWInfoFlagNoCopySWTLB equ 4 ; set if the software TLB walk code for 603 should NOT be copied +HardwareInfoFlags ds.l 1 ; 094, irp+f94 ; 32 bits of flags (see enum above) + +RTAS_Get_PowerOn_Time ds.l 1 ; 098, irp+f98 ; token for RTAS getting time for system startup + + align 5 ; pad to nice cache block alignment (did i get this right?) + endr + + + + +;_______________________________________________________________________ +; Processor State Record +; +; Used to save the state of the processor across sleep. +;_______________________________________________________________________ + +NKProcessorStatePtr equ $5FFFEFC8 ; logical address of ProcessorState record +NKProcessorStateVer equ $5FFFEFCC ; version number of ProcessorState record +NKProcessorStateLen equ $5FFFEFCE ; length of ProcessorState record + +NKProcessorState record 0,increment +saveDBAT0u ds.l 1 ; 000 ; place to store DBAT0U +saveDBAT0l ds.l 1 ; 004 ; place to store DBAT0L +saveDBAT1u ds.l 1 ; 008 ; place to store DBAT1U +saveDBAT1l ds.l 1 ; 00c ; place to store DBAT1L +saveDBAT2u ds.l 1 ; 010 ; place to store DBAT2U +saveDBAT2l ds.l 1 ; 014 ; place to store DBAT2L +saveDBAT3u ds.l 1 ; 018 ; place to store DBAT3U +saveDBAT3l ds.l 1 ; 01c ; place to store DBAT3L + +saveIBAT0u ds.l 1 ; 020 ; place to store IBAT0U +saveIBAT0l ds.l 1 ; 024 ; place to store IBAT0L +saveIBAT1u ds.l 1 ; 028 ; place to store IBAT1U +saveIBAT1l ds.l 1 ; 02c ; place to store IBAT1L +saveIBAT2u ds.l 1 ; 030 ; place to store IBAT2U +saveIBAT2l ds.l 1 ; 034 ; place to store IBAT2L +saveIBAT3u ds.l 1 ; 038 ; place to store IBAT3U +saveIBAT3l ds.l 1 ; 03c ; place to store IBAT3L + +saveSPRG0 ds.l 1 ; 040 ; place to store SPRG0 +saveSPRG1 ds.l 1 ; 044 ; place to store SPRG1 +saveSPRG2 ds.l 1 ; 048 ; place to store SPRG2 +saveSPRG3 ds.l 1 ; 04c ; place to store SPRG3 + +saveL2CR ds.l 1 ; 050 ; place to store Arthur's L2CR + +saveSRR0 ds.l 1 ; 054 ; place to store SRR0 +saveSRR1 ds.l 1 ; 058 ; place to store SRR1 +saveTBU ds.l 1 ; 05c ; place to store TBU +saveTBL ds.l 1 ; 060 ; place to store TBL +saveHID0 ds.l 1 ; 064 ; place to store HID0 +saveDEC ds.l 1 ; 068 ; place to store DEC +saveMSR ds.l 1 ; 06c ; place to store MSR +saveSDR1 ds.l 1 ; 070 ; place to store SDR1 + + ; saveKernelDataPtr needs to always be right after saveReturnAddr + ; because of how the code works. DO NOT CHANGE THIS ORDERING! + +saveReturnAddr ds.l 1 ; 074 ; place to store the addr to jump to. +saveKernelDataPtr ds.l 1 ; 078 ; place to store the KernelDataPtr +saveContextPtr ds.l 1 ; 07c ; place to store the ContextPtr + endr diff --git a/Internal/NKOpaque.a b/Internal/NKOpaque.a new file mode 100644 index 0000000..5b13cd6 --- /dev/null +++ b/Internal/NKOpaque.a @@ -0,0 +1,544 @@ +; Opaque NanoKernel structures: +; - stored in the NanoKernel pool (not always) +; - associated with a class number and opaque ID (not always) +; - referenced by opaque ID (for MPLibrary's benefit) + + + + + +;_______________________________________________________________________ +; ID CLASS 1: PROCESS +; (size: 32b, thud command: id -p) +; +; The NanoKernel's internal representation of a cooperative process +; within the blue environment. Processes and tasks have a many-to-one +; relationship. +; +; There is a special 'blue' process that owns the blue task and all +; the CPU idle tasks. +;_______________________________________________________________________ + +Process record 0,INCR + +kIDClass equ 1 +kSignature equ 'PROC' + +;_______________________ +; Fields +;_______________________ + +ID ds.l 1 ; 00 +Signature ds.l 1 ; 04 ; 'PROC' +Unused ds.l 1 ; 08 ; MPCall_5 does something here +SystemAddressSpaceID ds.l 1 ; 0c ; set by Init.s after addrspc creation +TaskCount ds.l 1 ; 10 ; incremented by CreateTask +SystemAddressSpacePtr ds.l 1 ; 14 +AddressSpaceCount ds.l 1 ; 18 ; incremented by NKCreateAddressSpaceSub + ds.l 1 ; 1c + +Size equ * + endr + + + + +;_______________________________________________________________________ +; ID CLASS 2: TASK +; (size: 1k, thud command: id -t) +; +; What the MPLibrary and NanoKernel call the unit of multitasking. +; (Remember that 'Thread' and 'Process' were taken.) +; +; Contains space for a ContextBlock in the style of the ECB, but +; blue's ContextBlockPtr is redirected to the ECB. +;_______________________________________________________________________ + +Task record 0,INCR + +kIDClass equ 2 +kSignature equ 'TASK' + +;_______________________ +; Task priorities +;_______________________ + +kCriticalPriority equ 0 +kLatencyProtectPriority equ 1 +kNominalPriority equ 2 +kIdlePriority equ 3 + +;_______________________ +; Fields +;_______________________ + +ID ds.l 1 ; 000 +Signature ds.l 1 ; 004 +QueueMember ds.l 4 ; 008:018 ; a task is always a member of a queue, e.g. the RDYQ +MysteryByte1 ds.b 1 ; 018 ; CreateTask sets 0 by default (blue = 2) +Priority ds.b 1 ; 019 ; CreateTask sets 2 by default +MysteryHalf ds.w 1 ; 01a +Weight ds.l 1 ; 01c ; default is 100, blue gets 200, idle gets 1 + ds.l 1 ; 020 + ds.l 1 ; 024 + ds.l 1 ; 028 + ds.l 1 ; 02c + ds.l 1 ; 030 + ds.l 1 ; 034 + ds.l 1 ; 038 + ds.l 1 ; 03c + ds.l 1 ; 040 + ds.l 1 ; 044 + ds.l 1 ; 048 + ds.l 1 ; 04c + ds.l 1 ; 050 + ds.l 1 ; 054 + ds.l 1 ; 058 + ds.l 1 ; 05c +ProcessID ds.l 1 ; 060 +ThingThatAlignVecHits ds.l 1 ; 064 ; IntAlignment is interested in bit 9, MPCall 116 in bit 15 + ds.l 1 ; 068 +OwningProcessPtr ds.l 1 ; 06c +AddressSpacePtr ds.l 1 ; 070 ; borrowed from PROC argument to CreateTask +Name ds.l 1 ; 074 ; 'blue', creator of owning cooperative process, etc +CpuID ds.l 1 ; 078 + ds.l 1 ; 07c +CreateTime3 ds.d 1 ; 080 +ContextBlockPtr ds.l 1 ; 088 ; points internally by default, and to EDP.ECB in blue +VectorSaveArea ds.l 1 ; 08c + ds.l 1 ; 090 + ds.l 1 ; 094 + ds.l 1 ; 098 +NotificationPtr ds.l 1 ; 09c +SemaphoreLLL ds.l 4 ; 0a0:0b0 +Zero ds.l 1 ; 0b0 +One ds.l 1 ; 0b4 + ds.l 1 ; 0b8 + ds.l 1 ; 0bc +Zero1 ds.l 1 ; 0c0 +Zero2 ds.l 1 ; 0c4 +CreateTime1 ds.d 1 ; 0c8 +CreateTime2 ds.d 1 ; 0d0 + ds.l 1 ; 0d8 + ds.l 1 ; 0dc +Zero3 ds.l 1 ; 0e0 +Zero4 ds.l 1 ; 0e4 +Zero5 ds.l 1 ; 0e8 + ds.l 1 ; 0ec +YellowVecTblPtr ds.l 1 ; 0f0 + ds.l 1 ; 0f4 + ds.l 1 ; 0f8 + ds.l 1 ; 0fc +ContextBlock ds.b 768 ; 100:400 ; like the EDP's Emulator Context Block -- unsure of size + +Size equ * + endr + + + + +;_______________________________________________________________________ +; ID CLASS 3: TIMER +; (size: 64b, thud command: id -tm) +; +;_______________________________________________________________________ + +Timer record 0,INCR + +kIDClass equ 3 +kSignature equ 'TIME' + +;_______________________ +; Fields +;_______________________ + +ID ds.l 1 ; 00 +Signature ds.l 1 ; 04 + ds.l 1 ; 08 + ds.l 1 ; 0c +ProcessID ds.l 1 ; 10 + ds.l 1 ; 14 + ds.l 1 ; 18 + ds.l 1 ; 1c + ds.l 1 ; 20 + ds.l 1 ; 24 + ds.l 1 ; 28 + ds.l 1 ; 2c + ds.l 1 ; 30 + ds.l 1 ; 34 + ds.l 1 ; 38 + ds.l 1 ; 3c + +Size equ * + endr + + + + +;_______________________________________________________________________ +; ID CLASS 4: QUEUE +; (size: 52b, thud command: id -q) +; +;_______________________________________________________________________ + +Queue record 0,INCR + +kIDClass equ 4 + +;_______________________ +; Fields +;_______________________ + +LLL ds.l 4 ; 00:10 + ds.l 4 ; 10:20 +ProcessID ds.l 1 ; 20 + ds.l 1 ; 24 + ds.l 1 ; 28 + ds.l 1 ; 2c + ds.l 1 ; 30 + +Size equ * + endr + + + +ReadyQueue record 0,INCR + +LLL ds.l 4 ; 00:10 ; nothing fancy +Counter ds.l 1 ; 10 ; InitRDYQs sets, TaskReadyAsNext bumps +TotalWeight ds.l 1 ; 14 ; divide available time by these +Timecake ds.d 1 ; 18 ; period of ~1ms, 8ms, 64ms, 512ms + + + org 0x20 +; Constants +kSignature equ 'RDYQ' + + endr + + + + +kTimerQueueSignature equ 'TMRQ' +kDelayQueueSignature equ 'DLYQ' +kDbugQueueSignature equ 'DBUG' +kPageQueueSignature equ 'PAGQ' +kNotQueueSignature equ 'NOTQ' +kSemaQueueSignature equ 'SEMQ' + + + + +;_______________________________________________________________________ +; ID CLASS 5: SEMAPHORE +; (size: 32b, thud command: id -s) +; +;_______________________________________________________________________ + +Semaphore record 0,INCR + +kIDClass equ 5 +kSignature equ 'SEMA' + +;_______________________ +; Fields +;_______________________ + +LLL ds.l 4 ; 00:10 + ds.l 1 ; 10 + ds.l 1 ; 14 +ProcessID ds.l 1 ; 18 + ds.l 1 ; 1c + +Size equ * + endr + + + + +;_______________________________________________________________________ +; ID CLASS 6: CRITICAL REGION +; (size: 36b, thud command: id -r) +; +;_______________________________________________________________________ + +CriticalRegion record 0,INCR + +kIDClass equ 6 +kSignature equ 'CRGN' + +;_______________________ +; Fields +;_______________________ + +LLL ds.l 4 ; 00:10 +ProcessID ds.l 4 ; 10:20 ; lll.freeform is the field? + ds.l 1 ; 20 + +Size equ * + endr + + + + +;_______________________________________________________________________ +; ID CLASS 7: CPU +; (size: 32+800+128 = 960b, thud command: id -c) +; +;_______________________________________________________________________ + +CPU record 0,INCR + +kIDClass equ 7 +kSignature equ 'CPU ' + +;_______________________ +; Fields +;_______________________ + +ID ds.l 1 ; 00 +Signature ds.l 1 ; 04 +CgrpList ds.l 4 ; 08:18 +Eff ds.l 1 ; 18 ; contains 0x0000000f +IdleTaskPtr ds.l 1 ; 1c + +EWABase ds.b 800 ; negative-indexed parts of EWA +EWA ds.b 128 ; positive-indexed parts of EWA + +Size equ * + endr + + + + + +;_______________________________________________________________________ +; ID CLASS 8: ADDRESS SPACE +; (size: 192b, thud command: id -sp) +; +;_______________________________________________________________________ + +AddressSpace record 0,INCR + +kIDClass equ 8 +kSignature equ 'SPAC' + +;_______________________ +; Fields +;_______________________ + +ID ds.l 1 ; 00 +Signature ds.l 1 ; 04 + ds.l 1 ; 08 +TaskCount ds.l 1 ; 0c ; incremented by CreateTask +RsrvList ds.l 4 ; 10:20 ; LLL +AreaList ds.l 4 ; 20:30 ; LLL +SRs ds.l 16 ; 30:70 ; segment register values +ParentCoherenceSpecialPtr ds.l 1 ; 70 ; SpecialPtr of owning cgrp (in list owned by Cpu) +ProcessID ds.l 1 ; 74 ; ID of owning PROC + ds.l 1 ; 78 + ds.l 1 ; 7c +BATs +BAT0U ds.l 1 ; 80 +BAT0L ds.l 1 ; 84 +BAT1U ds.l 1 ; 88 +BAT1L ds.l 1 ; 8c +BAT2U ds.l 1 ; 90 +BAT2L ds.l 1 ; 94 +BAT3U ds.l 1 ; 98 +BAT3L ds.l 1 ; 9c +ExtraBATs ; the flag that enables these is never set? +ExtraBAT0U ds.l 1 ; a0 +ExtraBAT0L ds.l 1 ; a4 +ExtraBAT1U ds.l 1 ; a8 +ExtraBAT1L ds.l 1 ; ac +ExtraBAT2U ds.l 1 ; b0 +ExtraBAT2L ds.l 1 ; b4 +ExtraBAT3U ds.l 1 ; b8 +ExtraBAT3L ds.l 1 ; bc + +Size equ * + endr + + + + +;_______________________________________________________________________ +; ID CLASS 9: EVENT GROUP +; (size: 32b, thud command: id -e) +; +;_______________________________________________________________________ + +EventGroup record 0,INCR + +kIDClass equ 9 +kSignature equ 'EVNT' + +;_______________________ +; Fields +;_______________________ + +LLL ds.l 4 ; 00:10 ; first field is ID + ds.l 1 ; 10 +ProcessID ds.l 1 ; 14 + ds.l 1 ; 18 ; contains 1-8 +/- 16 + ds.l 1 ; 1c + +Size equ * + endr + + + + +;_______________________________________________________________________ +; ID CLASS 10: COHERENCE GROUP +; (size: 88b, thud command: id -cg) +; +;_______________________________________________________________________ + +CoherenceGroup record 0,INCR + +kIDClass equ 10 +kSignature equ 'CGRP' + +;_______________________ +; Fields +;_______________________ + +LLL ds.l 4 ; 00:10 ; element in CpuStructs list of cgrps +GRPSList ds.l 4 ; 10:20 ; my own list of GRPSes (what are they?) +CpuCount ds.l 1 ; 20 +ScheduledCpuCount ds.l 1 ; 24 + ds.l 1 ; 28 + ds.l 1 ; 2c + ds.l 1 ; 30 + ds.l 1 ; 34 + ds.l 1 ; 38 + ds.l 1 ; 3c + ds.l 1 ; 40 + ds.l 1 ; 44 +Incrementer ds.l 1 ; 48 ; number of NKCreateAddressSpaceSub calls % 1M + ds.l 1 ; 4c + ds.l 1 ; 50 + ds.l 1 ; 54 + +Size equ * + endr + + + + +;_______________________________________________________________________ +; ID CLASS 11: AREA +; (size: 160b, thud command: id -a) +; +; A contiguous region of effective addresses with similar properties. +;_______________________________________________________________________ + +Area record 0,INCR + +kIDClass equ 11 +kSignature equ 'AREA' + +;_______________________ +; Fields +;_______________________ + +ID ds.l 1 ; 00 +Signature ds.l 1 ; 04 +TwoFiftySix ds.l 1 ; 08 +ProcessID ds.l 1 ; 0c +AddressSpaceID ds.l 1 ; 10 + ds.l 1 ; 14 + ds.l 1 ; 18 + ds.l 1 ; 1c + ds.l 1 ; 20 +LogicalBase ds.l 1 ; 24 +LogicalBase2 ds.l 1 ; 28 +Length ds.l 1 ; 2c ; in actual bytes! +Zero ds.l 1 ; 30 + ds.l 1 ; 34 +Length2 ds.l 1 ; 38 + ds.l 1 ; 3c + ds.l 1 ; 40 + ds.l 1 ; 44 + ds.l 1 ; 48 + ds.l 1 ; 4c + ds.l 1 ; 50 +LLL ds.l 4 ; 54:64 ; member of address space + ds.l 1 ; 64 + ds.l 1 ; 68 +AddressSpacePtr ds.l 1 ; 6c + ds.l 1 ; 70 + ds.l 1 ; 74 + ds.l 1 ; 78 + ds.l 1 ; 7c + ds.l 1 ; 80 + ds.l 1 ; 84 + ds.l 1 ; 88 + ds.l 1 ; 8c + ds.l 1 ; 90 + ds.l 1 ; 94 + ds.l 1 ; 98 + ds.l 1 ; 9c + +Size equ * + endr + + + + +;_______________________________________________________________________ +; ID CLASS 12: NOTIFICATION +; (size: 40b, thud command: id -n) +; +;_______________________________________________________________________ + +Notification record 0,INCR + +kIDClass equ 12 +kSignature equ 'KNOT' + +;_______________________ +; Fields +;_______________________ + + ds.l 1 ; 00 +Signature ds.l 1 ; 04 +ProcessID ds.l 1 ; 08 + ds.l 1 ; 0c + ds.l 1 ; 10 + ds.l 1 ; 14 + ds.l 1 ; 18 + ds.l 1 ; 1c + ds.l 1 ; 20 + ds.l 1 ; 24 + +Size equ * + endr + + + + +;_______________________________________________________________________ +; ID CLASS 13: CONSOLE LOG +; (size: 16b, thud command: id -nc) +; +; Never seen one in the wild -- must have been in debug builds. +;_______________________________________________________________________ + +ConsoleLog record 0,INCR + +kIDClass equ 13 + +;_______________________ +; Fields +;_______________________ + + ds.l 1 ; 00 + ds.l 1 ; 04 +ProcessID ds.l 1 ; 08 + ds.l 1 ; 0c + +Size equ * + endr diff --git a/Internal/NKPublic.a b/Internal/NKPublic.a new file mode 100644 index 0000000..f63a689 --- /dev/null +++ b/Internal/NKPublic.a @@ -0,0 +1,1001 @@ +;_______________________________________________________________________ +; Data structures internal to the NanoKernel +;_______________________________________________________________________ + +;_______________________________________________________________________ +; NOTE: DECLARING BIT FIELDS +; +; Bit fields get defined inside a record only in order to give them a +; namespace (e.g. MSR_IP). The _bitEqu macro is used to produce three +; equates per bit: +; (name) = the bit's place value +; (name)bit = the bit's PowerPC index (0 is leftmost) +; (name)shift = the bit's 68k index (0 is rightmost) +;_______________________________________________________________________ + + macro + _bitEqu &name, &bit +&name equ 1 << (31-&bit) +&name.bit equ &bit +&name.shift equ 31 - &bit + endm + + + + +;_______________________________________________________________________ +; INFORECORD PAGE +; +; Lives at 5fffe000 on most (all?) PowerPC Macs. The public-ish part +; is the InfoRecord, which lives in the upper 64 bytes. This contains +; logical pointers, sizes and versions for the data structures that +; are shared between the NanoKernel and userspace. See +; PPCInfoRecordsPriv.s for the contents of these structures. +; +;_______________________________________________________________________ + +IRP record 0xdc0,INCR + +SystemInfo ds.l 80 ; dc0:f00 ; other NK versions keep their structures elsewhere, +HWInfo ds.l 48 ; f00:fc0 ; so always use InfoRecord to find them from userspace +InfoRecord ds.l 16 ; fc0:1000 ; the public part + + endr + + + +; Some InfoRecord fields are obliquely referenced from PPCInfoRecordsPriv.h +; (e.g. nkSystemInfoPtr = 0x5FFFEFF0) + +InfoRecord record 0,INCR +InfoRecordPtr ds.l 1 ; 00 kdp/irp+fc0 ; set in kdp, copied to irp + +Zero ds.l 1 ; 04 kdp/irp+fc4 ; const + +NKProcessorStatePtr ds.l 1 ; 08 kdp/irp+fc8 ; in PSA +NKProcessorStateVer ds.w 1 ; 0c kdp/irp+fcc ; const +NKProcessorStateLen ds.w 1 ; 0e kdp/irp+fce ; const + +NKHWInfoPtr ds.l 1 ; 10 kdp/irp+fd0 ; in IRP +NKHWInfoVer ds.w 1 ; 14 kdp/irp+fd4 ; const +NKHWInfoLen ds.w 1 ; 16 kdp/irp+fd6 ; const + +NKProcessorInfoPtr ds.l 1 ; 18 kdp/irp+fd8 ; in KDP +NKProcessorInfoVer ds.w 1 ; 1c kdp/irp+fdc ; const +NKProcessorInfoLen ds.w 1 ; 1e kdp/irp+fde ; const + +NKNanoKernelInfoPtr ds.l 1 ; 20 kdp/irp+fe0 ; in KDP +NKNanoKernelInfoVer ds.w 1 ; 24 kdp/irp+fe4 ; BCD +NKNanoKernelInfoLen ds.w 1 ; 26 kdp/irp+fe6 ; const + +NKDiagInfoPtr ds.l 1 ; 28 kdp/irp+fe8 ; in PSA +NKDiagInfoVer ds.w 1 ; 2c kdp/irp+fec ; const +NKDiagInfoLen ds.w 1 ; 2e kdp/irp+fee ; const + +NKSystemInfoPtr ds.l 1 ; 30 kdp/irp+ff0 ; in IRP +NKSystemInfoVer ds.w 1 ; 34 kdp/irp+ff4 ; const +NKSystemInfoLen ds.w 1 ; 36 kdp/irp+ff6 ; const + +NKProcessorInfoPtr2 ds.l 1 ; 38 kdp/irp+ff8 ; in KDP (same as above) +NKProcessorInfoVer2 ds.w 1 ; 3c kdp/irp+ffc ; const +NKProcessorInfoLen2 ds.w 1 ; 3e kdp/irp+ffe ; const + +Size equ * + endr + + + + +;_______________________________________________________________________ +; PRIMARY SYSTEM AREA +; +; The PSA is Rene's homage to the ESA390's prefix storage area. +; It contains "the PowerPC IVT and some NK pointers." +; +; New to NKv2, it lives in the page below the KDP. On CPU0, this is +; also just below the below-SPRG0 part of the Exception Work Area. +; It is almost always accessed by negative offset from GPR1, hence +; the negative offsets. +;_______________________________________________________________________ + +PSA record -0xb90,INCR + +Base + +HTABLock ds.l 8 ; -b90:-b70 +PIHLock ds.l 8 ; -b70:-b50 +SchLock ds.l 8 ; -b50:-b30 +ThudLock ds.l 8 ; -b30:-b10 ; for the interactive debugger +RTASLock ds.l 8 ; -b10:-af0 +DbugLock ds.l 8 ; -af0:-ad0 +PoolLock ds.l 8 ; -ad0:-ab0 +FreePool ds.l 4 ; -ab0 ; LLL with signature 'POOL' + ds.l 1 ; -aa0 + ds.l 1 ; -a9c +IndexPtr ds.l 1 ; -a98 ; index of opaque IDs +FirstGRPS ds.l 4 ; -a94:-a84 +TimerQueue ds.l 16 ; -a84:-a44 ; there are more of these in the pool +DelayQueue ds.l 4 ; -a44:-a34 +DbugQueue ds.l 4 ; -a34:-a24 +PageQueue ds.l 4 ; -a24:-a14 +NotQueue ds.l 4 ; -a14:-a04 + ds.l 1 ; -a04 +QueueRelatedZero1 ds.l 1 ; -a00 ; set to zero when queues are inited +QueueRelatedZero2 ds.l 1 ; -9fc ; same again + ds.l 1 ; -9f8 + ds.l 1 ; -9f4 +ReadyQueues +CriticalReadyQ ds.l 8 ; -9f0:-9d0 +LatencyProtectReadyQ ds.l 8 ; -9d0:-9b0 +NominalReadyQ ds.l 8 ; -9b0:-990 +IdleReadyQ ds.l 8 ; -990:-970 +PriorityFlags ds.l 1 ; -970 ; bit 0 is 0, bit 1 is 1, etc... +ScrambledMPCallTime ds.l 1 ; -96c ; by MP call return +EmpiricalCpuFeatures ds.l 1 ; -968 ; Init.s saves MQ (should be possible) here +MQFeatureBit equ 13 ; equals 0x00040000 +AVFeatureBit equ 12 ; equals 0x00080000 +; 8 0x00800000 +; 10 0x00200000 +;int vector checks 9 0x00400000 + +UserModeMSR ds.l 1 ; -964 +ThudBuffer ds.b 96 ; -960:-900 ; that's the kernel debugger +NoIdeaR23 ds.l 1 ; -900 ; r23 copies here... replated to RTAS? + ds.l 1 ; -8fc + ds.l 1 ; -8f8 + ds.l 1 ; -8f4 +PA_BlueTask ds.l 1 ; -8f0 ; set at the same time as the one below + ds.l 1 ; -8ec + ds.l 1 ; -8e8 + ds.l 1 ; -8e4 +VectorRegInitWord ds.l 1 ; -8e0 ; task vector regs get inited with this word x 4 +SevenFFFDead2 ds.l 1 ; -8dc +SevenFFFDead3 ds.l 1 ; -8d8 +SevenFFFDead4 ds.l 1 ; -8d4 +VioletVecBase ds.l 48 ; -8d0:-810 +IndigoVecBase ds.l 48 ; -810:-750 +BlueVecBase ds.l 48 ; -750:-690 ; gets enabled by PDM PIH +GreenVecBase ds.l 48 ; -690:-5d0 +DiagInfo ds.b 256 ; -5d0:-4d0 +ProcessorState ds.b 128 ; -4d0:-450 ; interesting what this gets used by +FreeList ds.l 4 ; -450:-440 + ds.l 1 ; -440 +Int ds.w 1 ; -43c ; set by CommonPIHPath: a one-byte 68k int ID or -1 + ds.w 1 ; -43a +DecClockRateHzCopy ds.l 1 ; -438 ; copied by Init.s +OtherTimerQueuePtr ds.l 1 ; -434 ; unsigned timer queue in the pool, set by InitTMRQs +FreePageCount ds.l 1 ; -430 ; zeroed by InitFreeList +UnheldFreePageCount ds.l 1 ; -42c +ExternalHandlerID ds.l 1 ; -428 ; notification for PIH to bump +SystemAddressSpaceID ds.l 1 ; -424 + ds.l 1 ; -420 +blueProcessPtr ds.l 1 ; -41c ; physical ptr to first type-1 struct created +ThermalHandlerID ds.l 1 ; -418 ; is a Note struct +PMFHandlerID ds.l 1 ; -414 ; also a Note struct + ds.l 1 ; -410 + ds.l 1 ; -40c + ds.l 1 ; -408 + ds.l 1 ; -404 + ds.l 1 ; -400 +OtherSystemAddrSpcPtr ds.l 1 ; -3fc +OtherSystemAddrSpcPtr2 ds.l 1 ; -3f8 ; copied from the one above by InitFreeList +ZeroedByInitFreeList3 ds.l 1 ; -3f4 + ds.l 1 ; -3f0 + ds.l 1 ; -3ec + ds.l 1 ; -3e8 + ds.l 1 ; -3e4 + ds.l 1 ; -3e0 + ds.l 1 ; -3dc + ds.l 1 ; -3d8 + ds.l 1 ; -3d4 + ds.l 1 ; -3d0 + ds.l 1 ; -3cc + ds.l 1 ; -3c8 + ds.l 1 ; -3c4 + ds.l 1 ; -3c0 + ds.l 1 ; -3bc + ds.l 1 ; -3b8 + ds.l 1 ; -3b4 + ds.l 1 ; -3b0 + ds.l 1 ; -3ac + ds.l 1 ; -3a8 + ds.l 1 ; -3a4 + ds.l 1 ; -3a0 + ds.l 1 ; -39c + ds.l 1 ; -398 + ds.l 1 ; -394 + ds.l 1 ; -390 + ds.l 1 ; -38c + ds.l 1 ; -388 + ds.l 1 ; -384 + ds.l 1 ; -380 + ds.l 1 ; -37c + ds.l 1 ; -378 + ds.l 1 ; -374 + ds.l 1 ; -370 + ds.l 1 ; -36c + ds.l 1 ; -368 + ds.l 1 ; -364 + ds.l 1 ; -360 + ds.l 1 ; -35c + ds.l 1 ; -358 + ds.l 1 ; -354 + ds.l 1 ; -350 + ds.l 1 ; -34c + ds.l 1 ; -348 + ds.l 1 ; -344 + + endr + + + + +;_______________________________________________________________________ +; EXCEPTION WORK AREA +; +; Each CPU has one of these. It is half-heartedly enclosed by a "CPU" +; MP struct. Along with the SPRG registers, it is essential in order +; for the CPU to get its bearings at interrupt time. Each CPU's SPRG0 +; always points *into* that CPU's EWA. +;_______________________________________________________________________ + +EWA record -0x340,INCR + +; Fun fact: offsets before here contain the additional kernel globals +; ("Primary System Area"), but only on CPU-0. + +; It's kind of complicated, but the CPU MP struct of CPU-0 +; starts life as a chunk of the kernel globals, carefully placed +; so the "middle" (zero offset) of the Exception Work Area +; within that CPU struct will equal the "middle" (zero offset) +; of the kernel globals (i.e. between the negative-index v2-only +; Primary System Area and the positive-offset Kernel Data Page). + +; Subsequent CPU structs are just large allocations in the kernel +; pool, with the CPU's SPRG0 register being pointed to the zero +; point of that CPU struct's EWA. + +CPUBase ds.b 32 ; -340:-320 ; not really part of the EWA, but more an MP struct + +Base ; used when init'ed as part of the enclosing CPU struct + +; Now for the actual meat of sandwich. + +; Many of these fields are used by functions at interrupt time +; to save/restore registers, in lieu of a stack. + +TimeList ds.l 4 ; -320:-310, cpu+020 + ds.l 1 ; -310, cpu+030 + ds.l 1 ; -30c, cpu+034 + ds.l 1 ; -308, cpu+038 + ds.l 1 ; -304, cpu+03c + ds.l 1 ; -300, cpu+040 + ds.l 1 ; -2fc, cpu+044 + ds.l 1 ; -2f8, cpu+048 + ds.l 1 ; -2f4, cpu+04c + ds.l 1 ; -2f0, cpu+050 + ds.l 1 ; -2ec, cpu+054 + ds.l 1 ; -2e8, cpu+058 + ds.l 1 ; -2e4, cpu+05c +ThudSavedR29 ds.l 1 ; -2e0, cpu+060 +ThudSavedR30 ds.l 1 ; -2dc, cpu+064 +ThudSavedR31 ds.l 1 ; -2d8, cpu+068 + ds.l 1 ; -2d4, cpu+06c + ds.l 1 ; -2d0, cpu+070 + ds.l 1 ; -2cc, cpu+074 + ds.l 1 ; -2c8, cpu+078 + ds.l 1 ; -2c4, cpu+07c + ds.l 1 ; -2c0, cpu+080 + ds.l 1 ; -2bc, cpu+084 + ds.l 1 ; -2b8, cpu+088 + ds.l 1 ; -2b4, cpu+08c + ds.l 1 ; -2b0, cpu+090 + ds.l 1 ; -2ac, cpu+094 + ds.l 1 ; -2a8, cpu+098 + ds.l 1 ; -2a4, cpu+09c + ds.l 1 ; -2a0, cpu+0a0 + ds.l 1 ; -29c, cpu+0a4 + ds.l 1 ; -298, cpu+0a8 + ds.l 1 ; -294, cpu+0ac + ds.l 1 ; -290, cpu+0b0 + ds.l 1 ; -28c, cpu+0b4 + ds.l 1 ; -288, cpu+0b8 + ds.l 1 ; -284, cpu+0bc + ds.l 1 ; -280, cpu+0c0 + ds.l 1 ; -27c, cpu+0c4 +SpacesSavedLR ds.l 1 ; -278, cpu+0c8 +SpacesSavedCR ds.l 1 ; -274, cpu+0cc +SpacesSavedAreaBase ds.l 1 ; -270, cpu+0d0 +SpacesDeferredAreaPtr ds.l 1 ; -26c, cpu+0d4 + ds.l 1 ; -268, cpu+0d8 + ds.l 1 ; -264, cpu+0dc + ds.l 1 ; -260, cpu+0e0 + ds.l 1 ; -25c, cpu+0e4 + ds.l 1 ; -258, cpu+0e8 + ds.l 1 ; -254, cpu+0ec + ds.l 1 ; -250, cpu+0f0 + ds.l 1 ; -24c, cpu+0f4 + ds.l 1 ; -248, cpu+0f8 + ds.l 1 ; -244, cpu+0fc + ds.l 1 ; -240, cpu+100 + ds.l 1 ; -23c, cpu+104 + ds.l 1 ; -238, cpu+108 + ds.l 1 ; -234, cpu+10c + ds.l 1 ; -230, cpu+110 + ds.l 1 ; -22c, cpu+114 + ds.l 1 ; -228, cpu+118 + ds.l 1 ; -224, cpu+11c + ds.l 1 ; -220, cpu+120 + ds.l 1 ; -21c, cpu+124 + ds.l 1 ; -218, cpu+128 + ds.l 1 ; -214, cpu+12c + ds.l 1 ; -210, cpu+130 + ds.l 1 ; -20c, cpu+134 + ds.l 1 ; -208, cpu+138 + ds.l 1 ; -204, cpu+13c + ds.l 1 ; -200, cpu+140 + ds.l 1 ; -1fc, cpu+144 + ds.l 1 ; -1f8, cpu+148 + ds.l 1 ; -1f4, cpu+14c + ds.l 1 ; -1f0, cpu+150 + ds.l 1 ; -1ec, cpu+154 + ds.l 1 ; -1e8, cpu+158 + ds.l 1 ; -1e4, cpu+15c + ds.l 1 ; -1e0, cpu+160 + ds.l 1 ; -1dc, cpu+164 + ds.l 1 ; -1d8, cpu+168 + ds.l 1 ; -1d4, cpu+16c + ds.l 1 ; -1d0, cpu+170 + ds.l 1 ; -1cc, cpu+174 + ds.l 1 ; -1c8, cpu+178 + ds.l 1 ; -1c4, cpu+17c + ds.l 1 ; -1c0, cpu+180 + ds.l 1 ; -1bc, cpu+184 + ds.l 1 ; -1b8, cpu+188 + ds.l 1 ; -1b4, cpu+18c + ds.l 1 ; -1b0, cpu+190 + ds.l 1 ; -1ac, cpu+194 + ds.l 1 ; -1a8, cpu+198 + ds.l 1 ; -1a4, cpu+19c + ds.l 1 ; -1a0, cpu+1a0 + ds.l 1 ; -19c, cpu+1a4 + ds.l 1 ; -198, cpu+1a8 + ds.l 1 ; -194, cpu+1ac + ds.l 1 ; -190, cpu+1b0 + ds.l 1 ; -18c, cpu+1b4 + ds.l 1 ; -188, cpu+1b8 + ds.l 1 ; -184, cpu+1bc + ds.l 1 ; -180, cpu+1c0 + ds.l 1 ; -17c, cpu+1c4 + ds.l 1 ; -178, cpu+1c8 + ds.l 1 ; -174, cpu+1cc + ds.l 1 ; -170, cpu+1d0 + ds.l 1 ; -16c, cpu+1d4 + ds.l 1 ; -168, cpu+1d8 + ds.l 1 ; -164, cpu+1dc + ds.l 1 ; -160, cpu+1e0 + ds.l 1 ; -15c, cpu+1e4 + ds.l 1 ; -158, cpu+1e8 + ds.l 1 ; -154, cpu+1ec + ds.l 1 ; -150, cpu+1f0 + ds.l 1 ; -14c, cpu+1f4 + ds.l 1 ; -148, cpu+1f8 + ds.l 1 ; -144, cpu+1fc + ds.l 1 ; -140, cpu+200 + ds.l 1 ; -13c, cpu+204 + ds.l 1 ; -138, cpu+208 + ds.l 1 ; -134, cpu+20c + ds.l 1 ; -130, cpu+210 + ds.l 1 ; -12c, cpu+214 + ds.l 1 ; -128, cpu+218 + ds.l 1 ; -124, cpu+21c + ds.l 1 ; -120, cpu+220 + ds.l 1 ; -11c, cpu+224 + ds.l 1 ; -118, cpu+228 + ds.l 1 ; -114, cpu+22c + ds.l 1 ; -110, cpu+230 + ds.l 1 ; -10c, cpu+234 + ds.l 1 ; -108, cpu+238 + ds.l 1 ; -104, cpu+23c + ds.l 1 ; -100, cpu+240 + ds.l 1 ; -0fc, cpu+244 + ds.l 1 ; -0f8, cpu+248 + ds.l 1 ; -0f4, cpu+24c + ds.l 1 ; -0f0, cpu+250 + ds.l 1 ; -0ec, cpu+254 + ds.l 1 ; -0e8, cpu+258 + ds.l 1 ; -0e4, cpu+25c + ds.l 1 ; -0e0, cpu+260 + ds.l 1 ; -0dc, cpu+264 + ds.l 1 ; -0d8, cpu+268 + ds.l 1 ; -0d4, cpu+26c + ds.l 1 ; -0d0, cpu+270 + ds.l 1 ; -0cc, cpu+274 + ds.l 1 ; -0c8, cpu+278 + ds.l 1 ; -0c4, cpu+27c + ds.l 1 ; -0c0, cpu+280 + ds.l 1 ; -0bc, cpu+284 + ds.l 1 ; -0b8, cpu+288 + ds.l 1 ; -0b4, cpu+28c + ds.l 1 ; -0b0, cpu+290 + ds.l 1 ; -0ac, cpu+294 + ds.l 1 ; -0a8, cpu+298 + ds.l 1 ; -0a4, cpu+29c + ds.l 1 ; -0a0, cpu+2a0 + ds.l 1 ; -09c, cpu+2a4 + ds.l 1 ; -098, cpu+2a8 + ds.l 1 ; -094, cpu+2ac + ds.l 1 ; -090, cpu+2b0 + ds.l 1 ; -08c, cpu+2b4 + ds.l 1 ; -088, cpu+2b8 + ds.l 1 ; -084, cpu+2bc + ds.l 1 ; -080, cpu+2c0 + ds.l 1 ; -07c, cpu+2c4 + ds.l 1 ; -078, cpu+2c8 + ds.l 1 ; -074, cpu+2cc + ds.l 1 ; -070, cpu+2d0 + ds.l 1 ; -06c, cpu+2d4 + ds.l 1 ; -068, cpu+2d8 + ds.l 1 ; -064, cpu+2dc +PoolSavedLR ds.l 1 ; -060, cpu+2e0 +PoolSavedSizeArg ds.l 1 ; -05c, cpu+2e4 + ds.l 1 ; -058, cpu+2e8 + ds.l 1 ; -054, cpu+2ec + ds.l 1 ; -050, cpu+2f0 + ds.l 1 ; -04c, cpu+2f4 + ds.l 1 ; -048, cpu+2f8 + ds.l 1 ; -044, cpu+2fc +CreateAreaSavedLR ds.l 1 ; -040, cpu+300 +CreateAreaSavedR25 ds.l 1 ; -03c, cpu+304 ; ???!!! +CreateAreaSavedR26 ds.l 1 ; -038, cpu+308 +CreateAreaSavedR27 ds.l 1 ; -034, cpu+30c +CreateAreaSavedR28 ds.l 1 ; -030, cpu+310 +CreateAreaSavedR29 ds.l 1 ; -02c, cpu+314 +CreateAreaSavedR30 ds.l 1 ; -028, cpu+318 +CreateAreaSavedR31 ds.l 1 ; -024, cpu+31c +PA_IRP ds.l 1 ; -020, cpu+320 +PA_CurAddressSpace ds.l 1 ; -01c, cpu+324 +PA_PSA ds.l 1 ; -018, cpu+328 +PA_ContextBlock ds.l 1 ; -014, cpu+32c +Flags ds.l 1 ; -010, cpu+330 + ds.l 1 ; -00c, cpu+334 +PA_CurTask ds.l 1 ; -008, cpu+338 +PA_KDP ds.l 1 ; -004, cpu+33c + +; ZERO (SPRG0 points here) + +r0 ds.l 1 ; 000, cpu+340 ; used for quick register saves at exception time... +r1 ds.l 1 ; 004, cpu+344 +r2 ds.l 1 ; 008, cpu+348 +r3 ds.l 1 ; 00c, cpu+34c +r4 ds.l 1 ; 010, cpu+350 +r5 ds.l 1 ; 014, cpu+354 +r6 ds.l 1 ; 018, cpu+358 +r7 ds.l 1 ; 01c, cpu+35c +r8 ds.l 1 ; 020, cpu+360 +r9 ds.l 1 ; 024, cpu+364 +r10 ds.l 1 ; 028, cpu+368 +r11 ds.l 1 ; 02c, cpu+36c +r12 ds.l 1 ; 030, cpu+370 +r13 ds.l 1 ; 034, cpu+374 +r14 ds.l 1 ; 038, cpu+378 +r15 ds.l 1 ; 03c, cpu+37c +r16 ds.l 1 ; 040, cpu+380 +r17 ds.l 1 ; 044, cpu+384 +r18 ds.l 1 ; 048, cpu+388 +r19 ds.l 1 ; 04c, cpu+38c +r20 ds.l 1 ; 050, cpu+390 +r21 ds.l 1 ; 054, cpu+394 +r22 ds.l 1 ; 058, cpu+398 +r23 ds.l 1 ; 05c, cpu+39c +r24 ds.l 1 ; 060, cpu+3a0 +r25 ds.l 1 ; 064, cpu+3a4 +r26 ds.l 1 ; 068, cpu+3a8 +r27 ds.l 1 ; 06c, cpu+3ac +r28 ds.l 1 ; 070, cpu+3b0 +r29 ds.l 1 ; 074, cpu+3b4 +r30 ds.l 1 ; 078, cpu+3b8 +r31 ds.l 1 ; 07c, cpu+3bc + +; Fun fact: offsets past here contain the main kernel globals +; ("Kernel Data Page"), but only on CPU-0. + + endr + + + + +;_______________________________________________________________________ +; KERNEL DATA PAGE +; +; Positive offsets from the kernel global pointer (which can be found +; in the PA_KDP field of any CPU's EWA, and directly in the SPRG0 of +; CPU-0). Except for offsets < 128 bytes, which belong to the GPR save +; area of CPU-0's EWA (see the r0, r1 etc. directly above here?) +;_______________________________________________________________________ + +KDP record 0x80,INCR + +SegMaps +SegMap32SupInit ds.l 32 ; 080:100 +SegMap32UsrInit ds.l 32 ; 100:180 +SegMap32CPUInit ds.l 32 ; 180:200 +SegMap32OvlInit ds.l 32 ; 200:280 +BATs ds.l 32 ; 280:300 + +; GAP + org 0x340 +MinusOne1 ds.l 1 ; 340 ; several longs set at once + ds.l 1 ; 344 +MinusOne2 ds.l 1 ; 348 + ds.l 1 ; 34c +MinusOne3 ds.l 1 ; 350 + ds.l 1 ; 354 +MinusOne4 ds.l 1 ; 358 + ds.l 1 ; 35c +YellowVecBase ds.l 48 ; 360:420 ; used to ignore illegal AltiVec insns by Init.s +OrangeVecBase ds.l 48 ; 420:4e0 +RedVecBase ds.l 48 ; 4e0:5a0 +OldKDP ds.l 1 ; 5a0 ; gotten from the old SPRG0 +OtherFreeThing ds.l 1 ; 5a4 +TopOfFreePages ds.l 1 ; 5a8 ; gotten from the old SPRG0 + ds.l 1 ; 5ac +PA_InterruptHandler ds.l 1 ; 5b0 + ds.l 1 ; 5b4 +HiLevelPerfMonitorBits ds.l 1 ; 5b8 + ds.l 1 ; 5bc +PerfMonitorBits ds.l 1 ; 5c0 + ds.l 1 ; 5c4 +SegMap32SupInitPtr ds.l 1 ; 5c8 +BatMap32SupInit ds.l 1 ; 5cc +SegMap32UsrInitPtr ds.l 1 ; 5d0 +BatMap32UsrInit ds.l 1 ; 5d4 +SegMap32CPUInitPtr ds.l 1 ; 5d8 +BatMap32CPUInit ds.l 1 ; 5dc +SegMap32OvlInitPtr ds.l 1 ; 5e0 +BatMap32OvlInit ds.l 1 ; 5e4 + ds.l 1 ; 5e8 + ds.l 1 ; 5ec +NanoKernelCallTable ds.l 16 ; 5f0:630 +PA_ConfigInfo ds.l 1 ; 630 +PA_EmulatorData ds.l 1 ; 634 +KernelMemoryBase ds.l 1 ; 638 +KernelMemoryEnd ds.l 1 ; 63c ; Top of HTAB (and entire kernel reserved area). Set by Init.s +PA_RelocatedLowMemInit ds.l 1 ; 640 ; From ConfigInfo. Ptr to Mac LowMem vars, which Init.s sets up +SharedMemoryAddr ds.l 1 ; 644 ; From ConfigInfo. Not sure what latest use is. +LA_EmulatorKernelTrapTable ds.l 1 ; 648 ; Calculated from ConfigInfo. +PA_NanoKernelCode ds.l 1 ; 64c ; Calculated by NanoKernel itself. +PA_FDP ds.l 1 ; 650 ; See notes in NanoKernel. Very interesting. +LA_ECB ds.l 1 ; 654 ; Logical ptr into EDP. +PA_ECB ds.l 1 ; 658 ; gets called "system context" +PA_ECB_Old ds.l 1 ; 65c ; copied from NKv<=01.01 to EWA.PA_ContextBlock. + ds.l 1 ; 660 + ds.l 1 ; 664 + ds.l 1 ; 668 +PA_PageMapEnd ds.l 1 ; 66c ; Set at the same time as PA_PageMapStart below... +TestIntMaskInit ds.l 1 ; 670 ; These are all copied from ConfigInfo... +PostIntMaskInit ds.l 1 ; 674 +ClearIntMaskInit ds.l 1 ; 678 +PA_EmulatorIplValue ds.l 1 ; 67c ; Physical ptr into EDP +SharedMemoryAddrPlus ds.l 1 ; 680 ; Really not sure +PA_PageMapStart ds.l 1 ; 684 ; Physical ptr to PageMap (= KDP+0x920) +PageAttributeInit ds.l 1 ; 688 ; defaults for page table entries (see ConfigInfo) + ds.l 1 ; 68c + ds.l 1 ; 690 + ds.l 1 ; 694 + ds.l 1 ; 698 + ds.l 1 ; 69c +PTEGMask ds.l 1 ; 6a0 +HTABORG ds.l 1 ; 6a4 +UsablePhysicalPages ds.l 1 ; 6a8 ; does take MacOS into account +TotalPhysicalPages ds.l 1 ; 6ac ; does not take into acct maximum MacOS memory +FlatPageListPtr ds.l 1 ; 6b0 +VMMaxVirtualPages ds.l 1 ; 6b4 ; size of main contiguous segment? +CpuSpecificBytes +CpuSpecificByte1 ds.b 1 ; 6b8 ; seems to contain flags (set from PVR & tbl by Init.s) +CpuSpecificByte2 ds.b 1 ; 6b9 ; probably not flags (set in same way) + ds.b 1 ; 6ba + ds.b 1 ; 6bb +FlatPageListSegPtrs ds.l 16 ; 6bc + ds.l 1 ; 6fc + +StartOfPanicArea ; PROTECTED BY THUD LOCK +ThudSavedR0 ds.l 1 ; 700 +ThudSavedR1 ds.l 1 ; 704 ; via SPRG1 +ThudSavedR2 ds.l 1 ; 708 +ThudSavedR3 ds.l 1 ; 70c +ThudSavedR4 ds.l 1 ; 710 +ThudSavedR5 ds.l 1 ; 714 +ThudSavedR6 ds.l 1 ; 718 +ThudSavedR7 ds.l 1 ; 71c +ThudSavedR8 ds.l 1 ; 720 +ThudSavedR9 ds.l 1 ; 724 +ThudSavedR10 ds.l 1 ; 728 +ThudSavedR11 ds.l 1 ; 72c +ThudSavedR12 ds.l 1 ; 730 +ThudSavedR13 ds.l 1 ; 734 +ThudSavedR14 ds.l 1 ; 738 +ThudSavedR15 ds.l 1 ; 73c +ThudSavedR16 ds.l 1 ; 740 +ThudSavedR17 ds.l 1 ; 744 +ThudSavedR18 ds.l 1 ; 748 +ThudSavedR19 ds.l 1 ; 74c +ThudSavedR20 ds.l 1 ; 750 +ThudSavedR21 ds.l 1 ; 754 +ThudSavedR22 ds.l 1 ; 758 +ThudSavedR23 ds.l 1 ; 75c +ThudSavedR24 ds.l 1 ; 760 +ThudSavedR25 ds.l 1 ; 764 +ThudSavedR26 ds.l 1 ; 768 +ThudSavedR27 ds.l 1 ; 76c +ThudSavedR28 ds.l 1 ; 770 +ThudSavedR29 ds.l 1 ; 774 +ThudSavedR30 ds.l 1 ; 778 +ThudSavedR31 ds.l 1 ; 77c +ThudSavedCR ds.l 1 ; 780 +ThudSavedMQ ds.l 1 ; 784 +ThudSavedXER ds.l 1 ; 788 +ThudSavedSPRG2 ds.l 1 ; 78c +ThudSavedCTR ds.l 1 ; 790 +ThudSavedPVR ds.l 1 ; 794 +ThudSavedDSISR ds.l 1 ; 798 +ThudSavedDAR ds.l 1 ; 79c +ThudSavedTBU ds.l 1 ; 7a0 ; RTCU on 601 +ThudSavedTB ds.l 1 ; 7a4 ; RTCL on 601 +ThudSavedDEC ds.l 1 ; 7a8 +ThudSavedHID0 ds.l 1 ; 7ac +ThudSavedSDR1 ds.l 1 ; 7b0 +ThudSavedSRR0 ds.l 1 ; 7b4 +ThudSavedSRR1 ds.l 1 ; 7b8 +ThudSavedMSR ds.l 1 ; 7bc +ThudSavedSR0 ds.l 1 ; 7c0 +ThudSavedSR1 ds.l 1 ; 7c4 +ThudSavedSR2 ds.l 1 ; 7c8 +ThudSavedSR3 ds.l 1 ; 7cc +ThudSavedSR4 ds.l 1 ; 7d0 +ThudSavedSR5 ds.l 1 ; 7d4 +ThudSavedSR6 ds.l 1 ; 7d8 +ThudSavedSR7 ds.l 1 ; 7dc +ThudSavedSR8 ds.l 1 ; 7e0 +ThudSavedSR9 ds.l 1 ; 7e4 +ThudSavedSR10 ds.l 1 ; 7e8 +ThudSavedSR11 ds.l 1 ; 7ec +ThudSavedSR12 ds.l 1 ; 7f0 +ThudSavedSR13 ds.l 1 ; 7f4 +ThudSavedSR14 ds.l 1 ; 7f8 +ThudSavedSR15 ds.l 1 ; 7fc +ThudSavedF0 ds.d 1 ; 800 +ThudSavedF1 ds.d 1 ; 808 +ThudSavedF2 ds.d 1 ; 810 +ThudSavedF3 ds.d 1 ; 818 +ThudSavedF4 ds.d 1 ; 820 +ThudSavedF5 ds.d 1 ; 828 +ThudSavedF6 ds.d 1 ; 830 +ThudSavedF7 ds.d 1 ; 838 +ThudSavedF8 ds.d 1 ; 840 +ThudSavedF9 ds.d 1 ; 848 +ThudSavedF10 ds.d 1 ; 850 +ThudSavedF11 ds.d 1 ; 858 +ThudSavedF12 ds.d 1 ; 860 +ThudSavedF13 ds.d 1 ; 868 +ThudSavedF14 ds.d 1 ; 870 +ThudSavedF15 ds.d 1 ; 878 +ThudSavedF16 ds.d 1 ; 880 +ThudSavedF17 ds.d 1 ; 888 +ThudSavedF18 ds.d 1 ; 890 +ThudSavedF19 ds.d 1 ; 898 +ThudSavedF20 ds.d 1 ; 8a0 +ThudSavedF21 ds.d 1 ; 8a8 +ThudSavedF22 ds.d 1 ; 8b0 +ThudSavedF23 ds.d 1 ; 8b8 +ThudSavedF24 ds.d 1 ; 8c0 +ThudSavedF25 ds.d 1 ; 8c8 +ThudSavedF26 ds.d 1 ; 8d0 +ThudSavedF27 ds.d 1 ; 8d8 +ThudSavedF28 ds.d 1 ; 8e0 +ThudSavedF29 ds.d 1 ; 8e8 +ThudSavedF30 ds.d 1 ; 8f0 +ThudSavedF31 ds.d 1 ; 8f8 +SomethingSerial ds.l 1 ; 900 +ThudSavedLR ds.l 1 ; 904 +RTAS_Proc ds.l 1 ; 908 ; r8 on kernel entry +EndOfPanicArea + +RTAS_PrivDataArea ds.l 1 ; 90c ; copied from HWInfo +ZeroWord ds.l 1 ; 910 ; Only NewWorld and Unknown PIHes touch this + ds.l 1 ; 914 + ds.l 1 ; 918 + ds.l 1 ; 91c +PageMap ds.b 1184; 920:dc0 +NanoKernelInfo ds.b 352 ; dc0:f20 ; see NKNanoKernelInfo in PPCInfoRecordsPriv +ProcessorInfo ds.b 160 ; f20:fc0 +InfoRecord ds.b 64 ; fc0:1000 ; was main copy in NKv1, now vestigial? + + endr + + + + + +;_______________________________________________________________________ +; KERNEL VECTOR TABLE +; +; The kernel creates several of these, and activates one by pointing +; a CPU's SPRG3 ("vecBase") register at it. Find them in PSA and KDP. +; (For want of more information, I have colour coded them for now.) +; +; Each entry is a (hopefully 64-byte aligned) physical pointer to an +; interrupt service routine in the kernel. One entry roughly +; corresponds with one of the 256-byte aligned entry points into +; the PowerPC interrupt (="exception") vector table. Code for those +; can be found in :RISC:ExceptionTable.s. +;_______________________________________________________________________ + +VecTable record 0,INCR +; VBGYOR + ds.l 1 ; 00 ; scratch for IVT? +SystemResetVector ds.l 1 ; 04 ; called by IVT+100 (system reset) +MachineCheckVector ds.l 1 ; 08 ; called by IVT+200 (machine check) +DSIVector ds.l 1 ; 0c ; called by IVT+300 (DSI) +ISIVector ds.l 1 ; 10 ; called by IVT+400 (ISI) +ExternalIntVector ds.l 1 ; 14 ; called by IVT+500 (external interrupt) +AlignmentIntVector ds.l 1 ; 18 ; called by IVT+600 (alignment) +ProgramIntVector ds.l 1 ; 1c ; called by IVT+700 (program) +FPUnavailVector ds.l 1 ; 20 ; called by IVT+800 (FP unavail) +DecrementerVector ds.l 1 ; 24 ; called by IVT+900 (decrementer) +ReservedVector1 ds.l 1 ; 28 ; called by IVT+a00 (reserved) +ReservedVector2 ds.l 1 ; 2c ; called by IVT+b00 (reserved) +SyscallVector ds.l 1 ; 30 ; called by IVT+c00 (system call) +TraceVector ds.l 1 ; 34 ; called by IVT+d00 (trace) +FPAssistVector ds.l 1 ; 38 ; called by IVT+e00 (FP assist) +PerfMonitorVector ds.l 1 ; 3c ; called by IVT+f00 (perf monitor) + ds.l 1 ; 40 ; + ds.l 1 ; 44 ; + ds.l 1 ; 48 ; + ds.l 1 ; 4c ; Vectors from here downwards are called from + ds.l 1 ; 50 ; odd places in the IVT???? + ds.l 1 ; 54 ; + ds.l 1 ; 58 ; seems AltiVec-related +ThermalEventVector ds.l 1 ; 5c ; + ds.l 1 ; 60 ; + ds.l 1 ; 64 ; + ds.l 1 ; 68 ; + ds.l 1 ; 6c ; + ds.l 1 ; 70 ; + ds.l 1 ; 74 ; + ds.l 1 ; 78 ; + ds.l 1 ; 7c ; + ds.l 1 ; 80 ; shares with TraceVector in Y and G + ds.l 1 ; 84 ; + ds.l 1 ; 88 ; + ds.l 1 ; 8c ; + ds.l 1 ; 90 ; + ds.l 1 ; 94 ; + ds.l 1 ; 98 ; + ds.l 1 ; 9c ; + ds.l 1 ; a0 ; + ds.l 1 ; a4 ; + ds.l 1 ; a8 ; + ds.l 1 ; ac ; + ds.l 1 ; b0 ; + ds.l 1 ; b4 ; + ds.l 1 ; b8 ; + ds.l 1 ; bc ; called by IVT+0 (reserved) + +Size equ * + endr + + + + +;_______________________________________________________________________ +; NANOKERNEL CALL (KCALL) TABLE +; +; You can also use this record to index the NanoKernelCallCounts in +; PPCInfoRecordsPriv.s:NKNanoKernelInfo. +;_______________________________________________________________________ + +NanoKernelCallTable record 0,INCR + +ReturnFromException ds.l 1 ; 00, kdp+5f0, trap 0 ; SS replaces with jump to emu+f900 +RunAlternateContext ds.l 1 ; 04, kdp+5f4, trap 1 +ResetSystem ds.l 1 ; 08, kdp+5f8, trap 2 ; SS replaces with jump to emu+fb00 +VMDispatch ds.l 1 ; 0c, kdp+5fc, trap 3 ; FE0A (VM/MMU/NK) trap +PrioritizeInterrupts ds.l 1 ; 10, kdp+600, trap 4 ; SS forbids +PowerDispatch ds.l 1 ; 14, kdp+604, trap 5 ; FEOF +RTASDispatch ds.l 1 ; 18, kdp+608, trap 6 ; SS forbids the use of this trap and below +CacheDispatch ds.l 1 ; 1c, kdp+60c, trap 7 +MPDispatch ds.l 1 ; 20, kdp+610, trap 8 ; also accessible via syscall interface + ds.l 1 ; 24, kdp+614, trap 9 ; unused + ds.l 1 ; 28, kdp+618, trap 10 ; unused + ds.l 1 ; 2c, kdp+61c, trap 11 ; unused +CallAdapterProcPPC ds.l 1 ; 30, kdp+620, trap 12 ; unused + ds.l 1 ; 34, kdp+624, trap 13 ; unused +CallAdapterProc68k ds.l 1 ; 38, kdp+628, trap 14 ; unused +Thud ds.l 1 ; 3c, kdp+62c, trap 15 ; basically just panic + +Size equ * + endr + + + + + +;_______________________________________________________________________ +; PAGEMAP DESCRIPTOR TABLE +; +; An 8-byte entry in the PageMap tables passed to the NanoKernel via +; ConfigInfo. Roughly corresponds with a contiguous logical address +; range lying within 256MB (segment) boundaries, and therefore +; roughly corresponds with the NKv2 MP "Area" struct. +; +; It could be that these are actually PageMap Descriptor *Entries*, +; and I have misunderstood. +;_______________________________________________________________________ + +PMDT record 0,INCR +LBase ds.w 1 ; 0 ; (base - segment) >> 12 +PageCount ds.w 1 ; 2 ; page count MINUS ONE +PBaseAndFlags ds.l 1 ; 4 ; PBase page aligned + +PBaseBits equ 20 +FirstFlagBit equ 20 +FirstFlag equ 0x800 + +DaddyFlag equ 0x800 +CountingFlag equ 0x400 +PhysicalIsRelativeFlag equ 0x200 + +Size equ * + endr + + + + + +;_______________________________________________________________________ +; KERNEL SPINLOCK +; +; Seven of these, each with a four-byte signature, live in the PSA. +; The signatures describe the protected structures adequately. +; +; The function to acquire a lock seems to have been inlined, because +; it always saves and restores r8 and r9 (even to and from themselves) +; around a bl to NanoKernelInit.s:AcquireLock. It has therefore been +; macrofied as NanoKernelMacros.s:_Lock. +;_______________________________________________________________________ + +Lock record 0,INCR +Count ds.l 1 ; 00 ; target for lwarx/stwcx + +Signature ds.l 1 ; 04 + +kHTABLockSignature equ 'htab' +kPIHLockSignature equ 'pih ' +kSchLockSignature equ 'sch ' +kThudLockSignature equ 'thud' +kRTASLockSignature equ 'rtas' +kDbugLockSignature equ 'dbug' +kPoolLockSignature equ 'pool' + + org 0x10 +Holder ds.l 1 ; 10 + + org 0x20 + endr + + + + +; Structs after this point are inadequately commented. Sorry! + + + +Index record 0,INCR +kSignature equ 'INDX' + +HalfOne ds.w 1 ; 000 +HalfTwo ds.w 1 ; 002 +Signature ds.l 1 ; 004 +IDsPtr ds.l 1 ; 008 + + org 520 +Size equ * + endr + + + + +PoolPage record 0,INCR +FreeBytes ds.l 1 ; 000 + + org 4096 +Size equ * + endr + + + + +; Special opaque NanoKernel stuff! + + + + + +GRPSStruct record 0,INCR +kSignature equ 'GRPS' + +LLL ds.l 4 ; 00:10 + + endr + + + + + + + + + + + + +; These seem to go in a notification queue? + + + + + + + + + + +LLL record 0,INCR +Freeform ds.l 1 ; 0 +Signature ds.l 1 ; 4 +Next ds.l 1 ; 8 +Prev ds.l 1 ; c + endr + + + + + + +; Special case of LLL +; Init'ed by InitTMRQs (called by Init.s) +; There is one copy of this struct at kdp-a84 below the (shorter) queue structs, +; and two copies in the pool, pointed to by kdp-434 and kdp-364. +TimerQueueStruct record 0,INCR + +LLL ds.l 4 ; 00 +Unused ds.l 1 ; 10 +ZeroByte ds.b 1 ; 14 ; can also be set to 7 or 8 +UnusedByte ds.b 1 ; 15 +OneByte1 ds.b 1 ; 16 +OneByte2 ds.b 1 ; 17 ; can also be unset + +; GAP + + org 0x38 +TimeCtr ds.d 1 ; 38 ; high half in DEC reg or whole thing in TB + + endr + + + + +; For altivec, mofo +VectorSaveArea record 0,INCR + + org 23*16 +;RegisterAreaSize equ *-VectorSaveArea +RegisterAreaSize equ 23*16 + + org 32*16 + 20 + + endr + + + diff --git a/Linker/LinkPowerROM b/Linker/LinkPowerROM new file mode 100644 index 0000000..20c3cdf --- /dev/null +++ b/Linker/LinkPowerROM @@ -0,0 +1,151 @@ +Set Streamer " | StreamEdit -d -e '/?Å/ Pr ¶¶¶"1¶¶¶"'" + + + +If {#} ¶< 2 + Echo "USAGE: {0} DEST SRC ... > ShellScript" + Exit 1 +End + + + +Set DestFile "{1}" +Shift + + + +Set TempPrepFile "{TempFolder}PPCROMLinkPrepCmds" +Set TempCmdFile "{TempFolder}PPCROMLinkCmds" +Echo -n "" > "{TempPrepFile}" + +Echo -n "PPCLink -xm library -codestart 0 -warn -o " > "{TempCmdFile}" +Quote -n "{DestFile}.x" >> "{TempCmdFile}" + + +Set OffsetSoFar 0 +Set NeedTool 1 # Always extract binary, so always need tool + + +Loop # over arguments + If !{#} + Break + End + + If "{1}" =~ /[0-9]+/ || "{1}" =~ /0x[0-9a-f]+/ + # Move-to-offset argument (hex or decimal literal) + + If `Evaluate {1} ¶< {OffsetSoFar}` + Echo "{0} failed: cannot pad to offset {1} because we are already past it!" + Exit 1 + End + + Set Delta `Evaluate -h {1} - {OffsetSoFar}` + + If {Delta} + Echo -n "Set F ¶"¶{TempFolder¶}Zeros_{Delta}.s¶";¶t" >> "{TempPrepFile}" + Echo -n 'If !`Exists "{F}"' >> "{TempPrepFile}" + Echo -n "{Streamer}" >> "{TempPrepFile}" + Echo -n '`; ' >> "{TempPrepFile}" + Echo -n "Echo ¶¶tDCB.B {Delta}, 0" '> "{F}"; ' >> "{TempPrepFile}" + Echo -n 'PPCAsm "{F}"; ' >> "{TempPrepFile}" + Echo "End" >> "{TempPrepFile}" + + Echo -n "¶t¶¶¶n¶t" >> "{TempCmdFile}" + Echo -n "¶"¶{TempFolder¶}Zeros_{Delta}.s.o¶"" >> "{TempCmdFile}" + + Set OffsetSoFar {1} + End + Else If "{1}" =~ /([A-Za-z0-9]+)¨1:/ + # Label argument + + Echo -n "Set F ¶"¶{TempFolder¶}{¨1}.s¶";¶t" >> "{TempPrepFile}" + Echo -n 'If !`Exists "{F}"' >> "{TempPrepFile}" + Echo -n "{Streamer}" >> "{TempPrepFile}" + Echo -n '`; ' >> "{TempPrepFile}" + Echo -n "Echo ¶¶tEXPORT {¨1}¶¶n{¨1}" '> "{F}"; ' >> "{TempPrepFile}" + Echo -n 'PPCAsm "{F}"; ' >> "{TempPrepFile}" + Echo "End" >> "{TempPrepFile}" + + Echo -n "¶t¶¶¶n¶t" >> "{TempCmdFile}" + Echo -n "¶"¶{TempFolder¶}{¨1}.s.o¶"" >> "{TempCmdFile}" + Else + # Filename argument + + If "{1}" !~ /Å.x/ + Echo -n "Set F " >> "{TempPrepFile}" + Quote -n "{1}" >> "{TempPrepFile}" + Echo -n "; " >> "{TempPrepFile}" + Echo -n 'If !`Exists "{F}.x"' >> "{TempPrepFile}" + Echo -n "{Streamer}" >> "{TempPrepFile}" + Echo -n '` || `Newer "{F}" "{F}.x"' >> "{TempPrepFile}" + Echo -n "{Streamer}" >> "{TempPrepFile}" + Echo -n '`; ' >> "{TempPrepFile}" + Quote -n "{0}.tool" >> "{TempPrepFile}" + Echo -n ' tox "{F}" "{F}.x"; ' >> "{TempPrepFile}" + Echo "End" >> "{TempPrepFile}" + + Set NeedTool 1 + Set TheXCOFF "{1}.x" + Set TextLen `Files -x b -n "{1}" | StreamEdit -d -e '/([0-9]+)¨1b°/ Print ¨1'` + Else + Set TheXCOFF "{1}" + Set TextLen `DumpXCOFF -do h "{TheXCOFF}" | StreamEdit -d -e '/s_nameŶ".(Å)¨1¶"/ Set CurSec ¨1' -e '/s_sizeŶ((Å)¨1¶)/ Print CurSec " " ¨1' | StreamEdit -d -e '/text (Å)¨1/ Print ¨1'` + End + + Echo -n "¶t¶¶¶n¶t" >> "{TempCmdFile}" + Quote -n "{TheXCOFF}" >> "{TempCmdFile}" + + Set OffsetSoFar `Evaluate {OffsetSoFar} + {TextLen}` + End + + Shift +End + +If {NeedTool} + Echo "# Compile a C program to create/extract basic XCOFFs" + Echo -n 'If !`Exists ' + Quote -n "{0}.tool" + Echo -n "{Streamer}" + Echo '`' + + Echo -n "¶tSC " + Echo -n '-o "{TempFolder}LinkPowerROM.o" ' + Quote "{0}.c" + + Echo -n "¶tILink -d -t MPST -c 'MPS ' -o " + Quote -n "{0}.tool" + Echo ' "{Libraries}Stubs.o" "{CLibraries}StdCLib.o" "{Libraries}MacRuntime.o" "{Libraries}IntEnv.o" "{Libraries}Interface.o" "{TempFolder}LinkPowerROM.o"' + + Echo "End" + Echo +End + +Echo "# Auto-generate some XCOFFs (padding and labels)" +Catenate "{TempPrepFile}" + +Echo + +Echo "# Link whole-ROM XCOFF" +Catenate "{TempCmdFile}" + +Echo +Echo + +Echo "# Extract raw ROM binary" +Quote -n "{0}.tool" +Echo -n " fromx " +Quote -n "{DestFile}.x" +Echo -n " " +Quote "{DestFile}" + +Echo + +Echo "# Checksum the ConfigInfo structure(s)" +Echo -n 'Set CksumOffsets "`DumpXCOFF -do s ' +Quote -n "{DestFile}.x" +Echo ' | StreamEdit -d -e "/C_EXTÅAddrÅ(0x[A-Fa-f0-9]+)¨1ÅConfigInfoChecksum/ Print ¨1"`"' + +Quote -n "{0}.tool" +Echo -n " cksum " +Quote -n "{DestFile}" +Echo ' {CksumOffsets}' diff --git a/Linker/LinkPowerROM.c b/Linker/LinkPowerROM.c new file mode 100644 index 0000000..698569f --- /dev/null +++ b/Linker/LinkPowerROM.c @@ -0,0 +1,216 @@ +#include +#include +#include + +#ifdef macintosh +typedef unsigned long uint32_t; +typedef long int32_t; +typedef unsigned short uint16_t; +typedef short int16_t; +typedef unsigned char uint8_t; +typedef char int8_t; +#endif + +uint32_t narrow[8]; +uint32_t wide[2]; + +int slurp(char *path, uint8_t **datap, unsigned long *sizep) +{ + FILE *f; + long pos; + uint8_t *bytes; + + f = fopen(path, "rb"); + if(f == NULL) return 1; + + fseek(f, 0, SEEK_END); + pos = ftell(f); + fseek(f, 0, SEEK_SET); + + bytes = (uint8_t *)malloc(pos); + if(bytes == NULL) return 1; + + fread(bytes, pos, 1, f); + + fclose(f); + + *datap = bytes; + *sizep = pos; + + return 0; /* no error */ +} + +const uint16_t pretend_header[] = { + 0x01df /*f_magic*/, + 1 /*f_nscns*/, + 0xd611, 0x2977 /*f_timdat*/, + 0, 0 /*f_symptr*/, + 0, 2 /*f_nsyms*/, + 0 /*f_opthdr*/, + 0 /*f_flags*/, + + /* now for single .text symbol header */ + 0x2e74, 0x6578, 0x7400, 0x0000 /*s_name = .text*/, + 0, 0 /*s_paddr*/, + 0, 0 /*s_vaddr*/, + 1234, 5678 /*s_size*/, + 0, 0x3c /*s_scnptr = len of this header*/, + 0, 0 /*s_relptr*/, + 0, 0 /*s_lnnoptr*/, + 0 /*s_nreloc*/, + 0 /*s_nlnno*/, + 0, 0x20 /*s_flags = text*/ +}; + +const uint16_t pretend_footer[] = { + 0, 0, + 0, 0, + 0, 0, + 1, 0, + 0x6b01, + 1234, 5678, + 0, 0, 0, + 0x1100, 0, 0, 0 +}; + + +int main(int argc, char **argv) +{ + FILE *fp; + uint8_t *buf, *sec, *dest; + unsigned long buflen, seclen, destlen; + unsigned long i; + + if(argc < 2) + { + fprintf(stderr, "%s: No command specified -- use tox, fromx or cksum\n", argv[0]); + return 1; + } + + if(!strcmp(argv[1], "cksum")) + { + unsigned long offset; + + if(argc < 3) + { + fprintf(stderr, "%s: %s: Specify a file!\n", argv[0], argv[1]); + return 1; + } + + if(argc < 4) + { + return 0; /* No offset specified -- fail silently */ + } + + if(slurp(argv[2], &buf, &buflen)) + { + fprintf(stderr, "%s: %s: Could not open input\n", argv[0], argv[1]); + return 1; + } + + offset = strtoul(argv[3], NULL, 0); + + if(offset > buflen - 40) { + fprintf(stderr, "%s: Bad offset for ConfigInfo checksum: 0x%x\n", argv[0], offset); + return 1; + } + + memset(buf + offset, 0, 40); + + for(i=0; if_opthdr); + + sec = buf + shp->s_scnptr; + seclen = shp->s_size; + } + + /* now to create my template XCOFF */ + + if(!strcmp(argv[1], "tox")) + { + destlen = sizeof pretend_header + seclen + sizeof pretend_footer; + dest = (uint8_t *)malloc(destlen); + if(dest == NULL) + { + fprintf(stderr, "%s: OOM\n", argv[0]); + return 1; + } + + memcpy(dest, (const char *)pretend_header, sizeof pretend_header); + memcpy(dest + sizeof pretend_header, sec, seclen); + memcpy(dest + sizeof pretend_header + seclen, (const char *)pretend_footer, sizeof pretend_footer); + + *(uint32_t *)(dest + 36) = seclen; + *(uint32_t *)(dest + 8) = sizeof pretend_header + seclen; + *(uint32_t *)(dest + sizeof pretend_header + seclen + 18) = seclen; + } + else if(!strcmp(argv[1], "fromx")) + { + dest = sec; + destlen = seclen; + } + + fp = fopen(argv[3], "wb"); + if(!fp) { + fprintf(stderr, "%s: Could not open output\n", argv[0]); + return 1; + } + + fwrite(dest, 1, destlen, fp); + + fclose(fp); + } + + return 0; +} diff --git a/MakeFile b/MakeFile new file mode 100644 index 0000000..af774f8 --- /dev/null +++ b/MakeFile @@ -0,0 +1,60 @@ +ResultDir = :BuildResults: +LinkerDir = :Linker: + + + +MainTarget Ä {ResultDir}PowerROM + + + +RomBin = :RomMondo.bin + + + +ExceptionTableBin = {ResultDir}PPCExceptionTable.x + +{ExceptionTableBin} Ä PPCExceptionTable.s + PPCAsm -o {Targ} {Deps} + + + +ConfigInfoBin = {ResultDir}ConfigInfo.x + +{ConfigInfoBin} Ä ConfigInfo.s + PPCAsm -o {Targ} {Deps} + + + +#### PowerPC NanoKernel #### +NKDir = :NanoKernel: +NKIncDir = :Internal: +NKBin = {ResultDir}NanoKernel.x +NKOpts = +#include "{NKDir}InnerMakeFile" + + + +EmulatorBin = Emulator.x + + + +{ResultDir}PowerROM Ä {RomBin} {ExceptionTableBin} {ConfigInfoBin} {NKBin} {EmulatorBin} + {LinkerDir}LinkPowerROM {Targ} ¶ + RomTop: ¶ + 0x000000 Mac68kRomTop: ¶ + {RomBin} ¶ + Mac68kRomBtm: ¶ + ¶ + 0x300000 ExTblTop: ¶ + {ExceptionTableBin} ¶ + ¶ + 0x30d000 ConfigInfoChecksum: ¶ + {ConfigInfoBin} ¶ + ¶ + 0x310000 NKTop: ¶ + {NKBin} ¶ + ¶ + 0x360000 ¶ + {EmulatorBin} ¶ + 0x400000 RomBtm: ¶ + > {ResultDir}LinkerScript ; {ResultDir}LinkerScript diff --git a/NanoKernel/InnerMakeFile b/NanoKernel/InnerMakeFile new file mode 100644 index 0000000..c4f2df2 --- /dev/null +++ b/NanoKernel/InnerMakeFile @@ -0,0 +1,42 @@ +# I expect these variables to be set already: +# NKDir, NKIncDir, NKBin + +NKFiles = ¶ + {NKDir}NKInit.s ¶ + {NKDir}NKReplacementInit.s ¶ + {NKDir}NKBuiltinInit.s ¶ + {NKDir}NKProcFlagsTbl.s ¶ + {NKDir}NKProcInfoTbl.s ¶ + {NKDir}NKInterrupts.s ¶ + {NKDir}NKPaging.s ¶ + {NKDir}NKTranslation.s ¶ + {NKDir}NKVMCalls.s ¶ + {NKDir}NKPowerCalls.s ¶ + {NKDir}NKRTASCalls.s ¶ + {NKDir}NKCacheCalls.s ¶ + {NKDir}NKMPCalls.s ¶ + {NKDir}NKSync.s ¶ + {NKDir}NKTasks.s ¶ + {NKDir}NKAddressSpaceMPCalls.s ¶ + {NKDir}NKPoolAllocator.s ¶ + {NKDir}NKTimers.s ¶ + {NKDir}NKScheduler.s ¶ + {NKDir}NKIndex.s ¶ + {NKDir}NKPrimaryIntHandlers.s ¶ + {NKDir}NKConsoleLog.s ¶ + {NKDir}NKSleep.s ¶ + {NKDir}NKThud.s ¶ + {NKDir}NKScreenConsole.s ¶ + {NKDir}NKAdditions.s ¶ + +NKIncludes = ¶ + {NKDir}NKMacros.s ¶ + {NKDir}NKEquates.s ¶ + {NKIncDir}InfoRecords.a ¶ + {NKIncDir}EmulatorPublic.a ¶ + {NKIncDir}NKPublic.a ¶ + {NKIncDir}NKOpaque.a ¶ + +# We get warning 3202 from ALIGN directives -- kill it +{NKBin} Ä {NKDir}NanoKernel.s {NKFiles} {NKIncludes} + PPCAsm -o {Targ} -w 3202 -i {NKIncDir} -i "{AIncludes}" {NKDir}NanoKernel.s diff --git a/NanoKernel/MakeFile b/NanoKernel/MakeFile new file mode 100644 index 0000000..6c27ac4 --- /dev/null +++ b/NanoKernel/MakeFile @@ -0,0 +1,9 @@ +# Lets you just run Make in this directory, +# while ignoring the rest of the build system + +NKDir = : +NKIncDir = {NKDir}:Internal: +NKBin = {NKDir}NanoKernel.s.x +NKOpts = + +#include "{NKDir}InnerMakeFile" diff --git a/NanoKernel/NKAdditions.s b/NanoKernel/NKAdditions.s new file mode 100644 index 0000000..371be32 --- /dev/null +++ b/NanoKernel/NKAdditions.s @@ -0,0 +1,61 @@ +;_______________________________________________________________________ +; My additions to the NanoKernel, to go at the end of the code image +;_______________________________________________________________________ + + if &TYPE('NKDebugShim') != 'UNDEFINED' + + DeclareMPCall 200, NKDebug + +NKDebug + + ; Lifted from NKxprintf: + ; Put the physical address of the r3 arg in r8 + + rlwinm. r9, r11, 0, MSR_DRbit, MSR_DRbit ; IntSyscall sets this + mr r8, r3 + + beq- @already_physical + li r9, 0 + bl V2P ; takes page EA in r8, r9=0, returns page PA in r17 + beq- @fail + rlwimi r8, r17, 0, 0, 19 +@already_physical + + + ; Copy the command into the KDP buffer reserved for this purpose: + ; r8 = src + ; r29 = dest + ; r30 = ctr + ; r31 = val + + mfsprg r1, 0 + lwz r1, EWA.PA_KDP(r1) + + li r30, 0 + addi r29, r1, -0x960 +@cmdloop + lbzx r31, r8, r30 + stbx r31, r29, r30 + addi r30, r30, 1 + cmpwi r31, 0 + bne @cmdloop + + lwz r31, -0x404(r1) + + stw r8, -0x404(r1) + + bl panic + + lwz r8, -0x404(r1) + li r0, 0 + stw r0, 0(r8) + + stw r31, -0x404(r1) + + b ReturnZeroFromMPCall + + +@fail + b ReturnMPCallOOM + + endif diff --git a/NanoKernel/NKAddressSpaceMPCalls.s b/NanoKernel/NKAddressSpaceMPCalls.s new file mode 100644 index 0000000..ea54401 --- /dev/null +++ b/NanoKernel/NKAddressSpaceMPCalls.s @@ -0,0 +1,4454 @@ +Local_Panic set * + b panic + + + +InitFreeList + addi r9, r1, PSA.FreeList + + InitList r9, 'PHYS', scratch=r8 + + li r8, 0 + stw r8, PSA.FreePageCount(r1) + stw r8, PSA.UnheldFreePageCount(r1) + stw r8, PSA.ZeroedByInitFreeList3(r1) + + lwz r8, PSA.OtherSystemAddrSpcPtr(r1) + stw r8, PSA.OtherSystemAddrSpcPtr2(r1) + + blr + + + +; convert_pmdts_to_areas + +; Pretty obvious from log output. + +; Xrefs: +; setup + +convert_pmdts_to_areas ; OUTSIDE REFERER + + ; The kind of crap we have to do without a stack + mflr r16 + mfcr r17 + stw r16, EWA.SpacesSavedLR(r1) + stw r17, EWA.SpacesSavedCR(r1) + + _log 'Converting PMDTs to areas^n' + + lwz r17, PSA.UnheldFreePageCount(r1) + lwz r16, KDP.TotalPhysicalPages(r1) + add r17, r17, r16 + stw r17, PSA.UnheldFreePageCount(r1) + + +;_______________________________________________________________________ +; Code to increment a loop that: +; iterates over segmap entries, and +; iterates over PMDTs, starting at the one +; ref'd by the segmap entry +;_______________________________________________________________________ + + addi r27, r1, KDP.SegMaps - 8 + lis r26, 0 + +@next_segment_entry + _wlog 'SEGMENT ', r26, '^n' + + lwzu r25, 8(r27) + + b @this_pmdt +@next_pmdt + addi r25, r25, PMDT.Size +@this_pmdt + + +;_______________________________________________________________________ +; Now we enter the loop body: +; r27 points to segmap entry +; r25 points to the PMDT +; r26 equals the base address of this segment +;_______________________________________________________________________ + + + ; Load the contents of the PMDT. + + lwz r17, PMDT.PBaseAndFlags(r25) + _wlog ' PMDT PBaseAndFlags ', r17, ' ' + + lhz r15, PMDT.LBase(r25) + _wlogh 'LBase ', r15, ' ' + + andi. r8, r17, $800 | $400 | $200 ; interested in 3 PBase flags + + lhz r16, PMDT.PageCount(r25) + _wlogh 'PageCount ', r16, '^n', scratch=r9 ; cannot clobber r8 here + + + ; Based on those flags, do one of two things + cmplwi r8, 0 + cmplwi cr1, r8, $800 | $400 + beq- @pmdt_flags_are_zero + beq- cr1, @pmdt_flags_are_c00 + + ; Else if not a full-segment PMDT, next PMDT + cmplwi cr2, r15, 0x0000 + cmplwi cr3, r16, 0xffff + bne+ cr2, @next_pmdt + bne+ cr3, @next_pmdt + + ; Else if there are segments remaining (16 total), next segment. + addis r26, r26, 0x1000 + cmplwi r26, 0 ; once it wraps to zero, we're done + bne+ @next_segment_entry + + ; Else create special one-page Areas to catch naughty pointer derefs, + ; then return. + + ; 61F168F1 (magic bus error incantation) + + li r8, Area.Size + bl PoolAlloc + mr. r31, r8 + beq+ Local_Panic + + lwz r8, EWA.PA_CurAddressSpace(r1) + stw r8, Area.AddressSpacePtr(r31) + + lisori r15, 0x68f168f1 + stw r15, Area.LogicalBase(r31) + + li r16, 0x1000 + stw r16, Area.Length(r31) + + lisori r8, 0x00008000 + stw r8, Area.Zero(r31) + + li r8, 0 + stw r8, 0x001c(r31) + + lisori r8, 0x0000e00c + stw r8, 0x0020(r31) + + mr r8, r31 + bl createarea + + cmpwi r9, noErr + beq- @success_68f168f1 + mr r8, r31 + bl PoolFree +@success_68f168f1 + + + ; DEADBEEF (all over the place) + + li r8, Area.Size + bl PoolAlloc + mr. r31, r8 + beq+ Local_Panic + + lwz r8, EWA.PA_CurAddressSpace(r1) + stw r8, Area.AddressSpacePtr(r31) + + lisori r15, 0xdeadbeef + stw r15, Area.LogicalBase(r31) + + li r16, 0x1000 + stw r16, Area.Length(r31) + + lisori r8, 0x00008000 + stw r8, Area.Zero(r31) + + li r8, 0 + stw r8, 0x001c(r31) + + lisori r8, 0x0000e00c + stw r8, 0x0020(r31) + + mr r8, r31 + bl createarea + + cmpwi r9, noErr + beq- @success_deadbeef + mr r8, r31 + bl PoolFree +@success_deadbeef + + + ; Done -- return. + lwz r16, EWA.SpacesSavedLR(r1) + lwz r17, EWA.SpacesSavedCR(r1) + mtlr r16 + mtcr r17 + blr + + + ; ONE OF THE "FLAGS" CASES: all tests bits unset + +@pmdt_flags_are_zero + _clog ' pmdt_flags_are_zero^n' + + ; Apparently other iterations leave this to find? + lwz r8, EWA.SpacesDeferredAreaPtr(r1) + cmpwi r8, 0 + beq- @thing_is_zero + + bl createarea + cmpwi r9, noErr + bne+ Local_Panic + + li r8, 0 + stw r8, EWA.SpacesDeferredAreaPtr(r1) +@thing_is_zero + + + + li r8, Area.Size + bl PoolAlloc + mr. r31, r8 + beq+ Local_Panic + + ; Reload PMDT details + lwz r17, PMDT.PBaseAndFlags(r25) + lhz r15, PMDT.LBase(r25) + lhz r16, PMDT.PageCount(r25) + + ; Why do we need to sign the area? Isn't it 'AREA'? + lisori r8, 'area' + stw r8, Area.Signature(r31) + + ; Set r15/r16 to true logical base/length + slwi r15, r15, 12 + addi r16, r16, 1 + add r15, r15, r26 ; add a page, I think + slwi r16, r16, 12 + + lwz r8, KDP.NanoKernelInfo + NKNanoKernelInfo.blueProcessID(r1) + stw r8, Area.ProcessID(r31) + + lwz r8, EWA.PA_CurAddressSpace(r1) + stw r8, Area.AddressSpacePtr(r31) + + stw r15, Area.LogicalBase(r31) + + stw r16, Area.Length(r31) + stw r16, Area.Length2(r31) + + li r8, 0 + stw r8, Area.Zero(r31) + + lwz r18, 0x007c(r31) + rlwinm r9, r17, 0, 0, 19 + stw r9, 0x0070(r31) + andi. r16, r17, 0x03 + bne- @_20c + ori r17, r17, 0x02 +@_20c + + bl major_0x10d38_0x58 + stw r18, 0x001c(r31) + + +@_214 + + + + lisori r8, 0x0000e00c + stw r8, 0x0020(r31) + + + ; Try to create the Area. If we succeed then do the next PMDT. + mr r8, r31 + bl createarea + cmpwi r9, noErr + mr r31, r8 + beq+ @next_pmdt + + ; If CreateArea failed, assume that it was due to overlap with another Area. + + ; Find that AboveArea that we impinged on (=> r24). + lwz r9, Area.LogicalBase(r31) + lwz r8, Area.AddressSpacePtr(r31) + bl FindAreaAbove + mr r24, r8 + + ; Shorten our FailedArea to fit below AboveArea. + lwz r15, Area.LogicalBase(r31) + lwz r16, Area.LogicalBase(r24) + lwz r17, Area.LogicalBase2(r31) + subf. r16, r15, r16 ; r16 = offset of found area from this one + stw r17, EWA.SpacesSavedAreaBase(r1) ; ??? + stw r16, Area.Length(r31) ; we will try again, with no overlap + + beq- @found_area_has_same_base + + ; If FoundArea < FailedArea, panic (impossible for FindAreaAbove to return this) + bltl+ Local_Panic ; below would be impossible + + ; If AboveArea > FailedArea, create NewArea (=> r30) + mr r8, r31 + bl createarea + + cmpwi r9, noErr ; strike three + mr r30, r8 + bnel+ Local_Panic + + ; If AboveArea.LogicalBase2 >= FailedArea.LogicalBase2 then continue to next PMDT. + lwz r15, Area.LogicalBase2(r24) + lwz r16, EWA.SpacesSavedAreaBase(r1) + subf. r16, r15, r16 + ble+ @next_pmdt + + ; Else replace FailedArea with an Area copied from NewArea + li r8, Area.Size + bl PoolAlloc + mr. r31, r8 + beq+ Local_Panic + + li r8, Area.Size - 4 +@area_copy_loop + lwzx r9, r8, r30 + stwx r9, r8, r31 + cmpwi r8, 0 + subi r8, r8, 4 + bgt+ @area_copy_loop +@found_area_has_same_base + + ; Else (AboveArea == ThisArea), do nothing special (endif) + + + lwz r9, Area.LogicalBase(r31) + + lwz r15, 0x0028(r24) + lwz r16, EWA.SpacesSavedAreaBase(r1) ; this is FailedArea.LogicalBase2 + subf. r16, r15, r16 + addi r15, r15, 1 + blel+ Local_Panic + + stw r16, Area.Length(r31) + stw r15, Area.LogicalBase(r31) + subf r9, r9, r15 + lwz r8, 0x0070(r31) + add r8, r8, r9 + stw r8, 0x0070(r31) + b @_214 + + + + +@pmdt_flags_are_c00 + _clog ' pmdt_flags_are_c00^n' + li r8, Area.Size + bl PoolAlloc + mr. r31, r8 + beq+ Local_Panic + + lwz r17, 0x0004(r25) + lhz r15, 0x0000(r25) + lhz r16, 0x0002(r25) + lis r8, 0x6172 + ori r8, r8, 0x6561 + stw r8, Area.Signature(r31) + slwi r15, r15, 12 + addi r16, r16, 0x01 + add r15, r15, r26 + slwi r16, r16, 12 + lwz r8, 0x0ec0(r1) + stw r8, Area.ProcessID(r31) + lwz r8, EWA.PA_CurAddressSpace(r1) + stw r8, Area.AddressSpacePtr(r31) + stw r15, Area.LogicalBase(r31) + stw r16, Area.Length(r31) + stw r16, Area.Length2(r31) + li r8, 0x00 + stw r8, Area.Zero(r31) + li r8, 0x07 + stw r8, 0x001c(r31) + lis r8, 0x00 + ori r8, r8, 0x600c + stw r8, 0x0020(r31) + rlwinm r8, r17, 22, 0, 29 + stw r8, 0x0040(r31) + lwz r8, Area.TwoFiftySix(r31) + ori r8, r8, 0x40 + lwz r9, -0x0430(r1) + cmpwi r9, noErr + + bgt- @_374 + ori r8, r8, 0x80 +@_374 + + stw r8, Area.TwoFiftySix(r31) + cmpwi r15, 0x00 + + bne- @_388 + stw r31, EWA.SpacesDeferredAreaPtr(r1) + b @next_pmdt +@_388 + + lwz r18, EWA.SpacesDeferredAreaPtr(r1) + cmpwi r18, 0x00 + beq- @_3c8 + lwz r8, 0x0024(r18) + lwz r9, 0x002c(r18) + add r19, r8, r9 + cmplw r19, r15 + bne- @_3c8 + add r9, r9, r16 + addi r19, r9, -0x01 + stw r9, 0x002c(r18) + stw r9, 0x0038(r18) + stw r19, 0x0028(r18) + mr r8, r31 + bl PoolFree + b @next_pmdt +@_3c8 + + lwz r8, Area.TwoFiftySix(r31) + ori r8, r8, 0x80 + stw r8, Area.TwoFiftySix(r31) + mr r8, r31 + bl createarea + cmpwi r9, noErr + bne+ Local_Panic + b @next_pmdt + + + + + +; KCGetPageSizeClasses + + +; > r1 = kdp + +; < r3 = pageClass + + DeclareMPCall 68, KCGetPageSizeClasses + +KCGetPageSizeClasses ; OUTSIDE REFERER + li r3, 0x01 + b CommonMPCallReturnPath + + + +; KCGetPageSize + + +; > r1 = kdp +; > r3 = pageClass + +; < r3 = byteCount + + DeclareMPCall 69, KCGetPageSize + +KCGetPageSize ; OUTSIDE REFERER + cmpwi r3, 0x01 + bne+ ReturnParamErrFromMPCall + lwz r3, 0x0f30(r1) + b CommonMPCallReturnPath + + + + DeclareMPCall 70, MPCall_70 + +MPCall_70 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mfsprg r16, 0 + lwz r17, -0x0008(r16) + mr r8, r3 + lwz r9, Area.AddressSpacePtr(r17) + lwz r16, 0x0008(r9) + rlwinm. r16, r16, 0, 30, 30 + bne+ ReleaseAndReturnMPCallOOM + bl NKCreateAddressSpaceSub + sync + lwz r16, PSA.SchLock + Lock.Count(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + bne+ cr1, MPCall_70_0x54 + mflr r16 + bl panic + +MPCall_70_0x54 + stw r16, PSA.SchLock + Lock.Count(r1) + mr. r3, r8 + li r4, 0x00 + bne+ CommonMPCallReturnPath + lwz r4, 0x0000(r9) + b CommonMPCallReturnPath + + + +; ARG MPCoherenceID r8 owningcgrp ; 0 to use mobo cgrp +; Process *r9 owningPROC + +; RET osErr r8 +; AddressSpace *r9 + +NKCreateAddressSpaceSub + cmpwi r8, 0 + mr r27, r9 ; Save the process arg for later + mflr r30 + + ; Use the motherboard coherence group if none is provided in r8 + bne- @cgrp_provided + mfsprg r15, 0 + lwz r28, EWA.CPUBase + CPU.CgrpList + LLL.Freeform(r15) + + b @got_cgrp + +@cgrp_provided + bl LookupID ; takes id in r8, returns ptr in r8 and kind in r9 + + cmpwi r9, CoherenceGroup.kIDClass + mr r28, r8 + bne- @fail_notcgrp + lwz r28, CoherenceGroup.GRPSList + LLL.Next(r28) + +@got_cgrp + + + ; Read the SpecialPtr of this cgrp element in list of the owning CpuStruct + ; But why? cgrp.LLL.Freeform does not seem to be set for the mobo cgrp + lwz r29, LLL.Freeform(r28) + + + ; Boast (including the SpecialPtr) + _log 'NKCreateAddressSpaceSub - group at 0x' + + mr r8, r28 + bl printw + + mr r8, r29 + bl printw + + _log '^n' + + + ; Create the AddressSpace + li r8, AddressSpace.Size + bl PoolAlloc + mr. r31, r8 + beq- @fail_OOM + + + ; Give the addr spc a copy of the SpecialPtr of its parent cgrp + stw r29, AddressSpace.ParentCoherenceSpecialPtr(r31) + + + ; Give the addr spc an ID + li r9, AddressSpace.kIDClass + bl MakeID + + cmpwi r8, 0x00 + beq- @fail_MakeID + + stw r8, AddressSpace.ID(r31) + + + ; Increment a counter in the cgrp (modulo a million, fail on overflow) + lwz r16, CoherenceGroup.Incrementer(r28) + addi r16, r16, 1 + clrlwi. r16, r16, 12 + beq- @fail_toomanycalls + stw r16, CoherenceGroup.Incrementer(r28) + + + ; Fill segment register fields in the address space struct like so: + ; (8 bits = 0x20) || (4 bits = word idx) || (20 bits = prev call count) + + addi r16, r16, -1 + li r17, 0x40 - 4 + oris r16, r16, 0x2000 + addi r18, r31, AddressSpace.SRs + +@fill_loop + cmpwi r17, 0 + rlwimi r16, r17, 18, 8, 11 ; = index (15, 14, 13...) << 20 + stwx r16, r17, r18 + addi r17, r17, -4 + bne+ @fill_loop + + + ; Sign the addr spc struct + lisori r8, AddressSpace.kSignature + stw r8, AddressSpace.Signature(r31) + + + ; Create an empty linked list of 'rsrv's (what are they?) + addi r16, r31, AddressSpace.RsrvList + InitList r16, 'rsrv', scratch=r17 + + + ; Create a linked list with one Area + addi r16, r31, AddressSpace.AreaList + InitList r16, 'area', scratch=r17 + + ; Allocate the Area, check for errors + li r8, Area.Size + bl PoolAlloc + mr. r29, r8 + beq- @fail_OOM_again + + ; Sign the Area + lisori r8, Area.kSignature + stw r8, Area.Signature(r29) + + ; Pop some constants in + lisori r8, -1 + stw r8, Area.LogicalBase(r29) + stw r8, Area.LogicalBase2(r29) + li r8, 256 + stw r8, Area.TwoFiftySix(r29) + + ; Give it a copy of the ID of its parent address space + lwz r8, AddressSpace.ID(r31) + stw r8, Area.AddressSpaceID(r29) + + ; Point the SpecialPtr to it and insert it in the list + addi r16, r31, AddressSpace.AreaList + addi r29, r29, Area.LLL + stw r16, LLL.Freeform(r29) + InsertAsPrev r29, r16, scratch=r17 + + + ; Point this struct by ID to its owning Process, + ; and increment a counter in that struct. + lwz r18, Process.ID(r27) + stw r18, AddressSpace.ProcessID(r31) + + lwz r17, Process.AddressSpaceCount(r27) + addi r17, r17, 1 + stw r17, Process.AddressSpaceCount(r27) + + + ; Done, with no errors + li r8, 0 ; kMPNoErr + mr r9, r31 ; ptr to new AddressSpace + b @return + +@fail_OOM_again + lwz r8,Area.ID(r31) + +@fail_toomanycalls + bl DeleteID + mr r8, r31 + bl PoolFree + li r8, kMPInsufficientResourcesErr + b @return + +@fail_MakeID + mr r8, r31 + bl PoolFree + +@fail_OOM + li r8, -0x726e + b @return + +@fail_notcgrp + li r8, kMPInvalidIDErr + +@return + mtlr r30 + blr + + + + DeclareMPCall 71, MPCall_71 + +MPCall_71 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, AddressSpace.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + lwz r16, Area.ProcessID(r31) + cmpwi r16, 0x00 + bne+ ReleaseAndReturnMPCallOOM + addi r16, r31, 0x10 + lwz r17, 0x0018(r31) + cmpw r16, r17 + bne+ ReleaseAndReturnMPCallOOM + addi r16, r31, 0x20 + lwz r17, Area.LogicalBase2(r31) + cmpw r16, r17 + bne+ ReleaseAndReturnMPCallOOM + lwz r8, 0x0074(r31) + +; r8 = id + bl LookupID +; r8 = something not sure what +; r9 = 0:inval, 1:proc, 2:task, 3:timer, 4:q, 5:sema, 6:cr, 7:cpu, 8:addrspc, 9:evtg, 10:cgrp, 11:area, 12:not, 13:log + + lwz r17, 0x0018(r8) + addi r17, r17, -0x01 + stw r17, 0x0018(r8) + lwz r8, Area.ID(r31) + bl DeleteID + mr r8, r31 + bl PoolFree + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + +; KCCurrentAddressSpace + + + DeclareMPCall 117, KCCurrentAddressSpace + +KCCurrentAddressSpace ; OUTSIDE REFERER + mfsprg r16, 0 + lwz r17, EWA.PA_CurAddressSpace(r16) + lwz r3, AddressSpace.ID(r17) + b CommonMPCallReturnPath + + + +; KCHomeAddressSpace + + + DeclareMPCall 118, KCHomeAddressSpace + +KCHomeAddressSpace ; OUTSIDE REFERER + mfsprg r16, 0 + lwz r17, EWA.PA_CurTask(r16) + lwz r18, Task.OwningProcessPtr(r17) + lwz r19, Process.SystemAddressSpacePtr(r18) + lwz r3, AddressSpace.ID(r19) + b CommonMPCallReturnPath + + + +; KCSetTaskAddressSpace + + + DeclareMPCall 119, KCSetTaskAddressSpace + +KCSetTaskAddressSpace ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID +; r8 = something not sure what +; r9 = 0:inval, 1:proc, 2:task, 3:timer, 4:q, 5:sema, 6:cr, 7:cpu, 8:addrspc, 9:evtg, 10:cgrp, 11:area, 12:not, 13:log + + mr r31, r8 + cmpwi r9, 0x02 + bne+ ReleaseAndReturnMPCallInvalidIDErr + lwz r16, 0x0064(r31) + mtcr r16 + li r3, -0x7271 + beq+ cr7, ReleaseAndReturnMPCall + bne+ cr5, ReleaseAndReturnMPCallOOM + lbz r16, 0x0018(r31) + cmpwi r16, 0x00 + bne+ ReleaseAndReturnMPCallOOM + mr r8, r4 + +; r8 = id + bl LookupID +; r8 = something not sure what +; r9 = 0:inval, 1:proc, 2:task, 3:timer, 4:q, 5:sema, 6:cr, 7:cpu, 8:addrspc, 9:evtg, 10:cgrp, 11:area, 12:not, 13:log + + mr r30, r8 + lwz r16, 0x0060(r31) + cmpwi r9, 0x08 + lwz r17, 0x0074(r30) + bne+ ReleaseAndReturnMPCallInvalidIDErr + cmpw r16, r17 + bne+ ReleaseAndReturnMPCallOOM + lwz r17, 0x0070(r31) + lwz r16, 0x000c(r17) + addi r16, r16, -0x01 + stw r16, 0x000c(r17) + lwz r16, 0x000c(r30) + addi r16, r16, 0x01 + stw r16, 0x000c(r30) + stw r30, 0x0070(r31) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 72, MPCall_72 + +MPCall_72 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr. r8, r3 + mfsprg r28, 0 + lwz r30, EWA.PA_CurAddressSpace(r28) + beq- MPCall_72_0x38 + +; r8 = id + bl LookupID + cmpwi r9, AddressSpace.kIDClass + + mr r30, r8 + bne+ ReleaseAndReturnMPCallInvalidIDErr + +MPCall_72_0x38 + li r8, 160 + +; r1 = kdp +; r8 = size + bl PoolAlloc +; r8 = ptr + + mr. r31, r8 + beq+ major_0x0af60 + stw r30, Area.AddressSpacePtr(r31) + stw r4, 0x001c(r31) + stw r5, Area.Length(r31) + lwz r8, 0x0134(r6) + stw r8, Area.Zero(r31) + lwz r8, 0x013c(r6) + stw r8, 0x0020(r31) + lwz r8, 0x0144(r6) + stw r8, Area.LogicalBase(r31) + mr r8, r31 + bl createarea + sync + lwz r16, PSA.SchLock + Lock.Count(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + bne+ cr1, MPCall_72_0x90 + mflr r16 + bl panic + +MPCall_72_0x90 + stw r16, PSA.SchLock + Lock.Count(r1) + mr. r3, r9 + bne- MPCall_72_0xb0 + lwz r8, Area.LogicalBase(r31) + stw r8, 0x0144(r6) + lwz r8, Area.ID(r31) + stw r8, 0x014c(r6) + b CommonMPCallReturnPath + +MPCall_72_0xb0 + bl PoolFree + b CommonMPCallReturnPath + + + +; createarea + +; Xrefs: +; convert_pmdts_to_areas +; MPCall_72 +; MPCall_73 + +; This function actually gets passed its own structure. +; What the frick? + +; Always returns via ReturnFromCreateArea + +; ARG Area *r8 +; RET ID r8, osErr r9 + +createarea ; OUTSIDE REFERER + + ; Always returns via ReturnFromCreateArea + mflr r16 + mfsprg r9, 0 + stw r16, EWA.CreateAreaSavedLR(r9) + stmw r25, EWA.CreateAreaSavedR25(r9) + + ; Keep the structure itself in r31 for the duration. + ; r8 must be used for other things + mr r31, r8 + + ; For if we need to return early + li r9, paramErr + + + lwz r16, Area.TwoFiftySix(r31) + lwz r17, 0x0020(r31) + rlwinm. r16, r16, 0, 28, 28 + + lisori r16, 0xfffc13e0 ; if bit 28 = 0 + beq- @use_other + lisori r16, 0xfff99be0 ; if bit 28 = 1 +@use_other + + and. r16, r16, r17 + bne- ReturnFromCreateArea + + andi. r16, r17, 0x1f + cmpwi cr1, r16, 0x0c + beq- createarea_0x50 + blt- cr1, ReturnFromCreateArea + +createarea_0x50 + bne- createarea_0x5c + ori r17, r17, 0x0c + stw r17, 0x0020(r31) + +createarea_0x5c + andi. r16, r17, 0x1f + li r18, -0x01 + slw r18, r18, r16 + stw r18, 0x0078(r31) + rlwinm. r16, r17, 27, 27, 31 + bne- ReturnFromCreateArea + addi r16, r16, 0x0c + li r18, -0x01 + slw r18, r18, r16 + stw r18, 0x007c(r31) + neg r16, r18 + not r19, r18 + stw r16, 0x0068(r31) + lwz r16, Area.Length(r31) + add r16, r16, r19 + and. r16, r16, r18 + stw r16, Area.Length(r31) + beq- ReturnFromCreateArea + lwz r18, 0x001c(r31) + lis r16, -0x01 + ori r16, r16, 0xff10 + and. r16, r16, r18 + bne- ReturnFromCreateArea + lwz r16, 0x0070(r31) + li r17, 0x200 + rlwimi r17, r16, 0, 0, 19 + bl major_0x10cb8 + stw r16, 0x0070(r31) + stw r17, 0x0074(r31) + mr r8, r31 + + li r9, Area.kIDClass + bl MakeID + cmpwi r8, 0 + beq- major_0x10320 + + stw r8, Area.ID(r31) + mfsprg r16, 0 + lwz r17, -0x0008(r16) + lwz r18, 0x0060(r17) + lwz r30, Area.AddressSpacePtr(r17) + stw r18, Area.ProcessID(r31) + lwz r16, Area.AddressSpacePtr(r31) + lwz r17, 0x0000(r16) + stw r17, Area.AddressSpaceID(r31) + lwz r16, 0x0008(r30) + rlwinm. r16, r16, 0, 30, 30 + bne- major_0x10320_0x64 + lis r16, 0x4152 + ori r16, r16, 0x4541 + stw r16, Area.Signature(r31) + lwz r17, 0x0020(r31) + lwz r16, Area.Zero(r31) + addi r16, r16, 0xfff + rlwinm r16, r16, 0, 0, 19 + stw r16, Area.Zero(r31) + rlwinm r16, r17, 0, 17, 18 + cmplwi cr7, r16, 0x6000 + rlwinm. r16, r17, 0, 17, 17 + beq- cr7, createarea_0x150 + bne- createarea_0x150 + crset cr7_gt + crclr cr7_lt + +createarea_0x150 + rlwinm. r16, r17, 0, 17, 18 + lwz r18, Area.LogicalBase(r31) + lwz r19, Area.Length(r31) + blt- cr7, createarea_0x16c + bne- createarea_0x170 + li r18, 0x00 + b createarea_0x170 + +createarea_0x16c + subf r18, r19, r18 + +createarea_0x170 + lwz r16, 0x0078(r31) + and r18, r18, r16 + stw r18, Area.LogicalBase(r31) + add r16, r18, r19 + addi r16, r16, -0x01 + stw r16, Area.LogicalBase2(r31) + + + ; Major hint here... + + _log ' CreateArea [ ' + mr r8, r18 + bl Printw + mr r8, r16 + bl Printw + _log '] ID ' + + + lwz r8, Area.ID(r31) + mr r8, r8 + bl Printw + + + bgt- cr7, createarea_0x1f4 + blt- cr7, createarea_0x218 + _log 'placed' + b createarea_0x234 + +createarea_0x1f4 + _log 'placed at or above' + b createarea_0x234 + +createarea_0x218 + _log 'placed below' + +createarea_0x234 + lwz r8, Area.AddressSpacePtr(r31) + lwz r16, Area.LogicalBase2(r31) + lwz r9, Area.LogicalBase(r31) + cmplw r9, r16 + bge- major_0x10320_0x64 + bl FindAreaAbove + mr r30, r8 + lwz r14, Area.LogicalBase(r31) + lwz r15, Area.LogicalBase2(r31) + lwz r16, Area.Zero(r31) + lwz r17, 0x0024(r30) + lwz r18, 0x0028(r30) + lwz r19, 0x0030(r30) + lwz r21, Area.AddressSpacePtr(r31) + cmpwi r17, -0x01 + add r8, r15, r16 + add r9, r15, r19 + beq- createarea_0x2b8 + cmplw r8, r17 + cmplw cr1, r9, r17 + bge- createarea_0x28c + blt- cr1, createarea_0x2b8 + +createarea_0x28c + beq- cr7, major_0x10320_0x64 + _log ' ... bc search^n' + bgt- cr7, createarea_0x34c + b createarea_0x31c + +createarea_0x2b8 + addi r21, r21, 0x20 + lwz r20, 0x0060(r30) + cmpw r20, r21 + beq- createarea_0x39c + addi r20, r20, -0x54 + lwz r17, 0x0024(r20) + lwz r18, 0x0028(r20) + lwz r19, 0x0030(r20) + add r8, r18, r16 + add r9, r18, r19 + cmplw r8, r14 + cmplw cr1, r9, r14 + bge- createarea_0x2f0 + blt- cr1, createarea_0x374 + +createarea_0x2f0 + beq- cr7, major_0x10320_0x64 + _log ' ... ab search^n' + bgt- cr7, createarea_0x34c + b createarea_0x31c + +createarea_0x31c + subf r8, r19, r17 + subf r9, r16, r17 + cmplw r8, r9 + lwz r21, Area.Length(r31) + ble- createarea_0x334 + mr r8, r9 + +createarea_0x334 + subf r8, r21, r8 + cmplw r8, r14 + addi r18, r8, 0x01 + lwz r19, Area.Length(r31) + bge- major_0x10320_0x64 + b createarea_0x170 + +createarea_0x34c + add r8, r18, r19 + add r9, r18, r16 + lwz r20, 0x0078(r31) + cmplw r8, r9 + neg r21, r20 + bge- createarea_0x368 + mr r8, r9 + +createarea_0x368 + add r18, r8, r21 + lwz r19, Area.Length(r31) + b createarea_0x170 + +createarea_0x374 + addi r19, r31, 0x54 + addi r20, r20, 0x54 + lwz r16, 0x0000(r20) + stw r16, 0x0000(r19) + lwz r16, 0x0008(r20) + stw r16, 0x0008(r19) + stw r20, 0x000c(r19) + stw r19, 0x000c(r16) + stw r19, 0x0008(r20) + b createarea_0x3b8 + +createarea_0x39c + addi r19, r31, 0x54 + stw r20, 0x0000(r19) + stw r20, 0x000c(r19) + lwz r16, 0x0008(r20) + stw r16, 0x0008(r19) + stw r19, 0x000c(r16) + stw r19, 0x0008(r20) + +createarea_0x3b8 + addi r16, r31, 0x90 + lis r17, 0x6665 + stw r16, 0x0008(r16) + ori r17, r17, 0x6e63 + stw r16, 0x000c(r16) + stw r17, 0x0004(r16) + lwz r16, 0x0020(r31) + lwz r17, Area.TwoFiftySix(r31) + rlwinm. r8, r16, 0, 16, 16 + bne- createarea_0x64c + rlwinm. r8, r17, 0, 25, 25 + bne- createarea_0x41c + lwz r8, Area.Length(r31) + rlwinm r8, r8, 22, 10, 29 + mr r29, r8 + +; r1 = kdp +; r8 = size + bl PoolAlloc +; r8 = ptr + + cmpwi r8, 0x00 + stw r8, 0x0040(r31) + beq- createarea_0x460 + lwz r9, Area.Length(r31) + srwi r9, r9, 12 + bl major_0x10284 + lwz r17, Area.TwoFiftySix(r31) + ori r17, r17, 0x10 + stw r17, Area.TwoFiftySix(r31) + +createarea_0x41c + lwz r17, Area.TwoFiftySix(r31) + andi. r8, r17, 0x88 + lwz r8, Area.Length(r31) + bne- createarea_0x45c + rlwinm r8, r8, 21, 11, 30 + mr r29, r8 + +; r1 = kdp +; r8 = size + bl PoolAlloc +; r8 = ptr + + cmpwi r8, 0x00 + stw r8, 0x003c(r31) + beq- createarea_0x460 + lwz r9, Area.Length(r31) + srwi r9, r9, 12 + bl major_0x102a8 + lwz r16, Area.TwoFiftySix(r31) + ori r16, r16, 0x01 + stw r16, Area.TwoFiftySix(r31) + +createarea_0x45c + b createarea_0x64c + +createarea_0x460 + cmpwi r29, 0xfd8 + ble- major_0x10320_0x20 + + _Lock PSA.PoolLock, scratch1=r16, scratch2=r17 + + lwz r17, Area.TwoFiftySix(r31) + li r27, 0x00 + rlwinm. r8, r17, 0, 25, 25 + bne- createarea_0x4b4 + lwz r27, Area.Length(r31) + srwi r27, r27, 12 + cmpwi r27, 0x400 + ble- createarea_0x4ac + ori r17, r17, 0x20 + stw r17, Area.TwoFiftySix(r31) + addi r27, r27, 0x400 + +createarea_0x4ac + addi r27, r27, 0x3ff + srwi r27, r27, 10 + +createarea_0x4b4 + lwz r8, Area.TwoFiftySix(r31) + li r29, 0x00 + rlwinm. r9, r8, 0, 28, 28 + bne- createarea_0x4e8 + lwz r29, Area.Length(r31) + srwi r29, r29, 12 + cmpwi r29, 0x800 + ble- createarea_0x4e0 + ori r8, r8, 0x02 + stw r8, Area.TwoFiftySix(r31) + addi r29, r29, 0x800 + +createarea_0x4e0 + addi r29, r29, 0x7ff + srwi r29, r29, 11 + +createarea_0x4e8 + lwz r18, -0x0430(r1) + add. r8, r27, r29 + ble- major_0x102c8 + cmpw r8, r18 + bgt- major_0x102c8 + lwz r16, -0x0430(r1) + lwz r17, PSA.UnheldFreePageCount(r1) + subf r16, r8, r16 + subf r17, r8, r17 + stw r16, -0x0430(r1) + stw r17, PSA.UnheldFreePageCount(r1) + mr. r18, r27 + beq- createarea_0x5a0 + lwz r16, -0x0448(r1) + lwz r17, 0x0008(r16) + lwz r19, 0x000c(r16) + stw r17, 0x0008(r19) + stw r19, 0x000c(r17) + li r17, 0x00 + stw r17, 0x0008(r16) + stw r17, 0x000c(r16) + addi r18, r18, -0x01 + stw r16, 0x0040(r31) + cmpwi r18, 0x00 + lwz r17, -0x0448(r1) + mr r8, r16 + subi r16, r16, 4 + bgt- createarea_0x564 + li r9, 0x400 + bl major_0x10284 + b createarea_0x5a0 + +createarea_0x564 + lwz r19, 0x0008(r17) + lwz r20, 0x000c(r17) + stw r19, 0x0008(r20) + stw r20, 0x000c(r19) + li r19, 0x00 + stw r19, 0x0008(r17) + stw r19, 0x000c(r17) + addi r18, r18, -0x01 + stwu r17, 0x0004(r16) + mr r8, r17 + li r9, 0x400 + bl major_0x10284 + lwz r17, -0x0448(r1) + cmpwi r18, 0x00 + bgt+ createarea_0x564 + +createarea_0x5a0 + mr. r18, r29 + beq- createarea_0x62c + lwz r16, -0x0448(r1) + lwz r17, 0x0008(r16) + lwz r19, 0x000c(r16) + stw r17, 0x0008(r19) + stw r19, 0x000c(r17) + li r17, 0x00 + stw r17, 0x0008(r16) + stw r17, 0x000c(r16) + addi r18, r18, -0x01 + stw r16, 0x003c(r31) + cmpwi r18, 0x00 + lwz r17, -0x0448(r1) + mr r8, r16 + subi r16, r16, 4 + bgt- createarea_0x5f0 + li r9, 0x800 + bl major_0x102a8 + b createarea_0x62c + +createarea_0x5f0 + lwz r19, 0x0008(r17) + lwz r20, 0x000c(r17) + stw r19, 0x0008(r20) + stw r20, 0x000c(r19) + li r19, 0x00 + stw r19, 0x0008(r17) + stw r19, 0x000c(r17) + addi r18, r18, -0x01 + stwu r17, 0x0004(r16) + mr r8, r17 + li r9, 0x800 + bl major_0x102a8 + lwz r17, -0x0448(r1) + cmpwi r18, 0x00 + bgt+ createarea_0x5f0 + +createarea_0x62c + sync + lwz r16, -0x0ad0(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + bne+ cr1, createarea_0x648 + mflr r16 + bl panic + +createarea_0x648 + stw r16, -0x0ad0(r1) + +createarea_0x64c + lwz r16, Area.TwoFiftySix(r31) + rlwinm. r8, r16, 0, 28, 28 + beq- createarea_0x67c + lwz r16, 0x0044(r31) + addi r17, r31, 0x44 + stw r16, 0x0000(r17) + stw r16, 0x0008(r17) + lwz r18, 0x000c(r16) + stw r18, 0x000c(r17) + stw r17, 0x0008(r18) + stw r17, 0x000c(r16) + b major_0x10320_0x94 + +createarea_0x67c + addi r16, r31, 0x44 + lis r17, 0x414b + stw r16, 0x0008(r16) + ori r17, r17, 0x4120 + stw r16, 0x000c(r16) + stw r17, 0x0004(r16) + b major_0x10320_0x94 + + + +; major_0x10284 + +; Xrefs: +; createarea + +major_0x10284 ; OUTSIDE REFERER + subi r8, r8, 4 + addi r9, r9, -0x01 + lwz r20, 0x0074(r31) + ori r20, r20, 0x200 + +major_0x10284_0x10 + cmpwi r9, noErr + stwu r20, 0x0004(r8) + addi r9, r9, -0x01 + bgt+ major_0x10284_0x10 + blr + + + +; major_0x102a8 + +; Xrefs: +; createarea + +major_0x102a8 ; OUTSIDE REFERER + addi r8, r8, -0x02 + addi r9, r9, -0x01 + li r20, 0x7fff + +major_0x102a8_0xc + cmpwi r9, noErr + sthu r20, 0x0002(r8) + addi r9, r9, -0x01 + bgt+ major_0x102a8_0xc + blr + + + +; major_0x102c8 + +; Xrefs: +; createarea + +major_0x102c8 ; OUTSIDE REFERER + sync + lwz r16, -0x0ad0(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + bne+ cr1, major_0x102c8_0x1c + mflr r16 + bl panic + +major_0x102c8_0x1c + stw r16, -0x0ad0(r1) + addi r30, r8, 0x08 + lwz r8, -0x0420(r1) + +; r8 = id + bl LookupID + cmpwi r9, Notification.kIDClass + + mr r26, r8 + bne- major_0x10320_0x20 + li r8, 0x02 + stw r8, 0x0010(r26) + stw r30, 0x0014(r26) + li r29, 0x00 + stw r29, 0x0018(r26) + mr r30, r26 + bl major_0x0db04 + b major_0x10320_0x20 + + + +; major_0x10320 + +; Xrefs: +; IntDSIOtherOther +; PagingFunc1 +; MPCall_60 +; convert_pmdts_to_areas +; createarea +; major_0x102c8 +; MPCall_80 +; MPCall_125 +; MPCall_95 + +major_0x10320 ; OUTSIDE REFERER + mr r8, r31 + li r9, -0x726e + b ReturnFromCreateArea + dc.l 0x811f0000 + dc.l 0x48004fd1 + dc.l 0x7fe8fb78 + dc.l 0x39208d8d + dc.l 0x4800009c + +major_0x10320_0x20 ; OUTSIDE REFERER + addi r19, r31, 0x54 + lwz r16, 0x0008(r19) + lwz r17, 0x000c(r19) + stw r16, 0x0008(r17) + stw r17, 0x000c(r16) + li r16, 0x00 + stw r16, 0x0008(r19) + stw r16, 0x000c(r19) + lwz r16, Area.TwoFiftySix(r31) + lwz r8, 0x0040(r31) + rlwinm. r16, r16, 0, 25, 25 + bne- major_0x10320_0x58 + cmpwi r8, 0x00 + bnel- PoolFree + +major_0x10320_0x58 + lwz r8, 0x003c(r31) + cmpwi r8, 0x00 + bnel- PoolFree + +major_0x10320_0x64 ; OUTSIDE REFERER + _log ' ... skipped^n' + lwz r8, Area.ID(r31) + bl DeleteID + mr r8, r31 + li r9, -0x7272 + b ReturnFromCreateArea + +major_0x10320_0x94 ; OUTSIDE REFERER + _log ' ... created^n' + mr r8, r31 + li r9, 0x00 + + + +ReturnFromCreateArea + mfsprg r16, 0 + lwz r17, EWA.CreateAreaSavedLR(r16) + mtlr r17 + lmw r25, EWA.CreateAreaSavedR25(r16) + blr + + + +; ARG AddressSpace *r8, +; RET Area *r8 + +FindAreaAbove ; OUTSIDE REFERER + lwz r8, AddressSpace.AreaList + LLL.Next(r8) + +@loop + subi r8, r8, Area.LLL + + ; Return an area such that: + ; max(Area.LogicalBase, Area.LogicalBase2) >= r9 + lwz r16, Area.LogicalBase(r8) + lwz r17, Area.LogicalBase2(r8) + cmplw r16, r9 + cmplw cr1, r17, r9 + bgelr- + bgelr- cr1 + + ; Iterate over linked list + lwz r8, Area.LLL + LLL.Next(r8) + b @loop + + + + DeclareMPCall 73, MPCall_73 + +MPCall_73 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + bl LookupID + cmpwi r9, Area.kIDClass + bne+ ReleaseAndReturnMPCallInvalidIDErr + + mr r30, r8 + lwz r16, 0x0008(r30) + rlwinm. r8, r16, 0, 28, 28 + bne+ major_0x0b054 + + li r8, Area.Size + bl PoolAlloc + mr. r31, r8 + beq+ major_0x0af60 + + mfsprg r28, 0 + lwz r8, EWA.PA_CurAddressSpace(r28) + stw r8, Area.AddressSpacePtr(r31) + stw r3, 0x0014(r31) + stw r30, 0x0044(r31) + stw r4, 0x001c(r31) + stw r5, Area.Length(r31) + lwz r8, 0x0134(r6) + stw r8, Area.Zero(r31) + lwz r8, 0x013c(r6) + stw r8, 0x0020(r31) + lwz r8, 0x0144(r6) + stw r8, Area.LogicalBase(r31) + lwz r8, 0x014c(r6) + stw r8, 0x0080(r31) + li r8, 0x08 + stw r8, Area.TwoFiftySix(r31) + mr r8, r31 + bl createarea + sync + lwz r16, PSA.SchLock + Lock.Count(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + bne+ cr1, MPCall_73_0xb0 + mflr r16 + bl panic + +MPCall_73_0xb0 + stw r16, PSA.SchLock + Lock.Count(r1) + mr. r3, r9 + bne- MPCall_73_0xd0 + lwz r8, Area.LogicalBase(r31) + stw r8, 0x0144(r6) + lwz r8, Area.ID(r31) + stw r8, 0x0154(r6) + b CommonMPCallReturnPath + +MPCall_73_0xd0 + bl PoolFree + b CommonMPCallReturnPath + + + + DeclareMPCall 74, MPCall_74 + +MPCall_74 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Area.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + lwz r17, Area.Length2(r31) + lwz r29, Area.TwoFiftySix(r31) + cmpwi cr1, r17, 0x00 + rlwinm. r8, r29, 0, 29, 29 + bne+ cr1, ReleaseAndReturnMPCallOOM + bne+ ReleaseAndReturnMPCallPrivilegedErr + rlwinm. r8, r29, 0, 28, 28 + lwz r16, 0x004c(r31) + bne- MPCall_74_0x5c + addi r17, r31, 0x44 + cmpw r16, r17 + bne+ ReleaseAndReturnMPCallOOM + +MPCall_74_0x5c + + _Lock PSA.HTABLock, scratch1=r18, scratch2=r9 + + addi r16, r31, 0x54 + lwz r17, 0x0008(r16) + lwz r18, 0x000c(r16) + stw r17, 0x0008(r18) + stw r18, 0x000c(r17) + li r17, 0x00 + stw r17, 0x0008(r16) + stw r17, 0x000c(r16) + rlwinm. r8, r29, 0, 28, 28 + addi r16, r31, 0x44 + beq- MPCall_74_0xbc + lwz r17, 0x0008(r16) + lwz r18, 0x000c(r16) + stw r17, 0x0008(r18) + stw r18, 0x000c(r17) + li r17, 0x00 + stw r17, 0x0008(r16) + stw r17, 0x000c(r16) + +MPCall_74_0xbc + sync + lwz r18, -0x0b90(r1) + cmpwi cr1, r18, 0x00 + li r18, 0x00 + bne+ cr1, MPCall_74_0xd8 + mflr r18 + bl panic + +MPCall_74_0xd8 + stw r18, -0x0b90(r1) + lwz r8, 0x0040(r31) + rlwinm. r16, r29, 0, 25, 25 + cmpwi cr1, r8, 0x00 + bne- MPCall_74_0x178 + rlwinm. r16, r29, 0, 27, 27 + beq- cr1, MPCall_74_0x178 + bne- MPCall_74_0x174 + + _Lock PSA.PoolLock, scratch1=r18, scratch2=r9 + + rlwinm. r16, r29, 0, 26, 26 + beq- MPCall_74_0x14c + lwz r19, Area.Length(r31) + mr r20, r8 + srwi r19, r19, 12 + addi r19, r19, 0x3ff + srwi r19, r19, 10 + slwi r19, r19, 2 + subi r19, r19, 4 + +MPCall_74_0x134 + lwzx r8, r19, r20 + +; r1 = kdp +; r8 = maybe the page + bl free_list_add_page + cmpwi r19, 0x00 + subi r19, r19, 4 + bgt+ MPCall_74_0x134 + mr r8, r20 + +MPCall_74_0x14c +; r1 = kdp +; r8 = maybe the page + bl free_list_add_page + sync + lwz r18, -0x0ad0(r1) + cmpwi cr1, r18, 0x00 + li r18, 0x00 + bne+ cr1, MPCall_74_0x16c + mflr r18 + bl panic + +MPCall_74_0x16c + stw r18, -0x0ad0(r1) + b MPCall_74_0x178 + +MPCall_74_0x174 + bl PoolFree + +MPCall_74_0x178 + lwz r8, 0x003c(r31) + clrlwi. r16, r29, 0x1f + cmpwi cr1, r8, 0x00 + beq- cr1, MPCall_74_0x20c + bne- MPCall_74_0x208 + + _Lock PSA.PoolLock, scratch1=r18, scratch2=r9 + + rlwinm. r16, r29, 0, 30, 30 + beq- MPCall_74_0x1e0 + lwz r19, Area.Length(r31) + mr r20, r8 + srwi r19, r19, 12 + addi r19, r19, 0x7ff + srwi r19, r19, 11 + slwi r19, r19, 2 + subi r19, r19, 4 + +MPCall_74_0x1c8 + lwzx r8, r19, r20 + +; r1 = kdp +; r8 = maybe the page + bl free_list_add_page + cmpwi r19, 0x00 + subi r19, r19, 4 + bgt+ MPCall_74_0x1c8 + mr r8, r20 + +MPCall_74_0x1e0 +; r1 = kdp +; r8 = maybe the page + bl free_list_add_page + sync + lwz r18, -0x0ad0(r1) + cmpwi cr1, r18, 0x00 + li r18, 0x00 + bne+ cr1, MPCall_74_0x200 + mflr r18 + bl panic + +MPCall_74_0x200 + stw r18, -0x0ad0(r1) + b MPCall_74_0x20c + +MPCall_74_0x208 + bl PoolFree + +MPCall_74_0x20c + lwz r8, Area.ID(r31) + bl DeleteID + mr r8, r31 + bl PoolFree + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 75, MPCall_75 + +MPCall_75 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Area.kIDClass + + mr r31, r8 + bne+ ReleaseAndReturnMPCallInvalidIDErr + lwz r16, 0x0020(r31) + rlwinm. r8, r16, 0, 16, 16 + bne+ ReleaseAndReturnMPCallOOM + lwz r18, 0x007c(r31) + lwz r17, Area.Length(r31) + and. r5, r5, r18 + and r17, r17, r18 + ble+ major_0x0b054 + subf. r27, r17, r5 + +; r1 = kdp + beq+ ReleaseAndReturnZeroFromMPCall + bgt- MPCall_75_0x1c8 + rlwinm. r8, r4, 0, 24, 24 + lwz r28, Area.LogicalBase(r31) + lwz r29, Area.LogicalBase2(r31) + bne- MPCall_75_0x74 + add r28, r27, r29 + addi r28, r28, 0x01 + b MPCall_75_0x7c + +MPCall_75_0x74 + subf r29, r27, r28 + addi r29, r29, -0x01 + +MPCall_75_0x7c + + _Lock PSA.PoolLock, scratch1=r14, scratch2=r15 + + + _Lock PSA.HTABLock, scratch1=r14, scratch2=r15 + + lwz r27, 0x0068(r31) + +MPCall_75_0xb0 + mr r8, r28 + bl MPCall_95_0x1e4 + beq+ Local_Panic + bl MPCall_95_0x2b0 + bns- cr7, MPCall_75_0xe0 + bltl- cr5, MPCall_95_0x2e0 + bltl- cr5, MPCall_95_0x348 + lwz r17, 0x0000(r30) + rlwinm r17, r17, 0, 0, 30 + rlwinm r8, r17, 0, 0, 19 + stw r17, 0x0000(r30) + +; r1 = kdp +; r8 = maybe the page + bl free_list_add_page + +MPCall_75_0xe0 + add r28, r28, r27 + cmplw r28, r29 + ble+ MPCall_75_0xb0 + rlwinm. r8, r4, 0, 24, 24 + lwz r28, Area.LogicalBase(r31) + beq- MPCall_75_0x138 + lwz r27, 0x0068(r31) + add r29, r29, r27 + +MPCall_75_0x100 + mr r8, r28 + bl MPCall_95_0x1e4 + beq+ Local_Panic + mr r26, r30 + mr r8, r29 + bl MPCall_95_0x1e4 + beq+ Local_Panic + lwz r17, 0x0000(r30) + stw r17, 0x0000(r26) + lwz r16, Area.LogicalBase2(r31) + add r28, r28, r27 + add r29, r29, r27 + cmplw r29, r16 + ble+ MPCall_75_0x100 + +MPCall_75_0x138 + sync + lwz r8, -0x0b90(r1) + cmpwi cr1, r8, 0x00 + li r8, 0x00 + bne+ cr1, MPCall_75_0x154 + mflr r8 + bl panic + +MPCall_75_0x154 + stw r8, -0x0b90(r1) + lwz r16, Area.TwoFiftySix(r31) + rlwinm. r8, r16, 0, 25, 25 + bne- MPCall_75_0x16c + rlwinm. r8, r16, 0, 27, 27 + bne- MPCall_75_0x16c + +MPCall_75_0x16c + sync + lwz r8, -0x0ad0(r1) + cmpwi cr1, r8, 0x00 + li r8, 0x00 + bne+ cr1, MPCall_75_0x188 + mflr r8 + bl panic + +MPCall_75_0x188 + stw r8, -0x0ad0(r1) + b MPCall_75_0x190 + +MPCall_75_0x190 + rlwinm. r8, r4, 0, 24, 24 + lwz r16, Area.LogicalBase(r31) + bne- MPCall_75_0x1b0 + add r17, r16, r5 + addi r17, r17, -0x01 + stw r5, Area.Length(r31) + stw r17, Area.LogicalBase2(r31) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_75_0x1b0 + lwz r17, Area.LogicalBase2(r31) + subf r16, r5, r17 + stw r5, Area.Length(r31) + addi r16, r16, 0x01 + stw r16, Area.LogicalBase(r31) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_75_0x1c8 + rlwinm. r8, r4, 0, 24, 24 + lwz r28, Area.LogicalBase(r31) + lwz r29, Area.LogicalBase2(r31) + bne+ ReleaseAndMPCallWasBad + add r28, r27, r29 + addi r28, r28, 0x01 + b MPCall_75_0x1ec + dc.l 0x7fbbe050 + dc.l 0x3bbdffff + +MPCall_75_0x1ec + b ReleaseAndMPCallWasBad + + + + DeclareMPCall 130, MPCall_130 + +MPCall_130 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Area.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + lis r16, -0x01 + ori r16, r16, 0xfff8 + lwz r17, 0x0020(r31) + and. r16, r16, r4 + bne+ major_0x0b054 + rlwinm. r8, r17, 0, 16, 16 + bne+ major_0x0b054 + mr r29, r5 + lwz r18, 0x0134(r6) + lwz r19, 0x0068(r31) + lwz r16, Area.LogicalBase(r31) + cmplw r18, r19 + add r28, r18, r29 + bge+ major_0x0b054 + lwz r17, 0x007c(r31) + addi r28, r28, -0x01 + lwz r18, 0x0020(r31) + lwz r19, Area.LogicalBase2(r31) + cmplw cr1, r29, r16 + cmplw cr2, r28, r19 + blt+ cr1, major_0x0b054 + bgt+ cr2, major_0x0b054 + xor r8, r28, r29 + rlwinm. r8, r8, 0, 0, 19 + bne+ major_0x0b054 + + _Lock PSA.HTABLock, scratch1=r14, scratch2=r15 + + mr r8, r29 + bl MPCall_95_0x1e4 + sync + lwz r14, -0x0b90(r1) + cmpwi cr1, r14, 0x00 + li r14, 0x00 + bne+ cr1, MPCall_130_0xcc + mflr r14 + bl panic + +MPCall_130_0xcc + stw r14, -0x0b90(r1) + beq+ Local_Panic + rlwinm r8, r16, 0, 29, 30 + lwz r16, 0x0000(r30) + cmpwi cr7, r8, 0x04 + beq+ cr7, major_0x0b054 + lwz r16, 0x0098(r31) + +MPCall_130_0xe8 + addi r17, r31, 0x90 + cmpw r16, r17 + addi r17, r16, 0x14 + beq- MPCall_130_0x11c + lwz r8, 0x0010(r16) + cmplwi r8, 0x1f8 + add r9, r8, r17 + blt- MPCall_130_0x110 + lwz r16, 0x0008(r16) + b MPCall_130_0xe8 + +MPCall_130_0x110 + addi r8, r8, 0x08 + addi r9, r9, 0x08 + b MPCall_130_0x15c + +MPCall_130_0x11c + li r8, 0x214 + +; r1 = kdp +; r8 = size + bl PoolAlloc +; r8 = ptr + + mr. r16, r8 + beq+ major_0x0af60 + addi r18, r31, 0x90 + lis r17, 0x4645 + ori r17, r17, 0x4e43 + stw r17, 0x0004(r16) + stw r18, 0x0000(r16) + stw r18, 0x0008(r16) + lwz r19, 0x000c(r18) + stw r19, 0x000c(r16) + stw r16, 0x0008(r19) + stw r16, 0x000c(r18) + li r8, 0x00 + addi r9, r16, 0x14 + +MPCall_130_0x15c + stw r8, 0x0010(r16) + stw r29, 0x0000(r9) + stw r28, 0x0004(r9) + + _Lock PSA.HTABLock, scratch1=r14, scratch2=r15 + + mr r8, r29 + bl MPCall_95_0x1e4 + beq+ Local_Panic + bl MPCall_95_0x2b0 + bns- cr7, MPCall_130_0x19c + bltl- cr5, MPCall_95_0x2e0 + bltl- cr5, MPCall_95_0x348 + +MPCall_130_0x19c + lwz r17, 0x0000(r30) + li r16, 0x06 + rlwimi r17, r16, 0, 29, 30 + stw r17, 0x0000(r30) + sync + lwz r14, -0x0b90(r1) + cmpwi cr1, r14, 0x00 + li r14, 0x00 + bne+ cr1, MPCall_130_0x1c8 + mflr r14 + bl panic + +MPCall_130_0x1c8 + stw r14, -0x0b90(r1) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + +; KCSetAreaAccess + + + DeclareMPCall 76, KCSetAreaAccess + +KCSetAreaAccess ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Area.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + lis r16, -0x01 + ori r16, r16, 0xff10 + and. r16, r16, r4 + bne+ major_0x0b054 + lis r16, -0x01 + ori r16, r16, 0xff10 + and. r16, r16, r5 + bne+ major_0x0b054 + lwz r29, 0x0134(r6) + lwz r18, 0x013c(r6) + lwz r16, Area.LogicalBase(r31) + add r28, r18, r29 + lwz r17, 0x007c(r31) + addi r28, r28, -0x01 + lwz r18, 0x0020(r31) + lwz r19, Area.LogicalBase2(r31) + rlwinm. r8, r18, 0, 16, 16 + cmplw cr1, r29, r16 + cmplw cr2, r28, r19 + blt+ cr1, major_0x0b054 + bgt+ cr2, major_0x0b054 + bne- KCSetAreaAccess_0x154 + + _Lock PSA.HTABLock, scratch1=r14, scratch2=r15 + + +KCSetAreaAccess_0x9c + mr r8, r29 + bl MPCall_95_0x1e4 + beq+ Local_Panic + bl MPCall_95_0x2b0 + bns- cr7, KCSetAreaAccess_0xb8 + bltl- cr5, MPCall_95_0x2e0 + bltl- cr5, MPCall_95_0x348 + +KCSetAreaAccess_0xb8 + lwz r17, 0x0000(r30) + bl major_0x10d38 + and r8, r4, r5 + orc r9, r4, r5 + or r18, r18, r8 + and r18, r18, r9 + lwz r17, 0x0000(r30) + rlwinm. r8, r18, 0, 26, 26 + bns- cr7, KCSetAreaAccess_0x118 + bgt- cr6, KCSetAreaAccess_0x118 + beq- KCSetAreaAccess_0x118 + rlwinm r9, r17, 0, 0, 19 + lwz r8, 0x0068(r31) + +KCSetAreaAccess_0xec + addi r8, r8, -0x20 + dcbf r8, r9 + cmpwi r8, 0x00 + bgt+ KCSetAreaAccess_0xec + sync + lwz r8, 0x0068(r31) + +KCSetAreaAccess_0x104 + addi r8, r8, -0x20 + icbi r8, r9 + cmpwi r8, 0x00 + bgt+ KCSetAreaAccess_0x104 + isync + +KCSetAreaAccess_0x118 + bl major_0x10cb8 + lwz r19, 0x0068(r31) + stw r17, 0x0000(r30) + add r29, r29, r19 + subf. r8, r29, r28 + bge+ KCSetAreaAccess_0x9c + sync + lwz r14, -0x0b90(r1) + cmpwi cr1, r14, 0x00 + li r14, 0x00 + bne+ cr1, KCSetAreaAccess_0x14c + mflr r14 + bl panic + +KCSetAreaAccess_0x14c + stw r14, -0x0b90(r1) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +KCSetAreaAccess_0x154 + bne+ cr1, major_0x0b054 + lwz r18, 0x001c(r31) + and r8, r4, r5 + orc r9, r4, r5 + or r18, r18, r8 + and r18, r18, r9 + stw r18, 0x001c(r31) + lwz r16, 0x0070(r31) + lwz r17, 0x0074(r31) + bl major_0x10cb8 + stw r16, 0x0070(r31) + stw r17, 0x0074(r31) + + _Lock PSA.HTABLock, scratch1=r14, scratch2=r15 + + lwz r27, 0x0068(r31) + mr r28, r19 + +KCSetAreaAccess_0x1a4 + mr r8, r29 + lwz r9, Area.AddressSpacePtr(r31) + bl MPCall_95_0x45c + beq- KCSetAreaAccess_0x1bc + bl MPCall_95_0x2e0 + bl MPCall_95_0x348 + +KCSetAreaAccess_0x1bc + add r29, r29, r27 + subf. r8, r29, r28 + bge+ KCSetAreaAccess_0x1a4 + sync + lwz r14, -0x0b90(r1) + cmpwi cr1, r14, 0x00 + li r14, 0x00 + bne+ cr1, KCSetAreaAccess_0x1e4 + mflr r14 + bl panic + +KCSetAreaAccess_0x1e4 + stw r14, -0x0b90(r1) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + +; major_0x10cb8 + +; Xrefs: +; createarea +; KCSetAreaAccess + +major_0x10cb8 ; OUTSIDE REFERER + rlwinm r16, r16, 0, 29, 24 + rlwinm r17, r17, 0, 27, 23 + rlwinm r16, r16, 0, 0, 29 + rlwinm r17, r17, 0, 31, 28 + mtcr r18 + bge- cr6, major_0x10cb8_0x20 + ori r17, r17, 0x80 + ori r16, r16, 0x08 + +major_0x10cb8_0x20 + ble- cr6, major_0x10cb8_0x2c + ori r16, r16, 0x40 + b major_0x10cb8_0x30 + +major_0x10cb8_0x2c + ori r17, r17, 0x20 + +major_0x10cb8_0x30 + bne- cr6, major_0x10cb8_0x3c + ori r17, r17, 0x40 + ori r16, r16, 0x20 + +major_0x10cb8_0x3c + ble- cr7, major_0x10cb8_0x40 + +major_0x10cb8_0x40 + bge- cr7, major_0x10cb8_0x50 + ori r17, r17, 0x06 + ori r16, r16, 0x01 + b major_0x10cb8_0x78 + +major_0x10cb8_0x50 + bne- cr7, major_0x10cb8_0x60 + ori r17, r17, 0x00 + ori r16, r16, 0x02 + b major_0x10cb8_0x78 + +major_0x10cb8_0x60 + bns- cr7, major_0x10cb8_0x70 + ori r17, r17, 0x04 + ori r16, r16, 0x03 + b major_0x10cb8_0x78 + +major_0x10cb8_0x70 + ori r17, r17, 0x02 + ori r16, r16, 0x00 + +major_0x10cb8_0x78 + ori r16, r16, 0x10 + blr + + + +; major_0x10d38 + +; Xrefs: +; convert_pmdts_to_areas +; KCSetAreaAccess +; MPCall_123 + +major_0x10d38 ; OUTSIDE REFERER + andi. r16, r17, 0x06 + li r18, 0x00 + cmpwi r16, 0x02 + cmpwi cr1, r16, 0x06 + beq- major_0x10d38_0x28 + li r18, 0x04 + andi. r16, r17, 0x04 + ori r18, r18, 0x01 + bne- major_0x10d38_0x28 + ori r18, r18, 0x02 + +major_0x10d38_0x28 + bne- cr1, major_0x10d38_0x30 + ori r18, r18, 0x08 + +major_0x10d38_0x30 + andi. r16, r17, 0x20 + bne- major_0x10d38_0x3c + ori r18, r18, 0x40 + +major_0x10d38_0x3c + andi. r16, r17, 0x40 + beq- major_0x10d38_0x48 + ori r18, r18, 0x20 + +major_0x10d38_0x48 + andi. r16, r17, 0x80 + beq- major_0x10d38_0x54 + ori r18, r18, 0x80 + +major_0x10d38_0x54 + blr + +major_0x10d38_0x58 ; OUTSIDE REFERER + andi. r16, r17, 0x03 + li r18, 0x04 + cmpwi cr1, r16, 0x01 + beq- major_0x10d38_0x78 + andi. r16, r17, 0x01 + ori r18, r18, 0x01 + bne- major_0x10d38_0x78 + ori r18, r18, 0x02 + +major_0x10d38_0x78 + bne- cr1, major_0x10d38_0x80 + ori r18, r18, 0x08 + +major_0x10d38_0x80 + andi. r16, r17, 0x40 + beq- major_0x10d38_0x8c + ori r18, r18, 0x40 + +major_0x10d38_0x8c + andi. r16, r17, 0x20 + beq- major_0x10d38_0x98 + ori r18, r18, 0x20 + +major_0x10d38_0x98 + andi. r16, r17, 0x08 + beq- major_0x10d38_0xa4 + ori r18, r18, 0x80 + +major_0x10d38_0xa4 + blr + + + + DeclareMPCall 123, MPCall_123 + +MPCall_123 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Area.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + lwz r16, Area.LogicalBase(r31) + lwz r17, Area.LogicalBase2(r31) + lwz r18, 0x0020(r31) + cmplw r4, r16 + cmplw cr1, r4, r17 + blt+ major_0x0b054 + bgt+ cr1, major_0x0b054 + rlwinm. r8, r18, 0, 16, 16 + lwz r5, 0x001c(r31) + +; r1 = kdp + bne+ ReleaseAndReturnZeroFromMPCall + + _Lock PSA.HTABLock, scratch1=r14, scratch2=r15 + + mr r8, r4 + bl MPCall_95_0x1e4 + beq+ Local_Panic + bl MPCall_95_0x2b0 + bltl- cr5, MPCall_95_0x2e0 + bltl- cr5, MPCall_95_0x348 + lwz r17, 0x0000(r30) + sync + lwz r14, -0x0b90(r1) + cmpwi cr1, r14, 0x00 + li r14, 0x00 + bne+ cr1, MPCall_123_0xa4 + mflr r14 + bl panic + +MPCall_123_0xa4 + stw r14, -0x0b90(r1) + bl major_0x10d38 + mr r5, r18 + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 77, MPCall_77 + +MPCall_77 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Area.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + mr. r8, r4 + beq- MPCall_77_0x40 + +; r8 = id + bl LookupID + cmpwi r9, Notification.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + +MPCall_77_0x40 + stw r4, 0x0018(r31) + stw r5, 0x0084(r31) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 78, MPCall_78 + +MPCall_78 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Area.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + cmpwi r4, 0x01 + bne+ major_0x0b054 + cmplwi r5, 0x00 + bne- MPCall_78_0x68 + li r16, 0x01 + stw r16, 0x0134(r6) + lwz r16, Area.ProcessID(r31) + stw r16, 0x013c(r6) + lwz r16, Area.AddressSpaceID(r31) + stw r16, 0x0144(r6) + lwz r16, 0x0014(r31) + stw r16, 0x014c(r6) + li r16, 0x10 + stw r16, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_78_0x68 + cmplwi r5, 0x10 + bne- MPCall_78_0x9c + lwz r16, 0x0018(r31) + stw r16, 0x0134(r6) + lwz r16, 0x001c(r31) + stw r16, 0x013c(r6) + lwz r16, 0x0020(r31) + stw r16, 0x0144(r6) + lwz r16, Area.LogicalBase(r31) + stw r16, 0x014c(r6) + li r16, 0x10 + stw r16, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_78_0x9c + cmplwi r5, 0x20 + bne- MPCall_78_0xd0 + lwz r16, Area.Length(r31) + stw r16, 0x0134(r6) + lwz r16, Area.Zero(r31) + stw r16, 0x013c(r6) + lwz r16, 0x0034(r31) + stw r16, 0x0144(r6) + lwz r16, Area.Length2(r31) + stw r16, 0x014c(r6) + li r16, 0x10 + stw r16, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_78_0xd0 + cmplwi r5, 0x30 + bne- MPCall_78_0xfc + lwz r16, 0x0068(r31) + stw r16, 0x0134(r6) + lwz r16, 0x0080(r31) + stw r16, 0x013c(r6) + lwz r16, 0x0084(r31) + stw r16, 0x0144(r6) + li r16, 0x0c + stw r16, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_78_0xfc + cmpwi r5, 0x3c + bne+ major_0x0b054 + li r16, 0x00 + stw r16, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 79, MPCall_79 + +MPCall_79 ; OUTSIDE REFERER + mr. r8, r3 + mfsprg r28, 0 + lwz r31, EWA.PA_CurAddressSpace(r28) + beq- MPCall_79_0x20 + +; r8 = id + bl LookupID + cmpwi r9, AddressSpace.kIDClass + + bne+ ReturnMPCallInvalidIDErr + mr r31, r8 + +MPCall_79_0x20 + lwz r3, Area.ID(r31) + +MPCall_79_0x24 + mr r8, r4 + li r9, 0x0b + bl GetNextIDOfClass + cmpwi r8, 0x00 + beq+ ReturnMPCallInvalidIDErr + mr r4, r8 + +; r8 = id + bl LookupID +; r8 = something not sure what +; r9 = 0:inval, 1:proc, 2:task, 3:timer, 4:q, 5:sema, 6:cr, 7:cpu, 8:addrspc, 9:evtg, 10:cgrp, 11:area, 12:not, 13:log + + lwz r16, 0x0010(r8) + cmpw r16, r3 + bne+ MPCall_79_0x24 + b ReturnZeroFromMPCall + + + + DeclareMPCall 80, MPCall_80 + +MPCall_80 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr. r8, r3 + mfsprg r9, 0 + bne- MPCall_80_0x2c + lwz r8, EWA.PA_CurAddressSpace(r9) + b MPCall_80_0x38 + +MPCall_80_0x2c +; r8 = id + bl LookupID + cmpwi r9, AddressSpace.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + +MPCall_80_0x38 + mr r9, r4 + bl FindAreaAbove + lwz r16, 0x0024(r8) + li r5, 0x00 + cmplw r16, r4 + bgt+ major_0x0b054 + lwz r5, 0x0000(r8) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 125, MPCall_125 + +MPCall_125 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr. r8, r3 + mfsprg r9, 0 + bne- MPCall_125_0x2c + lwz r8, EWA.PA_CurAddressSpace(r9) + b MPCall_125_0x38 + +MPCall_125_0x2c +; r8 = id + bl LookupID + cmpwi r9, AddressSpace.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + +MPCall_125_0x38 + mr r9, r4 + bl FindAreaAbove + lwz r16, 0x0024(r8) + li r5, 0x00 + cmplw r16, r4 + bgt- MPCall_125_0x58 + lwz r8, 0x005c(r8) + addi r8, r8, -0x54 + +MPCall_125_0x58 + lwz r9, 0x002c(r8) + cmpwi r9, noErr + beq+ major_0x0b054 + lwz r5, 0x0000(r8) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 81, MPCall_81 + +MPCall_81 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Area.kIDClass + + mr r31, r8 + bne+ ReleaseAndReturnMPCallInvalidIDErr + lwz r16, Area.LogicalBase(r31) + lwz r17, Area.LogicalBase2(r31) + lwz r18, 0x0020(r31) + cmplw r4, r16 + cmplw cr1, r4, r17 + blt+ major_0x0b054 + bgt+ cr1, major_0x0b054 + rlwinm. r8, r18, 0, 16, 16 + lwz r19, 0x0070(r31) + beq- MPCall_81_0x70 + lwz r17, Area.Length2(r31) + rlwinm r19, r19, 0, 0, 19 + cmpwi r17, 0x00 + subf r18, r16, r4 + beq+ major_0x0b054 + add r5, r18, r19 + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_81_0x70 + li r3, 0x00 + + _Lock PSA.HTABLock, scratch1=r14, scratch2=r15 + + mr r8, r4 + bl MPCall_95_0x1e4 + bl MPCall_95_0x2b0 + bns- cr7, MPCall_81_0xc8 + mr r5, r17 + rlwimi r5, r4, 0, 20, 31 + +MPCall_81_0xa4 + sync + lwz r8, -0x0b90(r1) + cmpwi cr1, r8, 0x00 + li r8, 0x00 + bne+ cr1, MPCall_81_0xc0 + mflr r8 + bl panic + +MPCall_81_0xc0 + stw r8, -0x0b90(r1) + b ReleaseAndReturnMPCall + +MPCall_81_0xc8 + li r3, -0x7272 + b MPCall_81_0xa4 + + + + DeclareMPCall 98, MPCall_98 + +MPCall_98 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Area.kIDClass + + mr r31, r8 + bne+ ReleaseAndReturnMPCallInvalidIDErr + lwz r16, Area.LogicalBase(r31) + lwz r17, Area.LogicalBase2(r31) + mr r29, r5 + add r5, r5, r4 + lwz r18, 0x0020(r31) + addi r5, r5, -0x01 + cmplw r4, r16 + cmplw cr1, r5, r17 + blt+ major_0x0b054 + bgt+ cr1, major_0x0b054 + lwz r20, Area.Length2(r31) + rlwinm. r8, r18, 0, 16, 16 + cmpwi cr1, r20, 0x00 + beq- MPCall_98_0x84 + beq+ cr1, major_0x0b054 + lwz r19, 0x0070(r31) + subf r18, r16, r4 + rlwinm r19, r19, 0, 0, 19 + add r16, r18, r19 + stw r16, 0x0134(r6) + stw r29, 0x013c(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_98_0x84 + + _Lock PSA.HTABLock, scratch1=r14, scratch2=r15 + + mr r8, r4 + mr r28, r4 + bl MPCall_95_0x1e4 + beq+ Local_Panic + bl MPCall_95_0x2b0 + crclr cr3_eq + li r3, 0x00 + bso- cr7, MPCall_98_0xc4 + crset cr3_eq + li r3, -0x7272 + +MPCall_98_0xc4 + rlwimi r17, r4, 0, 20, 31 + rlwinm r29, r17, 0, 0, 19 + stw r17, 0x0134(r6) + +MPCall_98_0xd0 + lwz r16, 0x0068(r31) + add r28, r28, r16 + add r29, r29, r16 + cmplw cr2, r28, r5 + bgt- cr2, MPCall_98_0x140 + mr r8, r28 + bl MPCall_95_0x1e4 + beq+ Local_Panic + bl MPCall_95_0x2b0 + rlwinm r17, r17, 0, 0, 19 + crxor 31, 31, 14 + bns- cr7, MPCall_98_0x10c + beq+ cr3, MPCall_98_0xd0 + cmplw r29, r17 + beq+ MPCall_98_0xd0 + +MPCall_98_0x10c + lwz r16, 0x007c(r31) + and r28, r28, r16 + subf r16, r4, r28 + +MPCall_98_0x118 + stw r16, 0x013c(r6) + sync + lwz r8, -0x0b90(r1) + cmpwi cr1, r8, 0x00 + li r8, 0x00 + bne+ cr1, MPCall_98_0x138 + mflr r8 + bl panic + +MPCall_98_0x138 + stw r8, -0x0b90(r1) + b ReleaseAndReturnMPCall + +MPCall_98_0x140 + addi r5, r5, 0x01 + beq- cr3, MPCall_98_0x170 + mr r8, r28 + bl MPCall_95_0x1e4 + beq+ Local_Panic + bl MPCall_95_0x2b0 + rlwinm r17, r17, 0, 0, 19 + bns- cr7, MPCall_98_0x170 + cmplw r29, r17 + bne- MPCall_98_0x170 + subf r16, r4, r5 + b MPCall_98_0x118 + +MPCall_98_0x170 + lwz r16, 0x007c(r31) + and r28, r28, r16 + cmplw r5, r28 + bge- MPCall_98_0x184 + mr r28, r5 + +MPCall_98_0x184 + subf r16, r4, r28 + b MPCall_98_0x118 + + + + DeclareMPCall 82, MPCall_82 + +MPCall_82 ; OUTSIDE REFERER + lwz r8, -0x0420(r1) + cmpwi r8, 0x00 + bne+ ReturnMPCallOOM + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Notification.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + stw r3, -0x0420(r1) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + +; MPCall_83 + +; Xrefs: +; kcMPDispatch +; KCMapPage + + DeclareMPCall 83, MPCall_83 + +MPCall_83 ; OUTSIDE REFERER + + _Lock PSA.PoolLock, scratch1=r16, scratch2=r17 + + bl MPCall_83_0x90 + sync + lwz r16, -0x0ad0(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + bne+ cr1, MPCall_83_0x38 + mflr r16 + bl panic + +MPCall_83_0x38 + stw r16, -0x0ad0(r1) + mr. r4, r8 + bne+ ReturnZeroFromMPCall + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + +MPCall_83_0x5c ; OUTSIDE REFERER + lwz r8, -0x0420(r1) + +; r8 = id + bl LookupID + cmpwi r9, Notification.kIDClass + + mr r31, r8 + bne+ ReleaseAndReturnMPCallOOM + lwz r8, 0x001c(r31) + +; r8 = id + bl LookupID + cmpwi r9, EventGroup.kIDClass + + mr r31, r8 + bne+ ReleaseAndReturnMPCallOOM + lwz r8, 0x0020(r31) + bl major_0x0d35c + b ReleaseAndReturnMPCallOOM + +MPCall_83_0x90 ; OUTSIDE REFERER + addi r18, r1, -0x450 + lwz r8, -0x0448(r1) + cmpw r8, r18 + beq- MPCall_83_0xec + lwz r16, 0x0008(r8) + lwz r17, 0x000c(r8) + stw r16, 0x0008(r17) + stw r17, 0x000c(r16) + li r16, 0x00 + stw r16, 0x0008(r8) + stw r16, 0x000c(r8) + lwz r16, -0x0430(r1) + addi r16, r16, -0x01 + stw r16, -0x0430(r1) + lwz r17, 0x0004(r8) + mfspr r16, dec + eqv. r17, r18, r17 + stw r16, 0x0000(r8) + bne+ Local_Panic + stw r16, 0x0004(r8) + stw r16, 0x0008(r8) + stw r16, 0x000c(r8) + blr + +MPCall_83_0xec + li r8, 0x00 + blr + + + + DeclareMPCall 84, MPCall_84 + +MPCall_84 ; OUTSIDE REFERER + + _Lock PSA.PoolLock, scratch1=r16, scratch2=r17 + + lwz r16, 0x0004(r3) + lwz r17, 0x0000(r3) + addi r18, r1, -0x450 + eqv. r16, r16, r17 + cmpw cr1, r17, r18 + bne- MPCall_84_0x3c + bne- cr1, MPCall_84_0x3c + li r3, -0x32 + b MPCall_84_0x48 + +MPCall_84_0x3c + mr r8, r3 + +; r1 = kdp +; r8 = maybe the page + bl free_list_add_page + li r3, 0x00 + +MPCall_84_0x48 + sync + lwz r16, -0x0ad0(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + bne+ cr1, MPCall_84_0x64 + mflr r16 + bl panic + +MPCall_84_0x64 + stw r16, -0x0ad0(r1) + b CommonMPCallReturnPath + + + +; free_list_add_page + +; Xrefs: +; setup +; MPCall_74 +; MPCall_75 +; MPCall_84 +; KCUnmapPages + +; > r1 = kdp +; > r8 = maybe the page + +free_list_add_page ; OUTSIDE REFERER + + ; Must be an actual page-aligned address + clrlwi. r9, r8, 20 + addi r9, r1, PSA.FreeList + bne+ Local_Panic + + + ; This is probably an alternative to heavyweight locks around the free list + + stw r9, 0(r8) ; store &parent in Freeform field + + InsertAsPrev r8, r9, scratch=r16 + + not r9, r9 + stw r9, 4(r8) ; store ^&parent in Signature field + + + lwz r8, PSA.FreePageCount(r1) + addi r8, r8, 1 + stw r8, PSA.FreePageCount(r1) + + blr + + + +; KCGetFreePageCount + + + DeclareMPCall 100, KCGetFreePageCount + +KCGetFreePageCount ; OUTSIDE REFERER + lwz r3, PSA.FreePageCount(r1) + b CommonMPCallReturnPath + + + +; KCGetUnheldFreePageCount + + + DeclareMPCall 101, KCGetUnheldFreePageCount + +KCGetUnheldFreePageCount ; OUTSIDE REFERER + lwz r3, PSA.UnheldFreePageCount(r1) + b CommonMPCallReturnPath + + + +; KCMapPage + + + DeclareMPCall 85, KCMapPage + +KCMapPage ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Area.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + lwz r16, Area.TwoFiftySix(r31) + rlwinm. r8, r16, 0, 28, 28 + bne+ major_0x0b054 + lwz r16, Area.LogicalBase(r31) + lwz r17, Area.LogicalBase2(r31) + lwz r19, 0x0020(r31) + cmplw r4, r16 + cmplw cr1, r4, r17 + blt+ major_0x0b054 + bgt+ cr1, major_0x0b054 + rlwinm. r8, r19, 0, 16, 16 + cmplw cr1, r4, r16 + lwz r20, Area.Length2(r31) + beq- KCMapPage_0x8c + bne+ cr1, major_0x0b054 + cmpwi r20, 0x00 + lwz r8, 0x0070(r31) + bne+ ReleaseAndReturnMPCallOOM + rlwimi r8, r5, 0, 0, 19 + lwz r18, 0x007c(r31) + lwz r20, Area.Length(r31) + stw r8, 0x0070(r31) + stw r20, Area.Length2(r31) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +KCMapPage_0x8c + + _Lock PSA.HTABLock, scratch1=r14, scratch2=r15 + + mr r8, r4 + bl MPCall_95_0x1e4 + beq+ Local_Panic + lwz r29, 0x0000(r30) + sync + lwz r14, -0x0b90(r1) + cmpwi cr1, r14, 0x00 + li r14, 0x00 + bne+ cr1, KCMapPage_0xd0 + mflr r14 + bl panic + +KCMapPage_0xd0 + stw r14, -0x0b90(r1) + clrlwi. r8, r29, 0x1f + bne+ ReleaseAndReturnMPCallOOM + lwz r17, 0x0134(r6) + rlwinm. r8, r17, 0, 30, 30 + bne- KCMapPage_0x12c + + _Lock PSA.PoolLock, scratch1=r16, scratch2=r17 + + bl MPCall_83_0x90 + sync + lwz r16, -0x0ad0(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + bne+ cr1, KCMapPage_0x120 + mflr r16 + bl panic + +KCMapPage_0x120 + stw r16, -0x0ad0(r1) + mr. r5, r8 + beq+ MPCall_83_0x5c + +KCMapPage_0x12c + lwz r17, 0x0134(r6) + rlwinm. r8, r17, 0, 29, 29 + beq- KCMapPage_0x17c + rlwinm. r8, r29, 0, 25, 25 + lwz r18, 0x0068(r31) + +KCMapPage_0x140 + addi r18, r18, -0x20 + bne- KCMapPage_0x174 + dcbst r18, r5 + +KCMapPage_0x14c + cmpwi cr1, r18, 0x00 + bgt+ cr1, KCMapPage_0x140 + sync + lwz r18, 0x0068(r31) + +KCMapPage_0x15c + addi r18, r18, -0x20 + icbi r18, r5 + cmpwi cr1, r18, 0x00 + bgt+ cr1, KCMapPage_0x15c + isync + b KCMapPage_0x17c + +KCMapPage_0x174 + dcbf r18, r5 + b KCMapPage_0x14c + +KCMapPage_0x17c + lwz r18, 0x0068(r31) + andi. r29, r29, 0x7e7 + ori r29, r29, 0x01 + rlwimi r29, r5, 0, 0, 19 + lwz r17, Area.Length2(r31) + stw r29, 0x0000(r30) + add r17, r17, r18 + stw r17, Area.Length2(r31) + lwz r17, 0x0134(r6) + clrlwi. r8, r17, 0x1f + +; r1 = kdp + beq+ ReleaseAndReturnZeroFromMPCall + lwz r5, 0x0068(r31) + b KCHoldPages_0x2c + + + +; KCUnmapPages + + + DeclareMPCall 86, KCUnmapPages + +KCUnmapPages ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Area.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + lwz r8, 0x0134(r6) + lwz r16, Area.TwoFiftySix(r31) + rlwinm. r16, r16, 0, 28, 28 + bne+ major_0x0b054 + clrlwi. r8, r8, 0x1f + add r5, r5, r4 + lwz r16, Area.LogicalBase(r31) + lwz r17, Area.LogicalBase2(r31) + lwz r19, 0x0020(r31) + crmove 14, 2 + addi r5, r5, -0x01 + cmplw r4, r16 + cmplw cr1, r5, r17 + blt+ major_0x0b054 + bgt+ cr1, major_0x0b054 + lwz r29, 0x0068(r31) + lwz r20, Area.Length2(r31) + rlwinm. r8, r19, 0, 16, 16 + cmplw cr1, r4, r16 + beq- KCUnmapPages_0xd8 + bne+ cr1, major_0x0b054 + cmpwi r20, 0x00 + li r20, 0x00 + ble+ ReleaseAndReturnMPCallOOM + stw r20, Area.Length2(r31) + + _Lock PSA.HTABLock, scratch1=r14, scratch2=r15 + + li r30, 0x00 + +KCUnmapPages_0xac + mr r8, r4 + lwz r9, Area.AddressSpacePtr(r31) + bl MPCall_95_0x45c + beq- KCUnmapPages_0xc4 + bl MPCall_95_0x2e0 + bl MPCall_95_0x348 + +KCUnmapPages_0xc4 + add r4, r4, r29 + subf. r8, r4, r5 + bge+ KCUnmapPages_0xac + crclr cr3_eq + b KCUnmapPages_0x158 + +KCUnmapPages_0xd8 + bne- cr3, KCUnmapPages_0xf4 + + _Lock PSA.PoolLock, scratch1=r14, scratch2=r15 + + +KCUnmapPages_0xf4 + + _Lock PSA.HTABLock, scratch1=r14, scratch2=r15 + + lwz r28, Area.Length2(r31) + +KCUnmapPages_0x110 + mr r8, r4 + bl MPCall_95_0x1e4 + beq+ Local_Panic + bl MPCall_95_0x2b0 + bns- cr7, KCUnmapPages_0x148 + bltl- cr5, MPCall_95_0x2e0 + bltl- cr5, MPCall_95_0x348 + lwz r18, 0x0000(r30) + subf r28, r29, r28 + rlwinm r18, r18, 0, 0, 30 + stw r18, 0x0000(r30) + bne- cr3, KCUnmapPages_0x148 + rlwinm r8, r18, 0, 0, 19 + +; r1 = kdp +; r8 = maybe the page + bl free_list_add_page + +KCUnmapPages_0x148 + add r4, r4, r29 + subf. r8, r4, r5 + bge+ KCUnmapPages_0x110 + stw r28, Area.Length2(r31) + +KCUnmapPages_0x158 + sync + lwz r14, -0x0b90(r1) + cmpwi cr1, r14, 0x00 + li r14, 0x00 + bne+ cr1, KCUnmapPages_0x174 + mflr r14 + bl panic + +KCUnmapPages_0x174 + stw r14, -0x0b90(r1) + +; r1 = kdp + bne+ cr3, ReleaseAndReturnZeroFromMPCall + sync + lwz r14, -0x0ad0(r1) + cmpwi cr1, r14, 0x00 + li r14, 0x00 + bne+ cr1, KCUnmapPages_0x198 + mflr r14 + bl panic + +KCUnmapPages_0x198 + stw r14, -0x0ad0(r1) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + +; KCMakePhysicallyContiguous + + + DeclareMPCall 127, KCMakePhysicallyContiguous + +KCMakePhysicallyContiguous ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Area.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + mr r27, r5 + add r5, r5, r4 + lwz r16, Area.LogicalBase(r31) + lwz r17, Area.LogicalBase2(r31) + addi r5, r5, -0x01 + cmplw r4, r16 + cmplw cr1, r5, r17 + blt+ major_0x0b054 + bgt+ cr1, major_0x0b054 + lwz r19, 0x0020(r31) + lwz r29, 0x0068(r31) + rlwinm. r8, r19, 0, 16, 16 + bne+ major_0x0b054 + + _Lock PSA.HTABLock, scratch1=r14, scratch2=r15 + + mr r27, r4 + li r28, -0x01 + +NKMakePhysicallyContiguous_0x80 + mr r8, r27 + bl MPCall_95_0x1e4 + beq+ Local_Panic + bl MPCall_95_0x2b0 + bns- cr7, NKMakePhysicallyContiguous_0x150 + rlwinm r8, r17, 0, 0, 19 + cmpwi r28, -0x01 + cmpw cr1, r28, r8 + mr r28, r8 + beq- NKMakePhysicallyContiguous_0xac + bne- cr1, NKMakePhysicallyContiguous_0xe0 + +NKMakePhysicallyContiguous_0xac + add r27, r27, r29 + add r28, r28, r29 + subf. r8, r27, r5 + bge+ NKMakePhysicallyContiguous_0x80 + sync + lwz r14, -0x0b90(r1) + cmpwi cr1, r14, 0x00 + li r14, 0x00 + bne+ cr1, NKMakePhysicallyContiguous_0xd8 + mflr r14 + bl panic + +NKMakePhysicallyContiguous_0xd8 + stw r14, -0x0b90(r1) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +NKMakePhysicallyContiguous_0xe0 + sync + lwz r14, -0x0b90(r1) + cmpwi cr1, r14, 0x00 + li r14, 0x00 + bne+ cr1, NKMakePhysicallyContiguous_0xfc + mflr r14 + bl panic + +NKMakePhysicallyContiguous_0xfc + stw r14, -0x0b90(r1) + + _Lock PSA.PoolLock, scratch1=r16, scratch2=r17 + + addi r18, r1, -0x450 + lwz r8, -0x0448(r1) + cmpw r8, r18 + beq- NKMakePhysicallyContiguous_0x174 + b NKMakePhysicallyContiguous_0x174 + dc.l 0x7c0004ac ; probably dead code, not a jump table + dc.l 0x8201f530 + dc.l 0x2c900000 + dc.l 0x3a000000 + dc.l 0x40a6000c + dc.l 0x7e0802a6 + dc.l 0x48005905 + dc.l 0x9201f530 + dc.l 0x4bff9554 + +NKMakePhysicallyContiguous_0x150 + sync + lwz r16, -0x0b90(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + bne+ cr1, NKMakePhysicallyContiguous_0x16c + mflr r16 + bl panic + +NKMakePhysicallyContiguous_0x16c + stw r16, -0x0b90(r1) + b ReleaseAndReturnMPCallOOM + +NKMakePhysicallyContiguous_0x174 + sync + lwz r16, -0x0ad0(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + bne+ cr1, NKMakePhysicallyContiguous_0x190 + mflr r16 + bl panic + +NKMakePhysicallyContiguous_0x190 + stw r16, -0x0ad0(r1) + b ReleaseAndReturnMPCallOOM + + + +; KCLockPages + + + DeclareMPCall 87, KCLockPages + +KCLockPages ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Area.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + mr r27, r5 + add r5, r5, r4 + lwz r16, Area.LogicalBase(r31) + lwz r17, Area.LogicalBase2(r31) + addi r5, r5, -0x01 + cmplw r4, r16 + cmplw cr1, r5, r17 + blt+ major_0x0b054 + bgt+ cr1, major_0x0b054 + lwz r19, 0x0020(r31) + lwz r29, 0x0068(r31) + rlwinm. r8, r19, 0, 16, 16 + bne+ major_0x0b054 + mr r27, r4 + li r28, 0x00 + +KCLockPages_0x68 + mr r8, r27 + bl MPCall_95_0x254 + beq+ major_0x0b054 + lhz r18, 0x0000(r30) + rlwinm r17, r18, 24, 25, 31 + rlwinm. r8, r18, 0, 16, 16 + cmpwi cr1, r17, 0x7f + addi r28, r28, 0x01 + beq- KCLockPages_0x94 + addi r28, r28, -0x01 + bge+ cr1, major_0x0b0cc + +KCLockPages_0x94 + add r27, r27, r29 + subf. r8, r27, r5 + bge+ KCLockPages_0x68 + + _Lock PSA.PoolLock, scratch1=r16, scratch2=r17 + + lwz r16, PSA.UnheldFreePageCount(r1) + subf. r16, r28, r16 + ble- KCLockPages_0xc8 + stw r16, PSA.UnheldFreePageCount(r1) + +KCLockPages_0xc8 + sync + lwz r16, -0x0ad0(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + bne+ cr1, KCLockPages_0xe4 + mflr r16 + bl panic + +KCLockPages_0xe4 + stw r16, -0x0ad0(r1) + ble+ ReleaseAndReturnMPCallOOM + mr r27, r4 + +KCLockPages_0xf0 + mr r8, r27 + bl MPCall_95_0x254 + beq+ Local_Panic + lhz r18, 0x0000(r30) + rlwinm. r17, r18, 0, 16, 16 + bne- KCLockPages_0x10c + li r18, -0x8000 + +KCLockPages_0x10c + rlwinm r17, r18, 24, 25, 31 + addi r17, r17, 0x01 + rlwimi r18, r17, 8, 17, 23 + sth r18, 0x0000(r30) + add r27, r27, r29 + subf. r8, r27, r5 + bge+ KCLockPages_0xf0 + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + +; KCUnlockPages + + + DeclareMPCall 88, KCUnlockPages + +KCUnlockPages ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Area.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + add r5, r5, r4 + lwz r16, Area.LogicalBase(r31) + lwz r17, Area.LogicalBase2(r31) + addi r5, r5, -0x01 + cmplw r4, r16 + cmplw cr1, r5, r17 + blt+ major_0x0b054 + bgt+ cr1, major_0x0b054 + lwz r19, 0x0020(r31) + lwz r29, 0x0068(r31) + rlwinm. r8, r19, 0, 16, 16 + bne+ major_0x0b054 + mr r27, r4 + +KCUnlockPages_0x60 + mr r8, r27 + bl MPCall_95_0x254 + beq+ major_0x0b054 + lhz r18, 0x0000(r30) + rlwinm r17, r18, 24, 25, 31 + rlwinm. r8, r18, 0, 16, 16 + cmpwi cr1, r17, 0x00 + beq+ major_0x0b0cc + addi r28, r28, 0x01 + beq+ cr1, major_0x0b0cc + add r27, r27, r29 + subf. r8, r27, r5 + bge+ KCUnlockPages_0x60 + li r28, 0x00 + +KCUnlockPages_0x98 + mr r8, r4 + bl MPCall_95_0x254 + beq+ major_0x0b054 + lhz r18, 0x0000(r30) + rlwinm r17, r18, 24, 25, 31 + addi r17, r17, -0x01 + rlwimi r18, r17, 8, 17, 23 + clrlwi. r8, r18, 0x11 + bne- KCUnlockPages_0xc4 + rlwinm r18, r18, 0, 17, 15 + addi r28, r28, 0x01 + +KCUnlockPages_0xc4 + sth r18, 0x0000(r30) + add r4, r4, r29 + subf. r8, r4, r5 + bge+ KCUnlockPages_0x98 + + _Lock PSA.PoolLock, scratch1=r16, scratch2=r17 + + lwz r16, PSA.UnheldFreePageCount(r1) + add r16, r16, r28 + stw r16, PSA.UnheldFreePageCount(r1) + sync + lwz r16, -0x0ad0(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + bne+ cr1, KCUnlockPages_0x114 + mflr r16 + bl panic + +KCUnlockPages_0x114 + stw r16, -0x0ad0(r1) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + +; KCHoldPages + + +; Xrefs: +; kcMPDispatch +; KCMapPage + + DeclareMPCall 89, KCHoldPages + +KCHoldPages ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Area.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + +KCHoldPages_0x2c ; OUTSIDE REFERER + add r5, r5, r4 + lwz r16, Area.LogicalBase(r31) + lwz r17, Area.LogicalBase2(r31) + addi r5, r5, -0x01 + cmplw r4, r16 + cmplw cr1, r5, r17 + blt+ major_0x0b054 + bgt+ cr1, major_0x0b054 + lwz r19, 0x0020(r31) + lwz r29, 0x0068(r31) + rlwinm. r8, r19, 0, 16, 16 + bne+ major_0x0b054 + mr r27, r4 + li r28, 0x00 + +KCHoldPages_0x64 + mr r8, r27 + bl MPCall_95_0x254 + beq+ major_0x0b054 + lhz r18, 0x0000(r30) + clrlwi r17, r18, 0x18 + rlwinm. r8, r18, 0, 16, 16 + cmpwi cr1, r17, 0xff + addi r28, r28, 0x01 + beq- KCHoldPages_0x90 + addi r28, r28, -0x01 + bge+ cr1, major_0x0b0cc + +KCHoldPages_0x90 + add r27, r27, r29 + subf. r8, r27, r5 + bge+ KCHoldPages_0x64 + + _Lock PSA.PoolLock, scratch1=r16, scratch2=r17 + + lwz r16, PSA.UnheldFreePageCount(r1) + subf. r16, r28, r16 + ble- KCHoldPages_0xc4 + stw r16, PSA.UnheldFreePageCount(r1) + +KCHoldPages_0xc4 + sync + lwz r16, -0x0ad0(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + bne+ cr1, KCHoldPages_0xe0 + mflr r16 + bl panic + +KCHoldPages_0xe0 + stw r16, -0x0ad0(r1) + ble+ ReleaseAndReturnMPCallOOM + mr r27, r4 + +KCHoldPages_0xec + mr r8, r27 + bl MPCall_95_0x254 + beq+ Local_Panic + lhz r18, 0x0000(r30) + rlwinm. r17, r18, 0, 16, 16 + bne- KCHoldPages_0x108 + li r18, -0x8000 + +KCHoldPages_0x108 + clrlwi r17, r18, 0x18 + addi r17, r17, 0x01 + rlwimi r18, r17, 0, 24, 31 + sth r18, 0x0000(r30) + add r27, r27, r29 + subf. r8, r27, r5 + bge+ KCHoldPages_0xec + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + +; KCUnholdPages + + + DeclareMPCall 90, KCUnholdPages + +KCUnholdPages ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Area.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + add r5, r5, r4 + lwz r16, Area.LogicalBase(r31) + lwz r17, Area.LogicalBase2(r31) + addi r5, r5, -0x01 + cmplw r4, r16 + cmplw cr1, r5, r17 + blt+ major_0x0b054 + bgt+ cr1, major_0x0b054 + lwz r19, 0x0020(r31) + lwz r29, 0x0068(r31) + rlwinm. r8, r19, 0, 16, 16 + bne+ major_0x0b054 + mr r27, r4 + +KCUnholdPages_0x60 + mr r8, r27 + bl MPCall_95_0x254 + beq+ major_0x0b054 + lhz r18, 0x0000(r30) + clrlwi r17, r18, 0x18 + rlwinm. r8, r18, 0, 16, 16 + cmpwi cr1, r17, 0x00 + beq+ major_0x0b0cc + addi r28, r28, 0x01 + beq+ cr1, major_0x0b0cc + add r27, r27, r29 + subf. r8, r27, r5 + bge+ KCUnholdPages_0x60 + li r28, 0x00 + +KCUnholdPages_0x98 + mr r8, r4 + bl MPCall_95_0x254 + beq+ major_0x0b054 + lhz r18, 0x0000(r30) + clrlwi r17, r18, 0x18 + addi r17, r17, -0x01 + rlwimi r18, r17, 0, 24, 31 + clrlwi. r8, r18, 0x11 + bne- KCUnholdPages_0xc4 + rlwinm r18, r18, 0, 17, 15 + addi r28, r28, 0x01 + +KCUnholdPages_0xc4 + sth r18, 0x0000(r30) + add r4, r4, r29 + subf. r8, r4, r5 + bge+ KCUnholdPages_0x98 + + _Lock PSA.PoolLock, scratch1=r16, scratch2=r17 + + lwz r16, PSA.UnheldFreePageCount(r1) + add r16, r16, r28 + stw r16, PSA.UnheldFreePageCount(r1) + sync + lwz r16, -0x0ad0(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + bne+ cr1, KCUnholdPages_0x114 + mflr r16 + bl panic + +KCUnholdPages_0x114 + stw r16, -0x0ad0(r1) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 91, MPCall_91 + +MPCall_91 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Area.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + lwz r16, Area.LogicalBase(r31) + lwz r17, Area.LogicalBase2(r31) + cmplw r4, r16 + cmplw cr1, r4, r17 + blt+ major_0x0b054 + bgt+ cr1, major_0x0b054 + + _Lock PSA.HTABLock, scratch1=r14, scratch2=r15 + + mr r8, r4 + bl MPCall_95_0x1e4 + beq- MPCall_91_0xcc + bl MPCall_95_0x2b0 + bltl- cr5, MPCall_95_0x2e0 + bltl- cr5, MPCall_95_0x348 + lwz r29, 0x0000(r30) + sync + lwz r14, -0x0b90(r1) + cmpwi cr1, r14, 0x00 + li r14, 0x00 + bne+ cr1, MPCall_91_0x94 + mflr r14 + bl panic + +MPCall_91_0x94 + stw r14, -0x0b90(r1) + mr r8, r4 + bl MPCall_95_0x254 + li r19, 0x00 + beq- MPCall_91_0xac + lhz r19, 0x0000(r30) + +MPCall_91_0xac + andi. r5, r29, 0x319 + rlwinm. r8, r19, 0, 16, 16 + rlwimi r5, r19, 0, 16, 16 + +; r1 = kdp + beq+ ReleaseAndReturnZeroFromMPCall + rlwinm. r8, r19, 0, 17, 23 + +; r1 = kdp + beq+ ReleaseAndReturnZeroFromMPCall + ori r5, r5, 0x4000 + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_91_0xcc + sync + lwz r14, -0x0b90(r1) + cmpwi cr1, r14, 0x00 + li r14, 0x00 + bne+ cr1, MPCall_91_0xe8 + mflr r14 + bl panic + +MPCall_91_0xe8 + stw r14, -0x0b90(r1) + b ReleaseAndReturnMPCallOOM + + + + DeclareMPCall 92, MPCall_92 + +MPCall_92 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Area.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + lwz r16, Area.TwoFiftySix(r31) + rlwinm. r8, r16, 0, 28, 28 + bne+ major_0x0b054 + lwz r29, 0x0134(r6) + li r8, 0x318 + andc. r9, r5, r8 + bne+ major_0x0b054 + andc. r9, r29, r8 + bne+ major_0x0b054 + lwz r16, Area.LogicalBase(r31) + lwz r17, Area.LogicalBase2(r31) + cmplw r4, r16 + cmplw cr1, r4, r17 + blt+ major_0x0b054 + bgt+ cr1, major_0x0b054 + + _Lock PSA.HTABLock, scratch1=r14, scratch2=r15 + + mr r8, r4 + bl MPCall_95_0x1e4 + beq- MPCall_92_0xd8 + bl MPCall_95_0x2b0 + bns- cr7, MPCall_92_0x9c + bltl- cr5, MPCall_95_0x2e0 + bltl- cr5, MPCall_95_0x348 + +MPCall_92_0x9c + lwz r16, 0x0000(r30) + and r8, r5, r29 + orc r9, r5, r29 + or r16, r16, r8 + and r16, r16, r9 + stw r16, 0x0000(r30) + sync + lwz r14, -0x0b90(r1) + cmpwi cr1, r14, 0x00 + li r14, 0x00 + bne+ cr1, MPCall_92_0xd0 + mflr r14 + bl panic + +MPCall_92_0xd0 + stw r14, -0x0b90(r1) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_92_0xd8 + sync + lwz r14, -0x0b90(r1) + cmpwi cr1, r14, 0x00 + li r14, 0x00 + bne+ cr1, MPCall_92_0xf4 + mflr r14 + bl panic + +MPCall_92_0xf4 + stw r14, -0x0b90(r1) + b ReleaseAndReturnMPCallOOM + + + + DeclareMPCall 93, MPCall_93 + +MPCall_93 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Area.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + lwz r16, Area.LogicalBase(r31) + lwz r17, Area.LogicalBase2(r31) + cmplw r4, r16 + cmplw cr1, r4, r17 + blt+ major_0x0b054 + bgt+ cr1, major_0x0b054 + mr r8, r4 + bl MPCall_95_0x254 + beq+ major_0x0b054 + lhz r18, 0x0000(r30) + rlwinm. r8, r18, 0, 16, 16 + li r5, 0x00 + +; r1 = kdp + bne+ ReleaseAndReturnZeroFromMPCall + clrlwi r5, r18, 0x11 + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 94, MPCall_94 + +MPCall_94 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Area.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + lwz r16, Area.LogicalBase(r31) + lwz r17, Area.LogicalBase2(r31) + cmplw r4, r16 + cmplw cr1, r4, r17 + blt+ major_0x0b054 + bgt+ cr1, major_0x0b054 + mr r8, r4 + bl MPCall_95_0x254 + beq+ major_0x0b054 + cmplwi r5, 0x7fff + bgt+ major_0x0b054 + lhz r18, 0x0000(r30) + rlwinm. r8, r18, 0, 16, 16 + bne+ ReleaseAndReturnMPCallOOM + rlwimi r18, r5, 0, 17, 31 + sth r18, 0x0000(r30) + + _Lock PSA.HTABLock, scratch1=r16, scratch2=r17 + + mr r8, r4 + bl MPCall_95_0x1e4 + beq+ Local_Panic + bl MPCall_95_0x2b0 + bns- cr7, MPCall_94_0xa0 + bltl- cr5, MPCall_95_0x2e0 + bltl- cr5, MPCall_95_0x348 + +MPCall_94_0xa0 + sync + lwz r16, -0x0b90(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + bne+ cr1, MPCall_94_0xbc + mflr r16 + bl panic + +MPCall_94_0xbc + stw r16, -0x0b90(r1) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 129, MPCall_129 + +MPCall_129 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Area.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + lwz r16, Area.LogicalBase(r31) + lwz r17, Area.LogicalBase2(r31) + cmplw r4, r16 + cmplw cr1, r4, r17 + blt+ major_0x0b054 + bgt+ cr1, major_0x0b054 + mr r8, r4 + bl MPCall_95_0x254 + beq+ major_0x0b054 + lhz r18, 0x0000(r30) + li r5, 0x00 + rlwinm. r8, r18, 0, 16, 16 + li r16, 0x00 + beq- MPCall_129_0x6c + rlwinm r16, r18, 24, 25, 31 + clrlwi r5, r18, 0x18 + +MPCall_129_0x6c + stw r16, 0x0134(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + +; MPCall_95 + +; Xrefs: +; major_0x03324 +; IntDSIOtherOther +; PagingFunc1 +; kcMPDispatch +; NKxprintf +; MPCall_115 +; MPCall_75 +; MPCall_130 +; KCSetAreaAccess +; MPCall_123 +; MPCall_81 +; MPCall_98 +; KCMapPage +; KCUnmapPages +; KCMakePhysicallyContiguous +; KCLockPages +; KCUnlockPages +; KCHoldPages +; KCUnholdPages +; MPCall_91 +; MPCall_92 +; MPCall_93 +; MPCall_94 +; MPCall_129 + + DeclareMPCall 95, MPCall_95 + +MPCall_95 ; OUTSIDE REFERER + or. r8, r3, r4 + bne- MPCall_95_0x44 + li r16, 0x00 + stw r16, 0x06b4(r1) + _log 'Areas capability probe detected^n' + b ReturnParamErrFromMPCall + +MPCall_95_0x44 + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + li r28, -0x01 + li r4, 0x00 + li r5, 0x00 + lwz r8, PSA.UnheldFreePageCount(r1) + cmpwi r8, 0x00 + ble+ ReleaseAndReturnMPCallOOM + lwz r27, -0x0438(r1) + srwi r27, r27, 15 + mfspr r8, dec + subf r27, r27, r8 + lwz r8, -0x03f8(r1) + lwz r9, -0x03f4(r1) + mr r30, r9 + bl FindAreaAbove + mr r31, r8 + lwz r29, Area.LogicalBase(r31) + cmplw r29, r30 + bgt- MPCall_95_0xa8 + mr r29, r30 + +MPCall_95_0xa8 + crset cr2_eq + +MPCall_95_0xac + mfspr r9, dec + subf. r9, r27, r9 + blt- MPCall_95_0x1c8 + +MPCall_95_0xb8 + lwz r8, 0x0020(r31) + lwz r9, 0x0018(r31) + rlwinm. r8, r8, 0, 16, 16 + cmpwi cr1, r3, 0x00 + bne- MPCall_95_0x19c + beq- cr1, MPCall_95_0xe0 + cmpwi cr3, r9, 0x00 + beq- cr3, MPCall_95_0xe0 + cmpw cr1, r9, r3 + bne- cr1, MPCall_95_0x19c + +MPCall_95_0xe0 + lwz r9, Area.TwoFiftySix(r31) + rlwinm. r8, r9, 0, 28, 28 + bne- MPCall_95_0x19c + rlwinm. r8, r9, 0, 23, 23 + bne- MPCall_95_0x19c + + _Lock PSA.HTABLock, scratch1=r16, scratch2=r17 + + mr r8, r29 + bl MPCall_95_0x1e4 + beq+ Local_Panic + sync + lwz r16, -0x0b90(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + bne+ cr1, MPCall_95_0x134 + mflr r16 + bl panic + +MPCall_95_0x134 + stw r16, -0x0b90(r1) + lwz r16, 0x0000(r30) + clrlwi. r8, r16, 0x1f + beq- MPCall_95_0x180 + mr r8, r29 + bl MPCall_95_0x254 + beq- MPCall_95_0x1c8 + lhz r17, 0x0000(r30) + rlwinm. r8, r17, 0, 16, 16 + clrlwi r17, r17, 0x11 + bne- MPCall_95_0x180 + cmpw r17, r28 + crclr cr2_eq + ble- MPCall_95_0x180 + mr r28, r17 + lwz r4, Area.ID(r31) + cmplwi r17, 0x7fff + mr r5, r29 + bge- MPCall_95_0x1c8 + +MPCall_95_0x180 + lwz r8, 0x0068(r31) + lwz r9, Area.LogicalBase2(r31) + add r29, r29, r8 + subf. r9, r9, r29 + bge- MPCall_95_0x19c + bne+ cr2, MPCall_95_0xac + b MPCall_95_0xb8 + +MPCall_95_0x19c + lwz r8, 0x0054(r31) + lwz r9, 0x005c(r31) + cmpw r8, r9 + addi r31, r9, -0x54 + lwz r29, Area.LogicalBase(r31) + bne- MPCall_95_0x1c0 + lwz r9, 0x0008(r8) + addi r31, r9, -0x54 + lwz r29, Area.LogicalBase(r31) + +MPCall_95_0x1c0 + bne+ cr2, MPCall_95_0xac + b MPCall_95_0xb8 + +MPCall_95_0x1c8 + cmpwi r4, 0x00 + stw r29, -0x03f4(r1) + beq+ ReleaseAndReturnMPCallOOM + lwz r8, 0x0068(r31) + add r8, r8, r5 + stw r8, -0x03f4(r1) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_95_0x1e4 ; OUTSIDE REFERER + lwz r16, Area.LogicalBase(r31) + lwz r18, Area.TwoFiftySix(r31) + lwz r30, 0x0040(r31) + subf r17, r16, r8 + cmpwi r30, 0x00 + rlwinm r17, r17, 22, 10, 29 + beqlr- + rlwinm. r16, r18, 0, 26, 26 + rlwinm r16, r17, 22, 20, 29 + beq- MPCall_95_0x214 + rlwinm r17, r17, 0, 20, 29 + lwzx r30, r30, r16 + +MPCall_95_0x214 + add. r30, r30, r17 + blr + + dc.l 0x821f0024 ; again, probably just dead code + dc.l 0x825f0008 + dc.l 0x83df0040 + dc.l 0x56510739 + dc.l 0x7e304050 + dc.l 0x4182ffc4 + dc.l 0x83df0044 + dc.l 0x825f0080 + dc.l 0x3bdeffbc + dc.l 0x7e304050 + dc.l 0x7e319214 + dc.l 0x825e0008 + dc.l 0x83de0040 + dc.l 0x4bffffa4 + +MPCall_95_0x254 ; OUTSIDE REFERER + lwz r16, Area.LogicalBase(r31) + lwz r18, Area.TwoFiftySix(r31) + lwz r30, 0x003c(r31) + rlwinm. r17, r18, 0, 28, 28 + subf r17, r16, r8 + beq- MPCall_95_0x288 + lwz r30, 0x0044(r31) + lwz r18, 0x0080(r31) + addi r30, r30, -0x44 + subf r17, r16, r8 + add r17, r17, r18 + lwz r18, 0x0008(r30) + lwz r30, 0x003c(r30) + +MPCall_95_0x288 + cmpwi r30, 0x00 + rlwinm r17, r17, 21, 11, 30 + beqlr- + rlwinm. r16, r18, 0, 30, 30 + rlwinm r16, r17, 22, 20, 29 + beq- MPCall_95_0x2a8 + rlwinm r17, r17, 0, 20, 30 + lwzx r30, r30, r16 + +MPCall_95_0x2a8 + add. r30, r30, r17 + blr + +MPCall_95_0x2b0 ; OUTSIDE REFERER + lwz r19, 0x0000(r30) + lwz r18, 0x06a4(r1) + mtcrf 0x07, r19 + rlwinm r17, r19, 0, 0, 19 + rlwinm r16, r19, 23, 9, 28 + bnslr- cr7 + bgelr- cr5 + lwzux r16, r18, r16 + lwz r17, 0x0004(r18) + mtcrf 0x80, r16 + bge+ Local_Panic + blr + +MPCall_95_0x2e0 ; OUTSIDE REFERER + mfspr r14, pvr + clrlwi r16, r16, 0x01 + rlwinm. r14, r14, 0, 0, 14 + stw r16, 0x0000(r18) + sync + tlbie r8 + beq- MPCall_95_0x304 + sync + tlbsync + +MPCall_95_0x304 + sync + isync + cmpwi r30, 0x00 + lwz r14, 0x0000(r30) + lwz r17, 0x0004(r18) + oris r16, r16, 0x8000 + beqlr- + rlwimi r14, r17, 29, 27, 27 + rlwimi r14, r17, 27, 28, 28 + mtcrf 0x07, r14 + stw r14, 0x0000(r30) + blr + +MPCall_95_0x334 + stw r17, 0x0004(r18) + eieio + stw r16, 0x0000(r18) + sync + blr + +MPCall_95_0x348 ; OUTSIDE REFERER + lwz r14, 0x0000(r30) + li r16, -0x01 + stw r16, 0x0340(r1) + stw r16, 0x0348(r1) + stw r16, 0x0350(r1) + stw r16, 0x0358(r1) + lwz r16, 0x0e98(r1) + rlwinm r14, r14, 0, 21, 19 + addi r16, r16, 0x01 + stw r16, 0x0e98(r1) + rlwimi r14, r17, 0, 0, 19 + cmpwi r30, 0x00 + li r16, 0x00 + li r17, 0x00 + beq+ MPCall_95_0x334 + stw r14, 0x0000(r30) + b MPCall_95_0x334 + +V2P ; OUTSIDE REFERER + mr. r19, r9 + mfsprg r17, 0 + bne- MPCall_95_0x39c + lwz r19, EWA.PA_CurAddressSpace(r17) + +MPCall_95_0x39c + addi r18, r19, 0x80 + lwz r16, 0x0000(r18) + li r19, -0x01 + rlwimi r19, r16, 15, 0, 14 + xor r17, r8, r16 + andc. r17, r17, r19 + beq- MPCall_95_0x444 + lwzu r16, 0x0008(r18) + rlwimi r19, r16, 15, 0, 14 + xor r17, r8, r16 + andc. r17, r17, r19 + beq- MPCall_95_0x444 + lwzu r16, 0x0008(r18) + rlwimi r19, r16, 15, 0, 14 + xor r17, r8, r16 + andc. r17, r17, r19 + beq- MPCall_95_0x444 + lwzu r16, 0x0008(r18) + rlwimi r19, r16, 15, 0, 14 + xor r17, r8, r16 + andc. r17, r17, r19 + beq- MPCall_95_0x444 + lwzu r16, 0x0008(r18) + rlwimi r19, r16, 15, 0, 14 + xor r17, r8, r16 + andc. r17, r17, r19 + beq- MPCall_95_0x444 + lwzu r16, 0x0008(r18) + rlwimi r19, r16, 15, 0, 14 + xor r17, r8, r16 + andc. r17, r17, r19 + beq- MPCall_95_0x444 + lwzu r16, 0x0008(r18) + rlwimi r19, r16, 15, 0, 14 + xor r17, r8, r16 + andc. r17, r17, r19 + beq- MPCall_95_0x444 + lwzu r16, 0x0008(r18) + rlwimi r19, r16, 15, 0, 14 + xor r17, r8, r16 + andc. r17, r17, r19 + bne- MPCall_95_0x45c + +MPCall_95_0x444 + andi. r17, r16, 0x01 + rlwinm r19, r19, 0, 8, 19 + lwzu r17, 0x0004(r18) + and r19, r8, r19 + or r17, r17, r19 + bnelr- + +MPCall_95_0x45c ; OUTSIDE REFERER + cmpwi r9, noErr + addi r16, r9, 0x30 + beq- MPCall_95_0x474 + rlwinm r17, r8, 6, 26, 29 + lwzx r17, r16, r17 + b MPCall_95_0x478 + +MPCall_95_0x474 + mfsrin r17, r8 + +MPCall_95_0x478 + rlwinm r16, r8, 10, 26, 31 + rlwimi r16, r17, 7, 1, 24 + rlwinm r9, r8, 26, 10, 25 + oris r16, r16, 0x8000 + rlwinm r17, r17, 6, 7, 25 + xor r9, r9, r17 + lwz r17, 0x06a0(r1) + lwz r18, 0x06a4(r1) + and r9, r9, r17 + or. r18, r18, r9 + +MPCall_95_0x4a0 + lwz r17, 0x0000(r18) + lwz r9, 0x0008(r18) + cmpw cr6, r16, r17 + lwz r17, 0x0010(r18) + cmpw cr7, r16, r9 + lwzu r9, 0x0018(r18) + bne- cr6, MPCall_95_0x4c4 + +MPCall_95_0x4bc + lwzu r17, -0x0014(r18) + blr + +MPCall_95_0x4c4 + cmpw cr6, r16, r17 + lwzu r17, 0x0008(r18) + beq+ cr7, MPCall_95_0x4bc + cmpw cr7, r16, r9 + lwzu r9, 0x0008(r18) + beq+ cr6, MPCall_95_0x4bc + cmpw cr6, r16, r17 + lwzu r17, 0x0008(r18) + beq+ cr7, MPCall_95_0x4bc + cmpw cr7, r16, r9 + lwzu r9, 0x0008(r18) + beq+ cr6, MPCall_95_0x4bc + cmpw cr6, r16, r17 + lwzu r17, -0x000c(r18) + beqlr- cr7 + cmpw cr7, r16, r9 + lwzu r17, 0x0008(r18) + beqlr- cr6 + lwzu r17, 0x0008(r18) + beqlr- cr7 + lwz r17, 0x06a0(r1) + xori r16, r16, 0x40 + andi. r9, r16, 0x40 + addi r18, r18, -0x3c + xor r18, r18, r17 + bne+ MPCall_95_0x4a0 + blr diff --git a/NanoKernel/NKBuiltinInit.s b/NanoKernel/NKBuiltinInit.s new file mode 100644 index 0000000..0c1d458 --- /dev/null +++ b/NanoKernel/NKBuiltinInit.s @@ -0,0 +1,1379 @@ +; When we receive control: +; r3 = ConfigInfo +; r4 = ProcessorInfo +; r5 = SystemInfo +; r6 = DiagInfo +; r7 = RTAS_flag ('RTAS' or 0) +; r8 = RTAS_proc +; r9 = HWInfo + + + +InitBuiltin + + + +; Leave zero in r0 (it is rather a silly place). + + li r0, 0 + + + +; Initialize segment registers (understand these better!) + + isync + lis r12, 0x2000 + mtsr 0, r12 + mtsr 1, r0 + mtsr 2, r0 + mtsr 3, r0 + mtsr 4, r0 + mtsr 5, r0 + mtsr 6, r0 + mtsr 7, r0 + mtsr 8, r0 + mtsr 9, r0 + mtsr 10, r0 + mtsr 11, r0 + mtsr 12, r0 + mtsr 13, r0 + mtsr 14, r0 + mtsr 15, r0 + isync + + + +; Zero out the timebase (rtc on 601) and upper BAT registers +; (this is best practice for invalidating BATs) +; (Interestingly, SheepShaver also uses r12 for this PVR access.) + + mfspr r12, pvr + rlwinm. r12, r12, 0, 0, 14 + bne- @not601 + + mtspr rtcl, r0 + mtspr rtcu, r0 + mtspr ibat0l, r0 + mtspr ibat1l, r0 + mtspr ibat2l, r0 + mtspr ibat3l, r0 + + b @endif601 +@not601 + + mtspr tbl, r0 + mtspr tbu, r0 + mtspr ibat0u, r0 + mtspr ibat1u, r0 + mtspr ibat2u, r0 + mtspr ibat3u, r0 + mtspr dbat0u, r0 + mtspr dbat1u, r0 + mtspr dbat2u, r0 + mtspr dbat3u, r0 + +@endif601 + + + + +; The Trampoline instructs us to put the base of the blue area at +; this physical address, which seems always to be the base of the +; first RAM bank reported by the trampoline. (The kernel is also +; expected to initialise MacOS LowMemory from a key/valye list.) + + lwz r12, NKConfigurationInfo.PA_RelocatedLowMemInit(r3) + + + +; Search SysInfo for the first nonzero size RAM bank. + + addi r10, r5, NKSystemInfo.Bank0Start - 4 +@rambank_loop + lwzu r11, 8(r10) ; Bank0Size, Bank1Size... + cmpwi r11, 0 + beq+ @rambank_loop + + ; r10 points to BankXSize, r11 contains BankXSize + + + +; DeltaMemory = PA_RelocatedLowMemInit if fits in bank, else 0. + + subf r11, r12, r11 + srawi r11, r11, 31 ; f... if PA_ > BankSize else 0... + andc r12, r12, r11 ; zero DeltaMemory if PA_ > BankSize + + + +; BankSize -= DeltaMemory + + lwz r11, 0(r10) + subf r11, r12, r11 + stw r11, 0(r10) + + + +; BankStart += DeltaMemory + + lwz r11, -4(r10) + add r11, r11, r12 + stw r11, -4(r10) + + + +; PhysicalMemorySize -= DeltaMemory (+ another page if there is close to 2GB) + + lwz r11, NKSystemInfo.PhysicalMemorySize(r5) + addis r15, r11, 1 + cmpwi r15, 0 + bgt- @skip_reducing_ram + addi r11, r11, -4096 +@skip_reducing_ram + subf r11, r12, r11 + stw r11, 0(r5) + + + +; Load PhysicalMemorySize - 1 into r15. +; +; Create the HTABMASK for eventual insertion in lo half of SDR1: +; - Is number of bits used from hash func to index PTEGs in HTAB. +; - Arch allows 10..19 bits. +; - Bits 0-9 assumed by architecture. +; - Bits 10-18 in the low field of SDR1. +; - Bits 19-31 also in low field, but must be zeroed. +; - Our r14 "mask" = (future low half of SDR1) || 0xffff. +; - Therefore has an extra six ones. +; - Therefore equals HTAB size - 1. +; - Computed from PhysicalMemorySize as follows: +; +; --------------------------------------------------------------------- +; Phys RAM r14 HTABMASK bits PTEGs in HTAB HTAB size +; (MB) (10-19 allowed) +; --------------------------------------------------------------------- +; <= 8 0000ffff 10 1k 64k +; <= 16 0001ffff 11 2k 128k +; <= 32 0003ffff 12 4k 256k +; <= 64 0007ffff 13 8k 512k +; <= 128 000fffff 14 16k 1024k +; <= 256 001fffff 15 32k 2048k +; > 256 003fffff 16 64k 4096k + + lwz r15, NKSystemInfo.PhysicalMemorySize(r5) + addi r15, r15, -1 + cntlzw r12, r15 + + lis r14, 0x01ff + srw r14, r14, r12 + ori r14, r14, 0xffff + clrlwi r14, r14, 10 + + + +; Based on PhysicalMemorySize, guess how much memory the +; kernel needs, including the HTAB. Leave it in r15. +; +; ----------------------------- +; Phys RAM r15 Kern +; (MB) pages +; ----------------------------- +; >= 4 0001d000 29 +; >= 8 0001e000 30 +; >= 16 00030000 48 +; >= 32 00054000 84 +; >= 64 0009c000 156 +; >= 128 0012c000 300 +; >= 256 0024c000 588 +; >= 512 0048c000 1164 +; >=1024 0050c000 1292 +; >=2048 0060c000 1548 + + addis r15, r15, 0x40 + rlwinm r15, r15, 22, 10, 19 + add r15, r15, r14 + lisori r10, 0x0000c001 + add r15, r15, r10 + + + +; Search SysInfo backwards for a RAM bank that can fit: +; - A HTAB aligned to a multiple of its own length +; - An r15-size area immediately below that +; +; Kernel structures (HTAB at top) will butt up against +; BankEnd % HTABSIZE. Leave bottom in r13 and top in r12. + + addi r10, r5, NKSystemInfo.EndOfBanks +@try_another_bank + lwz r11, -4(r10) ; size + lwzu r12, -8(r10) ; start + add r11, r12, r11 ; end + andc r13, r11, r14 ; end % HTABSIZE + subf r13, r15, r13 ; end % HTABSIZE - r15 + cmplw r13, r12 + blt+ @try_another_bank + cmplw r13, r11 + bgt+ @try_another_bank + + add r12, r13, r15 + + + +; Populate SDR1 with HTABORG || HTABMASK: +; - HTABORG = top_of_bank % HTABSIZE (only top half) +; - HTABMASK = top half of r14 (which equals HTABSIZE-1) +; +; Leave SDR1 in r12 and HTABORG (a full address) in r11. + + subf r12, r14, r12 + rlwimi r12, r14, 16, 16, 31 + mtspr sdr1, r12 + + rlwinm r11, r12, 0, 0, 15 + + + +; Recap: (matches SheepShaver notes on NKv1) +; r11 HTABORG +; r12 SDR1 +; r13 base of "reserved" kernel area +; r14 HTABSIZE - 1 +; r15 size of "reserved" kernel area + + + +; Place the kernel data page (KDP) 8k below the HTAB, +; and point SPRG0 at it. r1 almost always points to KDP. +; +; Page above KDP becomes emulator data page (EDP). +; Page below KDP becomes private v2 kernel globals. + + lisori r1, -0x2000 + add r1, r1, r11 + + mtsprg 0, r1 + + + +; Init the reserved area to zero, up to the HTAB. +; +; But if the machine has Thudded and dumped all its registers +; (as evidenced by a saved SDR1) then don't zero that dump. + + lwz r11, KDP.ThudSavedSDR1(r1) + cmpw r12, r11 + lis r11, 0x7fff + + bne- @did_not_panic + subf r11, r13, r1 + addi r11, r11, KDP.StartOfPanicArea +@did_not_panic + + subf r12, r14, r15 + addi r12, r12, -0x01 + +@eraseloop + addic. r12, r12, -4 + + subf r10, r11, r12 + cmplwi cr7, r10, KDP.EndOfPanicArea - KDP.StartOfPanicArea - 4 + + ble- cr7, @skipwrite + stwx r0, r13, r12 +@skipwrite + + bne+ @eraseloop + + + +; Put r1 pointer (for indexing PSA/KDP) in CPU-0 EWA + + stw r1, EWA.PA_KDP(r1) + + + +; Set up the interrupt response page (IRP) at KDP - (10 pages). +; +; (Point CPU-0 EWA to it and fill it with 0x68f168f1.) + + lisori r12, IRPOffset + add r12, r12, r1 + stw r12, EWA.PA_IRP(r1) + + bl InitIRP + + + +; Set up runtime abstraction services (RTAS). +; +; Kernel argument r7 is either 'RTAS' or zero. If 'RTAS': +; - Arg r8 points to RTAS dispatch proc. +; - Arg r9 points to HWInfo points to RTAS private data +; - Copy HWInfo into IRP +; +; TODO: neaten, use records! + + + lisori r12, 'RTAS' + cmpw r7, r12 + bne- @RTAS_absent + + stw r8, KDP.RTAS_Proc(r1) + + lwz r7, NKHWInfo.RTAS_PrivDataArea(r9) + stw r7, KDP.RTAS_PrivDataArea(r1) + + lwz r11, EWA.PA_IRP(r1) + addi r11, r11, IRP.HWInfo + li r10, 0xc0 + +@RTAS_copyloop + addic. r10, r10, -4 + lwzx r12, r9, r10 + stwx r12, r11, r10 + bgt+ @RTAS_copyloop + + stw r23, PSA.NoIdeaR23(r1) + b @RTAS_done + +@RTAS_absent + stw r0, KDP.RTAS_Proc(r1) + stw r0, KDP.RTAS_PrivDataArea(r1) + +@RTAS_done + + + +; Copy 160 bytes of ProcessorInfo into KDP +; (Way longer than anything I know about!) + + addi r11, r1, KDP.ProcessorInfo + li r10, 160 +@ProcessorInfo_copyloop + addic. r10, r10, -4 + lwzx r12, r4, r10 + stwx r12, r11, r10 + bgt+ @ProcessorInfo_copyloop + + + +; Copy 320 bytes of SystemInfo into IRP + + lwz r11, EWA.PA_IRP(r1) + addi r11, r11, IRP.SystemInfo + li r10, 320 +@SystemInfo_copyloop + addic. r10, r10, -4 + lwzx r12, r5, r10 + stwx r12, r11, r10 + bgt+ @SystemInfo_copyloop + + + +; If DiagnosticInfo != 0, copy it to PSA + + cmpwi r6, 0 + beq- @DiagInfo_skipcopy + + addi r11, r1, PSA.DiagInfo + li r10, 256; NKDiagInfo.Size + +@DiagInfo_copyloop + addic. r10, r10, -4 + lwzx r12, r6, r10 + stwx r12, r11, r10 + bgt+ @DiagInfo_copyloop + +@DiagInfo_skipcopy + + + +; Store a ConfigInfo pointer in KDP + + stw r3, KDP.PA_ConfigInfo(r1) + + + +; Add to (presumably empty) ConfigFlags + + lwz r9, KDP.PA_ConfigInfo(r1) + lhz r8, NKConfigurationInfo.Debug(r9) + + ; If CI.Debug >= 257 && CI.DebugFlags & 2 ... + cmplwi r8, NKConfigurationInfo.DebugThreshold + lwz r8, KDP.NanoKernelInfo + NKNanoKernelInfo.ConfigFlags(r1) + + if &TYPE('NKShowLog') = 'UNDEFINED' + blt- @no_screen_log + lwz r8, NKConfigurationInfo.DebugFlags(r9) + rlwinm. r8, r8, 0, NKConfigurationInfo.LogFlagBit, NKConfigurationInfo.LogFlagBit + lwz r8, KDP.NanoKernelInfo + NKNanoKernelInfo.ConfigFlags(r1) + beq- @no_screen_log + endif + + ; Enable the screen log + ori r8, r8, 1<< 3 +@no_screen_log + + ; Switch on two other flags + ori r8, r8, 1<< 0 ; not sure + ori r8, r8, 1<< 4 ; to do with interrupts + stw r8, KDP.NanoKernelInfo + NKNanoKernelInfo.ConfigFlags(r1) + + + +; Turns out that there was a CPU struct hiding between PSA and KDP, +; which contains our main CPU ewa + + addi r9, r1, EWA.CPUBase + li r8, -1 + stw r8, CPU.ID(r9) + + + +; Say hello. + + bl InitScreenConsole + + _log 'Hello from the builtin multitasking NanoKernel. Version: ' + + li r8, kNanoKernelVersion + mr r8, r8 + bl Printh + + _log '^n' + + + +; Save a pointer to the kernel memory area in KDP +; (will get upped by pool extends?) + + stw r13, KDP.KernelMemoryBase(r1) + + + +; PA_NanoKernelCode is uninitialized, but this loaded value gets +; clobbered straight away anyway. Compiler! + + lwz r12, KDP.PA_NanoKernelCode(r1) + + + +; Choose a primary interrupt handler (PIH) +; + ; ARG NKConfigurationInfo *r3 + bl LookupInterruptHandler + ; RET InterruptHandler *r7 + ; CLOB r12 + + stw r7, KDP.PA_InterruptHandler(r1) + + + +; Store HTABSIZE in the IRP + + lwz r11, EWA.PA_IRP(r1) + addi r12, r14, 1 + stw r12, IRP.SystemInfo + NKSystemInfo.HashTableSize(r11) + + + +; Populate KDP... + + ; Place EDP pointer (and leave it in r8). + addi r8, r1, 0x1000 + stw r8, KDP.PA_EmulatorData(r1) + + + ; Place pointer to top of reserved kernel area. + ; (= ptr to top of HTAB) + add r12, r13, r15 + stw r12, KDP.KernelMemoryEnd(r1) + + + ; Place PA_RelocatedLowMemInit from ConfigInfo in KDP. + ; (See note above.) + lwz r12, NKConfigurationInfo.PA_RelocatedLowMemInit(r3) + stw r12, KDP.PA_RelocatedLowMemInit(r1) + + + ; Place something from ConfigInfo in KDP. + ; This address seems to contain 0x40820160. + ; Trampoline ns old SharedMemoryAddr, which was 0 anyway. + lwz r12, NKConfigurationInfo.SharedMemoryAddr(r3) + stw r12, KDP.SharedMemoryAddr(r1) + + + ; Place (LA_EmulatorCode + KernelTrapTableOffset) from ConfigInfo in KDP. + ; (Call this LA_EmulatorKernelTrapTable?) + lwz r12, NKConfigurationInfo.LA_EmulatorCode(r3) + lwz r11, NKConfigurationInfo.KernelTrapTableOffset(r3) + add r12, r12, r11 + stw r12, KDP.LA_EmulatorKernelTrapTable(r1) + + + ; Place "PA_NanoKernelCode" in KDP and leave it in r12. + bl * + 4 + mflr r12 + addi r12, r12, 4 - * + stw r12, KDP.PA_NanoKernelCode(r1) + + + ; FDP. Got its name from an embarrassing mistake by me. Needs a better one. + ; Probably written by Gary, it emulates bad PowerPC instructions. + llabel r11, FDP + add r12, r11, r12 + stw r12, KDP.PA_FDP(r1) + + + ; Place "LA_ECB" and "PA_ECB" (twice) from ConfigInfo in KDP. + ; (This gets called the System Context.) + lwz r12, NKConfigurationInfo.LA_EmulatorData(r3) + lwz r11, NKConfigurationInfo.ECBOffset(r3) + add r12, r12, r11 + stw r12, KDP.LA_ECB(r1) + + + add r12, r8, r11 ; PA_EmulatorData + ECBOffset + stw r12, KDP.PA_ECB(r1) + stw r12, EWA.PA_ContextBlock(r1) + + + ; Place init vals for rupt masks from ConfigInfo in KDP. + lwz r12, NKConfigurationInfo.TestIntMaskInit(r3) + stw r12, KDP.TestIntMaskInit(r1) + lwz r12, NKConfigurationInfo.ClearIntMaskInit(r3) + stw r12, KDP.ClearIntMaskInit(r1) + lwz r12, NKConfigurationInfo.PostIntMaskInit(r3) + stw r12, KDP.PostIntMaskInit(r1) + + + ; Place "PA_EmulatorIplValue" from ConfigInfo in KDP. + lwz r12, NKConfigurationInfo.IplValueOffset(r3) + add r12, r8, r12 + stw r12, KDP.PA_EmulatorIplValue(r1) + + + ; Copy this value from ConfigInfo to KDP *again* (see above). + ; But this time, add 0x7c to get 0x408201DC. + lwz r12, NKConfigurationInfo.SharedMemoryAddr(r3) + addi r12, r12, 0x7c + stw r12, KDP.SharedMemoryAddrPlus(r1) + + + ; Place PageAttributeInit from ConfigInfo in KDP. + lwz r12, NKConfigurationInfo.PageAttributeInit(r3) + stw r12, KDP.PageAttributeInit(r1) + + + ; Make space at KDP + 0x920 for PageMap, + ; according to ConfigInfo.PageMapInitSize. + ; 0x1b8 might be a typical value + addi r13, r1, KDP.PageMap + lwz r12, NKConfigurationInfo.PageMapInitSize(r3) + stw r13, KDP.PA_PageMapStart(r1) + add r13, r13, r12 + stw r13, KDP.PA_PageMapEnd(r1) + + + ; Zero out a word in KDP a bit below &PA_PageMap. + ; Only NewWorld and Unknown PIHes touch this. + stw r0, KDP.ZeroWord(r1) + + + +; The InfoRecord contains metadata about the Power Mac structures +; described in PPCInfoRecordsPriv. + +; It lives in the top 64b of the InfoRecord (nee Interrupt Response) Page, +; which on PCI machines is mapped to 5fffe000 (just under 1.5GB). Here we +; populate it at the top of our KDP, and later we copy it to our IRP. + + ; Logical self-pointer to the copy of InfoRecord in KDP + ; (Will this be altered when the InfoRecord is copied to IRP?) + lwz r11, NKConfigurationInfo.LA_KernelData(r3) + addi r12, r11, KDP.InfoRecord + stw r12, KDP.InfoRecord + InfoRecord.InfoRecordPtr(r1) + + + ; Constant + stw r0, KDP.InfoRecord + InfoRecord.Zero(r1) + + + ; NKProcessorState (created by kernel, lives in PSA) + + lwz r11, NKConfigurationInfo.LA_KernelData(r3) + addi r12, r11, PSA.ProcessorState + stw r12, KDP.InfoRecord + InfoRecord.NKProcessorStatePtr(r1) + + li r12, 0x0100 + sth r12, KDP.InfoRecord + InfoRecord.NKProcessorStateVer(r1) + + li r12, 128 + sth r12, KDP.InfoRecord + InfoRecord.NKProcessorStateLen(r1) + + + ; NKHWInfo (created by bootloader, copied to IRP) + + lwz r11, NKConfigurationInfo.LA_InfoRecord(r3) + addi r12, r11, IRP.HWInfo + stw r12, KDP.InfoRecord + InfoRecord.NKHWInfoPtr(r1) + + li r12, 0x0108 + sth r12, KDP.InfoRecord + InfoRecord.NKHWInfoVer(r1) + + li r12, 192 + sth r12, KDP.InfoRecord + InfoRecord.NKHWInfoLen(r1) + + + ; NKProcessorInfo (created by bootloader, copied to KDP) + + lwz r11, NKConfigurationInfo.LA_KernelData(r3) + addi r12, r11, KDP.ProcessorInfo + stw r12, KDP.InfoRecord + InfoRecord.NKProcessorInfoPtr(r1) + + li r12, 0x0112 + sth r12, KDP.InfoRecord + InfoRecord.NKProcessorInfoVer(r1) + + li r12, 160 + sth r12, KDP.InfoRecord + InfoRecord.NKProcessorInfoLen(r1) + + + ; NKNanoKernelInfo (created by kernel, lives in KDP) + + lwz r11, NKConfigurationInfo.LA_KernelData(r3) + addi r12, r11, KDP.NanoKernelInfo + stw r12, KDP.InfoRecord + InfoRecord.NKNanoKernelInfoPtr(r1) + + li r12, kNanoKernelVersion + sth r12, KDP.InfoRecord + InfoRecord.NKNanoKernelInfoVer(r1) + + li r12, 352 + sth r12, KDP.InfoRecord + InfoRecord.NKNanoKernelInfoLen(r1) + + + ; NKDiagInfo (created by bootloader, copied to PSA) + + lwz r11, NKConfigurationInfo.LA_KernelData(r3) + addi r12, r11, PSA.DiagInfo + stw r12, KDP.InfoRecord + InfoRecord.NKDiagInfoPtr(r1) + + li r12, 0x0100 + sth r12, KDP.InfoRecord + InfoRecord.NKDiagInfoVer(r1) + + li r12, 256 + sth r12, KDP.InfoRecord + InfoRecord.NKDiagInfoLen(r1) + + + ; NKSystemInfo (created by bootloader, copied to IRP) + + lwz r11, NKConfigurationInfo.LA_InfoRecord(r3) + addi r12, r11, IRP.SystemInfo + stw r12, KDP.InfoRecord + InfoRecord.NKSystemInfoPtr(r1) + + li r12, 0x0107 + sth r12, KDP.InfoRecord + InfoRecord.NKSystemInfoVer(r1) + + li r12, 320 + sth r12, KDP.InfoRecord + InfoRecord.NKSystemInfoLen(r1) + + + ; NKProcessorInfo... again! + + lwz r11, NKConfigurationInfo.LA_KernelData(r3) + addi r12, r11, KDP.ProcessorInfo + stw r12, KDP.InfoRecord + InfoRecord.NKProcessorInfoPtr2(r1) + + li r12, 0x0112 + sth r12, KDP.InfoRecord + InfoRecord.NKProcessorInfoVer2(r1) + + li r12, 160 + sth r12, KDP.InfoRecord + InfoRecord.NKProcessorInfoLen2(r1) + + + +; Populate emulator data page (EDP). + + ; Copy 16-byte BootstrapVersion string from ConfigInfo + lwz r11, NKConfigurationInfo.BootVersionOffset(r3) + lwz r12, NKConfigurationInfo.BootstrapVersion(r3) + stwux r12, r11, r8 + lwz r12, NKConfigurationInfo.BootstrapVersion + 4(r3) + stw r12, 4(r11) + lwz r12, NKConfigurationInfo.BootstrapVersion + 8(r3) + stw r12, 8(r11) + lwz r12, NKConfigurationInfo.BootstrapVersion + 12(r3) + stw r12, 12(r11) + + + ; Place logical pointer to emulator entry point in ContextBlock. + ; Leave pointer to ECB in r11. + lwz r12, NKConfigurationInfo.LA_EmulatorCode(r3) + lwz r11, NKConfigurationInfo.EmulatorEntryOffset(r3) + add r12, r11, r12 + lwz r11, NKConfigurationInfo.ECBOffset(r3) + add r11, r11, r8 + stw r12, ContextBlock.LA_EmulatorEntry(r11) + + + ; Place LA_EmulatorData from ConfigInfo in ContextBlock. + lwz r12, NKConfigurationInfo.LA_EmulatorData(r3) + stw r12, ContextBlock.LA_EmulatorData(r11) + + + ; Place LA_DispatchTable from ConfigInfo in ContextBlock. + lwz r12, NKConfigurationInfo.LA_DispatchTable(r3) + stw r12, ContextBlock.LA_DispatchTable(r11) + + + ; Place LA_EmulatorKernelTrapTable from KDP in ContextBlock. + lwz r12, KDP.LA_EmulatorKernelTrapTable(r1) + stw r12, ContextBlock.LA_EmulatorKernelTrapTable(r11) + + + +; Initialize MacOS LowMem globals at PA_RelocatedLowMemInit + + ; Zero out 8k + lwz r10, KDP.PA_RelocatedLowMemInit(r1) + li r9, 0x2000 +@LowMem_zeroloop + addic. r9, r9, -4 + stwx r0, r10, r9 + bne+ @LowMem_zeroloop + + + ; Populate from LowMemInit "key-value" table. + lwz r11, NKConfigurationInfo.MacLowMemInitOffset(r3) + lwz r10, KDP.PA_RelocatedLowMemInit(r1) + + lwzux r9, r11, r3 ; get first word and point r11 at it +@LowMem_setloop + mr. r9, r9 + beq- @LowMem_done + lwzu r12, 4(r11) + stwx r12, r10, r9 + lwzu r9, 4(r11) + b @LowMem_setloop +@LowMem_done + + + +; We expect a 'Hnfo' signature (from Trampoline) in HWInfo. +; +; If HWInfo IS signed, great -- we can move on with the init process, +; and skip all the nasty cache-probing, table-consulting madness that +; follows. Just ignore the rest of this file. +; +; But if HWInfo is unsigned, then this is going to hurt. + + lwz r11, EWA.PA_IRP(r1) + lwz r11, IRP.HWInfo + NKHWInfo.Signature(r11) + lisori r12, 'Hnfo' + cmplw r12, r11 + beq- FinishInitBuiltin + + + +; Darn. All right, see if we can copy ProcessorInfo from +; ProcessorInfoTable.s + + mfpvr r12 + stw r12, KDP.ProcessorInfo + NKProcessorInfo.ProcessorVersionReg(r1) + srwi r12, r12, 16 + lwz r11, KDP.PA_NanoKernelCode(r1) + addi r10, r1, KDP.ProcessorInfo + NKProcessorInfo.Ovr + li r9, NKProcessorInfo.OvrEnd - NKProcessorInfo.Ovr + +; check for several (some unknown) pre-7410 CPUs, and load their info + cmpwi r12, 0x0001 ; 601 + addi r11, r11, ProcessorInfoTable - NKTop + beq- OverrideProcessorInfo + + cmpwi r12, 0x0003 ; 603 + addi r11, r11, NKProcessorInfo.OvrEnd - NKProcessorInfo.Ovr + beq- OverrideProcessorInfo + + cmpwi r12, 0x0004 ; 604 + addi r11, r11, NKProcessorInfo.OvrEnd - NKProcessorInfo.Ovr + beq- OverrideProcessorInfo + + cmpwi r12, 0x0006 ; 603e + addi r11, r11, NKProcessorInfo.OvrEnd - NKProcessorInfo.Ovr + beq- OverrideProcessorInfo + + cmpwi r12, 0x0007 ; 750FX + addi r11, r11, NKProcessorInfo.OvrEnd - NKProcessorInfo.Ovr + beq- OverrideProcessorInfo + + cmpwi r12, 0x0008 ; 750 + addi r11, r11, NKProcessorInfo.OvrEnd - NKProcessorInfo.Ovr + beq- OverrideProcessorInfo + + cmpwi r12, 0x0009 ; ??? + addi r11, r11, NKProcessorInfo.OvrEnd - NKProcessorInfo.Ovr + beq- OverrideProcessorInfo + cmpwi r12, 0x000a ; ??? + beq- OverrideProcessorInfo + + cmpwi r12, 0x000c ; 7400 + addi r11, r11, NKProcessorInfo.OvrEnd - NKProcessorInfo.Ovr + beq- OverrideProcessorInfo + + cmpwi r12, 0x000d ; ??? + addi r11, r11, NKProcessorInfo.OvrEnd - NKProcessorInfo.Ovr + beq- OverrideProcessorInfo + + + +; Now things get crazy. Have barely touched this... + +; get base of page table (why?) + mfsdr1 r22 + +; r21 = SDR1 & 0xffff0000 + rlwinm r21, r22, 0, 0, 15 + +; r22 = (SDR1 << 16) & 0x007F0000 + rlwinm r22, r22, 16, 9, 15 + addis r22, r22, 0x01 + li r15, 0x00 + li r12, 0x1a + mtctr r12 + lwz r12, -0x0020(r1) + addi r10, r12, 0xec0 + +new_world_0x60c + lwz r11, -0x0004(r10) + lwzu r12, -0x0008(r10) + subf r9, r12, r21 + cmplw r9, r11 + bge- new_world_0x624 + mr r11, r9 + +new_world_0x624 + cmplw r11, r15 + ble- new_world_0x634 + mr r13, r12 + mr r15, r11 + +new_world_0x634 + bdnz+ new_world_0x60c + addi r12, r22, -0x01 + neg r11, r13 + and r12, r11, r12 + add r13, r13, r12 + subf r15, r12, r15 + rlwinm r15, r15, 0, 0, 21 + li r11, 0x1000 + stw r11, 0x0f30(r1) + li r11, -0x01 + li r10, 0x400 + +new_world_0x660 + subic. r10, r10, 4 + stwx r11, r21, r10 + bne+ new_world_0x660 + dcbz 0, r21 + +new_world_0x670 + addi r10, r10, 0x01 + lbzx r11, r21, r10 + cmpwi r11, 0x00 + beq+ new_world_0x670 + sth r10, 0x0f3c(r1) + sth r10, 0x0f3e(r1) + sth r10, 0x0f46(r1) + sth r10, 0x0f48(r1) + sth r10, 0x0f4a(r1) + lis r12, -0x8000 + add r11, r21, r22 + addi r11, r11, -0xe6e + addis r10, r21, 0x01 + +new_world_0x6a4 + stwu r11, -0x0004(r10) + rlwimi r12, r10, 29, 29, 31 + stwu r12, -0x0004(r10) + cmpw r10, r21 + rlwinm r9, r10, 9, 7, 19 + tlbie r9 + bne+ new_world_0x6a4 + sync + isync + lwz r11, 0x064c(r1) + li r12, (copied_code_1_end - copied_code_1) / 4 + mtctr r12 + add r20, r21, r22 + addi r11, r11, copied_code_1_end - NKTop + +new_world_0x6dc + lwzu r12, -0x0004(r11) + stwu r12, -0x0004(r20) + dcbst 0, r20 + sync + icbi 0, r20 + bdnz+ new_world_0x6dc + sync + isync + stw r0, 0x0f34(r1) + li r17, 0x00 + li r18, 0x200 + li r19, 0x00 + li r16, -0x01 + b new_world_0x720 + +new_world_0x714 + addi r17, r17, 0x200 + cmplw r17, r15 + bge- new_world_0x734 + +new_world_0x720 + mtlr r20 + blrl + ble+ new_world_0x714 + addi r12, r17, -0x200 + stw r12, 0x0f34(r1) + +new_world_0x734 + li r12, 0x01 + sth r12, 0x0f4e(r1) + lwz r18, 0x0f34(r1) + mr r17, r18 + li r19, 0x00 + li r16, -0x01 + b new_world_0x75c + +new_world_0x750 + add r17, r17, r18 + cmplw r17, r15 + bge- new_world_0x774 + +new_world_0x75c + mtlr r20 + blrl + ble+ new_world_0x750 + subf r17, r18, r17 + divwu r12, r17, r18 + sth r12, 0x0f4e(r1) + +new_world_0x774 + lwz r17, 0x0f34(r1) + lhz r18, 0x0f4e(r1) + slwi r17, r17, 1 + divwu r18, r17, r18 + srwi r19, r18, 1 + li r14, 0x200 + add r19, r19, r14 + li r16, -0x01 + b new_world_0x7ac + +new_world_0x798 + lhz r12, 0x0f4a(r1) + cmplw r14, r12 + ble- new_world_0x7bc + srwi r14, r14, 1 + subf r19, r14, r19 + +new_world_0x7ac + mtlr r20 + blrl + ble+ new_world_0x798 + slwi r12, r14, 1 + +new_world_0x7bc + sth r12, 0x0f44(r1) + mtsdr1 r21 + mr r14, r13 + li r13, 0xff0 + sth r0, 0x0f50(r1) + li r17, 0x00 + lwz r18, 0x0f30(r1) + li r19, 0x00 + li r16, -0x01 + b new_world_0x7f4 + +new_world_0x7e4 + add r17, r17, r18 + lis r12, 0x3f + cmplw r17, r12 + bge- new_world_0x82c + +new_world_0x7f4 + mtlr r20 + mfmsr r12 + ori r12, r12, 0x10 + mtmsr r12 + isync + blrl + mfmsr r12 + rlwinm r12, r12, 0, 28, 26 + mtmsr r12 + isync + ble+ new_world_0x7e4 + subf r17, r18, r17 + divwu r12, r17, r18 + sth r12, 0x0f50(r1) + +new_world_0x82c + li r12, 0x01 + sth r12, 0x0f52(r1) + li r17, 0x00 + lis r18, 0x40 + li r19, 0x00 + li r16, -0x01 + b new_world_0x858 + +new_world_0x848 + add r17, r17, r18 + lis r12, 0x200 + cmplw r17, r12 + bge- new_world_0x890 + +new_world_0x858 + mtlr r20 + mfmsr r12 + ori r12, r12, 0x10 + mtmsr r12 + isync + blrl + mfmsr r12 + rlwinm r12, r12, 0, 28, 26 + mtmsr r12 + isync + ble+ new_world_0x848 + subf r17, r18, r17 + divwu r12, r17, r18 + sth r12, 0x0f52(r1) + +new_world_0x890 + mr r13, r14 + addi r12, r22, -0x01 + srwi r12, r12, 16 + or r12, r12, r21 + mtsdr1 r12 + lwz r12, 0x0f34(r1) + stw r12, 0x0f38(r1) + lhz r12, 0x0f4e(r1) + sth r12, 0x0f4c(r1) + lhz r12, 0x0f44(r1) + sth r12, 0x0f42(r1) + lis r11, 0x3960 + stw r11, 0x0000(r21) + lis r11, 0x4e80 + ori r11, r11, 0x20 + stw r11, 0x0004(r21) + dcbst 0, r21 + sync + icbi 0, r21 + sync + isync + mtlr r21 + blrl + li r11, 0x01 + sth r11, 0x0002(r21) + sync + isync + mtlr r21 + blrl + sth r11, 0x0f40(r1) + cmpwi r11, 0x01 + beq- skip_cache_hackery_never + lwz r11, 0x064c(r1) + li r12, (copied_code_2_end - copied_code_2) / 4 + mtctr r12 + add r20, r21, r22 + addi r11, r11, copied_code_2_end - NKTop + +new_world_0x924 + lwzu r12, -0x0004(r11) + stwu r12, -0x0004(r20) + dcbst 0, r20 + sync + icbi 0, r20 + bdnz+ new_world_0x924 + sync + isync + subf r12, r21, r20 + mulli r12, r12, 0x80 + cmplw r12, r15 + bge- new_world_0x958 + mr r15, r12 + +new_world_0x958 + add r12, r13, r15 + mr r11, r20 + lis r10, 0x4e80 + ori r10, r10, 0x20 + +new_world_0x968 + lwzu r9, -0x0200(r12) + stw r10, 0x0000(r12) + cmpw r12, r13 + stwu r9, -0x0004(r11) + dcbst 0, r12 + sync + icbi 0, r12 + bne+ new_world_0x968 + sync + isync + stw r0, 0x0f38(r1) + li r17, 0x00 + li r18, 0x200 + li r19, 0x00 + li r16, -0x01 + b new_world_0x9b4 + +new_world_0x9a8 + addi r17, r17, 0x200 + cmplw r17, r15 + bge- new_world_0x9c8 + +new_world_0x9b4 + mtlr r20 + blrl + ble+ new_world_0x9a8 + addi r12, r17, -0x200 + stw r12, 0x0f38(r1) + +new_world_0x9c8 + li r12, 0x01 + sth r12, 0x0f4c(r1) + lwz r18, 0x0f38(r1) + mr r17, r18 + li r19, 0x00 + li r16, -0x01 + b new_world_0x9f0 + +new_world_0x9e4 + add r17, r17, r18 + cmplw r17, r15 + bge- new_world_0xa08 + +new_world_0x9f0 + mtlr r20 + blrl + ble+ new_world_0x9e4 + subf r17, r18, r17 + divwu r12, r17, r18 + sth r12, 0x0f4c(r1) + +new_world_0xa08 + add r12, r13, r15 + mr r11, r20 + +new_world_0xa10 + lwzu r9, -0x0004(r11) + stwu r9, -0x0200(r12) + cmpw r12, r13 + dcbst 0, r12 + sync + icbi 0, r12 + bne+ new_world_0xa10 + sync + isync + lwz r17, 0x0f38(r1) + lhz r18, 0x0f4c(r1) + divwu r18, r17, r18 + slwi r17, r17, 1 + add r12, r13, r17 + subi r11, r21, 4 + +new_world_0xa4c + subf r12, r18, r12 + li r14, 0x400 + +new_world_0xa54 + rlwinm. r14, r14, 31, 0, 28 + lwzx r9, r12, r14 + lis r10, 0x4e80 + ori r10, r10, 0x20 + stwx r10, r12, r14 + stwu r9, 0x0004(r11) + dcbst r12, r14 + sync + icbi r12, r14 + addi r14, r14, 0x04 + lwzx r9, r12, r14 + lis r10, 0x4bff + ori r10, r10, 0xfffc + stwx r10, r12, r14 + stwu r9, 0x0004(r11) + dcbst r12, r14 + sync + icbi r12, r14 + bne+ new_world_0xa54 + cmpw r12, r13 + bne+ new_world_0xa4c + sync + isync + mr r19, r18 + slwi r18, r18, 1 + li r14, 0x200 + add r19, r19, r14 + li r16, -0x01 + b new_world_0xadc + +new_world_0xac8 + li r12, 0x08 + cmplw r14, r12 + ble- new_world_0xaec + srwi r14, r14, 1 + subf r19, r14, r19 + +new_world_0xadc + mtlr r20 + blrl + ble+ new_world_0xac8 + slwi r12, r14, 1 + +new_world_0xaec + sth r12, 0x0f42(r1) + srwi r18, r18, 1 + add r12, r13, r17 + subi r11, r21, 4 + +new_world_0xafc + subf r12, r18, r12 + li r14, 0x400 + +new_world_0xb04 + rlwinm. r14, r14, 31, 0, 28 + lwzu r9, 0x0004(r11) + stwx r9, r12, r14 + addi r14, r14, 0x04 + lwzu r9, 0x0004(r11) + stwx r9, r12, r14 + bne+ new_world_0xb04 + cmpw r12, r13 + bne+ new_world_0xafc + +skip_cache_hackery_never + ; Clearly can't just fall through + b FinishInitBuiltin + + +; copied_code_1 + +; Xrefs: +; new_world + +copied_code_1 ; OUTSIDE REFERER + li r10, 0x03 + +copied_code_1_0x4 + li r12, 0x800 + mtctr r12 + add r19, r19, r13 + li r11, 0x00 + mtdec r11 + +copied_code_1_0x18 + subf r12, r17, r11 + srawi r12, r12, 31 + and r11, r11, r12 + lbzx r12, r13, r11 + add r12, r12, r12 + lbzx r12, r19, r11 + add r12, r12, r12 + add r11, r11, r18 + bdnz+ copied_code_1_0x18 + subf r19, r13, r19 + mfdec r12 + neg r12, r12 + cmplw r12, r16 + bgt- copied_code_1_0x54 + mr r16, r12 + +copied_code_1_0x54 + srwi r11, r12, 7 + subf r12, r11, r12 + cmpw r12, r16 + blelr- + addic. r10, r10, -0x01 + bgt+ copied_code_1_0x4 + cmpw r12, r16 + blr + isync + isync + isync + isync + isync + isync + isync + isync + isync + isync + isync + isync + isync + isync + isync + isync +copied_code_1_end ; OUTSIDE REFERER + + + +; copied_code_2 + +; Xrefs: +; new_world + +copied_code_2 ; OUTSIDE REFERER + li r10, 0x03 + mflr r9 + +copied_code_2_0x8 + li r12, 0x800 + mtctr r12 + add r19, r19, r13 + li r11, 0x00 + mtdec r11 + +copied_code_2_0x1c + subf r12, r17, r11 + srawi r12, r12, 31 + and r11, r11, r12 + add r12, r13, r11 + mtlr r12 + blrl + add r12, r19, r11 + mtlr r12 + blrl + add r11, r11, r18 + bdnz+ copied_code_2_0x1c + subf r19, r13, r19 + mfdec r12 + neg r12, r12 + cmplw r12, r16 + bgt- copied_code_2_0x60 + mr r16, r12 + +copied_code_2_0x60 + srwi r11, r12, 7 + subf r12, r11, r12 + cmpw r12, r16 + mtlr r9 + blelr- + addic. r10, r10, -0x01 + bgt+ copied_code_2_0x8 + cmpw r12, r16 + blr + isync + isync + isync + isync + isync + isync + isync + isync + isync + isync + isync + isync + isync + isync + isync + isync +copied_code_2_end ; OUTSIDE REFERER diff --git a/NanoKernel/NKCacheCalls.s b/NanoKernel/NKCacheCalls.s new file mode 100644 index 0000000..922feab --- /dev/null +++ b/NanoKernel/NKCacheCalls.s @@ -0,0 +1,300 @@ +kcCacheDispatch ; OUTSIDE REFERER + stw r21, 0x01ac(r6) + stw r22, 0x01b4(r6) + stw r23, 0x01bc(r6) + clrlwi r8, r3, 0x10 + cmplwi r8, 0x02 + bgt- kcCacheDispatch_0x4c + lwz r8, 0x0f68(r1) + andi. r8, r8, 0x01 + beq- kcCacheDispatch_0x178 + rlwinm. r9, r3, 0, 2, 2 + bnel- kcCacheDispatch_0x1e4 + srwi r8, r3, 30 + cmpwi r8, 0x03 + beq- kcCacheDispatch_0xd8 + clrlwi r8, r3, 0x10 + cmplwi r8, 0x01 + beq- kcCacheDispatch_0x58 + cmplwi r8, 0x02 + beq- kcCacheDispatch_0xb8 + +kcCacheDispatch_0x4c + lis r3, -0x01 + ori r3, r3, 0xfffe + b kcCacheDispatch_0x1c4 + +kcCacheDispatch_0x58 + rlwinm. r9, r3, 0, 1, 1 + bne- kcCacheDispatch_0x74 + rlwinm. r9, r3, 0, 0, 0 + bne- kcCacheDispatch_0x98 + rlwinm. r9, r3, 0, 3, 3 + bl kcCacheDispatch_0x258 + b kcCacheDispatch_0x1c4 + +kcCacheDispatch_0x74 + bl kcCacheDispatch_0x258 + rlwinm r22, r3, 0, 4, 5 + srwi r22, r22, 12 + mfspr r21, hid0 + andc r21, r21, r22 + sync + mtspr hid0, r21 + li r3, 0x00 + b kcCacheDispatch_0x1c4 + +kcCacheDispatch_0x98 + rlwinm r22, r3, 0, 4, 5 + srwi r22, r22, 12 + mfspr r21, hid0 + or r21, r21, r22 + sync + mtspr hid0, r21 + li r3, 0x00 + b kcCacheDispatch_0x1c4 + +kcCacheDispatch_0xb8 + rlwinm. r9, r3, 0, 1, 1 + bne- kcCacheDispatch_0x180 + rlwinm. r9, r3, 0, 0, 0 + bne- kcCacheDispatch_0xe8 + rlwinm. r9, r3, 0, 3, 3 + bne- kcCacheDispatch_0xe4 + rlwinm. r9, r3, 0, 2, 2 + bne- kcCacheDispatch_0x1c4 + +kcCacheDispatch_0xd8 + lis r3, -0x01 + ori r3, r3, 0xfffc + b kcCacheDispatch_0x1c4 + +kcCacheDispatch_0xe4 + bl kcCacheDispatch_0x180 + +kcCacheDispatch_0xe8 + mfspr r21, l2cr + sync + andis. r21, r21, 0x8000 + bne- kcCacheDispatch_0x1c4 + lwz r8, 0x0f54(r1) + and. r8, r8, r8 + beq- kcCacheDispatch_0x178 + mfspr r21, hid0 + rlwinm r8, r21, 0, 12, 10 + mtspr hid0, r8 + sync + addi r8, r1, -0x4d0 + lwz r8, 0x0050(r8) + and. r8, r8, r8 + beq- kcCacheDispatch_0x1c4 + sync + lis r9, 0x20 + or r8, r8, r9 + mtspr l2cr, r8 + sync + +kcCacheDispatch_0x138 + mfspr r8, l2cr + sync + andi. r9, r8, 0x01 + bne+ kcCacheDispatch_0x138 + lis r9, 0x20 + andc r8, r8, r9 + mtspr l2cr, r8 + sync + lis r9, -0x8000 + or r8, r8, r9 + mtspr l2cr, r8 + sync + mtspr hid0, r21 + sync + li r3, 0x00 + b kcCacheDispatch_0x1c4 + +kcCacheDispatch_0x178 + li r3, -0x02 + b kcCacheDispatch_0x1c4 + +kcCacheDispatch_0x180 + mfspr r22, l2cr + sync + andis. r22, r22, 0x8000 + beq- kcCacheDispatch_0x1c4 + bl kcCacheDispatch_0x258 + mfspr r22, l2cr + sync + clrlwi r22, r22, 0x01 + mtspr l2cr, r22 + sync + addi r8, r1, -0x4d0 + stw r22, 0x0050(r8) + sync + rlwinm r22, r22, 0, 7, 3 + oris r22, r22, 0x10 + mtspr l2cr, r22 + sync + +kcCacheDispatch_0x1c4 + ori r23, r23, 0xffff + oris r3, r3, 0xffff + and r3, r3, r23 + +kcCacheDispatch_0x1d0 + lwz r21, 0x01ac(r6) + lwz r22, 0x01b4(r6) + lwz r23, 0x01bc(r6) + sync + b skeleton_key + +kcCacheDispatch_0x1e4 + clrlwi r8, r3, 0x10 + cmplwi r8, 0x01 + beq- kcCacheDispatch_0x204 + cmplwi r8, 0x02 + beq- kcCacheDispatch_0x218 + lis r3, -0x01 + ori r3, r3, 0xfffb + b kcCacheDispatch_0x1d0 + +kcCacheDispatch_0x204 + mfspr r21, hid0 + rlwinm. r21, r21, 12, 4, 5 + beq- kcCacheDispatch_0x24c + oris r23, r21, 0x8000 + blr + +kcCacheDispatch_0x218 + lwz r8, 0x0f54(r1) + and. r8, r8, r8 + beq+ kcCacheDispatch_0x178 + mfspr r21, hid0 + rlwinm r21, r21, 12, 4, 5 + mfspr r22, l2cr + rlwinm r22, r22, 5, 4, 4 + andc r21, r21, r22 + mfspr r22, l2cr + andis. r22, r22, 0x8000 + beq- kcCacheDispatch_0x24c + or r23, r21, r22 + blr + +kcCacheDispatch_0x24c + lis r23, 0x4000 + ori r23, r23, 0x00 + blr + +kcCacheDispatch_0x258 ; OUTSIDE REFERER + mfctr r8 + stw r25, 0x01cc(r6) + stw r24, 0x01c4(r6) + stw r8, 0x00f4(r6) + lhz r25, 0x0f44(r1) + and. r25, r25, r25 + cntlzw r8, r25 + beq- kcCacheDispatch_0x338 + subfic r9, r8, 0x1f + lwz r8, 0x0f34(r1) + and. r8, r8, r8 + beq- kcCacheDispatch_0x338 + lwz r24, 0x0f68(r1) + mtcr r24 + bso- cr6, kcCacheDispatch_0x350 + bne- cr7, kcCacheDispatch_0x2a4 + slwi r24, r8, 1 + add r8, r8, r24 + srwi r8, r8, 1 + +kcCacheDispatch_0x2a4 + srw r8, r8, r9 + mtctr r8 + lwz r8, 0x0630(r1) + lwz r9, 0x0028(r8) + add r8, r8, r9 + +kcCacheDispatch_0x2b8 + lwzux r9, r8, r25 + bdnz+ kcCacheDispatch_0x2b8 + lwz r24, 0x0f68(r1) + andi. r24, r24, 0x01 + beq- kcCacheDispatch_0x338 + mfspr r24, l2cr + andis. r24, r24, 0x8000 + beq- kcCacheDispatch_0x338 + lhz r25, 0x0f60(r1) + and. r25, r25, r25 + cntlzw r8, r25 + beq- kcCacheDispatch_0x338 + subfic r9, r8, 0x1f + lwz r8, 0x0f54(r1) + and. r8, r8, r8 + beq- kcCacheDispatch_0x338 + srw r8, r8, r9 + mtctr r8 + mfspr r24, l2cr + oris r24, r24, 0x40 + mtspr l2cr, r24 + isync + lwz r8, 0x0630(r1) + lwz r9, 0x0028(r8) + add r8, r8, r9 + addis r8, r8, 0x19 + neg r25, r25 + +kcCacheDispatch_0x324 + lwzux r9, r8, r25 + bdnz+ kcCacheDispatch_0x324 + rlwinm r24, r24, 0, 10, 8 + mtspr l2cr, r24 + isync + +kcCacheDispatch_0x338 + lwz r8, 0x00f4(r6) + lwz r25, 0x01cc(r6) + lwz r24, 0x01c4(r6) + sync + mtctr r8 + blr + +kcCacheDispatch_0x350 + dssall + sync + mfspr r8, 1014 + oris r8, r8, 0x80 + mtspr 1014, r8 + sync + +kcCacheDispatch_0x368 + mfspr r8, 1014 + sync + andis. r8, r8, 0x80 + bne+ kcCacheDispatch_0x368 + mfspr r8, l2cr + ori r8, r8, 0x800 + mtspr l2cr, r8 + sync + +kcCacheDispatch_0x388 + mfspr r8, l2cr + sync + andi. r8, r8, 0x800 + bne+ kcCacheDispatch_0x388 + b kcCacheDispatch_0x338 + +kcCacheDispatch_0x39c ; OUTSIDE REFERER + lwz r8, 0x0f68(r1) + mtcr r8 + bnslr- cr6 + dssall + sync + mfspr r8, 1014 + oris r8, r8, 0x80 + mtspr 1014, r8 + sync + +kcCacheDispatch_0x3c0 + mfspr r8, 1014 + sync + andis. r8, r8, 0x80 + bne+ kcCacheDispatch_0x3c0 + blr diff --git a/NanoKernel/NKConsoleLog.s b/NanoKernel/NKConsoleLog.s new file mode 100644 index 0000000..bfb3da4 --- /dev/null +++ b/NanoKernel/NKConsoleLog.s @@ -0,0 +1,802 @@ +; prints + +; _log null-terminated string with a few special escapes. +; Not done figuring this out, with the serial and stuff. + +; Xrefs: +; replace_old_kernel +; new_world +; setup +; undo_failed_kernel_replacement +; AcquireLock +; spinlock_what +; major_0x02ccc +; IntMachineCheckMemRetry +; IntMachineCheck +; major_0x03ab0 +; IntThermalEvent +; kcResetSystem +; non_skeleton_reset_trap +; PagingFunc1 +; KCRegisterCpuPlugin +; KCStartCPU +; NKxprintf +; MPCall_108 +; NKSetClockStep +; NKSetClockDriftCorrection +; convert_pmdts_to_areas +; NKCreateAddressSpaceSub +; createarea +; major_0x10320 +; MPCall_95 +; ExtendPool +; major_0x12b94 +; InitTMRQs +; StartTimeslicing +; InitRDYQs +; major_0x14bcc +; panic +; major_0x18040 +; print_xpt_info +; print_sprgs +; print_sprs +; print_segment_registers +; print_gprs +; print_memory +; print_memory_logical + +prints ; OUTSIDE REFERER + mfsprg r1, 0 + stmw r24, -0x0108(r1) + mflr r24 + mfcr r25 + stw r24, -0x0110(r1) + stw r25, -0x010c(r1) + lwz r1, -0x0004(r1) + lwz r28, -0x0900(r1) + lwz r29, 0x0edc(r1) + + _Lock PSA.DbugLock, scratch1=r30, scratch2=r31 + + cmpwi cr7, r28, 0x00 + andi. r29, r29, 0x02 + beq- cr7, prints_skip_serial + crmove 30, 2 + beq- PrintS_skip_serial + mfmsr r31 + bl serial_io + bl serial_flush + +prints_skip_serial + addi r8, r8, -0x01 + +prints_next_char + bl serial_busywait + lbzu r29, 0x0001(r8) + cmpwi r29, 0x00 + beq- print_common + cmpwi r29, 10 + beq- PrintS_newline + cmpwi r29, 13 + beq- PrintS_newline + cmpwi r29, '\\' + beq- PrintS_escape_code + cmpwi r29, '^' + bne- PrintS_normal_char + +prints_escape_code + lbzu r29, 0x0001(r8) + cmpwi r29, 'n' + beq- PrintS_newline + cmpwi r29, 'r' + beq- PrintS_newline + cmpwi r29, 'b' + bne- PrintS_literal_backslash_or_caret + li r29, 0x07 + b PrintS_normal_char + +prints_literal_backslash_or_caret + lbzu r29, -0x0001(r8) + addi r8, r8, 0x01 + +prints_normal_char + mr r24, r29 + +; r1 = kdp + bl ScreenConsole_putchar + beq- cr7, prints_0xe4 + ori r30, r31, 0x10 + mtmsr r30 + isync + stb r24, 0x0006(r28) + eieio + mtmsr r31 + isync + +prints_0xe4 + b PrintS_next_char + +prints_newline + li r29, 0x0d + +; r1 = kdp + bl ScreenConsole_putchar + li r29, 0x0a + +; r1 = kdp + bl ScreenConsole_putchar + +; r1 = kdp + bl ScreenConsole_redraw + beq- cr7, prints_0x13c + ori r30, r31, 0x10 + mtmsr r30 + isync + li r29, 0x0d + stb r29, 0x0006(r28) + eieio + +prints_0x118 + lbz r29, 0x0002(r28) + eieio + andi. r29, r29, 0x04 + beq+ PrintS_0x118 + li r29, 0x0a + stb r29, 0x0006(r28) + eieio + mtmsr r31 + isync + +prints_0x13c + b PrintS_next_char + + + +; print_common + +; Xrefs: +; PrintS +; Printd +; print_digity_common +; getchar +; Printc + +print_common ; OUTSIDE REFERER + beq- cr7, print_common_0x8c + mtmsr r31 + isync + lwz r29, -0x0438(r1) + srwi r29, r29, 8 + mfspr r30, dec + subf r29, r29, r30 + ori r30, r31, 0x10 + mtmsr r30 + isync + +print_common_0x28 + mfspr r30, dec + subf. r30, r29, r30 + ble- print_common_0x50 + li r30, 0x01 + stb r30, 0x0002(r28) + eieio + lbz r30, 0x0002(r28) + eieio + andi. r30, r30, 0x01 + beq+ print_common_0x28 + +print_common_0x50 + sync + mtmsr r31 + isync + mfspr r30, pvr + rlwinm. r30, r30, 0, 0, 14 + li r31, 0x00 + beq- print_common_0x78 + mtspr dbat3u, r31 + mtspr dbat3l, r31 + b print_common_0x80 + +print_common_0x78 + mtspr ibat3l, r31 + mtspr ibat3u, r31 + +print_common_0x80 + isync + mtspr srr0, r26 + mtspr srr1, r27 + +print_common_0x8c + sync + lwz r30, -0x0af0(r1) + cmpwi cr1, r30, 0x00 + li r30, 0x00 + bne+ cr1, print_common_0xa8 + mflr r30 + bl panic + +print_common_0xa8 + stw r30, -0x0af0(r1) + + + +; print_return + +; Restores registers from EWA and returns. + +; Xrefs: +; print_common +; getchar + +print_return ; OUTSIDE REFERER + mfsprg r1, 0 + lwz r24, -0x0110(r1) + lwz r25, -0x010c(r1) + mtlr r24 + mtcr r25 + lmw r24, -0x0108(r1) + lwz r1, -0x0004(r1) + blr + + + +; printd + +; _log decimal + +; Xrefs: +; setup +; NKPrintDecimal +; MPCall_108 +; NKSetClockStep +; NKSetClockDriftCorrection +; ExtendPool +; major_0x12b94 + +printd ; OUTSIDE REFERER + mfsprg r1, 0 + stmw r24, -0x0108(r1) + mflr r24 + mfcr r25 + stw r24, -0x0110(r1) + stw r25, -0x010c(r1) + lwz r1, -0x0004(r1) + lwz r28, -0x0900(r1) + lwz r29, 0x0edc(r1) + + _Lock PSA.DbugLock, scratch1=r30, scratch2=r31 + + cmpwi cr7, r28, 0x00 + andi. r29, r29, 0x02 + beq- cr7, printd_0x58 + crmove 30, 2 + beq- Printd_0x58 + bl serial_io + bl serial_flush + +printd_0x58 + cmpwi r8, 0x00 + li r25, 0x2d + blt- Printd_0x9c + +printd_0x64 + mr. r24, r8 + li r25, 0x30 + beq- Printd_0x9c + lis r24, 0x3b9a + ori r24, r24, 0xca00 + +printd_0x78 + divw. r25, r8, r24 + bne- Printd_0x8c + li r25, 0x0a + divw r24, r24, r25 + b Printd_0x78 + +printd_0x8c + divw r29, r8, r24 + addi r25, r29, 0x30 + mullw r29, r29, r24 + subf r8, r29, r8 + +printd_0x9c + bl serial_busywait + mr r29, r25 + +; r1 = kdp + bl ScreenConsole_putchar + beq- cr7, printd_0xc8 + ori r30, r31, 0x10 + mtmsr r30 + isync + stb r25, 0x0006(r28) + eieio + mtmsr r31 + isync + +printd_0xc8 + cmpwi r8, 0x00 + bge- Printd_0xd8 + neg r8, r8 + b Printd_0x64 + +printd_0xd8 + li r25, 0x0a + divw. r24, r24, r25 + bne+ Printd_0x8c + li r29, 0x20 + +; r1 = kdp + bl ScreenConsole_putchar + beq- cr7, printd_0x120 + ori r30, r31, 0x10 + mtmsr r30 + isync + +printd_0xfc + lbz r30, 0x0002(r28) + eieio + andi. r30, r30, 0x04 + beq+ Printd_0xfc + li r29, 0x20 + stb r29, 0x0006(r28) + eieio + mtmsr r31 + isync + +printd_0x120 + b print_common + + + +; printw + +; _log word (hex) then a space + +; Xrefs: +; replace_old_kernel +; setup +; AcquireLock +; spinlock_what +; major_0x02ccc +; IntMachineCheckMemRetry +; IntMachineCheck +; major_0x03ab0 +; kcResetSystem +; PagingFunc1 +; NKPrintHex +; NKCreateAddressSpaceSub +; createarea +; ExtendPool +; major_0x12b94 +; InitRDYQs +; major_0x14bcc +; panic +; print_xpt_info +; print_sprgs +; print_sprs +; print_segment_registers +; print_gprs +; print_memory +; print_memory_logical + +printw ; OUTSIDE REFERER + mfsprg r1, 0 + stmw r24, -0x0108(r1) + mflr r24 + mfcr r25 + stw r24, -0x0110(r1) + stw r25, -0x010c(r1) + li r24, 0x08 + crset cr6_eq + b print_digity_common + + + +; printh + +; _log halfword (hex) then a space + +; Xrefs: +; replace_old_kernel +; new_world +; NKPrintHex +; major_0x14bcc +; panic + +printh ; OUTSIDE REFERER + mfsprg r1, 0 + stmw r24, -0x0108(r1) + mflr r24 + mfcr r25 + stw r24, -0x0110(r1) + stw r25, -0x010c(r1) + li r24, 0x04 + rotlwi r8, r8, 0x10 + crset cr6_eq + b print_digity_common + + + +; printb + +; _log byte (hex) then a space + +; Xrefs: +; setup +; NKPrintHex + +printb ; OUTSIDE REFERER + mfsprg r1, 0 + stmw r24, -0x0108(r1) + mflr r24 + mfcr r25 + stw r24, -0x0110(r1) + stw r25, -0x010c(r1) + li r24, 0x02 + rotlwi r8, r8, 0x18 + crset cr6_eq + b print_digity_common + + + +; print_unknown + +; Xrefs: +; print_memory_logical + +print_unknown ; OUTSIDE REFERER + mfsprg r1, 0 + stmw r24, -0x0108(r1) + mflr r24 + mfcr r25 + stw r24, -0x0110(r1) + stw r25, -0x010c(r1) + li r24, 0x02 + rotlwi r8, r8, 0x18 + crclr cr6_eq + b print_digity_common + + + +; print_digity_common + +; Xrefs: +; Printw +; Printh +; Printb +; print_unknown + +print_digity_common ; OUTSIDE REFERER + lwz r1, -0x0004(r1) + lwz r28, -0x0900(r1) + lwz r29, 0x0edc(r1) + + _Lock PSA.DbugLock, scratch1=r30, scratch2=r31 + + cmpwi cr7, r28, 0x00 + andi. r29, r29, 0x02 + beq- cr7, print_digity_common_0x40 + crmove 30, 2 + beq- print_digity_common_0x40 + bl serial_io + bl serial_flush + +print_digity_common_0x40 + bl serial_busywait + li r25, 0x30 + rlwimi r25, r8, 4, 28, 31 + rotlwi r8, r8, 0x04 + cmpwi r25, 0x39 + ble- print_digity_common_0x5c + addi r25, r25, 0x27 + +print_digity_common_0x5c + mr r29, r25 + +; r1 = kdp + bl ScreenConsole_putchar + beq- cr7, print_digity_common_0x84 + ori r30, r31, 0x10 + mtmsr r30 + isync + stb r25, 0x0006(r28) + eieio + mtmsr r31 + isync + +print_digity_common_0x84 + addi r24, r24, -0x01 + mr. r24, r24 + bne+ print_digity_common_0x40 + bne- cr6, print_digity_common_0xd0 + li r29, 0x20 + +; r1 = kdp + bl ScreenConsole_putchar + beq- cr7, print_digity_common_0xd0 + ori r30, r31, 0x10 + mtmsr r30 + isync + +print_digity_common_0xac + lbz r30, 0x0002(r28) + eieio + andi. r30, r30, 0x04 + beq+ print_digity_common_0xac + li r29, 0x20 + stb r29, 0x0006(r28) + eieio + mtmsr r31 + isync + +print_digity_common_0xd0 + b print_common + + + +; getchar + +; Xrefs: +; panic +; print_memory +; print_memory_logical + +getchar ; OUTSIDE REFERER + mfsprg r1, 0 + stmw r24, -0x0108(r1) + mflr r24 + mfcr r25 + stw r24, -0x0110(r1) + stw r25, -0x010c(r1) + + lwz r1, EWA.PA_KDP(r1) + lwz r28, -0x0900(r1) + cmpwi cr7, r28, 0x00 + li r8, -0x01 + beq+ cr7, print_return + + _Lock PSA.DbugLock, scratch1=r30, scratch2=r31 + + bl serial_io + ori r30, r31, 0x10 + mtmsr r30 + isync + lbz r30, 0x0002(r28) + eieio + andi. r30, r30, 0x01 + beq+ print_common + lbz r8, 0x0006(r28) + b print_common + + + +; printc + +; _log char + +; Xrefs: +; spinlock_what +; major_0x12b94 +; panic +; print_memory +; print_memory_logical + +printc ; OUTSIDE REFERER + mfsprg r1, 0 + stmw r24, -0x0108(r1) + mflr r24 + mfcr r25 + stw r24, -0x0110(r1) + stw r25, -0x010c(r1) + lwz r1, -0x0004(r1) + lwz r28, -0x0900(r1) + lwz r29, 0x0edc(r1) + + _Lock PSA.DbugLock, scratch1=r30, scratch2=r31 + + cmpwi cr7, r28, 0x00 + andi. r29, r29, 0x02 + beq- cr7, printc_0x58 + crmove 30, 2 + beq- Printc_0x58 + bl serial_io + bl serial_flush + +printc_0x58 + mr r29, r8 + +; r1 = kdp + bl ScreenConsole_putchar + beq- cr7, printc_0x90 + ori r30, r31, 0x10 + mtmsr r30 + isync + +printc_0x70 + lbz r30, 0x0002(r28) + eieio + andi. r30, r30, 0x04 + beq+ Printc_0x70 + stb r8, 0x0006(r28) + eieio + mtmsr r31 + isync + +printc_0x90 + b print_common + + + +; serial_flush + +; This and the following func are a bit speculative, but +; whatever. + +; Whoa. Turns on data but not code paging. Crikey. + +; Xrefs: +; PrintS +; Printd +; print_digity_common +; Printc + +serial_flush ; OUTSIDE REFERER + ori r30, r31, MSR_DR + mtmsr r30 + isync + lbz r29, 0x0002(r28) + li r29, 0x09 + stb r29, 0x0002(r28) + eieio + li r29, 0x80 + stb r29, 0x0002(r28) + eieio + lbz r29, 0x0002(r28) + li r29, 0x04 + stb r29, 0x0002(r28) + eieio + li r29, 0x48 + stb r29, 0x0002(r28) + eieio + lbz r29, 0x0002(r28) + li r29, 0x03 + stb r29, 0x0002(r28) + eieio + li r29, 0xc0 + stb r29, 0x0002(r28) + eieio + lbz r29, 0x0002(r28) + li r29, 0x05 + stb r29, 0x0002(r28) + eieio + li r29, 0x60 + stb r29, 0x0002(r28) + eieio + lbz r29, 0x0002(r28) + li r29, 0x09 + stb r29, 0x0002(r28) + eieio + li r29, 0x00 + stb r29, 0x0002(r28) + eieio + lbz r29, 0x0002(r28) + li r29, 0x0a + stb r29, 0x0002(r28) + eieio + li r29, 0x00 + stb r29, 0x0002(r28) + eieio + lbz r29, 0x0002(r28) + li r29, 0x0b + stb r29, 0x0002(r28) + eieio + li r29, 0x50 + stb r29, 0x0002(r28) + eieio + lbz r29, 0x0002(r28) + li r29, 0x0c + stb r29, 0x0002(r28) + eieio + li r29, 0x00 + stb r29, 0x0002(r28) + eieio + lbz r29, 0x0002(r28) + li r29, 0x0d + stb r29, 0x0002(r28) + eieio + li r29, 0x00 + stb r29, 0x0002(r28) + eieio + lbz r29, 0x0002(r28) + li r29, 0x0e + stb r29, 0x0002(r28) + eieio + li r29, 0x01 + stb r29, 0x0002(r28) + eieio + lbz r29, 0x0002(r28) + li r29, 0x03 + stb r29, 0x0002(r28) + eieio + li r29, 0xc1 + stb r29, 0x0002(r28) + eieio + lbz r29, 0x0002(r28) + li r29, 0x05 + stb r29, 0x0002(r28) + eieio + li r29, 0xea + stb r29, 0x0002(r28) + eieio + mtmsr r31 + isync + blr + + + +; serial_io + +; See disclaimer above. + +; Xrefs: +; PrintS +; Printd +; print_digity_common +; getchar +; Printc + +serial_io ; OUTSIDE REFERER + mfspr r26, srr0 + mfspr r27, srr1 + isync + mfspr r30, pvr + rlwinm. r30, r30, 0, 0, 14 + rlwinm r29, r28, 0, 0, 14 + beq- serial_io_0x38 + li r30, 0x03 + or r30, r30, r29 + li r31, 0x3a + or r31, r31, r29 + mtspr dbat3l, r31 + mtspr dbat3u, r30 + b serial_io_0x50 + +serial_io_0x38 + li r30, 0x32 + or r30, r30, r29 + li r31, 0x40 + or r31, r31, r29 + mtspr ibat3u, r30 + mtspr ibat3l, r31 + +serial_io_0x50 + isync + mfmsr r31 + blr + + + +; serial_busywait + +; See disclaimer above. + +; Xrefs: +; PrintS +; Printd +; print_digity_common + +serial_busywait ; OUTSIDE + beqlr- cr7 + ori r30, r31, 0x10 + mtmsr r30 + isync + +serial_busywait_0x10 + lbz r30, 0x0002(r28) + eieio + andi. r30, r30, 0x04 + beq+ serial_busywait_0x10 + mtmsr r31 + isync + blr diff --git a/NanoKernel/NKEquates.s b/NanoKernel/NKEquates.s new file mode 100644 index 0000000..09145e3 --- /dev/null +++ b/NanoKernel/NKEquates.s @@ -0,0 +1,50 @@ +;_______________________________________________________________________ +; Equates for the whole NanoKernel +;_______________________________________________________________________ + + +kNanoKernelVersion equ $0228 + + +; PowerPC Machine Status Register (MSR) bits +; (borrowing the _bitEqu macro from NKInfoRecordsPriv.s) + + _bitEqu MSR_POW, 13 + _bitEqu MSR_ILE, 15 + _bitEqu MSR_EE, 16 + _bitEqu MSR_PR, 17 + _bitEqu MSR_FP, 18 + _bitEqu MSR_ME, 19 + _bitEqu MSR_FE0, 20 + _bitEqu MSR_SE, 21 + _bitEqu MSR_BE, 22 + _bitEqu MSR_FE1, 23 + _bitEqu MSR_IP, 25 + _bitEqu MSR_IR, 26 + _bitEqu MSR_DR, 27 + _bitEqu MSR_RI, 30 + _bitEqu MSR_LE, 31 + + +; Special Purpose Registers (SPRs) not understood by MPW + +l2cr equ 1017 + + +; Alignment for NanoKernel interrupt routines (mostly Interrupts.s) + +kIntAlign equ 5 + + + +; Junk + + +; IRP is 10 pages below KDP (measured start to start) +IRPOffset equ (-10) * 4096 +kKDPfromIRP equ 10 * 4096 + + + + +noErr equ 0 diff --git a/NanoKernel/NKIndex.s b/NanoKernel/NKIndex.s new file mode 100644 index 0000000..cfd4733 --- /dev/null +++ b/NanoKernel/NKIndex.s @@ -0,0 +1,298 @@ +;_______________________________________________________________________ +; NanoKernel Opaque ID Index +; +; Creates opaque structure IDs and stores them in the Pool. An opaque +; ID maps back to the (type, pointer) pair passed to MakeID. +; +; This abstraction is very important to the Multiprocessing Services. +; +; Rene on comp.sys.mac.programmer.help, 26 Oct 01: +; +; Total opaque IDs - The number of IDs currently in use. All MP +; objects: address spaces, areas, processors, memory coherence groups, +; queues, semaphores, critical regions, event groups, timers, +; notifications, etc. are assigned an ID when created, and they are +; accessed by way of this ID. The kernel presently handles 65,000 +; simultaneous IDs with a bit pattern reuse probability of 1 in 4 +; billion. +;_______________________________________________________________________ + +Local_Panic set * + b panic + + + +; ARG KDP *r1 + +InitIDIndex + mflr r23 + + li r8, Index.Size + bl PoolAlloc + + mr. r22, r8 + stw r8, PSA.IndexPtr(r1) + beq+ Local_Panic + + li r9, 0 + stw r9, KDP.NanoKernelInfo + NKNanoKernelInfo.IDCtr(r1) + + sth r9, Index.HalfOne(r22) + sth r9, Index.HalfTwo(r22) + + lisori r9, Index.kSignature + stw r9, Index.Signature(r22) + + + ; Then what the hell is this? + li r8, 0xfd8 + bl PoolAlloc + + cmpwi r8, 0 + stw r8, Index.IDsPtr(r22) + beq+ Local_Panic + + mtlr r23 + + li r9, 0x00 + sth r9, 0x0000(r8) + li r9, 0x1fa + sth r9, 0x0002(r8) + lisori r9, 'IDs ' + stw r9, 0x0004(r8) + blr + + + +; ARG void *r8, IDClass r9 +; RET ID r8 + +MakeID + lwz r18, -0x0a98(r1) + lhz r19, 0x0000(r18) + mr r21, r19 + +@_c + lwz r18, -0x0a98(r1) + rlwinm r20, r19, 25, 23, 29 + addi r20, r20, 0x08 + clrlwi. r19, r19, 0x17 + lwzx r18, r18, r20 + slwi r22, r19, 3 + addi r20, r18, 0x08 + cmpwi r18, 0x00 + add r22, r22, r20 + bne- @_48 + li r19, 0x00 + b @_c + +@_3c + add r20, r20, r19 + cmpw r20, r21 + beq- @_70 + +@_48 + lbz r23, 0x0000(r22) + cmpwi r23, 0x00 + beq- @_f0 + addi r19, r19, 0x01 + cmpwi cr1, r19, 0x1fa + addi r22, r22, 0x08 + lhz r20, 0x0000(r18) + blt+ cr1, @_3c + addi r19, r20, 0x200 + b @_c + +@_70 + lwz r18, -0x0a98(r1) + mr r21, r8 + lhz r19, 0x0002(r18) + mr r22, r9 + addi r19, r19, 0x200 + rlwinm. r20, r19, 25, 23, 29 + li r8, 0x00 + beqlr- + mflr r23 + li r8, 0xfd8 + +; r1 = kdp +; r8 = size + bl PoolAlloc +; r8 = ptr + + mr. r18, r8 + mtlr r23 + li r8, 0x00 + beqlr- + lwz r17, -0x0a98(r1) + lhz r19, 0x0002(r17) + addi r19, r19, 0x200 + rlwinm r20, r19, 25, 23, 29 + addi r20, r20, 0x08 + sth r19, 0x0002(r17) + stwx r18, r20, r17 + sth r19, 0x0000(r18) + li r9, 0x1fa + sth r9, 0x0002(r18) + lis r9, 0x4944 + ori r9, r9, 0x7320 + stw r9, 0x0004(r18) + li r19, 0x00 + mr r8, r21 + mr r9, r22 + addi r22, r18, 0x08 + +@_f0 + stw r8, 0x0004(r22) + stb r9, 0x0000(r22) + lwz r9, KDP.NanoKernelInfo + NKNanoKernelInfo.IDCtr(r1) + addi r9, r9, 0x01 + stw r9, KDP.NanoKernelInfo + NKNanoKernelInfo.IDCtr(r1) + lhz r20, 0x0000(r18) + lhz r8, 0x0002(r22) + lwz r21, -0x0a98(r1) + add r19, r19, r20 + addi r8, r8, 0x01 + lhz r20, 0x0002(r18) + sth r8, 0x0002(r22) + addi r20, r20, -0x01 + rlwimi. r8, r19, 16, 0, 15 + sth r20, 0x0002(r18) + sth r19, 0x0000(r21) + bnelr+ + lhz r8, 0x0002(r22) + addi r8, r8, 0x01 + sth r8, 0x0002(r22) + rlwimi r8, r19, 16, 0, 15 + blr + + + +; ARG ID r8 + + align 5 + +DeleteID + rlwinm r20, r8, 9, 23, 29 + lwz r18, -0x0a98(r1) + addi r20, r20, 0x08 + rlwinm. r19, r8, 16, 23, 31 + lwzx r18, r18, r20 + cmplwi cr1, r19, 0x1fa + cmpwi r18, 0x00 + addi r20, r18, 0x08 + slwi r22, r19, 3 + add r22, r22, r20 + clrlwi r20, r8, 0x10 + li r8, 0x00 + bgelr- cr1 + beqlr- + lbz r19, 0x0000(r22) + lhz r23, 0x0002(r22) + cmpwi r19, 0x00 + cmpw cr1, r23, r20 + beqlr- + bnelr- cr1 + lwz r9, KDP.NanoKernelInfo + NKNanoKernelInfo.IDCtr(r1) + addi r9, r9, -0x01 + stw r9, KDP.NanoKernelInfo + NKNanoKernelInfo.IDCtr(r1) + lhz r20, 0x0002(r18) + stb r8, 0x0000(r22) + addi r20, r20, 0x01 + li r8, 0x01 + sth r20, 0x0002(r18) + blr + + + +; ARG ID r8 +; RET Ptr r8, IDClass r9 + + align 5 + +LookupID + rlwinm r20, r8, 9, 23, 29 + lwz r18, -0x0a98(r1) + addi r20, r20, 0x08 + rlwinm. r19, r8, 16, 23, 31 + lwzx r18, r18, r20 + cmplwi cr1, r19, 0x1fa + cmpwi r18, 0x00 + addi r20, r18, 0x08 + slwi r22, r19, 3 + add r22, r22, r20 + clrlwi r20, r8, 0x10 + li r8, 0x00 + li r9, 0x00 + bgelr- cr1 + beqlr- + lbz r19, 0x0000(r22) + lhz r23, 0x0002(r22) + cmpwi r19, 0x00 + cmpw cr1, r23, r20 + beqlr- + bnelr- cr1 + lwz r8, 0x0004(r22) + mr r9, r19 + blr + + + +; ARG ID r8, IDClass r9 +; RET ID r8 + + align 5 + +GetNextIDOfClass + rlwinm r20, r8, 9, 23, 29 + lwz r18, -0x0a98(r1) + addi r20, r20, 0x08 + rlwinm. r19, r8, 16, 23, 31 + lwzx r18, r18, r20 + cmplwi cr1, r19, 0x1fa + cmpwi r18, 0x00 + cmpwi cr2, r8, 0x00 + addi r20, r18, 0x08 + slwi r22, r19, 3 + li r8, 0x00 + bgelr- cr1 + beqlr- + add r22, r22, r20 + bne- cr2, @_48 + +@_3c + lbz r23, 0x0000(r22) + cmpwi r23, 0x00 + bne- @_8c + +@_48 + addi r19, r19, 0x01 + cmpwi r19, 0x1fa + addi r22, r22, 0x08 + blt+ @_3c + lhz r20, 0x0000(r18) + addi r20, r20, 0x200 + rlwinm. r20, r20, 25, 23, 29 + lwz r18, -0x0a98(r1) + beqlr- + addi r20, r20, 0x08 + li r19, 0x00 + lwzx r18, r18, r20 + cmpwi r18, 0x00 + addi r22, r18, 0x08 + bne+ @_3c + li r8, 0x00 + blr + +@_8c + cmpwi r9, 0x00 + cmpw cr1, r9, r23 + beq- @_9c + bne+ cr1, @_48 + +@_9c + lhz r20, 0x0000(r18) + lhz r8, 0x0002(r22) + add r19, r19, r20 + rlwimi r8, r19, 16, 0, 15 + blr diff --git a/NanoKernel/NKInit.s b/NanoKernel/NKInit.s new file mode 100644 index 0000000..1b54609 --- /dev/null +++ b/NanoKernel/NKInit.s @@ -0,0 +1,2134 @@ +;_______________________________________________________________________ +; START OF NANOKERNEL +; +; Init.s is the first code file included by NanoKernel.s. It contains: +; the NanoKernel header (both declarative and executable) +; +; The NanoKernel header follows: +;_______________________________________________________________________ + + + + +; This is the entry point from the Trampoline (our Open Firmware-savvy +; bootloader for NewWorld Macs, which is part of the Mac OS ROM file). +; +; When we receive control: +; r3 = ConfigInfo +; r4 = ProcessorInfo +; r5 = SystemInfo +; r6 = DiagInfo +; r7 = RTAS_flag ('RTAS' or 0) +; r8 = RTAS_proc +; r9 = HWInfo +; (and also, we can be sure that we are executing from the +; NewWorld ROM image that the Trampoline loaded into RAM) +; +; First we need to avoid executing the data that follows: + + b EndOfNanoKernelHeader + + + +; On OldWorld Macs, the 68k code in the 'boot' 3 resource +; (of the System or enabler file) loads the NanoKernel +; from the 'krnl' 0 resource (of the System file), and +; uses it to replace the ROM kernel. +; +; This code probably uses the following header: + + dc.w kNanoKernelVersion + dc.w 12 + dc.w 0x400 + dc.w 0 +EndOfNanoKernelHeader + + + +; Do some sanity checking after receiving control from the Trampoline. + + ; cr5_eq is cleared for the builtin init process + + crclr cr5_eq + + + ; If data paging is off, jump straight to the builtin init code + + mfmsr r0 + rlwinm. r0, r0, 0, MSR_DRbit, MSR_DRbit + beql- InitBuiltin + + + ; But if data paging is on, do some very strange things... + + ; Does LR contain a return address, or my address, or...? + mflr r9 + subi r9, r9, 28 + + ; Prepare to jump to one of the filthy branch instructions + ; that Trampoline stuffs into ConfigInfo + addi r12, r3, 64 + + ; Unset MSR_POW, MSR_ILE, MSR_EE, MSR_IR and MSR_DR + mfmsr r11 + li r10, -0x7fd0 + andc r11, r11, r10 + + ; Jump and set MSR with an RFI. + mtspr srr0, r12 + mtspr srr1, r11 + rfi + + + +; This (offset 0x40) is the entry point from 'boot' 3 on OldWorld. +; +; The offset *might* be encoded in the header above! +; +; When we receive control: +; sprg0 = old KDP/EWA/r1 ptr +; r3 = PA_NanoKernelCode +; r4 = physical base of our global area +; r5 = NoIdeaR23 +; r6 = PA_EDP or zero? +; r7 = ROMHeader.ROMRelease (e.g. 0x10B5 is 1.0ß5) +; +; For clarity, the NanoKernel-replacement code is included from +; another file. It copies the old kernel structures to a new area +; and adopts them as our own, with some modifications. +; +; Jumps to InitHighLevel (below) when finished. + + include 'NKReplacementInit.s' + + + +; Function that fills a new InfoRecord Page (IRP) with the +; bus error-eliciting value, 0x68f1. +; (called by both builtin and replacement code paths) + +; CLOB r10, r12 + +InitIRP + lwz r12, EWA.PA_IRP(r1) + +@wipe_loop + lisori r10, 0x68f168f1 + stw r10, 0(r12) + stw r10, 4(r12) + addi r12, r12, 8 + andi. r10, r12, 0xfff + bne+ @wipe_loop + blr + + + +; This is the code that does the bulk of the builtin-specific init. +; +; If the Trampoline has not passed in a valid HWInfo struct then +; this code will depend on ProcessorInfoTable.s. In that case it +; will jump to ProcessorInfoTable.s:OverrideProcessorInfo, which +; will fall though to FinishInitBuiltin. +; +; But normally, this code will jump straight to FinishInitBuiltin. + + include 'NKBuiltinInit.s' + + + +; Table used by the common init code (below) to fill some KDP flags +; indicating processor capabilities (e.g. presence of L2CR register) +; +; No code here. + + include 'NKProcFlagsTbl.s' + + + +; Table used by the builtin init code (above) to populate some of +; the ProcessorInfo struct when information from the Trampoline +; is lacking. +; +; Includes OverrideProcessorInfo code for use by InitBuiltin.s. +; This code falls through to FinishInitBuiltin below. + + include 'NKProcInfoTbl.s' + + + +; Tidy up the builtin init process before joining the common +; init code path. +; +; This code might be accessed by fall-through from +; ProcessorInfoTable.s:OverrideProcessorInfo, or by branch +; from InitBuiltin.s + +FinishInitBuiltin + + ; Set ProcessorInfo version in case ProcessorInfo had to be loaded + ; from the table above. + + li r8, 0x0112 + sth r8, KDP.InfoRecord + InfoRecord.NKProcessorInfoVer(r1) + + + ; Copy some choice values out of KDP's copy of NKProcessorInfo + + lwz r9, KDP.ProcessorInfo + NKProcessorInfo.DecClockRateHz(r1) + stw r9, KDP.ProcessorInfo + NKProcessorInfo.DecClockRateHzCopy(r1) + + lwz r9, KDP.ProcessorInfo + NKProcessorInfo.BusClockRateHz(r1) + stw r9, KDP.ProcessorInfo + NKProcessorInfo.BusClockRateHzCopy(r1) + + lwz r9, KDP.ProcessorInfo + NKProcessorInfo.CpuClockRateHz(r1) + stw r9, KDP.ProcessorInfo + NKProcessorInfo.CpuClockRateHzCopy(r1) + + li r9, 0 + sth r9, KDP.ProcessorInfo + NKProcessorInfo.SetToZero(r1) + + lwz r8, KDP.ProcessorInfo + NKProcessorInfo.DecClockRateHz(r1) + stw r8, PSA.DecClockRateHzCopy(r1) + + + ; Test AltiVec and MQ registers + + ; Prepare a simple vector table to ignore illegal + ; instructions (like lvewx on a G3 ;) + lwz r9, KDP.PA_NanoKernelCode(r1) + + llabel r8, IgnoreSoftwareInt + add r8, r8, r9 + stw r8, KDP.YellowVecBase + VecTable.ProgramIntVector(r1) + + llabel r8, HandlePerfMonitorInt + add r8, r8, r9 + stw r8, KDP.YellowVecBase + VecTable.PerfMonitorVector(r1) + + addi r8, r1, KDP.YellowVecBase + mtsprg 3, r8 + + + ; Test MQ and save feature field + lis r8, 1 << (15 - PSA.MQFeatureBit) + mtspr mq, r8 + li r8, 0 + mfspr r8, mq + stw r8, PSA.EmpiricalCpuFeatures(r1) + + ; Add AV and save that in scratch field + oris r9, r8, 1 << (15 - PSA.AVFeatureBit) + stw r9, EWA.r0(r1) + + ; Load from scratch field into a vector register + addi r9, r1, 0 + lvewx v0, 0, r9 + + ; Save MQ into the scratch register in case vector save fails + stw r8, EWA.r0(r1) + + ; Try save vector register (with AV flag) to scratch field + stvewx v0, 0, r9 + + ; Scratch field now contains AltiVec and MQ flags. + ; Copy it to EmpiricalCpuFeatures + lwz r8, EWA.r0(r1) + stw r8, PSA.EmpiricalCpuFeatures(r1) + + ; AllCpuFeatures = EmpiricalCpuFeatures | 0x00a00000 + oris r7, r8, 0xa0 + stw r7, EWA.Flags(r1) + + + ; Emulator data and code pointers useful for the common code path? + + lwz r6, KDP.PA_ECB(r1) + lwz r10, KDP.LA_EmulatorKernelTrapTable(r1) + + + ; Create MSR (machine status register) values for use by the common code path + + mfmsr r14 + + ; Zero out a reserved bit. Considering next insn, should have no effect + rlwinm r14, r14, 0, 7, 5 + + ; Test for and keep MSR_IP (IVT location) flag + ; (presumably set by Trampoline) + andi. r14, r14, MSR_IP + + ; "KernelModeMSR" -- Seems not to get used? + ori r15, r14, MSR_ME + MSR_DR + MSR_RI + + ; "MSR" + ori r11, r14, MSR_EE + MSR_PR + MSR_ME + MSR_IR + MSR_DR + MSR_RI + stw r11, PSA.UserModeMSR(r1) + + + ; Zero out a bunch of registers. + + li r13, 0 + li r12, 0 + li r0, 0 + li r2, 0 + li r3, 0 + li r4, 0 + + + +; The builtin kernel can be partly reinited by a 68k RESET trap. +; Rene says this is for address space setup. + +ResetBuiltinKernel + + crclr cr5_eq + + + +; The common code path! InitIRP has been called but IRP is +; otherwise untouched (InfoRecord still in KDP). +; +; We get here by a jump from InitReplacement.s +; or by fallthough from FinishInitBuiltin above. +; +; When we get here: +; cr5_eq = is_replacement_kernel +; cr0 will be set if IVT is in high meg (MSR.IP) +; r1 = KDP +; r2 = 0 +; r3 = 0 +; r4 = 0 +; r5 = SystemInfo +; r6 = PA_ECB +; r7 = AllCpuFeatures +; r8 = EmpiricalCpuFeatures +; r9 = even more altivec crud +; r10 = LA_EmulatorKernelTrapTable +; r11 = MSR +; r12 = 0 +; r13 = 0 +; r15 = KernelModeMSR + +InitHighLevel + + +; The XER contains carries, overflows and string lengths. +; Apple seems to use it for all sorts of crap. + + mfxer r17 + stw r17, ContextBlock.XER(r6) + + + +; Boring intro from the high-level init code + + _log 'Kernel code base at 0x' + + lwz r8, KDP.PA_NanoKernelCode(r1) + mr r8, r8 + bl Printw + + _log ' Physical RAM size 0x' + + lwz r8, EWA.PA_IRP(r1) + lwz r8, IRP.SystemInfo + NKSystemInfo.PhysicalMemorySize(r8) + mr r8, r8 + bl Printw + + _log 'bytes^n' + + + +; Copy InfoRecord from KDP to IRP. +; (Does this become the authoritative version?) + + lisori r22, InfoRecord.Size + lwz r9, EWA.PA_IRP(r1) + addi r8, r1, KDP.InfoRecord + addi r9, r9, IRP.InfoRecord + +@loop + subic. r22, r22, 4 + lwzx r0, r22, r8 + stwx r0, r22, r9 + bgt+ @loop + + + +; Some useful values for filling tables + + lwz r26, KDP.PA_ConfigInfo(r1) + lwz r25, KDP.PA_NanoKernelCode(r1) + lwz r18, KDP.PA_PageMapStart(r1) + + + +; A quick reminder about wordfill: +; ARG void *r3 dest, long r22 len, long r23 fill + + + +; Fill with Panics: Yellow, Orange, Red (KDP) +; Violet, Blue (PSA) + + llabel r23, panic + add r23, r23, r25 + + addi r8, r1, KDP.YellowVecBase + li r22, VecTable.Size + bl wordfill + + addi r8, r1, KDP.OrangeVecBase + li r22, VecTable.Size + bl wordfill + + addi r8, r1, KDP.RedVecBase + li r22, VecTable.Size + bl wordfill + + addi r8, r1, PSA.VioletVecBase + li r22, VecTable.Size + bl wordfill + + addi r8, r1, PSA.BlueVecBase + li r22, VecTable.Size + bl wordfill + + + +; Fill Green (PSA) with IgnoreSoftwareInt + + llabel r23, IgnoreSoftwareInt + add r23, r23, r25 + + addi r8, r1, PSA.GreenVecBase + li r22, VecTable.Size + bl wordfill + + + +; Activate Yellow and fill Yellow and Orange (KDP) + + addi r9, r1, KDP.YellowVecBase + mtsprg 3, r9 + + addi r8, r1, KDP.OrangeVecBase + + llabel r23, panic + add r23, r23, r25 + stw r23, VecTable.SystemResetVector(r9) + stw r23, VecTable.SystemResetVector(r8) + + llabel r23, IntMachineCheck + add r23, r23, r25 + stw r23, VecTable.MachineCheckVector(r9) + stw r23, VecTable.MachineCheckVector(r8) + + llabel r23, IntDSI + add r23, r23, r25 + stw r23, VecTable.DSIVector(r9) + stw r23, VecTable.DSIVector(r8) + + llabel r23, IntISI + add r23, r23, r25 + stw r23, VecTable.ISIVector(r9) + stw r23, VecTable.ISIVector(r8) + + ; Difference: Yellow seems more likely to reach PIH + llabel r23, IntExternalYellow + add r23, r23, r25 + stw r23, VecTable.ExternalIntVector(r9) ; yellow + + llabel r23, IntExternalOrange + add r23, r23, r25 + stw r23, VecTable.ExternalIntVector(r8) ; orange + + llabel r23, IntAlignment + add r23, r23, r25 + stw r23, VecTable.AlignmentIntVector(r9) + stw r23, VecTable.AlignmentIntVector(r8) + + llabel r23, IntProgram + add r23, r23, r25 + stw r23, VecTable.ProgramIntVector(r9) + stw r23, VecTable.ProgramIntVector(r8) + + llabel r23, IntFPUnavail + add r23, r23, r25 + stw r23, VecTable.FPUnavailVector(r9) + stw r23, VecTable.FPUnavailVector(r8) + + llabel r23, IntDecrementer + add r23, r23, r25 + stw r23, VecTable.DecrementerVector(r9) + stw r23, VecTable.DecrementerVector(r8) + + llabel r23, IntSyscall + add r23, r23, r25 + stw r23, VecTable.SyscallVector(r9) + stw r23, VecTable.SyscallVector(r8) + + llabel r23, IntPerfMonitor + add r23, r23, r25 + stw r23, VecTable.PerfMonitorVector(r9) + stw r23, VecTable.PerfMonitorVector(r8) + + llabel r23, IntTrace + add r23, r23, r25 + stw r23, VecTable.TraceVector(r9) + stw r23, VecTable.TraceVector(r8) + stw r23, 0x0080(r9) ; Unexplored parts of vecBase + stw r23, 0x0080(r8) + + llabel r23, FDP_1c40 ; seems AltiVec-related + add r23, r23, r25 + stw r23, 0x0058(r9) + stw r23, 0x0058(r8) + + llabel r23, IntThermalEvent ; thermal event + add r23, r23, r25 + stw r23, VecTable.ThermalEventVector(r9) + stw r23, VecTable.ThermalEventVector(r8) + + + +; Fill Red (KDP), used while were emulating some instructions + + addi r8, r1, KDP.RedVecBase + + llabel r23, panic + add r23, r23, r25 + stw r23, VecTable.SystemResetVector(r8) + + llabel r23, IntMachineCheckMemRetry + add r23, r23, r25 + stw r23, VecTable.MachineCheckVector(r8) + + llabel r23, IntDSIOtherOther + add r23, r23, r25 + stw r23, VecTable.DSIVector(r8) + + llabel r23, IntSyscall + add r23, r23, r25 + stw r23, VecTable.SyscallVector(r8) + + + +; Fill Violet (PSA) + + ; Fill everything with this + llabel r23, major_0x04a20 + add r23, r23, r25 + addi r8, r1, PSA.VioletVecBase + li r22, VecTable.Size + bl wordfill + + ; Then override with these + llabel r23, panic + add r23, r23, r25 + stw r23, VecTable.SystemResetVector(r8) + + llabel r23, IntDSI + add r23, r23, r25 + stw r23, VecTable.DSIVector(r8) + + llabel r23, IntISI + add r23, r23, r25 + stw r23, VecTable.ISIVector(r8) + + llabel r23, IntAlignment + add r23, r23, r25 + stw r23, VecTable.AlignmentIntVector(r8) + + + +; Fill Indigo (PSA). All panics, except for IntIndigo in: +; - SystemResetVector +; - ExternalIntVector +; - DecrementerVector + + bl FillIndigo + + + +; Fill Blue (PSA) + + addi r8, r1, PSA.BlueVecBase + + llabel r23, panic + add r23, r23, r25 + stw r23, VecTable.SystemResetVector(r8) + + llabel r23, IntMachineCheck + add r23, r23, r25 + stw r23, VecTable.MachineCheckVector(r8) + + llabel r23, IntDSIOther + add r23, r23, r25 + stw r23, VecTable.DSIVector(r8) + + llabel r23, IntSyscall + add r23, r23, r25 + stw r23, VecTable.SyscallVector(r8) + + + +; Fill the NanoKernelCallTable, the IntProgram interface to the NanoKernel + + ; Start with a default function + + llabel r23, major_0x046d0 + add r23, r23, r25 + + addi r8, r1, KDP.NanoKernelCallTable + + li r22, NanoKernelCallTable.Size + +@kctab_initloop + subic. r22, r22, 4 + stwx r23, r8, r22 + bne+ @kctab_initloop + + + ; Then some overrides (names still pretty poor) + + llabel r23, kcReturnFromException + add r23, r23, r25 + stw r23, NanoKernelCallTable.ReturnFromException(r8) + + llabel r23, kcRunAlternateContext + add r23, r23, r25 + stw r23, NanoKernelCallTable.RunAlternateContext(r8) + + llabel r23, kcResetSystem + add r23, r23, r25 + stw r23, NanoKernelCallTable.ResetSystem(r8) + + llabel r23, kcVMDispatch + add r23, r23, r25 + stw r23, NanoKernelCallTable.VMDispatch(r8) + + llabel r23, kcPrioritizeInterrupts + add r23, r23, r25 + stw r23, NanoKernelCallTable.PrioritizeInterrupts(r8) + + llabel r23, kcPowerDispatch + add r23, r23, r25 + stw r23, NanoKernelCallTable.PowerDispatch(r8) + + llabel r23, kcRTASDispatch + add r23, r23, r25 + stw r23, NanoKernelCallTable.RTASDispatch(r8) + + llabel r23, kcCacheDispatch + add r23, r23, r25 + stw r23, NanoKernelCallTable.CacheDispatch(r8) + + llabel r23, kcMPDispatch + add r23, r23, r25 + stw r23, NanoKernelCallTable.MPDispatch(r8) + + llabel r23, kcThud + add r23, r23, r25 + stw r23, NanoKernelCallTable.Thud(r8) + + + +; Set ProcessorFlags (and two other bytes) from PVR. +; Nigh unforgivably ugly code, but ProcessorFlagsTable.s +; describes what it does pretty well. + +SetProcessorFlags + + mfpvr r23 + srwi r23, r23, 16 + andi. r8, r23, 0x8000 + bne- @pvr_has_high_bit_set + + ; PVR < 0x8000 (therefore probably equals 000*) + cmplwi r23, 0x000f ; but if not, pretend it's zero + ble- @pvr_not_low + li r23, 0x0000 +@pvr_not_low + + add r8, r25, r23 + lbz r23, ProcessorFlagsTable - NKTop + 0(r8) + stb r23, KDP.CpuSpecificByte1(r1) + lbz r23, ProcessorFlagsTable - NKTop + 32(r8) + stb r23, KDP.CpuSpecificByte2(r1) + mfpvr r23 + srwi r23, r23, 16 + slwi r23, r23, 2 + add r8, r25, r23 + lwz r23, ProcessorFlagsTable - NKTop + 64(r8) + stw r23, KDP.ProcessorInfo + NKProcessorInfo.ProcessorFlags(r1) + b @done + +@pvr_has_high_bit_set + andi. r23, r23, 0x7fff + + cmplwi r23, 0x000f + ble- @other_pvr_not_low + li r23, -0x10 +@other_pvr_not_low + + add r8, r25, r23 + lbz r23, ProcessorFlagsTable - NKTop + 16(r8) + stb r23, KDP.CpuSpecificByte1(r1) + lbz r23, ProcessorFlagsTable - NKTop + 48(r8) + stb r23, KDP.CpuSpecificByte2(r1) + mfpvr r23 + srwi r23, r23, 16 + andi. r23, r23, 0x7fff + slwi r23, r23, 2 + add r8, r25, r23 + lwz r23, ProcessorFlagsTable - NKTop + 128(r8) + stw r23, KDP.ProcessorInfo + NKProcessorInfo.ProcessorFlags(r1) + b @done + +@done + + +; These look like two-word structures. Not yet sure what they are. + + li r23, -1 + stw r23, KDP.MinusOne1(r1) ; kdp.0x340 + stw r23, KDP.MinusOne2(r1) ; kdp.0x348 + stw r23, KDP.MinusOne3(r1) ; kdp.0x350 + stw r23, KDP.MinusOne4(r1) ; kdp.0x358 + + + +; Initialize the seven kernel locks (Count and Signature fields) + + li r23, 0 + stw r23, PSA.HTABLock + Lock.Count(r1) + stw r23, PSA.PIHLock + Lock.Count(r1) + stw r23, PSA.SchLock + Lock.Count(r1) + stw r23, PSA.ThudLock + Lock.Count(r1) + stw r23, PSA.RTASLock + Lock.Count(r1) + stw r23, PSA.DbugLock + Lock.Count(r1) + stw r23, PSA.PoolLock + Lock.Count(r1) + + lisori r23, Lock.kHTABLockSignature + stw r23, PSA.HTABLock + Lock.Signature(r1) + + lisori r23, Lock.kPIHLockSignature + stw r23, PSA.PIHLock + Lock.Signature(r1) + + lisori r23, Lock.kSchLockSignature + stw r23, PSA.SchLock + Lock.Signature(r1) + + lisori r23, Lock.kThudLockSignature ; older kernel versions have a powr lock? + stw r23, PSA.ThudLock + Lock.Signature(r1) + + lisori r23, Lock.kRTASLockSignature + stw r23, PSA.RTASLock + Lock.Signature(r1) + + lisori r23, Lock.kDbugLockSignature + stw r23, PSA.DbugLock + Lock.Signature(r1) + + lisori r23, Lock.kPoolLockSignature + stw r23, PSA.PoolLock + Lock.Signature(r1) + + + +; These seem to be register templates. + + lisori r17, 0x7fffdead + + stw r17, PSA.VectorRegInitWord(r1) + stw r17, PSA.SevenFFFDead2(r1) + stw r17, PSA.SevenFFFDead3(r1) + stw r17, PSA.SevenFFFDead4(r1) + + + +; Set up the not-quite-a-heap 'pool' of dynamic NanoKernel storage. +; +; And then set up the structure (hash table?) mapping opaque +; usermode-facing IDs with numeric types to storage blocks. + + bl InitPool + bl InitIDIndex + + + +; Leave AllCpuFeatures in r7 for use waaaaay down there... + + lwz r7, EWA.Flags(r1) + + + +; Create a blue process to own the blue and idle tasks + + ; Allocate and check + li r8, 32 ;Process.Size + bl PoolAlloc ; takes size and returns ptr, all in r8 + + mr. r31, r8 + beq- Init_Panic + + ; Get opaque ID + li r9, Process.kIDClass + bl MakeID + + ; Point KDP to it + stw r31, PSA.blueProcessPtr(r1) + + ; Save ID in self and KDP + stw r8, Process.ID(r31) + stw r8, KDP.NanoKernelInfo + NKNanoKernelInfo.blueProcessID(r1) + + ; Sign it + lisori r8, Process.kSignature + stw r8, Process.Signature(r31) + + ; blue and idle + li r8, 2 + stw r8, Process.TaskCount(r31) + + + +; Create a GRPS struct in KDP. Make it into an +; infinite linked list for adoption by coherence group. +; So leave ptr in r30. + + addi r30, r1, PSA.FirstGRPS + InitList r30, GRPSStruct.kSignature, scratch=r17 + + + +; Create the motherboard coherence group (CGRP, ID class 10) in the pool. +; Owns a linked list of GRPSes, is itself a linked list member. +; Leave ptr in r29. + + ; Allocate the main structure in the kernel pool, and check for a null ptr + li r8, 0x58 ;CoherenceGroup.Size + bl PoolAlloc + mr. r31, r8 + beq- Init_Panic + + + ; Adopt the above-created list of GRPS structs (only one so far) + addi r17, r31, CoherenceGroup.GRPSList + stw r30, LLL.Freeform(r17) + InsertAsPrev r17, r30, scratch=r18 + + + ; Make me into an infinite linked list for adoption by CPU struct. + addi r29, r31, CoherenceGroup.LLL + InitList r29, CoherenceGroup.kSignature, scratch=r17 + + + ; Get opaque ID + mr r8, r31 + li r9, CoherenceGroup.kIDClass + bl MakeID + stw r8, CoherenceGroup.LLL + LLL.Freeform(r31) + + + ; Congratulate ourselves + mr r16, r8 ; Print macro clobbers r8 (opaque ID), so save it + + _log 'Created motherboard coherence group. ID ' + + mr r8, r16 + bl Printw + + _log '^n' + + + ; Fill in some actual fields (then still have 48 unused bytes) + li r16, 1 + stw r16, CoherenceGroup.CpuCount(r31) + stw r16, CoherenceGroup.ScheduledCpuCount(r31) + + + ; problem: expecting to see more stuff set here + + + +; Create a CPU struct in KDP with a linked list of coherence groups + + ; Place + subi r31, r1, CPU.EWA + addi r30, r31, CPU.EWABase + + + ; Get opaque ID + mr r8, r31 + li r9, CPU.kIDClass + bl MakeID + + + ; Identify and sign + stw r8, CPU.ID(r31) + + lisori r8, CPU.kSignature + stw r8, CPU.Signature(r31) + + + ; Adopt the above-created coherence group list + addi r17, r31, CPU.CgrpList + + stw r29, LLL.Freeform(r17) + InsertAsPrev r17, r29, scratch=r18 + + + ; Actually populate something useful (still have one unused long) + lisori r8, 15 + stw r8, CPU.Eff(r31) + + ; Matches code in KCCreateCpuStruct very closely + + addi r8, r1, PSA.Base + stw r8, EWA.PA_PSA - EWA.Base(r30) + + + stw r1, EWA.PA_KDP - EWA.Base(r30) + + li r8, 0 + stw r8, 0x0318(r30) ; -0x28 + sth r8, 0x020a(r30) ; -0x136 + + lisori r8, 'time' + stw r8, 0x0004(r30) + + li r8, 0x04 + stb r8, 0x0014(r30) + + li r8, 0x01 + stb r8, 0x0016(r30) + + li r8, 0x00 + stb r8, 0x0017(r30) + + lisori r8, 0x7fffffff + stw r8, 0x0038(r30) + + oris r8, r8, 0xffff + stw r8, 0x003c(r30) + + + +; Copy the 32-element BATRangeInit array from ConfigInfo +; For odd-indexed longs (offsets 0x*4 and 0x*c) with bit 22 set: +; - unset that bit +; - increment the value by PA_ConfigInfo (so... they were relative?) + + lwz r26, KDP.PA_ConfigInfo(r1) + addi r9, r26, NKConfigurationInfo.BATRangeInit - 4 + addi r8, r1, KDP.BATs - 4 + li r22, 0x80 + +@BAT_copyloop + lwzu r20, 4(r9) ; grab 8 bytes + lwzu r21, 4(r9) + + stwu r20, 4(r8) ; store the first byte directly + + rlwinm r23, r21, 0, 23, 21 ; munge the second byte + cmpw r21, r23 + + beq- @bitnotset + add r21, r23, r26 +@bitnotset + + addic. r22, r22, -8 + stwu r21, 4(r8) ; but store it eventually + bgt+ @BAT_copyloop + + + +; Create a 'system' address space owned by the motherboard coherence +; group and by the MacOS process that we created earlier. +; Leave a ptr to the new AddressSpace in r30 and its ID in r16. + + li r8, 0 + lwz r9, PSA.blueProcessPtr(r1) + + ; ARG MPCoherenceID r8 owningCOHG ; 0 to use mobo COHG + ; Process *r9 owningPROC + + bl NKCreateAddressSpaceSub + + ; RET MPErr r8 + ; AddressSpace *r9 + + cmpwi r8, 0 + mr r30, r9 + bne- Init_Panic + + + ; The relationship between SPACes and PROCs is still unclear... + lwz r31, PSA.blueProcessPtr(r1) + + + ; Save the new addr spc ID in system process struct and KDP + lwz r16, AddressSpace.ID(r30) + stw r16, Process.SystemAddressSpaceID(r31) + stw r16, PSA.SystemAddressSpaceID(r1) + + + ; Save a few pointers to it for good measure + stw r30, Process.SystemAddressSpacePtr(r31) + stw r30, EWA.PA_CurAddressSpace(r1) + stw r30, PSA.OtherSystemAddrSpcPtr(r1) + + + +; Show off the new address space struct, and at the same time, +; copy the BATs that we copied from ConfigInfo to KDP, into the struct. + + _log 'Created system address space. ID ' + + mr r8, r16 + bl Printw + + _log '^n BATs ' + + lwz r16, 0x0288(r1) ; kdp.bat0l + lwz r17, 0x028c(r1) ; kdp.bat0u + stw r16, 0x0080(r30) + stw r17, 0x0084(r30) + + mr r8, r16 + bl Printw + mr r8, r17 + bl Printw + _log ' ' + + lwz r16, 0x0298(r1) ; kdp.bat1l + lwz r17, 0x029c(r1) ; kdp.bat1u + stw r16, 0x0088(r30) + stw r17, 0x008c(r30) + + mr r8, r16 + bl Printw + mr r8, r17 + bl Printw + _log ' ' + + lwz r16, 0x02a8(r1) ; kdp.bat2l + lwz r17, 0x02ac(r1) ; kdp.bat2u + stw r16, 0x0090(r30) + stw r17, 0x0094(r30) + + mr r8, r16 + bl Printw + mr r8, r17 + bl Printw + _log ' ' + + lwz r16, 0x02b8(r1) ; kdp.bat3l + lwz r17, 0x02bc(r1) ; kdp.bat3u + stw r16, 0x0098(r30) + stw r17, 0x009c(r30) + + mr r8, r16 + bl Printw + mr r8, r17 + bl Printw + _log '^n' + + + +; Initialize the kernel queues. They are called: +; +; - PHYS (free list, in KDP, by InitFreeList) +; - DLYQ (in KDP, by me) +; - DBUG (in KDP, by me) +; - PAGQ (in KDP, has ID, by me) +; - NOTQ (in KDP, by me) +; - TMRQs (one in KDP, two in pool, one more in pool for Nanodebugger) +; - RDYQs (four in KDP, for each task priority) + + ; Free list in hardcoded KDP location + ; ARG KernelData *r1 + ; CLOB r8, r9 + bl InitFreeList + + + ; Delay queue in hardcoded KDP location + + addi r9, r1, PSA.DelayQueue + InitList r9, 'DLYQ', scratch=r8 + + + ; Debugger queue in hardcoded KDP location + + addi r9, r1, PSA.DbugQueue + InitList r9, 'DBUG', scratch=r8 + + + ; Page queue in hardcoded KDP location... + + addi r8, r1, PSA.PageQueue + + ; ...with opaque id... + li r9, Queue.kIDClass + bl MakeID + addi r9, r1, PSA.PageQueue + stw r8, LLL.Freeform(r9) + + ; ...which the blue task will probably want to know about + stw r8, KDP.NanoKernelInfo + NKNanoKernelInfo.pageQueueID(r1) + + InitList r9, 'PAGQ', scratch=r16 + + + ; Not sure what these globals relate to + + li r8, 0 + stw r8, PSA.QueueRelatedZero1(r1) + stw r8, PSA.QueueRelatedZero2(r1) + + + ; Notification queue in hardcoded KDP location + + addi r9, r1, PSA.NotQueue + InitList r9, 'NOTQ', scratch=r16 + + + ; TMRQs (see comments above and with InitTMRQs) + ; (These are all the same structure but only one is signed!) + + bl InitTMRQs + + + ; One ready for each task priority (critical, etc) + + bl InitRDYQs + + + +; Set the BAT and segment registers (how were SRs calculated?) + + lwz r8, EWA.PA_CurAddressSpace(r1) + li r9, 0 + bl SetAddrSpcRegisters + + + +; Create the Blue MacOS task + + ; ARG EmpiricalCpuFeatures r7, Process *r8 + ; RET Task *r8 + + lwz r8, PSA.blueProcessPtr(r1) + bl CreateTask + + ; Check + mr. r31, r8 + beq- Init_Panic + + lwz r8, Task.ID(r31) + stw r8, KDP.NanoKernelInfo + NKNanoKernelInfo.blueTaskID(r1) + + + ; Can equal -1 or a 68k interrupt number. PIHes touch it. + li r8, -1 + sth r8, PSA.Int(r1) + + ; + stw r31, PSA.PA_BlueTask(r1) + stw r31, EWA.PA_CurTask(r1) + + ; Misc population + lisori r8, 'blue' + stw r8, Task.Name(r31) + + li r8, 2 + stb r8, Task.MysteryByte1(r31) + + lisori r8, 0x00030028 + stw r8, 0x0064(r31) + + li r8, 200 + stw r8, Task.Weight(r31) + + li r8, Task.kNominalPriority + stb r8, Task.Priority(r31) + + lhz r8, -0x0116(r1) ; zero?????? + sth r8, 0x001a(r31) + + lwz r8, EWA.CPUBase + CPU.ID(r1) + stw r8, Task.CpuID(r31) + + lwz r6, KDP.PA_ECB(r1) + stw r6, Task.ContextBlockPtr(r31) ; override structs own ECB area + + lwz r16, Task.ContextBlock + ContextBlock.VectorSaveArea(r31) + stw r16, ContextBlock.VectorSaveArea(r6) + + + ; Bang on about some stuff + + _log 'System context at 0x' + mr r8, r6 + bl Printw + + _log ' Vector save area at 0x' + mr r8, r16 + bl Printw + + _log ' SDR1 0x' + mfspr r8, sdr1 + mr r8, r8 + bl Printw + _log '^n' + + + ; Task enqueueing is still a bit of a mystery to me + + _log 'Adding blue task ' + lwz r8, Task.ID(r31) + mr r8, r8 + bl Printw + _log 'to the ready queue^n' + + addi r16, r31, Task.QueueMember + RemoveFromList r16, scratch1=r17, scratch2=r18 + + + ; ARG Task *r8 + ; CLOB r16, r17, r18 + + mr r8, r31 + bl TaskReadyAsPrev + + bl CalculateTimeslice + + + +; Do some things I do not understand + bl major_0x14af8_0xa0 + bl StartTimeslicing + + + +; Create the idle task for the first CPU + + ; Unset the AV bit in EmpiricalCpuFeatures so that + ; idle task vector registers are not saved/restored + ; (Leave the old value in r31) +av set PSA.AVFeatureBit + mr r31, r7 + rlwinm r7, r7, 0, av + 1, av - 1 + + ; ARG EmpiricalCpuFeatures r7, Process *r8 + ; RET Task *r8 + + lwz r8, PSA.blueProcessPtr(r1) + bl CreateTask + + ; Restore EmpiricalCpuFeatures + mr r7, r31 + + ; Check + mr. r31, r8 + beq- Init_Panic + + ; Misc population + lisori r8, 'idle' + stw r8, Task.Name(r31) + + + ; Blue has 0x00030028 + lisori r8, 0x000a0040 + stw r8, Task.ThingThatAlignVecHits(r31) + + ; For the scheduler + li r8, 1 + stw r8, Task.Weight(r31) + + li r8, Task.kIdlePriority + stb r8, Task.Priority(r31) + + ; Blue does this too, probably zero, not sure why? + lhz r8, -0x116(r1) + sth r8, 0x01a(r31) + + lwz r8, EWA.CPUBase + CPU.ID(r1) + stw r8, Task.CpuID(r31) + + ; Add a feature!?!?!?! + lwz r8, Task.ContextBlock + ContextBlock.EmpiricalCpuFeatures(r31) + oris r8, r8, 0x40 + stw r8, Task.ContextBlock + ContextBlock.EmpiricalCpuFeatures(r31) + + ; Point task ECB at the idle loop within the nanokernel code + lwz r8, KDP.PA_NanoKernelCode(r1) + llabel r26, IdleCode + add r8, r8, r26 + stw r8, Task.ContextBlock + ContextBlock.CodePtr(r31) + + ; The idle task runs in privileged mode with physical addressing + lwz r8, 0x01a4(r31) + andi. r8, r8, 0xbfcf ; unset loword (MSR_POW, MSR_ILE), MSR_PR, MSR_IR, MSR_DR + stw r8, 0x01a4(r31) + + ; Idle task for first CPU + addi r30, r1, EWA.CPUBase + stw r31, CPU.IdleTaskPtr(r30) + + ; Boast a bit + _log 'Adding idle task ' + lwz r8, Task.ID(r31) + mr r8, r8 + bl Printw + _log 'to the ready queue^n' + + ; This sure looks like a linked-list insertion + addi r16, r31, Task.QueueMember + RemoveFromList r16, scratch1=r17, scratch2=r18 + + ; ARG Task *r8 + ; CLOB r16, r17, r18 + + mr r8, r31 + bl TaskReadyAsPrev + + bl CalculateTimeslice + + ; Create a 'dummy' address space + li r8, 0 + lwz r9, PSA.blueProcessPtr(r1) + + ; ARG MPCoherenceID r8 owningCOHG ; 0 to use mobo COHG + ; Process *r9 owningPROC + + bl NKCreateAddressSpaceSub + + ; RET MPErr r8 + ; AddressSpace *r9 + + cmpwi r8, 0 + mr r30, r9 + lwz r31, EWA.CPUBase + CPU.IdleTaskPtr(r1) + bne- Init_Panic + + stw r30, Task.AddressSpacePtr(r31) + + + +; Now do something with the page table + lwz r7, EWA.Flags(r1) + lwz r26, KDP.PA_ConfigInfo(r1) + lwz r18, KDP.PA_PageMapStart(r1) + + + +; Put HTABORG and PTEGMask in KDP, and zero out the last PTEG + + beq- cr5, @skip_zeroing_pteg + mfspr r8, sdr1 + + ; get settable HTABMASK bits + rlwinm r22, r8, 16, 7, 15 + + ; and HTABORG + rlwinm r8, r8, 0, 0, 15 + + ; get a PTEGMask from upper half of HTABMASK + ori r22, r22, (-64) & 0xffff + + ; Save in KDP (OldWorld must do this another way) + stw r8, KDP.HTABORG(r1) + stw r22, KDP.PTEGMask(r1) + + ; zero out the last PTEG in the HTAB + li r23, 0 + addi r22, r22, 64 +@loop + subic. r22, r22, 4 + stwx r23, r8, r22 + bgt+ @loop +@skip_zeroing_pteg + + +; Rather self-explanatory. Do this even if we did not just edit HTAB. + + bl PagingFlushTLB + + + +; Copy the ConfigInfo pagemap into KDP, absolut-ising entries +; whose physical addresses are relative to ConfigInfo. + + beq- cr5, @skip_copying_pagemap + lwz r9, NKConfigurationInfo.PageMapInitOffset(r26) ; from base of CI + lwz r22, NKConfigurationInfo.PageMapInitSize(r26) + add r9, r9, r26 + +@copyloop_pagemap + subi r22, r22, 4 ; load a word from the CI pagemap (top first) + lwzx r21, r9, r22 + + andi. r23, r21, PMDT.DaddyFlag | PMDT.PhysicalIsRelativeFlag + cmpwi r23, PMDT.PhysicalIsRelativeFlag + bne- @physical_address_not_relative_to_config_info + + rlwinm r21, r21, 0, ~PMDT.PhysicalIsRelativeFlag + add r21, r21, r26 +@physical_address_not_relative_to_config_info + + stwx r21, r18, r22 ; save in the KDP pagemap + + subic. r22, r22, 4 + lwzx r20, r9, r22 ; load another word, but no be cray + stwx r20, r18, r22 ; just save it in KDP + bgt+ @copyloop_pagemap +@skip_copying_pagemap + + + +; Edit the KDP's copied PageMap to contain the correct physical address +; of the parts that we know about: IRP, KDP & surrounds, EDP. +; (No changes to flags) + + ; IRP + + lwz r8, NKConfigurationInfo.PageMapIRPOffset(r26) + add r8, r18, r8 + + lisori r19, IRPOffset + add r19, r19, r1 + + ; Set physical address (top 20 bits of second word) + lwz r23, PMDT.PBaseAndFlags(r8) + rlwimi r23, r19, 0, 0, 19 + stw r23, PMDT.PBaseAndFlags(r8) + + + ; KDP (plus the nine pages below it) + +IRPTopOffset equ IRPOffset + 0x1000 + + lwz r8, NKConfigurationInfo.PageMapKDPOffset(r26) + add r8, r18, r8 + + lisori r19, IRPTopOffset + add r19, r1, r19 + + ; Page count - 1 + lisori r22, (-IRPTopOffset) >> 12 + + ; Set physical address (top 20 bits of second word) + lwz r23, PMDT.PBaseAndFlags(r8) + rlwimi r23, r19, 0, 0, 19 + stw r23, PMDT.PBaseAndFlags(r8) + + ; Set page count - 1 (bottom half of first word) + sth r22, PMDT.PageCount(r8) + + ; Whaaaaaa? + lhz r23, PMDT.LBase(r8) + subf r23, r22, r23 + sth r23, PMDT.LBase(r8) + + + ; EDP + + lwz r19, KDP.PA_EmulatorData(r1) + lwz r8, NKConfigurationInfo.PageMapEDPOffset(r26) + add r8, r18, r8 + + lwz r23, PMDT.PBaseAndFlags(r8) + rlwimi r23, r19, 0, 0, 19 + stw r23, PMDT.PBaseAndFlags(r8) + + + +; Copy segment maps from ConfigInfo +; (128 bytes per mode: supervisor, user, CPU, overlay) +; even-indexed words are offsets into the pagemap +; odd-indexed words are or-ed with 0x20000000 + + addi r9, r26, NKConfigurationInfo.SegMaps - 4 + addi r8, r1, KDP.SegMaps - 4 + li r22, 128 * 4 + +@copyloop_segmaps + lwzu r23, 4(r9) + subic. r22, r22, 8 + add r23, r18, r23 ; even-indexed words are PMDT offsets in PageMap + stwu r23, 4(r8) + + lwzu r23, 4(r9) + oris r23, r23, 0x2000 ; no clue? + stwu r23, 4(r8) + + bgt+ @copyloop_segmaps + + + +; Give KDP pointers to its own structures (how lame). + + addi r23, r1, KDP.SegMap32SupInit + stw r23, KDP.SegMap32SupInitPtr(r1) + + lwz r23, NKConfigurationInfo.BatMap32SupInit(r26) + stw r23, KDP.BatMap32SupInit(r1) + + + addi r23, r1, KDP.SegMap32UsrInit + stw r23, KDP.SegMap32UsrInitPtr(r1) + + lwz r23, NKConfigurationInfo.BatMap32UsrInit(r26) + stw r23, KDP.BatMap32UsrInit(r1) + + + addi r23, r1, KDP.SegMap32CPUInit + stw r23, KDP.SegMap32CPUInitPtr(r1) + + lwz r23, NKConfigurationInfo.BatMap32CPUInit(r26) + stw r23, KDP.BatMap32CPUInit(r1) + + + addi r23, r1, KDP.SegMap32OvlInit + stw r23, KDP.SegMap32OvlInitPtr(r1) + + lwz r23, NKConfigurationInfo.BatMap32OvlInit(r26) + stw r23, KDP.BatMap32OvlInit(r1) + + + +; Use the PageMap kindly provided by the Trampoline to count VMMaxVirtualPages +; (remembering that virtual is meant in the '68k VM' sense). + +; In brief: only big fat PMDTs on 256MB (i.e. segment) boundaries need apply. + +; INDEPENDENT OF INSTALLED RAM! + + li r22, 0 ; counter + addi r19, r1, KDP.SegMaps - 8 + b @next_segment + +@skip_pmdt + addi r8, r8, 0x08 + b @searchloop + +@next_segment + lwzu r8, 8(r19) + +@searchloop + ; Get both words of the pointed-to PMDT + lwz r30, 0(r8) ; OffsetWithinSegInPages(16b) || PageCount-1(16b) + lwz r31, 4(r8) ; PhysicalInPages(20b) || pageAttr(12b) + + ; Stop counting if we meet a PMDT not at the base of its segment. + + ; Stop counting if we meet a PMDT with its top two pageAttr bits both unset. + + ; If PMDT has its top two pageAttr bits both set, + ; check the PMDT following it in the PageMap. + ; (Never seen this in the wild.) + + cmplwi cr7, r30, 0xffff ; if not at base: + rlwinm. r31, r31, 0, PMDT.DaddyFlag | PMDT.CountingFlag ; if neither flag: + bgt- cr7, @finish_count ; stop counting + cmpwi cr6, r31, PMDT.DaddyFlag | PMDT.CountingFlag ; if both flags: + beq- @finish_count ; stop counting + beq+ cr6, @skip_pmdt ; next PMDT instead + + add r22, r22, r30 + addi r22, r22, 1 + beq+ cr7, @next_segment ; else count and move on to next segment descriptor + +@finish_count + stw r22, KDP.VMMaxVirtualPages(r1) + + + +; Create the Flat Page List: +; a draft PTE for every usable physical page. + +; Usable physical pages are: +; Inside a RAM bank, and +; NOT inside the kernel's reserved physical memory + +; By 'draft PTE', I mean these parts of the second word of a PTE: +; physical page number (base & 0xfffff000) +; WIMG bits (from oddly formatted ConfigInfo.PageAttributeInit) +; bottom PP bit always set + +; And all this goes at the bottom of the kernel reserved area. +; Leave ptr to kernel reserved area in r21 +; Leave ptr to topmost entry in r29. + +ListFreePhysicalPages + + beq- cr5, @skip + + lwz r21, KDP.KernelMemoryBase(r1) + lwz r20, KDP.KernelMemoryEnd(r1) + + stw r21, KDP.FlatPageListPtr(r1) + + lwz r30, EWA.PA_IRP(r1) + + ; Will be writing things to the very base of kernel memory. Oh dear. + subi r29, r21, 4 + + addi r19, r30, IRP.SystemInfo + NKSystemInfo.Bank0Start - 8 + + lwz r23, KDP.PageAttributeInit(r1) ; default WIMG/PP settings in PTEs + + ; Pull WIMG bits out of PageAttributeInit + li r30, 1 + rlwimi r30, r23, 1, 25, 25 + rlwimi r30, r23, 31, 26, 26 + xori r30, r30, 0x20 + rlwimi r30, r23, 29, 27, 27 + rlwimi r30, r23, 27, 28, 28 + + li r23, NKSystemInfo.MaxBanks + +@nextbank + subic. r23, r23, 1 + blt- @done + + lwzu r31, 8(r19) ; bank start address + lwz r22, 4(r19) ; bank size + or r31, r31, r30 ; looks a lot like the second word of a PTE + +@nextpage + cmplwi r22, 4096 + cmplw cr6, r31, r21 + cmplw cr7, r31, r20 + subi r22, r22, 4096 + blt+ @nextbank + + ; Check that this page is outside the kernel's reserved area + blt- cr6, @below_reserved + blt- cr7, @in_reserved +@below_reserved + stwu r31, 4(r29) ; write that part-PTE at the base of kernel memory +@in_reserved + + addi r31, r31, 4096 + b @nextpage + +@done +@skip + + + +PrimeFreeListFromBanks + + beq- cr5, PrimeFreeListFromSystemHeap + + ; Add ~18 to 20 of these pages to the free list, depending on RAM size + subf r22, r21, r29 + addi r8, r22, 4096 + srwi r17, r22, 13 + addi r17, r17, 18 + + _log 'Priming the system free list with ' + + mr r8, r17 + bl Printd + + _log 'pages.^n' + +@loop + lwz r8, 0(r29) + rlwinm r8, r8, 0, 0, 19 ; physical base of page + bl free_list_add_page + + subi r17, r17, 1 + subi r29, r29, 4 + cmpwi r17, 0 + bgt+ @loop + + b DonePrimingFreeList + + + +; Apparently the replacement kernel can find pages just above the EDP? + +; More power to it, I say. + +PrimeFreeListFromSystemHeap + + lwz r8, 0x05a8(r1) ; kdp.0x5a8 + addi r18, r1, 0x2000 ; kdp.0x2000 + subf. r8, r18, r8 + blt- DonePrimingFreeList + addi r8, r8, 0x1000 + srwi r17, r8, 12 + + _log 'Priming the system free list with ' + + mr r8, r17 + bl Printd + + _log 'system heap pages.^n' + + +@stupidloop + rlwinm r8, r18, 0, 0, 19 + + bl free_list_add_page + addi r17, r17, -0x01 + addi r18, r18, 0x1000 + cmpwi r17, 0x00 + bgt+ @stupidloop + + + + +DonePrimingFreeList + + + +; Bang on a little bit + + + _log 'VMMaxVirtualPages: ' ; 0005fffe + + lwz r8, KDP.VMMaxVirtualPages(r1) + mr r8, r8 + bl Printw + + _log 'VMLogicalPages: ' + + lwz r8, 0x06a8(r1) ; kdp.phys_pages + mr r8, r8 + bl Printw + + _log '^n' + + _log 'Interrupt handler kind: ' + + lwz r8, KDP.PA_ConfigInfo(r1) ; kdp.pa_ConfigInfo + lbz r8, NKConfigurationInfo.InterruptHandlerKind(r8) + mr r8, r8 + bl Printb + + _log '^n' + + + +; Now the code paths diverge again. +; +; The builtin kernel needs to start the 68k virtual machine. +; +; The replacement kernel needs to return to the Mac OS +; boot process. + + beq- cr5, finish_old_world + + + +; Here we reconcile the actual physical memory with the +; size of the contiguous part of the MacOS address space. + +; Going in: +; r21 points to base of long array +; r29 points (empty ascending) to top of long array + +; Pops have been made to prime the system free list, +; but otherwise, this contains all the physical memory +; that the Trampoline reported in the banks (Tramp already +; subtracted ROM and structures), minus the kernel data. + +ReconcileMemory + + ; r22 = pages still in array * 4 + subf r22, r21, r29 + + ; r8 = theoretical maximum MacOS page count * 4 + lwz r8, KDP.VMMaxVirtualPages(r1) + slwi r8, r8, 2 + + ; Memory We Have versus Memory We Could Use + ; (see blt- below) + cmplw r22, r8 + + ; TotalPhysicalPages equals pages not yet in free list but that could go in. + ; (Therefore exludes Trampoline areas, kernel areas, free list prime) + addi r19, r22, 4 + srwi r19, r19, 2 + stw r19, KDP.TotalPhysicalPages(r1) + + ; r22 = pages in array destined to be mapped to blue area + blt- @less_than_VMMaxVirtualPages + subi r22, r8, 4 +@less_than_VMMaxVirtualPages + + li r30, 0 + + lwz r8, EWA.PA_IRP(r1) + + ; That sets UsableMemorySize = LogicalMemorySize (= size of blue area), + addi r19, r22, 4 + slwi r19, r19, 10 + ori r30, r30, 0xffff + stw r19, IRP.SystemInfo + NKSystemInfo.UsableMemorySize(r8) + srwi r22, r22, 2 + stw r19, IRP.SystemInfo + NKSystemInfo.LogicalMemorySize(r8) + ; Now r22 is a page count + + ; The above, divided by 4096 + srwi r19, r19, 12 + stw r19, KDP.UsablePhysicalPages(r1) + + addi r29, r1, KDP.FlatPageListSegPtrs + addi r19, r1, KDP.SegMaps - 8 + + + + ; Divvy up the FlatPageList into segments +@persegment + ; r21 = fully ascending pointer (starts at base) + ; r + + cmplwi r22, 0xffff ; pages in a segment + lwzu r8, 8(r19) ; get the first word of a SegMap entry + + rotlwi r31, r21, 10 + ori r31, r31, 0xc00 ; r31 = second byte with fake-ass physical backing + + ; Rewrite the pagemap entry + stw r30, 0(r8) ; Whole segment + stw r31, 4(r8) ; Based on the FlatPageList, with weird shifts! + + stwu r21, 0x0004(r29) + addis r21, r21, 4 ; we just used a segment's worth of pages on this + subis r22, r22, 1 ; pages in a segment + bgt+ @persegment + + ; Number of pages in that last segment + sth r22, 0x0002(r8) + + lwz r17, KDP.UsablePhysicalPages(r1) + lwz r18, KDP.TotalPhysicalPages(r1) + stw r17, KDP.TotalPhysicalPages(r1) + + ; Get the number of 'unusable' physical pages (not [yet] wanted by main MacOS area) + ; If any, they will be chucked on the free list + subf. r18, r17, r18 + slwi r31, r17, 12 ; does this work with discontiguous banks? hmm... + ble- @no_leftover_ram + + ; See? + _log 'Physical RAM greater than the initial logical area.^n Moving ' + + mr r8, r18 + bl Printd + + _log 'pages into the system free page list.^n' + + +@loop + mr r8, r31 + bl free_list_add_page + addi r31, r31, 4096 + subi r18, r18, 1 + cmpwi r18, 0 + bgt+ @loop + +@no_leftover_ram + + + +; Create Areas (an abstract NKv2 structure) from the Trampoline's PageMap + + bl convert_pmdts_to_areas + + + +; No understandy + + addi r29, r1, 0x5e0 ; kdp.0x5e0 + bl PagingFunc2 + bl PagingFlushTLB + + + +; Makes QEMU complain + + bl ProbePerfMonitor + + + +; Done all we can + + _log 'Reset system - Into the 68K fire: ' + + mr r8, r11 + bl Printw + mr r8, r10 + bl Printw + + _log '^n' + + lwz r9, ContextBlock.XER(r6) + mfsprg r8, 0 + mtxer r9 + + bl Restore_r14_r31 + + b kcPrioritizeInterrupts + + + +finish_old_world + addi r29, r1, 0x5e8 + bl PagingFunc2 + bl PagingFlushTLB + bl convert_pmdts_to_areas + bl ProbePerfMonitor + lwz r27, 0x0630(r1) + lwz r27, 0x0094(r27) + bl PagingFunc4 + beq- setup_0x1160 + li r30, 0x00 + stw r30, -0x0004(r29) + eieio + stw r30, 0x0000(r29) + sync + +setup_0x1160 + bl PagingFunc1 + lwz r27, 0x0630(r1) + lwz r27, 0x009c(r27) + bl PagingFunc4 + beq- setup_0x1188 + li r30, 0x00 + stw r30, -0x0004(r29) + eieio + stw r30, 0x0000(r29) + sync + +setup_0x1188 + bl PagingFunc1 + lwz r27, 0x0630(r1) + lwz r27, 0x00a0(r27) + lis r19, 0x00 + ori r19, r19, 0xa000 + subf r19, r19, r27 + +setup_0x11a0 + bl PagingFunc4 + beq- setup_0x11bc + li r30, 0x00 + stw r30, -0x0004(r29) + eieio + stw r30, 0x0000(r29) + sync + +setup_0x11bc + bl PagingFunc1 + cmplw r27, r19 + addi r27, r27, -0x1000 + bgt+ setup_0x11a0 + lwz r27, 0x0630(r1) + lwz r27, 0x00a4(r27) + bl PagingFunc4 + beq- setup_0x11f0 + li r30, 0x00 + stw r30, -0x0004(r29) + eieio + stw r30, 0x0000(r29) + sync + +setup_0x11f0 + bl PagingFunc1 + + _log 'Nanokernel replaced. Returning to boot process^n' + + addi r9, r1, 0x420 + mtsprg 3, r9 + +; r1 = kdp + b old_world_rfi_to_userspace_boot + + + +; Called by InitReplacement.s if we accidentally try +; to replace a v2 kernel (like ourself). +; +; All we need to do is restore +; sprg0 (ewa/kdp) and sprg3 (vecBase). + +CancelReplacement + + bl InitScreenConsole + + _log 'Nanokernel NOT replaced. Returning to boot process^n' + + lwz r8, KDP.OldKDP(r1) + mtsprg 0, r8 + + addi r9, r8, KDP.OrangeVecBase + mtsprg 3, r9 + + + +; old_world_rfi_to_userspace_boot + +; Xrefs: +; setup +; CancelReplacement + +; > r1 = kdp + +old_world_rfi_to_userspace_boot ; OUTSIDE REFERER + lwz r4, KDP.LA_EmulatorKernelTrapTable(r1) + lwz r8, KDP.OtherFreeThing(r1) + lwz r9, PSA.UserModeMSR(r1) + addi r8, r8, ReturnCode - NKTop + mtsrr0 r8 + mtsrr1 r9 + rfi + + +ReturnCode + li r3, 255 + mtlr r4 + blrl + + + +; ARG Lock *r8 + + align 5 + +AcquireLock ; OUTSIDE REFERER + lwarx r9, 0, r8 + cmpwi r9, 0 + mfsprg r9, 0 + bne- @already_held + lwz r9, -0x0340(r9) + sync + stwcx. r9, 0, r8 + bne- AcquireLock + mflr r9 + stw r9, 0x0010(r8) + isync + blr + +@already_held + stmw r22, -0x0094(r9) + mr r22, r9 + mflr r30 + mr r31, r8 + lwz r29, -0x0340(r22) + lwz r28, 0x0000(r31) + stw r30, -0x0098(r22) + cmpw r28, r29 + bne+ @0x84 + bl @start_logging + _log 'Recursive spinlock ***^n' + bl Init_Panic + +@0x84 + bl @0x184 + mr r24, r28 + mr r25, r29 + lwz r30, -0x0004(r22) + mfdec r29 + lwz r28, -0x0438(r30) + slwi r28, r28, 3 + subf r29, r28, r29 + b @0xc0 + +@0xa8 + lwz r30, -0x0004(r22) + lwz r28, -0x0b30(r30) + cmpwi r28, 0x00 + beq- @0xc0 + mfdec r29 + addis r29, r29, -0x01 + +@0xc0 + mfdec r28 + subf. r28, r29, r28 + bgt- @0x118 + bl @start_logging + _log 'Timeout - locked CpuID ' + mr r8, r30 + bl printw + _log '***^n' + bl Init_Panic + +@0x118 + lwz r30, 0x0000(r31) + cmpwi r30, 0x00 + bne+ @0xa8 + +@0x124 + lwarx r30, 0, r31 + cmpwi r30, 0 + bne+ @0xa8 + lwz r30, EWA.CPUBase + CPU.ID(r22) + sync + stwcx. r30, 0, r31 + bne- @0x124 + mfxer r30 + bl @0x184 + lwz r27, -0x0098(r22) + subfc r29, r25, r29 + lwz r25, 0x000c(r31) + subfe r28, r24, r28 + lwz r24, 0x0008(r31) + addc r25, r25, r29 + adde r24, r24, r28 + stw r25, 0x000c(r31) + stw r24, 0x0008(r31) + mtlr r27 + stw r27, 0x0010(r31) + mtxer r30 + mr r8, r22 + lmw r22, -0x0094(r8) + blr + +@0x184 + mftbu r28 + mftb r29 + mftbu r27 + cmpw r28, r27 + beqlr+ + b @0x184 + +@start_logging ; actually a func + mfsprg r28, 0 + mflr r27 + + lwz r29, EWA.CPUBase + CPU.ID(r28) + _log '^n*** On CPU ' + mr r8, r29 + bl printw + + _log 'spinlock 0x' + + mr r8, r31 + bl printw + + ; Print lock sig + lwz r8, Lock.Signature(r31) + rotlwi r8, r8, 8 + bl printc + rotlwi r8, r8, 8 + bl printc + rotlwi r8, r8, 8 + bl printc + rotlwi r8, r8, 8 + bl printc + + lwz r29, -0x0098(r28) + _log ' caller 0x' + mr r8, r29 + bl printw + + mtlr r27 + blr + + + +Init_Panic + b panic diff --git a/NanoKernel/NKInterrupts.s b/NanoKernel/NKInterrupts.s new file mode 100644 index 0000000..9beb6a3 --- /dev/null +++ b/NanoKernel/NKInterrupts.s @@ -0,0 +1,2851 @@ +Local_Panic set * + b panic + + + +; major_0x02964 + +; Xrefs: +; major_0x02ccc + +major_0x02964 ; OUTSIDE REFERER + b AlternateMPCallReturnPath + + + +; major_0x02980 + +; Xrefs: +; major_0x02ccc +; major_0x03548 +; IntDSIOtherOther +; IntMachineCheckMemRetry +; major_0x039dc +; IntMachineCheck +; MaskedInterruptTaken +; major_0x03be0 +; major_0x04180 +; kcRunAlternateContext +; major_0x046d0 +; IntExternalOrange +; IntProgram +; IntTrace +; FDP_1214 + + align 5 + +major_0x02980 ; OUTSIDE REFERER + mfsprg r1, 0 + mtsprg 3, r24 + lwz r9, -0x000c(r1) + rlwinm r23, r17, 31, 27, 31 + rlwnm. r9, r9, r8, 0x00, 0x00 + bsol- cr3, major_0x02980_0x100 + lwz r6, -0x0014(r1) + ori r7, r16, 0x10 + neg r23, r23 + mtcrf 0x3f, r7 + add r19, r19, r23 + rlwimi r7, r8, 24, 0, 7 + lwz r1, -0x0004(r1) + slwi r8, r8, 2 + add r8, r8, r1 + lwz r9, 0x0dc0(r8) + addi r9, r9, 0x01 + stw r9, 0x0dc0(r8) + srwi r9, r7, 24 + mfsprg r1, 0 + lwz r8, 0x0000(r1) + stw r8, 0x0104(r6) + lwz r8, 0x001c(r1) + stw r8, 0x013c(r6) + lwz r8, 0x0020(r1) + stw r8, 0x0144(r6) + lwz r8, 0x0024(r1) + stw r8, 0x014c(r6) + lwz r8, 0x0028(r1) + stw r8, 0x0154(r6) + lwz r8, 0x002c(r1) + stw r8, 0x015c(r6) + lwz r8, 0x0030(r1) + stw r8, 0x0164(r6) + lwz r8, 0x0034(r1) + stw r8, 0x016c(r6) + cmpwi cr1, r9, 0x14 + blt- cr4, major_0x04a20_0x18 + bne- cr2, major_0x02ccc_0x310 + blt- major_0x02980_0xa8 + bne- cr1, major_0x02980_0x178 + b major_0x02ccc_0x310 + +major_0x02980_0xa8 + mfsprg r1, 0 + stw r10, 0x0084(r6) + stw r12, 0x008c(r6) + stw r3, 0x0094(r6) + stw r4, 0x009c(r6) + lwz r8, -0x000c(r1) + stw r7, 0x0040(r6) + stw r8, 0x0044(r6) + li r8, 0x00 + lwz r10, 0x004c(r6) + stw r8, -0x000c(r1) + lwz r1, -0x0004(r1) + lwz r4, 0x0054(r6) + lwz r3, 0x0654(r1) + blt- cr2, major_0x02980_0xec + lwz r3, 0x05b4(r1) + rlwinm r11, r11, 0, 17, 15 + +major_0x02980_0xec + lwz r12, 0x0648(r1) + bsol- cr6, major_0x02980_0x114 + rlwinm r7, r7, 0, 29, 16 + rlwimi r11, r7, 0, 20, 23 + b skeleton_key + +major_0x02980_0x100 + lwz r2, 0x0008(r1) + lwz r3, 0x000c(r1) + lwz r4, 0x0010(r1) + lwz r5, 0x0014(r1) + blr + +major_0x02980_0x114 ; OUTSIDE REFERER + mfsprg r8, 0 + stw r17, 0x0064(r6) + stw r20, 0x0068(r6) + stw r21, 0x006c(r6) + stw r19, 0x0074(r6) + stw r18, 0x007c(r6) + lmw r14, 0x0038(r8) + blr + +major_0x02980_0x134 ; OUTSIDE REFERER + mfsprg r1, 0 + mtcrf 0x3f, r7 + lwz r9, -0x000c(r1) + lwz r1, -0x0004(r1) + rlwnm. r9, r9, r8, 0x00, 0x00 + rlwimi r7, r8, 24, 0, 7 + slwi r8, r8, 2 + add r8, r8, r1 + lwz r9, 0x0dc0(r8) + addi r9, r9, 0x01 + stw r9, 0x0dc0(r8) + srwi r9, r7, 24 + blt- cr4, major_0x04a20_0x18 + bne- cr2, major_0x02ccc_0x2a4 + cmpwi cr1, r9, 0x0c + blt+ major_0x02980_0xa8 + beq- cr1, major_0x02ccc_0x2a4 + +major_0x02980_0x178 ; OUTSIDE REFERER + lwz r1, -0x0004(r1) + lwz r9, 0x0658(r1) + addi r8, r1, 0x360 + mtsprg 3, r8 + bltl- cr2, major_0x02ccc_0x108 + +major_0x02980_0x18c ; OUTSIDE REFERER + mfsprg r1, 0 + lwz r8, -0x000c(r1) + stw r7, 0x0000(r6) + stw r8, 0x0004(r6) + bns- cr6, major_0x02980_0x1b8 + stw r17, 0x0024(r6) + stw r20, 0x0028(r6) + stw r21, 0x002c(r6) + stw r19, 0x0034(r6) + stw r18, 0x003c(r6) + lmw r14, 0x0038(r1) + +major_0x02980_0x1b8 + mfxer r8 + stw r13, 0x00dc(r6) + stw r8, 0x00d4(r6) + stw r12, 0x00ec(r6) + mfctr r8 + stw r10, 0x00fc(r6) + stw r8, 0x00f4(r6) + ble- cr3, major_0x02980_0x1e8 + lwz r8, 0x00c4(r9) + mfspr r12, mq + mtspr mq, r8 + stw r12, 0x00c4(r6) + +major_0x02980_0x1e8 + lwz r8, 0x0004(r1) + stw r8, 0x010c(r6) + stw r2, 0x0114(r6) + stw r3, 0x011c(r6) + stw r4, 0x0124(r6) + lwz r8, 0x0018(r1) + stw r5, 0x012c(r6) + stw r8, 0x0134(r6) + stw r14, 0x0174(r6) + stw r15, 0x017c(r6) + stw r16, 0x0184(r6) + stw r17, 0x018c(r6) + stw r18, 0x0194(r6) + stw r19, 0x019c(r6) + stw r20, 0x01a4(r6) + stw r21, 0x01ac(r6) + stw r22, 0x01b4(r6) + stw r23, 0x01bc(r6) + stw r24, 0x01c4(r6) + stw r25, 0x01cc(r6) + stw r26, 0x01d4(r6) + andi. r8, r11, 0x2000 + stw r27, 0x01dc(r6) + stw r28, 0x01e4(r6) + stw r29, 0x01ec(r6) + stw r30, 0x01f4(r6) + stw r31, 0x01fc(r6) + bnel- major_0x03e18_0xb4 + bge- cr3, major_0x02980_0x260 + bl Save_v0_v31 + +major_0x02980_0x260 + stw r11, 0x00a4(r6) + lwz r8, 0x0000(r9) + stw r9, -0x0014(r1) + xoris r7, r7, 0x80 + rlwimi r11, r8, 0, 20, 23 + mr r6, r9 + rlwimi r7, r8, 0, 17, 31 + andi. r8, r11, 0x900 + lwz r8, 0x0004(r6) + lwz r13, 0x00dc(r6) + stw r8, -0x000c(r1) + lwz r8, 0x00d4(r6) + lwz r12, 0x00ec(r6) + mtxer r8 + lwz r8, 0x00f4(r6) + lwz r10, 0x00fc(r6) + mtctr r8 + bnel- major_0x03e18_0x8 + lwarx r8, 0, r1 + sync + stwcx. r8, 0, r1 + lwz r29, 0x00d8(r6) + lwz r8, 0x010c(r6) + cmpwi r29, 0x00 + stw r8, 0x0004(r1) + lwz r28, 0x0210(r29) + beq- major_0x02980_0x2d0 + mtspr vrsave, r28 + +major_0x02980_0x2d0 + lwz r2, 0x0114(r6) + lwz r3, 0x011c(r6) + lwz r4, 0x0124(r6) + lwz r8, 0x0134(r6) + lwz r5, 0x012c(r6) + stw r8, 0x0018(r1) + lwz r14, 0x0174(r6) + lwz r15, 0x017c(r6) + lwz r16, 0x0184(r6) + lwz r17, 0x018c(r6) + lwz r18, 0x0194(r6) + lwz r19, 0x019c(r6) + lwz r20, 0x01a4(r6) + lwz r21, 0x01ac(r6) + lwz r22, 0x01b4(r6) + lwz r23, 0x01bc(r6) + lwz r24, 0x01c4(r6) + lwz r25, 0x01cc(r6) + lwz r26, 0x01d4(r6) + lwz r27, 0x01dc(r6) + lwz r28, 0x01e4(r6) + lwz r29, 0x01ec(r6) + lwz r30, 0x01f4(r6) + lwz r31, 0x01fc(r6) + + + +; skeleton_key + +; Called when a Gary reset trap is called. When else? + +; Xrefs: +; major_0x02980 +; IntDecrementer +; IntISI +; IntMachineCheck +; major_0x03be0 +; IntPerfMonitor +; IntThermalEvent +; kcRunAlternateContext +; kcResetSystem +; IntProgram +; IntExternalYellow +; kcVMDispatch +; major_0x09e28 +; major_0x0a600 +; kcRTASDispatch +; kcCacheDispatch +; CommonMPCallReturnPath +; CommonPIHPath + +skeleton_key ; OUTSIDE REFERER + andi. r8, r7, 0x30 + mfsprg r1, 0 + bnel- major_0x02ccc + li r8, 0x00 + stw r7, -0x0010(r1) + stw r8, -0x0114(r1) + b major_0x142a8 + + + +; major_0x02ccc + +; Xrefs: +; major_0x02980 +; skeleton_key + +major_0x02ccc ; OUTSIDE REFERER + mtcrf 0x3f, r7 + bns- cr6, major_0x02ccc_0x18 + rlwinm r7, r7, 0, 28, 26 + bso- cr7, major_0x02ccc_0x30 + rlwinm r7, r7, 0, 27, 25 + b major_0x02ccc_0x2c + +major_0x02ccc_0x18 + bne- cr6, major_0x02ccc_0x2c + rlwinm r7, r7, 0, 27, 25 + stw r7, -0x0010(r1) + li r8, 0x08 + b major_0x02980_0x134 + +major_0x02ccc_0x2c + blr + +major_0x02ccc_0x30 + rlwinm. r8, r7, 0, 8, 8 + beq- major_0x02ccc_0x108 + stw r7, -0x0010(r1) + lwz r8, 0x0104(r6) + stw r8, 0x0000(r1) + stw r2, 0x0008(r1) + stw r3, 0x000c(r1) + stw r4, 0x0010(r1) + stw r5, 0x0014(r1) + lwz r8, 0x013c(r6) + stw r8, 0x001c(r1) + lwz r8, 0x0144(r6) + stw r8, 0x0020(r1) + lwz r8, 0x014c(r6) + stw r8, 0x0024(r1) + lwz r8, 0x0154(r6) + stw r8, 0x0028(r1) + lwz r8, 0x015c(r6) + stw r8, 0x002c(r1) + lwz r8, 0x0164(r6) + stw r8, 0x0030(r1) + lwz r8, 0x016c(r6) + stw r8, 0x0034(r1) + stmw r14, 0x0038(r1) + lwz r8, -0x0004(r1) + lwz r17, 0x0024(r9) + lwz r20, 0x0028(r9) + lwz r21, 0x002c(r9) + lwz r19, 0x0034(r9) + lwz r18, 0x003c(r9) + rlwinm r16, r7, 0, 28, 26 + lwz r25, 0x0650(r8) + rlwinm. r22, r17, 31, 27, 31 + add r19, r19, r22 + rlwimi r25, r17, 7, 25, 30 + lhz r26, 0x0d20(r25) + rlwimi r25, r19, 1, 28, 30 + stw r16, -0x0010(r1) + rlwimi r26, r26, 8, 8, 15 ; copy hi byte of entry to second byte of word + rlwimi r25, r17, 4, 23, 27 + mtcrf 0x10, r26 ; so the second nybble of the entry is copied to cr3 + lha r22, 0x0c00(r25) + addi r23, r8, 0x4e0 + add r22, r22, r25 + mfsprg r24, 3 + mtlr r22 + mtsprg 3, r23 + mfmsr r14 + ori r15, r14, 0x10 + mtmsr r15 + isync + rlwimi r25, r26, 2, 22, 29 ; apparently the lower byte of the entry is an FDP (code?) offset, /4! + bnelr- + b FDP_011c + + + +major_0x02ccc_0x108 ; OUTSIDE REFERER + bl Save_r14_r31 ; r8 := EWA + + lwz r31, EWA.PA_CurTask(r8) + lwz r8, 0x00f4(r31) + +; r8 = id + bl LookupID + cmpwi r9, Queue.kIDClass + + mr r30, r8 + bnel- major_0x02ccc_0x20c + lwz r28, 0x0028(r30) + cmpwi r28, 0x00 + beql- major_0x02ccc_0x20c + + _Lock PSA.SchLock, scratch1=r8, scratch2=r9 + + lwz r29, 0x0064(r31) + ori r29, r29, 0x200 + ori r29, r29, 0x1000 + stw r29, 0x0064(r31) + lwz r17, 0x0008(r28) + stw r17, 0x0028(r30) + lwz r17, 0x0000(r31) + stw r17, 0x0010(r28) + li r18, -0x7271 + stw r18, 0x0014(r28) + stw r18, 0x00f8(r31) + stw r10, 0x0018(r28) + _log 'Blue task suspended. Notifying exception handler - srr1/0 ' + mr r8, r11 + bl Printw + mr r8, r10 + bl Printw + _log 'lr ' + mr r8, r12 + bl Printw + _log '^n' + mr r31, r30 + mr r8, r28 + bl major_0x0c8b4 + b major_0x142dc + +major_0x02ccc_0x20c + mflr r16 + _log 'Blue task terminated - no exception handler registered - srr1/0 ' + mr r8, r11 + bl Printw + mr r8, r10 + bl Printw + _log 'lr ' + mr r8, r12 + bl Printw + _log '^n' + mtlr r16 + b Local_Panic + +major_0x02ccc_0x2a4 ; OUTSIDE REFERER + bsol+ cr6, Local_Panic + +; r6 = ewa + bl Save_r14_r31 +; r8 = sprg0 (not used by me) + + mr r30, r10 + lwz r29, 0x0018(r8) + lwz r31, -0x0008(r8) + stw r29, 0x0134(r6) + stw r30, 0x0074(r6) + stw r7, 0x0040(r6) + lwz r1, -0x0004(r1) + + _Lock PSA.SchLock, scratch1=r28, scratch2=r29 + + mr r8, r31 + bl major_0x13e4c + lwz r16, 0x0064(r31) + srwi r8, r7, 24 + rlwinm. r16, r16, 0, 9, 9 + cmpwi cr1, r8, 0x0c + bne- major_0x02ccc_0x524 + bne- cr1, major_0x02ccc_0x524 + lwz r8, 0x00e0(r31) + addi r8, r8, 0x01 + stw r8, 0x00e0(r31) + b major_0x02ccc_0x380 + +major_0x02ccc_0x310 ; OUTSIDE REFERER + bnsl+ cr6, Local_Panic + bl major_0x02980_0x114 + stw r10, 0x0084(r6) + rlwinm r7, r7, 0, 28, 26 + +; r6 = ewa + bl Save_r14_r31 +; r8 = sprg0 (not used by me) + + lwz r30, 0x0074(r6) + lwz r29, 0x0018(r8) + lwz r31, -0x0008(r8) + stw r29, 0x0134(r6) + stw r7, 0x0040(r6) + lwz r1, -0x0004(r1) + + _Lock PSA.SchLock, scratch1=r28, scratch2=r29 + + mr r8, r31 + bl major_0x13e4c + lwz r16, 0x0064(r31) + srwi r8, r7, 24 + rlwinm. r16, r16, 0, 9, 9 + cmpwi cr1, r8, 0x14 + bne- major_0x02ccc_0x524 + bne- cr1, major_0x02ccc_0x524 + lwz r8, 0x00e4(r31) + addi r8, r8, 0x01 + stw r8, 0x00e4(r31) + +major_0x02ccc_0x380 + mfsprg r14, 0 + rlwinm r7, r7, 0, 27, 25 + rlwinm r7, r7, 0, 0, 30 + lwz r29, -0x00e4(r14) + lis r17, 0x4152 + ori r17, r17, 0x4541 + lwz r16, 0x0004(r29) + cmplw r16, r17 + bnel+ Local_Panic + lwz r17, 0x0034(r29) + addi r17, r17, 0x01 + stw r17, 0x0034(r29) + lwz r8, 0x0018(r29) + +; r8 = id + bl LookupID +; r8 = something not sure what +; r9 = 0:inval, 1:proc, 2:task, 3:timer, 4:q, 5:sema, 6:cr, 7:cpu, 8:addrspc, 9:evtg, 10:cohg, 11:area, 12:not, 13:log + + lwz r16, 0x06b4(r1) + cmpwi r9, 0x0c + cmpwi cr1, r16, 0x00 + mr r26, r8 + bne- major_0x02ccc_0x430 + beq- cr1, major_0x02ccc_0x3d4 + beq- cr2, major_0x02ccc_0x430 + +major_0x02ccc_0x3d4 + lwz r16, 0x0064(r31) + addi r17, r31, 0x08 + addi r18, r31, 160 + stw r18, 0x0000(r17) + stw r18, 0x0008(r17) + lwz r19, 0x000c(r18) + stw r19, 0x000c(r17) + stw r17, 0x0008(r19) + stw r17, 0x000c(r18) + li r17, 0x01 + ori r16, r16, 0x2000 + stw r17, 0x00b0(r31) + stw r16, 0x0064(r31) + rlwinm r30, r30, 0, 0, 19 + lwz r27, 0x0000(r29) + lwz r28, 0x0000(r31) + stw r30, 0x0010(r26) + stw r27, 0x0014(r26) + stw r28, 0x0018(r26) + mr r30, r26 + bl major_0x0db04 + cmpwi r8, 0x00 + beq+ major_0x02964 + +major_0x02ccc_0x430 + mfcr r28 + li r8, 0x1c + beq- cr2, major_0x02ccc_0x4a8 + bl PoolAlloc_with_crset + mr. r26, r8 + beq- major_0x02ccc_0x50c + addi r17, r31, 0x08 + addi r18, r31, 160 + stw r18, 0x0000(r17) + stw r18, 0x0008(r17) + lwz r19, 0x000c(r18) + stw r19, 0x000c(r17) + stw r17, 0x0008(r19) + stw r17, 0x000c(r18) + li r17, 0x01 + stw r17, 0x00b0(r31) + lwz r27, 0x0000(r29) + lis r8, 0x6e6f + ori r8, r8, 0x7465 + lwz r29, 0x00a0(r31) + stw r27, 0x0010(r26) + stw r29, 0x0014(r26) + stw r8, 0x0004(r26) + stw r30, 0x0018(r26) + mr r8, r26 + addi r31, r1, -0xa24 + bl major_0x0c8b4 + lwz r8, -0x0410(r1) + bl major_0x0dce8 + b AlternateMPCallReturnPath + +major_0x02ccc_0x4a8 + mr r8, r31 + bl TaskReadyAsPrev + sync + lwz r31, PSA.SchLock + Lock.Count(r1) + cmpwi cr1, r31, 0x00 + li r31, 0x00 + bne+ cr1, major_0x02ccc_0x4cc + mflr r31 + bl panic + +major_0x02ccc_0x4cc + stw r31, PSA.SchLock + Lock.Count(r1) + mtcr r28 + bns- cr6, major_0x02ccc_0x504 + lwz r8, 0x0064(r6) + lwz r9, 0x0068(r6) + stw r8, 0x0024(r6) + stw r9, 0x0028(r6) + lwz r8, 0x006c(r6) + lwz r9, 0x0074(r6) + stw r8, 0x002c(r6) + stw r9, 0x0034(r6) + lwz r8, 0x007c(r6) + stw r8, 0x003c(r6) + crclr cr6_so + +major_0x02ccc_0x504 +; r6 = ewa + bl Restore_r14_r31 + b major_0x02980_0x178 + +major_0x02ccc_0x50c + li r16, 0x02 + stb r16, 0x0019(r31) + mr r8, r31 + bl TaskReadyAsPrev + bl major_0x14af8_0xa0 + b AlternateMPCallReturnPath + +major_0x02ccc_0x524 + b FuncExportedFromTasks + + + +; IntDecrementer + +; Xrefs: +; "vec" + + align kIntAlign + +IntDecrementer ; OUTSIDE REFERER +; r6 = saved at *(ewa + 0x18) +; sprg1 = saved at *(ewa + 4) +; rN (0,7,8,9,10,11,12,13, not r1) = saved at *(*(ewa - 0x14) + 0x104 + 8*N) + bl int_prepare +; r0 = 0 +; r1 = *(ewa - 4) +; r6 = kdp +; r7 = *(ewa - 0x10) # flags? +; r8 = ewa +; r10 = srr0 +; r11 = srr1 +; r12 = sprg2 +; r13 = cr + + lwz r8, 0x05a0(r1) + rlwinm. r9, r11, 0, 16, 16 + cmpwi cr1, r8, 0x00 + beq- MaskedInterruptTaken + beq- cr1, IntDecrementer_0x54 + + stw r16, 0x0184(r6) + stw r17, 0x018c(r6) + stw r18, 0x0194(r6) + stw r25, 0x01cc(r6) + bl major_0x14a98 + ble- IntDecrementer_0x48 + lwz r8, -0x09d4(r1) + mtspr dec, r8 + lwz r16, 0x0184(r6) + lwz r17, 0x018c(r6) + lwz r18, 0x0194(r6) + b skeleton_key + +IntDecrementer_0x48 + lwz r16, 0x0184(r6) + lwz r17, 0x018c(r6) + lwz r18, 0x0194(r6) + +IntDecrementer_0x54 +; r6 = ewa + bl Save_r14_r31 +; r8 = sprg0 (not used by me) + + + _Lock PSA.SchLock, scratch1=r8, scratch2=r9 + + lwz r8, 0x0e8c(r1) + addi r8, r8, 0x01 + stw r8, 0x0e8c(r1) + bl TimerDispatch + sync + lwz r8, PSA.SchLock + Lock.Count(r1) + cmpwi cr1, r8, 0x00 + li r8, 0x00 + bne+ cr1, IntDecrementer_0x9c + mflr r8 + bl panic + +IntDecrementer_0x9c + stw r8, PSA.SchLock + Lock.Count(r1) + +; r6 = ewa + bl Restore_r14_r31 + b skeleton_key + + + +; IntDSI + +; Xrefs: +; "vec" + + align kIntAlign + +IntDSI ; OUTSIDE REFERER + mfsprg r1, 0 + stmw r2, 0x0008(r1) + mfsprg r11, 1 + stw r0, 0x0000(r1) + stw r11, 0x0004(r1) + li r0, 0x00 + mfspr r10, srr0 + mfspr r11, srr1 + mfsprg r12, 2 + mfcr r13 + mfsprg r24, 3 + lwz r16, -0x0010(r1) + lwz r1, -0x0004(r1) + mfspr r26, dsisr + addi r23, r1, 0x4e0 + andis. r28, r26, 0x400 + mtsprg 3, r23 + mfmsr r14 + bne- major_0x03324_0x9c + ori r15, r14, 0x10 + mtmsr r15 + isync + lwz r27, 0x0000(r10) + mtmsr r14 + isync + + + +; major_0x03324 + +; Xrefs: +; IntDSI +; FDP_1214 + +major_0x03324 ; OUTSIDE REFERER + rlwinm. r18, r27, 18, 25, 29 + lwz r25, 0x0650(r1) + li r21, 0x00 + mfsprg r1, 0 + beq- major_0x03324_0x18 + lwzx r18, r1, r18 + +major_0x03324_0x18 + andis. r26, r27, 0xec00 + lwz r16, -0x0010(r1) + rlwinm r17, r27, 0, 6, 15 + rlwimi r16, r16, 27, 26, 26 + bge- major_0x03324_0x58 + rlwimi r25, r27, 7, 26, 29 + rlwimi r25, r27, 12, 25, 25 + lwz r26, 0x0b80(r25) + extsh r23, r27 + rlwimi r25, r26, 26, 22, 29 + mtlr r25 + mtcr r26 + add r18, r18, r23 + crclr cr5_so + rlwimi r17, r26, 6, 26, 5 + blr + +major_0x03324_0x58 + rlwimi r25, r27, 27, 26, 29 + rlwimi r25, r27, 0, 25, 25 + rlwimi r25, r27, 6, 23, 24 + rlwimi r25, r27, 4, 22, 22 + lwz r26, 0x0800(r25) + rlwinm r23, r27, 23, 25, 29 + rlwimi r25, r26, 26, 22, 29 + mtlr r25 + mtcr r26 + lwzx r23, r1, r23 + crclr cr5_so + rlwimi r17, r26, 6, 26, 5 + add r18, r18, r23 + blelr- cr3 + neg r23, r23 + add r18, r18, r23 + blr + +major_0x03324_0x9c ; OUTSIDE REFERER + ori r15, r14, 0x10 + mr r28, r16 + mfspr r18, dar + mfspr r19, dsisr + mtmsr r15 + isync + lwz r27, 0x0000(r10) + mtmsr r14 + isync + mtsprg 3, r24 + lwz r1, -0x0004(r1) + mr r31, r19 + mr r8, r18 + li r9, 0x00 + bl V2P + mr r16, r28 + crset cr3_so + mfsprg r1, 0 + beq- major_0x03324_0x12c + mr r18, r8 + rlwinm r28, r27, 13, 25, 29 + andis. r9, r31, 0x200 + rlwimi r18, r17, 0, 0, 19 + beq- major_0x03324_0x118 + lwzx r31, r1, r28 + stwcx. r31, 0, r18 + sync + dcbf 0, r18 + mfcr r31 + rlwimi r13, r31, 0, 0, 3 + b FDP_0da0 + +major_0x03324_0x118 + lwarx r31, 0, r18 + sync + dcbf 0, r18 + stwx r31, r1, r28 + b FDP_0da0 + +major_0x03324_0x12c + subi r10, r10, 4 + b FDP_0da0 + + + +; IntAlignment + +; Xrefs: +; "vec" + +; This int handler is our best foothold into the FDP! + + align kIntAlign + +IntAlignment ; OUTSIDE REFERER + mfsprg r1, 0 + stmw r2, 0x0008(r1) + mfsprg r11, 1 + stw r0, 0x0000(r1) + stw r11, 0x0004(r1) + li r0, 0x00 + + lwz r11, EWA.PA_CurTask(r1) + lwz r16, EWA.Flags(r1) + lwz r21, Task.ThingThatAlignVecHits(r11) + lwz r1, -0x0004(r1) ; wha??? + + lwz r11, KDP.NanoKernelInfo + NKNanoKernelInfo.MisalignmentCount(r1) + addi r11, r11, 1 + stw r11, KDP.NanoKernelInfo + NKNanoKernelInfo.MisalignmentCount(r1) + + mfspr r10, srr0 + mfspr r11, srr1 + mfsprg r12, 2 + mfcr r13 + mfsprg r24, 3 + mfspr r27, dsisr + mfspr r18, dar + + rlwinm. r21, r21, 0, 9, 9 ; KDP.ThingThatAlignVecHits + + addi r23, r1, KDP.RedVecBase + + bne- major_0x03548_0x20 + + ; DSISR for misaligned X-form instruction: + + ; (0) 0 (14)||(15) 29:30 (16)||(17) 25 (17)||(18) 21:24 (21)||(22) rD (26)||(27) rA? (31) + + ; DSISR for misaligned D-form instruction: + + ; (0) zero (16)||(17) 5 (17)||(18) 1:4 (21)||(22) rD (26)||(27) rA? (31) + +FDP_TableBase equ 0xa00 + + ; Virtual PC might put the thing in MSR_LE mode + rlwinm. r21, r11, 0, MSR_LEbit, MSR_LEbit ; msr bits in srr1 + + ; Get the FDP and F.O. if we were in MSR_LE mode + lwz r25, KDP.PA_FDP(r1) + bne- major_0x03548_0x20 + + + rlwinm. r21, r27, 17, 30, 31 ; evaluate hi two bits of XO (or 0 for d-form?) + + rlwinm r17, r27, 16, 6, 15 ; save src and dest register indices in r17 + + mfsprg r1, 0 + + rlwimi r25, r27, 24, 23, 29 ; add constant fields from dsisr (*4) to FDP + + + rlwimi r16, r16, 27, 26, 26 ; AllCpuFeatures: copy bit 21 to bit 26 + + bne- @regidx + + ; D-form (immediate-indexed) instruction + lwz r26, FDP_TableBase + 4*(0x40 + 0x20)(r25) ; use upper quarter of table + mfmsr r14 + rlwimi r25, r26, 26, 22, 29 ; third byte of lookup value is a /4 code offset in FDP + mtlr r25 ; so get ready to go there + ori r15, r14, 0x10 + mtcr r26 + rlwimi r17, r26, 6, 26, 5 ; wrap some shite around the register values + crclr cr5_so + blr + +@regidx + ; X-form (register-indexed) instruction + lwz r26, FDP_TableBase(r25) + mfmsr r14 + mtsprg 3, r23 + rlwimi r25, r26, 26, 22, 29 + mtlr r25 + ori r15, r14, 0x10 + mtcr r26 + rlwimi r17, r26, 6, 26, 5 + crclr 23 ; unset bit 23 = cr5_so + bgelr- cr3 ; jump now if bit 12 is off + + ; if bit 12 was on, turn on paging and fetch the offending insn + ; and also activate the Red vector table + mtmsr r15 + isync + lwz r27, 0x0000(r10) + mtmsr r14 + isync + mtsprg 3, r24 + blr + + + +; major_0x03548 + +; Xrefs: +; IntAlignment +; major_0x05808 + +major_0x03548 ; OUTSIDE REFERER + sync + mtmsr r14 + isync + mflr r23 + icbi 0, r23 + sync + isync + blr + +major_0x03548_0x20 ; OUTSIDE REFERER + li r8, 0x00 + lis r17, -0x100 + mtcr r8 + mr r19, r18 + rlwimi r17, r27, 7, 31, 31 + xori r17, r17, 0x01 + li r8, 0x18 + b major_0x02980 + + + +; IntDSIOtherOther + +; Xrefs: +; "vec" + + align kIntAlign + +IntDSIOtherOther ; OUTSIDE REFERER + mfsprg r1, 0 + mfspr r31, dsisr + mfspr r27, dar + andis. r28, r31, 0xc030 + lwz r1, -0x0004(r1) + bne- IntDSIOtherOther_0x1c8 + mfspr r30, srr1 + andi. r28, r30, 0x4000 + mfsprg r30, 0 + beq- IntDSIOtherOther_0x100 + stw r8, -0x00e0(r30) + stw r9, -0x00dc(r30) + mfcr r8 + stw r16, -0x00d8(r30) + stw r17, -0x00d4(r30) + stw r18, -0x00d0(r30) + stw r19, -0x00cc(r30) + stw r8, -0x00c8(r30) + lwz r8, -0x001c(r30) + mr r9, r27 + bl FindAreaAbove + lwz r16, 0x0024(r8) + lwz r17, 0x0028(r8) + cmplw r27, r16 + cmplw cr7, r27, r17 + blt- IntDSIOtherOther_0xe0 + bgt- cr7, IntDSIOtherOther_0xe0 + mr r31, r8 + mr r8, r27 + bl MPCall_95_0x1e4 + beq- IntDSIOtherOther_0xe0 + lwz r8, 0x0000(r30) + lwz r16, 0x0098(r31) + rlwinm r28, r8, 0, 29, 30 + cmpwi cr7, r28, 0x04 + cmpwi r28, 0x02 + beq- cr7, IntDSIOtherOther_0xe0 + beq- IntDSIOtherOther_0xe0 + +IntDSIOtherOther_0x98 + addi r17, r31, 0x90 + cmpw r16, r17 + addi r17, r16, 0x14 + beq- IntDSIOtherOther_0x158 + lwz r9, 0x0010(r16) + add r9, r9, r17 + +IntDSIOtherOther_0xb0 + lwz r18, 0x0000(r17) + cmplw cr7, r17, r9 + lwz r19, 0x0004(r17) + bgt- cr7, IntDSIOtherOther_0xd8 + cmplw r27, r18 + cmplw cr7, r27, r19 + blt- IntDSIOtherOther_0xd0 + ble- cr7, IntDSIOtherOther_0xe0 + +IntDSIOtherOther_0xd0 + addi r17, r17, 0x08 + b IntDSIOtherOther_0xb0 + +IntDSIOtherOther_0xd8 + lwz r16, 0x0008(r16) + b IntDSIOtherOther_0x98 + +IntDSIOtherOther_0xe0 + mfsprg r30, 0 + mfspr r31, dsisr + lwz r8, -0x00e0(r30) + lwz r9, -0x00dc(r30) + lwz r16, -0x00d8(r30) + lwz r17, -0x00d4(r30) + lwz r18, -0x00d0(r30) + lwz r19, -0x00cc(r30) + +IntDSIOtherOther_0x100 + andis. r28, r31, 0x800 + addi r29, r1, 800 + bnel- PagingFunc3 + li r28, 0x43 + and r28, r31, r28 + cmpwi cr7, r28, 0x43 + beql+ Local_Panic + mfsprg r28, 2 + mtlr r28 + bne- cr7, IntDSIOtherOther_0x144 + mfspr r28, srr0 + addi r28, r28, 0x04 + lwz r26, 0x0e90(r1) + mtspr srr0, r28 + addi r26, r26, 0x01 + stw r26, 0x0e90(r1) + b IntDSIOtherOther_0x19c + +IntDSIOtherOther_0x144 + andi. r28, r31, 0x03 + li r8, 0x16 + beq+ major_0x02980 + li r8, 0x15 + b major_0x02980 + +IntDSIOtherOther_0x158 + mfsprg r30, 0 + lwz r16, 0x0f00(r1) + lwz r8, -0x00c8(r30) + addi r16, r16, 0x01 + mtcr r8 + lwz r9, -0x00dc(r30) + stw r16, 0x0f00(r1) + lwz r16, -0x00d8(r30) + lwz r17, -0x00d4(r30) + lwz r18, -0x00d0(r30) + lwz r19, -0x00cc(r30) + lwz r8, -0x00e0(r30) + mfspr r29, srr1 + mfsprg r28, 2 + rlwinm r29, r29, 0, 18, 16 + mtlr r28 + mtspr srr1, r29 + +IntDSIOtherOther_0x19c + mfsprg r1, 1 + rlwinm r26, r25, 30, 24, 31 + rfi + dcb.b 32, 0 + + +IntDSIOtherOther_0x1c8 + andis. r28, r31, 0x8010 + bne- IntMachineCheckMemRetry_0x14c + + _Lock PSA.HTABLock, scratch1=r28, scratch2=r31 + + bl PagingFunc1 + sync + lwz r28, -0x0b90(r1) + cmpwi cr1, r28, 0x00 + li r28, 0x00 + bne+ cr1, IntDSIOtherOther_0x208 + mflr r28 + bl panic + +IntDSIOtherOther_0x208 + stw r28, -0x0b90(r1) + mfsprg r28, 2 + mtlr r28 + beq+ IntDSIOtherOther_0x19c + li r8, 0x12 + bge+ major_0x02980 + li r8, 0x14 + b major_0x02980 + + + +; IntMachineCheckMemRetry + +; Xrefs: +; "vec" +; IntDSIOtherOther + +IntMachineCheckMemRetry ; OUTSIDE REFERER + mfsprg r1, 0 + mr r28, r8 + + lwz r27, EWA.CPUBase + CPU.ID(r1) + _log 'CPU ' + mr r8, r27 + bl Printw + + _log 'MemRetry machine check - last EA ' + lwz r1, EWA.PA_KDP(r1) + lwz r27, 0x0694(r1) + mr r8, r27 + bl Printw + + _log ' SRR1 ' + mfspr r8, srr1 + mr r8, r8 + bl Printw + + _log ' SRR0 ' + mfspr r8, srr0 + mr r8, r8 + bl Printw + _log '^n' + + mr r8, r28 + lwz r1, EWA.PA_KDP(r1) + lwz r27, 0x0694(r1) + subf r28, r19, r27 + cmpwi r28, -0x10 + blt- IntMachineCheckMemRetry_0x14c + cmpwi r28, 0x10 + bgt- IntMachineCheckMemRetry_0x14c + + _Lock PSA.HTABLock, scratch1=r28, scratch2=r29 + + lwz r28, 0x0e98(r1) + addi r28, r28, 0x01 + stw r28, 0x0e98(r1) + lwz r29, 0x0698(r1) + li r28, 0x00 + stw r28, 0x0000(r29) + mfspr r28, pvr + rlwinm. r28, r28, 0, 0, 14 + sync + tlbie r27 + beq- IntMachineCheckMemRetry_0x124 + sync + tlbsync + +IntMachineCheckMemRetry_0x124 + sync + isync + sync + lwz r28, -0x0b90(r1) + cmpwi cr1, r28, 0x00 + li r28, 0x00 + bne+ cr1, IntMachineCheckMemRetry_0x148 + mflr r28 + bl panic + +IntMachineCheckMemRetry_0x148 + stw r28, -0x0b90(r1) + +IntMachineCheckMemRetry_0x14c ; OUTSIDE REFERER + cmplw r10, r19 + li r8, 0x13 + bne+ major_0x02980 + mfsprg r1, 0 + mtsprg 3, r24 + lmw r14, 0x0038(r1) + li r8, 0x0b + b major_0x02980_0x134 + + + +; IntISI + +; Xrefs: +; "vec" + + align kIntAlign + +IntISI ; OUTSIDE REFERER +; r6 = saved at *(ewa + 0x18) +; sprg1 = saved at *(ewa + 4) +; rN (0,7,8,9,10,11,12,13, not r1) = saved at *(*(ewa - 0x14) + 0x104 + 8*N) + bl int_prepare +; r0 = 0 +; r1 = *(ewa - 4) +; r6 = kdp +; r7 = *(ewa - 0x10) # flags? +; r8 = ewa +; r10 = srr0 +; r11 = srr1 +; r12 = sprg2 +; r13 = cr + + andis. r8, r11, 0x4020 + beq- major_0x039dc_0x14 + mfsprg r8, 0 + stmw r14, 0x0038(r8) + + _Lock PSA.HTABLock, scratch1=r28, scratch2=r31 + + mr r27, r10 + bl PagingFunc1 + sync + lwz r28, -0x0b90(r1) + cmpwi cr1, r28, 0x00 + li r28, 0x00 + bne+ cr1, IntISI_0x50 + mflr r28 + bl panic + +IntISI_0x50 + stw r28, -0x0b90(r1) + mfsprg r8, 0 + bne- major_0x039dc + mfsprg r24, 3 + mfmsr r14 + ori r15, r14, 0x10 + addi r23, r1, 0x4e0 + mtsprg 3, r23 + mr r19, r10 + mtmsr r15 + isync + lbz r23, 0x0000(r19) + sync + mtmsr r14 + isync + mfsprg r8, 0 + mtsprg 3, r24 + lmw r14, 0x0038(r8) + b skeleton_key + + + +; major_0x039dc + +; Xrefs: +; IntISI +; IntDSIOther + +major_0x039dc ; OUTSIDE REFERER + lmw r14, 0x0038(r8) + li r8, 0x0c + blt+ major_0x02980_0x134 + li r8, 0x0a + b major_0x02980_0x134 + +major_0x039dc_0x14 ; OUTSIDE REFERER + andis. r8, r11, 0x800 + li r8, 0x0e + bne+ major_0x02980_0x134 + li r8, 0x0b + b major_0x02980_0x134 + + + +; IntMachineCheck + +; Xrefs: +; "vec" + +IntMachineCheck ; OUTSIDE REFERER +; r6 = saved at *(ewa + 0x18) +; sprg1 = saved at *(ewa + 4) +; rN (0,7,8,9,10,11,12,13, not r1) = saved at *(*(ewa - 0x14) + 0x104 + 8*N) + bl int_prepare +; r0 = 0 +; r1 = *(ewa - 4) +; r6 = kdp +; r7 = *(ewa - 0x10) # flags? +; r8 = ewa +; r10 = srr0 +; r11 = srr1 +; r12 = sprg2 +; r13 = cr + + lwz r9, EWA.CPUBase + CPU.ID(r8) + _log 'CPU ' + mr r8, r9 + bl Printw + + _log 'Machine check at ' ; srr1/srr0 + mr r8, r11 + bl Printw + mr r8, r10 + bl Printw + + _log '- last unmapped EA ' + lwz r8, 0x0694(r1) + mr r8, r8 + bl Printw + _log '^n' + + rlwinm. r8, r11, 0, 2, 2 + beq- IntMachineCheck_0xa4 + bl kcCacheDispatch_0x39c + b skeleton_key + +IntMachineCheck_0xa4 + li r8, 0x07 + b major_0x02980_0x134 + + + +; MaskedInterruptTaken + +; Xrefs: +; IntDecrementer +; IntPerfMonitor +; IntThermalEvent +; IntExternalYellow + +MaskedInterruptTaken ; OUTSIDE REFERER + _log '*** CPU MALFUNCTION - Masked interrupt punched through. SRR1/0 ' + mr r8, r11 + bl Printw + mr r8, r10 + bl Printw + _log '^n' + lis r10, -0x4523 + ori r10, r10, 0xcb00 + li r8, 0x07 + b major_0x02980_0x134 + + + +; IntDSIOther + +; Xrefs: +; "vec" + + align kIntAlign + +IntDSIOther ; OUTSIDE REFERER + mfspr r8, dsisr + rlwimi r11, r8, 0, 0, 9 + andis. r8, r11, 0x4020 + beq+ major_0x039dc_0x14 + mfsprg r8, 0 + stmw r14, 0x0038(r8) + lwz r1, -0x0004(r8) + + _Lock PSA.HTABLock, scratch1=r28, scratch2=r31 + + mfspr r27, dar + bl PagingFunc1 + sync + lwz r28, -0x0b90(r1) + cmpwi cr1, r28, 0x00 + li r28, 0x00 + bne+ cr1, IntDSIOther_0x58 + mflr r28 + bl panic + +IntDSIOther_0x58 + stw r28, -0x0b90(r1) + mfsprg r8, 0 + bne+ major_0x039dc + lmw r14, 0x0038(r8) + mfsprg r1, 2 + mtlr r1 + mfsprg r1, 1 + rfi + dcb.b 32, 0 + + + + +; major_0x03be0 + +; Xrefs: +; "sup" + + align kIntAlign + +; dead code? + + dc.l 0x81610e40 + dc.l 0x7d8a6378 + dc.l 0x396b0001 + dc.l 0x91610e40 + dc.l 0x7d7b02a6 + dc.l 0x50e7deb4 + +kcReturnFromException ; OUTSIDE REFERER + ori r11, r11, 0x8000 + mtcrf 0x3f, r7 + cmplwi cr1, r3, 0x01 + blt- cr4, major_0x04a20_0x18 + blt- cr1, major_0x03be0_0x58 + beq- cr1, major_0x03be0_0x90 + addi r8, r3, -0x20 + lwz r9, 0x0eac(r1) + cmplwi r8, 0xe0 + addi r9, r9, 0x01 + stw r9, 0x0eac(r1) + mfsprg r1, 0 + rlwimi r7, r3, 24, 0, 7 + blt- major_0x03be0_0xe8 + li r8, 0x02 + b major_0x02980_0x134 + +major_0x03be0_0x58 + mfsprg r1, 0 + lwz r8, 0x0040(r6) + lwz r10, 0x0084(r6) + rlwimi r7, r8, 0, 17, 7 + lwz r8, 0x0044(r6) + rlwimi r11, r7, 0, 20, 23 + stw r8, -0x000c(r1) + andi. r8, r11, 0x900 + lwz r12, 0x008c(r6) + lwz r3, 0x0094(r6) + lwz r4, 0x009c(r6) + bnel- major_0x03e18 + addi r9, r6, 0x40 + b skeleton_key + +major_0x03be0_0x90 + lwz r9, 0x0ea8(r1) + lwz r8, 0x0040(r6) + addi r9, r9, 0x01 + stw r9, 0x0ea8(r1) + mfsprg r1, 0 + lwz r10, 0x0084(r6) + rlwimi r7, r8, 0, 17, 7 + lwz r8, 0x0044(r6) + mtcrf 0x0f, r7 + rlwimi r11, r7, 0, 20, 23 + stw r8, -0x000c(r1) + lwz r12, 0x008c(r6) + lwz r3, 0x0094(r6) + lwz r4, 0x009c(r6) + bne- cr2, major_0x03be0_0xe8 + bns- cr6, major_0x03be0_0xe8 + stmw r14, 0x0038(r1) + lwz r17, 0x0064(r6) + lwz r20, 0x0068(r6) + lwz r21, 0x006c(r6) + lwz r19, 0x0074(r6) + lwz r18, 0x007c(r6) + +major_0x03be0_0xe8 + beq+ cr2, major_0x02980_0x178 + crclr cr6_so + mfspr r10, srr0 + li r8, 0x02 + b major_0x02980_0x134 + + + +; save_all_registers + +; Xrefs: +; IntPerfMonitor +; IntThermalEvent + + align 5 + +save_all_registers ; OUTSIDE REFERER + mfsprg r1, 0 + stw r6, 0x0018(r1) + mfsprg r6, 1 + stw r6, 0x0004(r1) + lwz r6, -0x0014(r1) + stw r0, 0x0104(r6) + stw r7, 0x013c(r6) + stw r8, 0x0144(r6) + stw r9, 0x014c(r6) + stw r10, 0x0154(r6) + stw r11, 0x015c(r6) + stw r12, 0x0164(r6) + stw r13, 0x016c(r6) + li r0, 0x00 + mfspr r10, srr0 + mfspr r11, srr1 + mfcr r13 + mfsprg r12, 2 + lwz r7, -0x0010(r1) + lwz r1, -0x0004(r1) + +; r6 = ewa + b Save_r14_r31 +; r8 = sprg0 (not used by me) + + + +; How we arrive here: +; +; PowerPC exception vector saved r1/LR in SPRG1/2 and +; jumped where directed by the vecTable pointed to by +; SPRG3. That function bl'ed here. +; +; +; When we arrive here: +; +; r1 is saved in SPRG1 (r1 itself is junk) +; LR is saved in SPRG2 (LR itself contains return addr) +; +; +; Before we return: +; +; Reg Contains Original saved in +; --------------------------------------------- +; r0 0 ContextBlock +; r1 KDP EWA +; r2 (itself) +; r3 (itself) +; r4 (itself) +; r5 (itself) +; r6 ContextBlock EWA +; r7 AllCpuFeatures ContextBlock +; r8 EWA ContextBlock +; r9 (itself) ContextBlock +; r10 SRR0 ContextBlock +; r11 SRR1 ContextBlock +; r12 LR ContextBlock +; r13 CR ContextBlock +; +; +; Can be followed up by a call to Save_r14_r31, +; (which will put them in the ContextBlock too). + + align 5 + +int_prepare + + ; Get EWA pointer in r1 (phew) + mfsprg r1, 0 + + ; Save r6 in EWA + stw r6, EWA.r6(r1) + + ; Save pre-interrupt r1 (which SPRG1 held) to EWA + mfsprg r6, 1 + stw r6, EWA.r1(r1) + + ; Get ContextBlock pointer in r6 (phew) + lwz r6, EWA.PA_ContextBlock(r1) + + ; Save r0, r7-r13 in ContextBlock + stw r0, ContextBlock.r0(r6) + stw r7, ContextBlock.r7(r6) + stw r8, ContextBlock.r8(r6) + stw r9, ContextBlock.r9(r6) + stw r10, ContextBlock.r10(r6) + stw r11, ContextBlock.r11(r6) + stw r12, ContextBlock.r12(r6) + stw r13, ContextBlock.r13(r6) + + ; Zero r0 (convenient) + li r0, 0 + + ; Make some useful special registers conveniently available + mfspr r10, srr0 + mfspr r11, srr1 + mfcr r13 + mfsprg r12, 2 + + ; Point r8 to EWA + mr r8, r1 + + ; Features in r7, KDP in r8 + lwz r7, EWA.Flags(r1) + lwz r1, EWA.PA_KDP(r1) + + blr + + + +; IntFPUnavail + +; Xrefs: +; "vec" + + align kIntAlign + +IntFPUnavail ; OUTSIDE REFERER + mfsprg r1, 0 + stw r11, -0x0290(r1) + stw r6, -0x028c(r1) + lwz r6, -0x0004(r1) + lwz r11, 0x0e88(r6) + addi r11, r11, 0x01 + stw r11, 0x0e88(r6) + mfspr r11, srr1 + ori r11, r11, 0x2000 + mtspr srr1, r11 + mfmsr r11 + ori r11, r11, 0x2000 + lwz r6, -0x0014(r1) + mtmsr r11 + isync + bl LoadFloatsFromContextBlock + lwz r11, -0x0290(r1) + lwz r6, -0x028c(r1) + mfsprg r1, 2 + mtlr r1 + mfsprg r1, 1 + rfi + dcb.b 32, 0 + + + + +; major_0x03e18 + +; Xrefs: +; major_0x02980 +; major_0x03be0 +; IntFPUnavail +; kcRTASDispatch + +major_0x03e18 ; OUTSIDE REFERER + rlwinm. r8, r11, 0, 18, 18 + bnelr- + +major_0x03e18_0x8 ; OUTSIDE REFERER + lwz r8, 0x00e4(r6) + rlwinm. r8, r8, 1, 0, 0 + mfmsr r8 + ori r8, r8, 0x2000 + beqlr- + mtmsr r8 + isync + ori r11, r11, 0x2000 + +LoadFloatsFromContextBlock ; OUTSIDE REFERER + lfd f31, 0x00e0(r6) + lfd f0, 0x0200(r6) + lfd f1, 0x0208(r6) + lfd f2, 0x0210(r6) + lfd f3, 0x0218(r6) + lfd f4, 0x0220(r6) + lfd f5, 0x0228(r6) + lfd f6, 0x0230(r6) + lfd f7, 0x0238(r6) + mtfsf 0xff, f31 + lfd f8, 0x0240(r6) + lfd f9, 0x0248(r6) + lfd f10, 0x0250(r6) + lfd f11, 0x0258(r6) + lfd f12, 0x0260(r6) + lfd f13, 0x0268(r6) + lfd f14, 0x0270(r6) + lfd f15, 0x0278(r6) + lfd f16, 0x0280(r6) + lfd f17, 0x0288(r6) + lfd f18, 0x0290(r6) + lfd f19, 0x0298(r6) + lfd f20, 0x02a0(r6) + lfd f21, 0x02a8(r6) + lfd f22, 0x02b0(r6) + lfd f23, 0x02b8(r6) + lfd f24, 0x02c0(r6) + lfd f25, 0x02c8(r6) + lfd f26, 0x02d0(r6) + lfd f27, 0x02d8(r6) + lfd f28, 0x02e0(r6) + lfd f29, 0x02e8(r6) + lfd f30, 0x02f0(r6) + lfd f31, 0x02f8(r6) + blr + + + + + +major_0x03e18_0xb4 ; OUTSIDE REFERER + mfmsr r8 + ori r8, r8, 0x2000 + mtmsr r8 + isync + rlwinm r11, r11, 0, 19, 17 + stfd f0, 0x0200(r6) + stfd f1, 0x0208(r6) + stfd f2, 0x0210(r6) + stfd f3, 0x0218(r6) + stfd f4, 0x0220(r6) + stfd f5, 0x0228(r6) + stfd f6, 0x0230(r6) + stfd f7, 0x0238(r6) + stfd f8, 0x0240(r6) + stfd f9, 0x0248(r6) + stfd f10, 0x0250(r6) + stfd f11, 0x0258(r6) + stfd f12, 0x0260(r6) + stfd f13, 0x0268(r6) + stfd f14, 0x0270(r6) + stfd f15, 0x0278(r6) + stfd f16, 0x0280(r6) + stfd f17, 0x0288(r6) + stfd f18, 0x0290(r6) + stfd f19, 0x0298(r6) + stfd f20, 0x02a0(r6) + stfd f21, 0x02a8(r6) + stfd f22, 0x02b0(r6) + stfd f23, 0x02b8(r6) + mffs f0 + stfd f24, 0x02c0(r6) + stfd f25, 0x02c8(r6) + stfd f26, 0x02d0(r6) + stfd f27, 0x02d8(r6) + stfd f28, 0x02e0(r6) + stfd f29, 0x02e8(r6) + stfd f30, 0x02f0(r6) + stfd f31, 0x02f8(r6) + stfd f0, 0x00e0(r6) + blr + + + + +; indexed emulation code, mofo + +;two instructions per load-store register + + macro + CreateFloatJumpTable &opcode, &dest, &highest==31 + + if &highest > 0 + CreateFloatJumpTable &opcode, &dest, highest = (&highest) - 1 + endif + + &opcode (&highest), -0x2e0(r1) + b &dest + + endm + + +FloatLoadJumpTable + CreateFloatJumpTable lfd, FDP_0da0 + + +FloatSaveJumpTable + CreateFloatJumpTable stfd, FDP_003c + + + + +; major_0x04180 + +; Xrefs: +; IntPerfMonitor + + align 6 + +major_0x04180 ; OUTSIDE REFERER + stw r6, -0x0290(r1) + stw r10, -0x028c(r1) + stw r11, -0x0288(r1) + lwz r6, -0x0014(r1) + lwz r10, 0x00d8(r6) + mfspr r11, srr1 + cmpwi r10, 0x00 + beql- major_0x04180_0x9c + oris r11, r11, 0x200 + stw r9, -0x027c(r1) + mtspr srr1, r11 + mfmsr r11 + oris r11, r11, 0x200 + mtmsr r11 + isync + bl Restore_v0_v31 + lwz r8, -0x0004(r1) + lwz r11, 0x0ed4(r8) + addi r11, r11, 0x01 + stw r11, 0x0ed4(r8) + mtcr r13 + lwz r6, -0x0290(r1) + lwz r10, -0x028c(r1) + lwz r11, -0x0288(r1) + lwz r13, -0x0284(r1) + lwz r8, -0x0280(r1) + lwz r9, -0x027c(r1) + mfsprg r1, 2 + mtlr r1 + mfsprg r1, 1 + rfi + dcb.b 32, 0 + + +major_0x04180_0x9c + mtcr r13 + lwz r6, -0x0290(r1) + lwz r10, -0x028c(r1) + lwz r11, -0x0288(r1) + lwz r13, -0x0284(r1) + +; r6 = saved at *(ewa + 0x18) +; sprg1 = saved at *(ewa + 4) +; rN (0,7,8,9,10,11,12,13, not r1) = saved at *(*(ewa - 0x14) + 0x104 + 8*N) + bl int_prepare +; r0 = 0 +; r1 = *(ewa - 4) +; r6 = kdp +; r7 = *(ewa - 0x10) # flags? +; r8 = ewa +; r10 = srr0 +; r11 = srr1 +; r12 = sprg2 +; r13 = cr + + li r8, 0x04 + b major_0x02980_0x134 + + + +; IntPerfMonitor + +; Xrefs: +; "vec" + + align kIntAlign + +IntPerfMonitor ; OUTSIDE REFERER + mtlr r1 + mfsprg r1, 0 + stw r8, -0x0280(r1) + stw r13, -0x0284(r1) + mflr r8 + mfcr r13 + cmpwi r8, 0xf20 + beq+ major_0x04180 + mtcr r13 + lwz r13, -0x0284(r1) + lwz r8, -0x0280(r1) + bl save_all_registers + mr r28, r8 + rlwinm. r9, r11, 0, 16, 16 + beq+ MaskedInterruptTaken + + _Lock PSA.SchLock, scratch1=r8, scratch2=r9 + + lwz r8, -0x0414(r1) + +; r8 = id + bl LookupID + cmpwi r9, Notification.kIDClass + + mr r30, r8 + bne- IntPerfMonitor_0x88 + lwz r16, -0x0340(r28) + lwz r17, -0x0008(r28) + stw r16, 0x0010(r30) + lwz r16, 0x0000(r17) + stw r16, 0x0014(r30) + mfspr r16, 955 + stw r16, 0x0018(r30) + bl major_0x0db04 + +IntPerfMonitor_0x88 + sync + lwz r8, PSA.SchLock + Lock.Count(r1) + cmpwi cr1, r8, 0x00 + li r8, 0x00 + bne+ cr1, IntPerfMonitor_0xa4 + mflr r8 + bl panic + +IntPerfMonitor_0xa4 + stw r8, PSA.SchLock + Lock.Count(r1) + +; r6 = ewa + bl Restore_r14_r31 + b skeleton_key + + + +; IntThermalEvent + +; Xrefs: +; "vec" + + align kIntAlign + +IntThermalEvent ; OUTSIDE REFERER + bl save_all_registers + mr r28, r8 + rlwinm. r9, r11, 0, 16, 16 + beq+ MaskedInterruptTaken + _log 'Thermal event^n' + + _Lock PSA.SchLock, scratch1=r8, scratch2=r9 + + lwz r8, -0x0418(r1) + +; r8 = id + bl LookupID + cmpwi r9, Notification.kIDClass + + mr r30, r8 + bne- IntThermalEvent_0x68 + lwz r16, -0x0340(r28) + stw r16, 0x0010(r30) + bl major_0x0db04 + +IntThermalEvent_0x68 + sync + lwz r8, PSA.SchLock + Lock.Count(r1) + cmpwi cr1, r8, 0x00 + li r8, 0x00 + bne+ cr1, IntThermalEvent_0x84 + mflr r8 + bl panic + +IntThermalEvent_0x84 + stw r8, PSA.SchLock + Lock.Count(r1) + +; r6 = ewa + bl Restore_r14_r31 + b skeleton_key + + + +; kcRunAlternateContext + +; Xrefs: +; "sup" + + align kIntAlign + +kcRunAlternateContext ; OUTSIDE REFERER + mtcrf 0x3f, r7 + bnel+ cr2, skeleton_key + and. r8, r4, r13 + lwz r9, 0x0340(r1) + rlwinm r8, r3, 0, 0, 25 + cmpw cr1, r8, r9 + bne+ skeleton_key + lwz r9, 0x0344(r1) + bne- cr1, major_0x043a0_0x48 + +major_0x043a0_0x24 + addi r8, r1, 0x420 + mtsprg 3, r8 + lwz r8, 0x0648(r1) + mtcrf 0x3f, r7 + mfsprg r1, 0 + clrlwi r7, r7, 0x08 + stw r8, 0x005c(r9) + stw r9, -0x0014(r1) + b major_0x02980_0x18c + +major_0x043a0_0x48 + lwz r9, 0x0348(r1) + cmpw cr1, r8, r9 + beq- cr1, major_0x043a0_0x130 + lwz r9, 0x0350(r1) + cmpw cr1, r8, r9 + beq- cr1, major_0x043a0_0x110 + lwz r9, 0x0358(r1) + cmpw cr1, r8, r9 + beq- cr1, major_0x043a0_0xf0 + mfsprg r1, 0 + stmw r14, 0x0038(r1) + lwz r1, -0x0004(r1) + cmpw cr1, r8, r6 + beq- cr1, major_0x043a0_0x154 + mr r27, r8 + addi r29, r1, 800 + bl PagingFunc3 + clrlwi r23, r8, 0x14 + beq- major_0x043a0_0x154 + cmplwi r23, 0xd00 + mr r9, r8 + mr r8, r31 + ble- major_0x043a0_0xc4 + addi r27, r27, 0x1000 + addi r29, r1, 800 + bl PagingFunc3 + beq- major_0x043a0_0x154 + addi r31, r31, -0x1000 + xor r23, r8, r31 + rlwinm. r23, r23, 0, 25, 22 + bne- major_0x043a0_0x154 + +major_0x043a0_0xc4 + clrlwi r23, r31, 0x1e + cmpwi r23, 0x03 + rlwimi r8, r9, 0, 20, 31 + beq- major_0x043a0_0x154 + lwz r23, 0x0ea4(r1) + addi r23, r23, 0x01 + stw r23, 0x0ea4(r1) + mfsprg r1, 0 + lmw r14, 0x0038(r1) + lwz r1, -0x0004(r1) + stw r8, 0x035c(r1) + +major_0x043a0_0xf0 + lwz r8, 0x0350(r1) + stw r9, 0x0350(r1) + stw r8, 0x0358(r1) + lwz r9, 0x035c(r1) + lwz r8, 0x0354(r1) + stw r9, 0x0354(r1) + stw r8, 0x035c(r1) + lwz r9, 0x0350(r1) + +major_0x043a0_0x110 + lwz r8, 0x0348(r1) + stw r9, 0x0348(r1) + stw r8, 0x0350(r1) + lwz r9, 0x0354(r1) + lwz r8, 0x034c(r1) + stw r9, 0x034c(r1) + stw r8, 0x0354(r1) + lwz r9, 0x0348(r1) + +major_0x043a0_0x130 + lwz r8, 0x0340(r1) + stw r9, 0x0340(r1) + stw r9, 0x05b4(r1) + stw r8, 0x0348(r1) + lwz r9, 0x034c(r1) + lwz r8, 0x0344(r1) + stw r9, 0x0344(r1) + stw r8, 0x034c(r1) + b major_0x043a0_0x24 + +major_0x043a0_0x154 + mfsprg r1, 0 + lmw r14, 0x0038(r1) + lwz r1, -0x0004(r1) + li r8, 0x02 + b major_0x02980_0x134 + + + +; wordfill + +; Xrefs: +; setup +; FillIndigo + +; > r8 = dest +; > r22 = len in bytes +; > r23 = fillword + +wordfill ; OUTSIDE REFERER + subic. r22, r22, 4 + stwx r23, r8, r22 + bne+ wordfill + blr + + + +; kcResetSystem + +; Handle a 68k reset trap. +; Some messing around with 601 RTC vs later timebase +; registers. +; If Gary Davidian's first name and birthdate were in the +; 68k's A0/A1 (the 'skeleton key'), do something. +; Otherwise, farm it out to non_skeleton_reset_trap. + +; Xrefs: +; "sup" + +; > r3 = a0 +; > r4 = a1 + + align kIntAlign + +kcResetSystem ; OUTSIDE REFERER +; r6 = ewa + bl Save_r14_r31 +; r8 = sprg0 (not used by me) + + ; Check for 601 (rtc vs timebase) + mfpvr r9 + rlwinm. r9, r9, 0, 0, 14 + + ; This xoris/cmplwi technique is very cool + xoris r8, r3, 'Ga' + + beq- @is_601 + mftb r9 + b @endif_601 +@is_601 + dialect POWER + mfrtcl r9 + dialect PowerPC +@endif_601 + + ; Not sure why this would need to hit cr0? + andis. r9, r9, 0xffff + + cmplwi r8, 'ry' + bne- non_skeleton_reset_trap + + ; r4 (i.e. A1) == 5 May 1956? + xoris r8, r4, 0x0505 + cmplwi r8, 0x1956 + bne- non_skeleton_reset_trap + + andc r11, r11, r5 + lwz r8, ContextBlock.r7(r6) + or r11, r11, r8 + + _log 'Skeleton key inserted at' + + mr r8, r11 + bl Printw + + mr r8, r10 + bl Printw + + _log '^n' + + b skeleton_key + + + +; non_skeleton_reset_trap + +; A 68k reset trap without Gary Davidian's magic numbers. + +; Xrefs: +; kcResetSystem + +non_skeleton_reset_trap + + _log 'ResetSystem trap entered^n' + + lwz r8, KDP.OldKDP(r1) + + cmpwi r8, 0 + beq+ ResetBuiltinKernel + + _log 'Unplugging the replacement nanokernel^n' + + lwz r8, KDP.OldKDP(r1) + mfsprg r1, 0 + addi r9, r8, KDP.YellowVecBase + mtsprg 0, r8 ; old NK has only one EWA! + mtsprg 3, r9 + + lwz r9, EWA.r1(r1) + stw r9, EWA.r1(r8) + + lwz r9, EWA.r6(r1) + stw r9, EWA.r6(r8) + + stw r6, 0x065c(r8) + stw r7, 0x0660(r8) ; ?????????? + + lwz r9, -0x000c(r1) + stw r9, 0x0664(r8) + +; r6 = ewa + bl Restore_r14_r31 + subi r10, r10, 4 + lwz r1, -0x0004(r1) + +; sprg0 = for r1 and r6 +; r1 = kdp +; r6 = register restore area +; r7 = flag to insert into XER +; r10 = new srr0 (return location) +; r11 = new srr1 +; r12 = lr restore +; r13 = cr restore + b int_teardown + + + +; kcPrioritizeInterrupts + +; Xrefs: +; "sup" +; setup +; IntExternalYellow + +; > r1 = kdp + +kcPrioritizeInterrupts ; OUTSIDE REFERER + lwz r9, KDP.PA_InterruptHandler(r1) + mtlr r9 + blr + + + +; Move registers from CB to EWA, and Thud. + + align kIntAlign + +kcThud + + stw r2, EWA.r2(r1) + stw r3, EWA.r3(r1) + stw r4, EWA.r4(r1) + stw r5, EWA.r5(r1) + + lwz r8, ContextBlock.r7(r6) + lwz r9, ContextBlock.r8(r6) + stw r8, EWA.r7(r1) + stw r9, EWA.r8(r1) + + lwz r8, ContextBlock.r9(r6) + lwz r9, ContextBlock.r10(r6) + stw r8, EWA.r9(r1) + stw r9, EWA.r10(r1) + + lwz r8, ContextBlock.r11(r6) + lwz r9, ContextBlock.r12(r6) + stw r8, EWA.r11(r1) + stw r9, EWA.r12(r1) + + lwz r8, ContextBlock.r13(r6) + stw r8, EWA.r13(r1) + + stmw r14, EWA.r14(r1) + + bl Local_Panic + + + +; major_0x046d0 + +; Xrefs: +; "vec" +; kcThud + +major_0x046d0 ; OUTSIDE REFERER +; r6 = saved at *(ewa + 0x18) +; sprg1 = saved at *(ewa + 4) +; rN (0,7,8,9,10,11,12,13, not r1) = saved at *(*(ewa - 0x14) + 0x104 + 8*N) + bl int_prepare +; r0 = 0 +; r1 = *(ewa - 4) +; r6 = kdp +; r7 = *(ewa - 0x10) # flags? +; r8 = ewa +; r10 = srr0 +; r11 = srr1 +; r12 = sprg2 +; r13 = cr + + li r8, 0x02 + b major_0x02980_0x134 + + + +; IntExternalOrange + +; Xrefs: +; "vec" + + align kIntAlign + +IntExternalOrange ; OUTSIDE REFERER +; r6 = saved at *(ewa + 0x18) +; sprg1 = saved at *(ewa + 4) +; rN (0,7,8,9,10,11,12,13, not r1) = saved at *(*(ewa - 0x14) + 0x104 + 8*N) + bl int_prepare +; r0 = 0 +; r1 = *(ewa - 4) +; r6 = kdp +; r7 = *(ewa - 0x10) # flags? +; r8 = ewa +; r10 = srr0 +; r11 = srr1 +; r12 = sprg2 +; r13 = cr + + mtcrf 0x3f, r7 + bnel+ cr2, Local_Panic + li r8, 0x00 + b major_0x02980_0x134 + + + +; IntProgram + +; Xrefs: +; "vec" + + align kIntAlign + +IntProgram ; OUTSIDE REFERER +; r6 = saved at *(ewa + 0x18) +; sprg1 = saved at *(ewa + 4) +; rN (0,7,8,9,10,11,12,13, not r1) = saved at *(*(ewa - 0x14) + 0x104 + 8*N) + bl int_prepare +; r0 = 0 +; r1 = *(ewa - 4) +; r6 = kdp +; r7 = *(ewa - 0x10) # flags? +; r8 = ewa +; r10 = srr0 +; r11 = srr1 +; r12 = sprg2 +; r13 = cr + + lwz r8, 0x0648(r1) + mtcr r11 + xor r8, r10, r8 + bne- cr3, IntProgram_0x144 + cmplwi r8, 0x00 + cmplwi cr1, r8, 0x20 + beq- IntProgram_0x120 + beq- cr1, IntProgram_0x120 + cmplwi r8, 0x0c + cmplwi cr1, r8, 0x40 + beq- IntProgram_0x120 + blt- cr1, IntProgram_0x110 + bne- cr6, IntProgram_0x58 + stw r14, 0x0174(r6) + mfsprg r14, 3 + addi r8, r1, -0x750 + mfmsr r9 + mtsprg 3, r8 + ori r8, r9, 0x10 + mtmsr r8 + isync + +IntProgram_0x58 + lwz r8, 0x0000(r10) + bne- cr6, IntProgram_0x74 + isync + mtmsr r9 + isync + mtsprg 3, r14 + lwz r14, 0x0174(r6) + +IntProgram_0x74 + mtcr r7 + xoris r8, r8, 0xfff + cmplwi r8, 0x10 + cmplwi cr1, r8, 0x00 + bge- IntProgram_0x150 + cmplwi cr7, r8, 0x08 + cmplwi r8, 0x03 + slwi r8, r8, 2 + beq- cr1, IntProgram_0xac + beq- cr7, IntProgram_0xd0 + beq- IntProgram_0xac + blt- cr4, IntProgram_0x150 + blt- cr2, IntProgram_0xac + ble- cr2, IntProgram_0x150 + +IntProgram_0xac + add r8, r8, r1 + lwz r9, KDP.NanoKernelInfo + NKNanoKernelInfo.NanoKernelCallCounts(r8) + addi r9, r9, 0x01 + stw r9, KDP.NanoKernelInfo + NKNanoKernelInfo.NanoKernelCallCounts(r8) + +IntProgram_0xbc + lwz r8, KDP.NanoKernelCallTable(r8) + mtlr r8 + addi r10, r10, 0x04 + rlwimi r7, r7, 27, 26, 26 + blr + +IntProgram_0xd0 + lwz r9, 0x0104(r6) + add r8, r8, r1 + cmpwi r9, -0x01 + lwz r9, KDP.NanoKernelInfo + NKNanoKernelInfo.NanoKernelCallCounts(r8) + addi r9, r9, 0x01 + stw r9, KDP.NanoKernelInfo + NKNanoKernelInfo.NanoKernelCallCounts(r8) + bne+ IntProgram_0xbc + addi r10, r10, 0x04 + rlwimi r7, r7, 27, 26, 26 + mfsprg r8, 0 + rlwimi r13, r7, 8, 2, 2 + lwz r9, -0x0008(r8) + xoris r13, r13, 0x2000 + lwz r8, 0x00ec(r9) + stw r8, 0x0104(r6) + b skeleton_key + +IntProgram_0x110 + mtcr r7 + blt- cr4, IntProgram_0x150 + blt- cr2, IntProgram_0x120 + ble- cr2, IntProgram_0x150 + +IntProgram_0x120 + add r8, r8, r1 + lwz r9, KDP.NanoKernelInfo + NKNanoKernelInfo.NanoKernelCallCounts(r8) + lwz r10, KDP.NanoKernelCallTable(r8) + addi r9, r9, 0x01 + stw r9, KDP.NanoKernelInfo + NKNanoKernelInfo.NanoKernelCallCounts(r8) + mtlr r10 + mr r10, r12 + rlwimi r7, r7, 27, 26, 26 + blr + +IntProgram_0x144 + blt+ cr3, FDP_1214 + bgt- cr3, FDP_1214 + bso- cr2, IntProgram_0x160 + +IntProgram_0x150 + rlwinm r8, r11, 17, 28, 29 + addi r8, r8, 0x4b3 + rlwnm r8, r8, r8, 0x1c, 0x1f + b major_0x02980_0x134 + +IntProgram_0x160 + li r8, 0x03 + bso+ cr3, major_0x02980_0x134 + addi r10, r10, 0x04 + rlwimi r7, r7, 27, 26, 26 + b major_0x02980_0x134 + + + +; IntExternalYellow + +; Xrefs: +; "vec" + + align kIntAlign + +IntExternalYellow ; OUTSIDE REFERER + + bl int_prepare + + ; RET r0 = 0 + ; r1 = KernelData + ; r6 = ECB + ; r7 = AllCpuFeatures + ; r8 = EWA (pretend KDP) + ; r10 = SRR0 + ; r11 = SRR1 + ; r12 = LR from SPRG2 + ; r13 = CR + + + ; Sanity check + + rlwinm. r9, r11, 0, MSR_EEbit, MSR_EEbit + beq+ MaskedInterruptTaken + + + ; How many CPUs? + + lwz r9, EWA.CPUBase + CPU.CgrpList + LLL.Freeform(r8) + lwz r9, CoherenceGroup.CpuCount(r9) + cmpwi r9, 2 + + + ; Uniprocessor machine: go straight to PIH + + blt+ kcPrioritizeInterrupts + + + ; Multiprocessor machine: signal another CPU? + + bl Save_r14_r31 + + li r9, 9 + stw r9, -0x0238(r8) + + li r8, 1 + bl SIGP + + bl Restore_r14_r31 + + ; These do not match any public Apple error codes? + cmpwi r8, -0x725e + cmpwi cr1, r8, -0x725d + cmpwi cr2, r8, -0x725f + + beq+ kcPrioritizeInterrupts + beq+ cr1, skeleton_key + bne+ cr2, kcPrioritizeInterrupts + + mfsprg r9, 0 + li r8, 0x01 + stb r8, -0x0118(r9) + b skeleton_key + + + +; SIGP + +; Really need to figure out what this does... + +; Xrefs: +; IntExternalYellow +; MPCall_43 +; KCStartCPU +; KCCpuPlugin +; major_0x14af8 +; MPCall_103 + +; > r7 = flags +; > r8 = usually 2? + + align 5 + +SIGP ; OUTSIDE REFERER + mfsprg r23, 0 + mtcr r7 + lwz r16, -0x001c(r23) + slwi r20, r3, 2 + stw r16, -0x02ac(r23) + blt- cr4, major_0x04a20_0x18 + cmpwi cr2, r8, 0x00 + lwz r18, -0x0238(r23) + beq- cr2, SIGP_0x28 + slwi r20, r18, 2 + +SIGP_0x28 + lwz r22, -0x0338(r23) + li r8, -0x7266 + lwz r17, 0x0038(r22) + lwz r16, 0x0044(r22) + mr. r17, r17 + beqlr- + slwi r16, r16, 2 + li r8, -0x7267 + cmplw r20, r16 + bgelr- + stw r10, -0x02d0(r23) + stw r11, -0x02cc(r23) + stw r12, -0x02c8(r23) + stw r13, -0x02c4(r23) + mfxer r16 + mfctr r17 + stw r16, -0x02c0(r23) + mflr r16 + stw r17, -0x02bc(r23) + stw r16, -0x02b8(r23) + stw r6, -0x02b4(r23) + stw r7, -0x02b0(r23) + lwz r9, -0x001c(r23) + lwz r8, 0x004c(r22) + cmpw r9, r8 + beq- SIGP_0x94 + bl SetAddrSpcRegisters + +SIGP_0x94 + lwz r16, 0x0004(r23) + lwz r17, 0x0018(r23) + stw r16, 0x010c(r6) + stw r2, 0x0114(r6) + stw r3, 0x011c(r6) + stw r4, 0x0124(r6) + stw r5, 0x012c(r6) + stw r17, 0x0134(r6) + lwz r17, 0x0648(r1) + lhz r16, -0x0116(r23) + lwz r19, -0x0964(r1) + slwi r16, r16, 2 + rlwinm r19, r19, 0, 18, 15 + lwz r8, 0x003c(r22) + lwz r9, 0x0040(r22) + lwzx r20, r8, r20 + lwz r18, 0x0000(r20) + mtlr r17 + mtspr srr0, r18 + mtspr srr1, r19 + lwzx r1, r9, r16 + lwz r2, 0x0004(r20) + srwi r3, r16, 2 + ori r7, r7, 0x8000 + mr r16, r6 + stw r7, -0x0010(r23) + addi r6, r23, -0x318 + stw r6, -0x0014(r23) + beq- cr2, SIGP_0x128 + lwz r4, -0x0234(r23) + lwz r5, -0x0230(r23) + lwz r6, -0x022c(r23) + lwz r7, -0x0228(r23) + lwz r8, -0x0224(r23) + lwz r9, -0x0220(r23) + lwz r10, -0x021c(r23) + rfi + +SIGP_0x128 + lwz r6, 0x0134(r16) + lwz r7, 0x013c(r16) + lwz r8, 0x0144(r16) + lwz r9, 0x014c(r16) + lwz r10, 0x0154(r16) + rfi + + + +; major_0x04a20 + +; Xrefs: +; "vec" +; major_0x02980 +; major_0x03be0 +; SIGP + +major_0x04a20 ; OUTSIDE REFERER + mfsprg r23, 0 + lwz r6, -0x0014(r23) + lwz r7, -0x0010(r23) + lwz r1, -0x0004(r23) + mfspr r10, srr0 + mfspr r11, srr1 + +major_0x04a20_0x18 ; OUTSIDE REFERER + mfsprg r23, 0 + lwz r7, -0x02b0(r23) + andis. r8, r11, 0x02 + stw r7, -0x0010(r23) + bne- major_0x04a20_0x30 + li r3, -0x7265 + +major_0x04a20_0x30 + lwz r8, -0x02ac(r23) + lwz r9, -0x001c(r23) + cmpw r9, r8 + beq- major_0x04a20_0x44 + bl SetAddrSpcRegisters + +major_0x04a20_0x44 + lwz r10, -0x02d0(r23) + lwz r11, -0x02cc(r23) + lwz r12, -0x02c8(r23) + lwz r13, -0x02c4(r23) + lwz r8, -0x02c0(r23) + lwz r9, -0x02bc(r23) + mtxer r8 + lwz r8, -0x02b8(r23) + lwz r6, -0x02b4(r23) + mtctr r9 + stw r6, -0x0014(r23) + mtlr r8 + mr r8, r3 + mr r9, r4 + lwz r16, 0x010c(r6) + lwz r2, 0x0114(r6) + lwz r3, 0x011c(r6) + lwz r4, 0x0124(r6) + lwz r5, 0x012c(r6) + lwz r17, 0x0134(r6) + stw r16, 0x0004(r23) + stw r17, 0x0018(r23) + blr + + + +; IntSyscall + +; Not fully sure about this one + +; Xrefs: +; "vec" + +IntSyscall ; OUTSIDE REFERER + + ; Only r1 and LR have been saved, so these compares clobber cr0 + + cmpwi r0, -3 + bne- @not_minus_3 + + ; sc -3: + + ; unset MSR_PR bit + mfspr r1, srr1 + rlwinm. r0, r1, 26, 26, 27 ; nonsense code? + rlwinm r1, r1, 0, 18, 16 + blt- @dont_unset_pr ; r0 should never have bit 0 set + mtspr srr1, r1 + @dont_unset_pr + + ; restore LR from SPRG2, r1 from SPRG1 + mfsprg r1, 2 + mtlr r1 + mfsprg r1, 1 + + rfi + +@not_minus_3 + cmpwi r0, -1 + mfsprg r1, 0 + bne- @not_minus_1 + + ; sc -1: mess around with flags + + lwz r0, -0x0010(r1) + mfsprg r1, 2 + rlwinm. r0, r0, 0, 10, 10 + mtlr r1 + mfsprg r1, 1 + rfi + +@not_minus_1 + cmpwi r0, -2 + bne- @not_any_special + + ; sc -2: more flag nonsense? + + lwz r0, -0x0010(r1) + lwz r1, -0x0008(r1) + rlwinm. r0, r0, 0, 10, 10 + lwz r0, 0x00ec(r1) + mfsprg r1, 2 + mtlr r1 + mfsprg r1, 1 + rfi + +@not_any_special + + ; Positive numbered syscalls are a fast path to MPDispatch (twi 31, r31, 8) + + bl int_prepare ; Save the usual suspects and get comfy + +; Reg Contains Original saved in +; --------------------------------------------- +; r0 0 ContextBlock +; r1 KDP EWA +; r2 (itself) +; r3 (itself) +; r4 (itself) +; r5 (itself) +; r6 ContextBlock EWA +; r7 AllCpuFeatures ContextBlock +; r8 EWA ContextBlock +; r9 (itself) ContextBlock +; r10 SRR0 ContextBlock +; r11 SRR1 ContextBlock +; r12 LR ContextBlock +; r13 CR ContextBlock + + lwz r9, KDP.NanoKernelInfo + NKNanoKernelInfo.NanoKernelCallCounts + 32(r1) + addi r9, r9, 1 + stw r9, KDP.NanoKernelInfo + NKNanoKernelInfo.NanoKernelCallCounts + 8*4(r1) + + ; Not sure what to make of these + _bset r11, r11, 14 + rlwimi r7, r7, 27, 26, 26 + + b kcMPDispatch + + + +; IntTrace + +; Xrefs: +; "vec" + + align kIntAlign + +IntTrace ; OUTSIDE REFERER +; r6 = saved at *(ewa + 0x18) +; sprg1 = saved at *(ewa + 4) +; rN (0,7,8,9,10,11,12,13, not r1) = saved at *(*(ewa - 0x14) + 0x104 + 8*N) + bl int_prepare +; r0 = 0 +; r1 = *(ewa - 4) +; r6 = kdp +; r7 = *(ewa - 0x10) # flags? +; r8 = ewa +; r10 = srr0 +; r11 = srr1 +; r12 = sprg2 +; r13 = cr + + li r8, 0x08 + b major_0x02980_0x134 + + + +; IgnoreSoftwareInt + +; Xrefs: +; "vec" + + align kIntAlign + +IgnoreSoftwareInt ; OUTSIDE REFERER + mfspr r1, srr0 + addi r1, r1, 0x04 + mtspr srr0, r1 + mfsprg r1, 2 + mtlr r1 + mfsprg r1, 1 + rfi + dcb.b 32, 0 + + + + +; HandlePerfMonitorInt + +; Xrefs: +; "vec" + + align kIntAlign + +HandlePerfMonitorInt ; OUTSIDE REFERER + mfspr r1, srr1 + oris r1, r1, 0x200 + mtspr srr1, r1 + mfsprg r1, 2 + mtlr r1 + mfsprg r1, 1 + rfi + dcb.b 32, 0 + diff --git a/NanoKernel/NKMPCalls.s b/NanoKernel/NKMPCalls.s new file mode 100644 index 0000000..3be93ca --- /dev/null +++ b/NanoKernel/NKMPCalls.s @@ -0,0 +1,2672 @@ +; Important note: If you want more than r3-r5, get them from ECB!!! + +; Unimplemented MPCalls from MPLibrary: +; NKSetPrInfoPageSize 109 +; NKSetPrInfoILockSizes 110 +; NKSetPrInfoTransCache 111 +; NKSetPrInfoL1Cache 112 +; NKSetPrInfoL2Cache 113 + + + +;MPCall_Panic set MPCall_Panic + + + + if &TYPE('NKDebugShim') != 'UNDEFINED' +MaxMPCallCount equ 300 + else +MaxMPCallCount equ 134 + endif + + + + MACRO + DeclareMPCall &n, &code +@h + org MPCallTable + 4*&n + dc.l &code - NKTop - 4*&n + org @h + ENDM + + + ; Creates a blank table without overflowing PPCAsm's default + ; macro stack size :) + + MACRO + CreateMPCallTbl &n + + if &n >= 1 + dc.l (MPCallBad - NKTop) - (* - MPCallTable) + endif + + if &n >= 2 + dc.l (MPCallBad - NKTop) - (* - MPCallTable) + endif + + if &n >= 3 + dc.l (MPCallBad - NKTop) - (* - MPCallTable) + endif + + if &n >= 4 + dc.l (MPCallBad - NKTop) - (* - MPCallTable) + endif + + if &n >= 5 + dc.l (MPCallBad - NKTop) - (* - MPCallTable) + endif + + if &n >= 6 + dc.l (MPCallBad - NKTop) - (* - MPCallTable) + endif + + if &n >= 7 + dc.l (MPCallBad - NKTop) - (* - MPCallTable) + endif + + if &n >= 8 + dc.l (MPCallBad - NKTop) - (* - MPCallTable) + endif + + if &n >= 9 + dc.l (MPCallBad - NKTop) - (* - MPCallTable) + endif + + if &n >= 10 + dc.l (MPCallBad - NKTop) - (* - MPCallTable) + endif + + if &n >= 11 + CreateMPCallTbl (&n) - 10 + endif + + ENDM + + + +kcMPDispatch ; reached by `sc`, or `twi *, *, 8` + + bl Save_r14_r31 + + lwz r8, EWA.r6(r8) ; clobbers our EWA pointer :( + lwz r14, KDP.PA_NanoKernelCode(r1) ; but r14... + lwz r15, ContextBlock.r0(r6) ; ...and r15 were saved + stw r8, ContextBlock.r6(r6) ; why move r6 from EWA to ContextBlock? + b MPCallTableEnd + +MPCallTable + CreateMPCallTbl MaxMPCallCount +MPCallTableEnd + +; Not sure where this counter table is? + + lwz r16, KDP.NanoKernelInfo + NKNanoKernelInfo.MPDispatchCountTblPtr(r1) + rlwinm r17, r15, 2, 20, 29 + cmplwi r16, 0 + beq- @no_count + lwzx r18, r16, r17 + addi r18, r18, 1 + stwx r18, r16, r17 +@no_count + + cmplwi r15, MaxMPCallCount + rlwimi r14, r15, 2, 21, 29 + llabel r16, MPCallTable + lwzx r15, r16, r14 + add r15, r15, r14 + mtlr r15 + bltlr- + + + +; Handler for out-of-range or unimplemented (debug) +; MPCalls. + +MPCallBad ; OUTSIDE REFERER + li r3, -4 + b CommonMPCallReturnPath + + + +; ReleaseAndMPCallWasBad + +; Xrefs: +; MPCall_75 + +ReleaseAndMPCallWasBad ; OUTSIDE REFERER + sync + lwz r16, PSA.SchLock + Lock.Count(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + + bne+ cr1, @dont_panic + mflr r16 + bl panic +@dont_panic + + stw r16, PSA.SchLock + Lock.Count(r1) + b MPCallBad + + + +; ReleaseAndReturnZeroFromMPCall + +; Xrefs: +; KCRegisterCpuPlugin +; KCCreateProcess +; MPCall_5 +; MPCall_55 +; KCCreateCpuStruct +; MPCall_43 +; KCStartCPU +; KCStopScheduling +; KCRegisterThermalHandler +; KCRegisterPMFHandler +; KCMarkPMFTask +; NKSetClockStep +; NKSetClockDriftCorrection +; MPCall_115 +; KCRegisterExternalHandler +; MPCall_133 +; MPCall_15 +; MPCall_16 +; MPCall_39 +; MPCall_17 +; MPCall_18 +; MPCall_19 +; MPCall_20 +; MPCall_23 +; MPCall_24 +; MPCall_21 +; MPCall_25 +; MPCall_27 +; MPCall_29 +; MPCall_28 +; MPCall_26 +; MPCall_49 +; MPCall_50 +; MPCall_51 +; MPCall_52 +; MPCall_53 +; MPCall_54 +; MPCall_40 +; MPCall_30 +; MPCall_31 +; MPCall_32 +; MPCall_64 +; MPCall_65 +; MPCall_66 +; MPCall_128 +; MPCall_120 +; MPCall_7 +; MPCall_8 +; MPCall_10 +; MPCall_14 +; MPCall_56 +; MPCall_58 +; MPCall_59 +; MPCall_60 +; MPCall_61 +; MPCall_63 +; MPCall_114 +; KCSetTaskType +; MPCall_71 +; KCSetTaskAddressSpace +; MPCall_74 +; MPCall_75 +; MPCall_130 +; KCSetAreaAccess +; MPCall_123 +; MPCall_77 +; MPCall_78 +; MPCall_80 +; MPCall_125 +; MPCall_81 +; MPCall_98 +; MPCall_82 +; KCMapPage +; KCUnmapPages +; KCMakePhysicallyContiguous +; KCLockPages +; KCUnlockPages +; KCHoldPages +; KCUnholdPages +; MPCall_91 +; MPCall_92 +; MPCall_93 +; MPCall_94 +; MPCall_129 +; MPCall_95 + +; > r1 = kdp + +ReleaseAndReturnZeroFromMPCall ; OUTSIDE REFERER + sync + lwz r16, PSA.SchLock + Lock.Count(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + + bne+ cr1, @dont_panic + mflr r16 + bl panic +@dont_panic + + stw r16, PSA.SchLock + Lock.Count(r1) + + + +; ReturnZeroFromMPCall + +; Xrefs: +; ReleaseAndReturnZeroFromMPCall +; MPCall_0 +; MPCall_6 +; MPCall_55 +; MPCall_34 +; MPCall_35 +; MPCall_36 +; KCGetNextID +; KCGetNextIDOwnedByProcess +; MPCall_38 +; MPCall_62 +; KCStartCPU +; MPCall_47 +; NKxprintf +; KCSetBlueProcessID +; NKLocateInfoRecord +; MPCall_108 +; NKSetClockDriftCorrection +; MPCall_41 +; MPCall_79 +; MPCall_83 +; MPCall_102 + +ReturnZeroFromMPCall ; OUTSIDE REFERER + li r3, 0x00 + b CommonMPCallReturnPath + + + +; major_0x0af60 + +; Xrefs: +; KCRegisterCpuPlugin +; KCCreateProcess +; MPCall_5 +; MPCall_6 +; MPCall_34 +; KCCreateCpuStruct +; MPCall_43 +; KCStartCPU +; KCStopScheduling +; MPCall_115 +; MPCall_15 +; MPCall_39 +; MPCall_17 +; MPCall_18 +; MPCall_19 +; MPCall_20 +; MPCall_23 +; MPCall_24 +; MPCall_25 +; MPCall_27 +; MPCall_29 +; MPCall_28 +; MPCall_49 +; MPCall_52 +; MPCall_53 +; MPCall_40 +; MPCall_31 +; MPCall_64 +; MPCall_7 +; MPCall_8 +; MPCall_9 +; MPCall_10 +; KCThrowException +; MPCall_58 +; MPCall_60 +; MPCall_61 +; MPCall_114 +; MPCall_70 +; MPCall_71 +; KCSetTaskAddressSpace +; MPCall_72 +; MPCall_73 +; MPCall_74 +; MPCall_75 +; MPCall_130 +; MPCall_83 +; KCMapPage +; KCUnmapPages +; KCMakePhysicallyContiguous +; KCLockPages +; KCHoldPages +; MPCall_91 +; MPCall_92 +; MPCall_94 +; MPCall_95 + +major_0x0af60 ; OUTSIDE REFERER + sync + lwz r16, PSA.SchLock + Lock.Count(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + + bne+ cr1, @dont_panic + mflr r16 + bl panic +@dont_panic + + stw r16, PSA.SchLock + Lock.Count(r1) + + + +; I'd really live a name for this. + +major_0x0af60_0x20 ; OUTSIDE REFERER + mfspr r16, pvr + rlwinm. r16, r16, 0, 0, 14 + + beq- @is_601 + mftb r4 + b @not_601 +@is_601 + mfspr r4, rtcl +@not_601 + + xori r16, r4, 0x1007 + xoris r16, r16, 0x1950 + + stw r16, PSA.ScrambledMPCallTime(r1) + li r3, -0x726e + b CommonMPCallReturnPath + + + + +; dead code? + li r3, kMPDeletedErr + b CommonMPCallReturnPath + + + +ReleaseAndTimeoutMPCall ; OUTSIDE REFERER + sync + lwz r16, PSA.SchLock + Lock.Count(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + + bne+ cr1, @dont_panic + mflr r16 + bl panic +@dont_panic + + stw r16, PSA.SchLock + Lock.Count(r1) + li r3, kMPTimeOutErr + b CommonMPCallReturnPath + + + +ReleaseAndReturnMPCallTaskAborted ; OUTSIDE REFERER + sync + lwz r16, PSA.SchLock + Lock.Count(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + + bne+ cr1, @dont_panic + mflr r16 + bl panic +@dont_panic + + stw r16, PSA.SchLock + Lock.Count(r1) + li r3, kMPTaskAbortedErr + b CommonMPCallReturnPath + + + +ReleaseAndReturnMPCallOOM ; OUTSIDE REFERER + sync + lwz r16, PSA.SchLock + Lock.Count(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + + bne+ cr1, @dont_panic + mflr r16 + bl panic +@dont_panic + + stw r16, PSA.SchLock + Lock.Count(r1) + + + +; ReturnMPCallOOM + +; Xrefs: +; major_0x0af60 +; MPCall_0 +; KCRegisterCpuPlugin +; MPCall_47 +; NKxprintf +; KCSetBlueProcessID +; NKSetClockStep +; NKSetClockDriftCorrection +; MPCall_39 +; MPCall_20 +; MPCall_7 +; MPCall_82 +; KCPropogateExternalInterrupt +; major_0x16b80 + +ReturnMPCallOOM ; OUTSIDE REFERER + li r3, kMPInsufficientResourcesErr + b CommonMPCallReturnPath + + + +; ReleaseAndReturnMPCallBlueBlocking + +; Xrefs: +; MPCall_18 +; MPCall_23 +; MPCall_27 +; MPCall_52 + +ReleaseAndReturnMPCallBlueBlocking ; OUTSIDE REFERER + sync + lwz r16, PSA.SchLock + Lock.Count(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + bne+ cr1, major_0x0b02c_0x1c + mflr r16 + bl panic + +major_0x0b02c_0x1c + stw r16, PSA.SchLock + Lock.Count(r1) + + + +; ReturnMPCallBlueBlocking + +; Xrefs: +; ReleaseAndReturnMPCallBlueBlocking +; MPCall_33 + +ReturnMPCallBlueBlocking ; OUTSIDE REFERER + li r3, kMPBlueBlockingErr + b CommonMPCallReturnPath + + + +; major_0x0b054 + +; Xrefs: +; MPCall_128 +; MPCall_120 +; MPCall_73 +; MPCall_75 +; MPCall_130 +; KCSetAreaAccess +; MPCall_123 +; MPCall_78 +; MPCall_80 +; MPCall_125 +; MPCall_81 +; MPCall_98 +; KCMapPage +; KCUnmapPages +; KCMakePhysicallyContiguous +; KCLockPages +; KCUnlockPages +; KCHoldPages +; KCUnholdPages +; MPCall_91 +; MPCall_92 +; MPCall_93 +; MPCall_94 +; MPCall_129 + +major_0x0b054 ; OUTSIDE REFERER + sync + lwz r16, PSA.SchLock + Lock.Count(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + bne+ cr1, major_0x0b054_0x1c + mflr r16 + bl panic + +major_0x0b054_0x1c + stw r16, PSA.SchLock + Lock.Count(r1) + + + +; ReturnParamErrFromMPCall + +; Xrefs: +; major_0x0b054 +; KCGetNextIDOwnedByProcess +; NKLocateInfoRecord +; MPCall_108 +; NKSetClockStep +; KCGetPageSize +; MPCall_95 +; KCPropogateExternalInterrupt +; major_0x16b80 + +ReturnParamErrFromMPCall ; OUTSIDE REFERER + li r3, -0x32 + b CommonMPCallReturnPath + + + +; ReleaseAndReturnMPCallPrivilegedErr + +; Xrefs: +; KCRegisterCpuPlugin +; KCCreateProcess +; MPCall_5 +; MPCall_6 +; MPCall_43 +; KCStartCPU +; KCStopScheduling +; KCRegisterThermalHandler +; KCRegisterPMFHandler +; KCMarkPMFTask +; MPCall_115 +; KCRegisterExternalHandler +; MPCall_16 +; MPCall_39 +; MPCall_17 +; MPCall_18 +; MPCall_19 +; MPCall_23 +; MPCall_24 +; MPCall_22 +; MPCall_21 +; MPCall_27 +; MPCall_29 +; MPCall_28 +; MPCall_26 +; MPCall_50 +; MPCall_51 +; MPCall_52 +; MPCall_53 +; MPCall_54 +; MPCall_41 +; MPCall_30 +; MPCall_31 +; MPCall_32 +; MPCall_65 +; MPCall_67 +; MPCall_66 +; MPCall_128 +; MPCall_7 +; MPCall_8 +; MPCall_9 +; MPCall_10 +; MPCall_14 +; MPCall_56 +; KCThrowException +; MPCall_58 +; MPCall_59 +; MPCall_60 +; MPCall_61 +; MPCall_63 +; MPCall_114 +; KCSetTaskType +; MPCall_71 +; KCSetTaskAddressSpace +; MPCall_72 +; MPCall_73 +; MPCall_74 +; MPCall_75 +; MPCall_130 +; KCSetAreaAccess +; MPCall_123 +; MPCall_77 +; MPCall_78 +; MPCall_80 +; MPCall_125 +; MPCall_81 +; MPCall_98 +; MPCall_82 +; KCMapPage +; KCUnmapPages +; KCMakePhysicallyContiguous +; KCLockPages +; KCUnlockPages +; KCHoldPages +; KCUnholdPages +; MPCall_91 +; MPCall_92 +; MPCall_93 +; MPCall_94 +; MPCall_129 + +ReleaseAndReturnMPCallPrivilegedErr ; OUTSIDE REFERER + sync + lwz r16, PSA.SchLock + Lock.Count(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + + bne+ cr1, @dont_panic + mflr r16 + bl panic +@dont_panic + + stw r16, PSA.SchLock + Lock.Count(r1) + li r3, kMPPrivilegedErr + b CommonMPCallReturnPath + + + +ReleaseAndReturnMPCallInvalidIDErr ; OUTSIDE REFERER + sync + lwz r16, PSA.SchLock + Lock.Count(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + + bne+ cr1, @dont_panic + mflr r16 + bl panic +@dont_panic + + stw r16, PSA.SchLock + Lock.Count(r1) + + + +; ReturnMPCallInvalidIDErr + +; Xrefs: +; ReleaseAndReturnMPCallPrivilegedErr +; KCRegisterCpuPlugin +; MPCall_35 +; MPCall_36 +; KCGetNextID +; KCGetNextIDOwnedByProcess +; MPCall_38 +; MPCall_62 +; KCCreateCpuStruct +; KCSetBlueProcessID +; MPCall_14 +; MPCall_79 + +ReturnMPCallInvalidIDErr ; OUTSIDE REFERER + li r3, kMPInvalidIDErr + b CommonMPCallReturnPath + + + +; major_0x0b0cc + +; Xrefs: +; KCLockPages +; KCUnlockPages +; KCHoldPages +; KCUnholdPages + +major_0x0b0cc ; OUTSIDE REFERER + sync + lwz r16, PSA.SchLock + Lock.Count(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + bne+ cr1, major_0x0b0cc_0x1c + mflr r16 + bl panic + +major_0x0b0cc_0x1c + stw r16, PSA.SchLock + Lock.Count(r1) + li r3, -0x725a + b CommonMPCallReturnPath + + + +; ReturnZeroFromMPCall_again + +; Xrefs: +; MPCall_1 + +ReturnZeroFromMPCall_again ; OUTSIDE REFERER + li r3, 0x00 + b CommonMPCallReturnPath + + + +; AlternateMPCallReturnPath + +; Xrefs: +; major_0x02964 +; major_0x02ccc +; MPCall_55 +; MPCall_18 +; MPCall_23 +; MPCall_22 +; MPCall_27 +; MPCall_52 +; MPCall_67 +; MPCall_9 +; KCThrowException +; MPCall_58 +; MPCall_60 +; MPCall_61 +; KCSetTaskAddressSpace +; MPCall_81 +; MPCall_98 + +AlternateMPCallReturnPath ; OUTSIDE REFERER + crclr cr2_eq + b TrulyCommonMPCallReturnPath + +ReleaseAndReturnMPCall ; OUTSIDE REFERER + sync + lwz r16, PSA.SchLock + Lock.Count(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + + bne+ cr1, @dont_panic + mflr r16 + bl panic +@dont_panic + + stw r16, PSA.SchLock + Lock.Count(r1) + + + +; CommonMPCallReturnPath + +; Xrefs: +; MPCallBad +; ReturnZeroFromMPCall +; major_0x0af60 +; ReturnMPCallOOM +; ReturnMPCallBlueBlocking +; ReturnParamErrFromMPCall +; ReleaseAndReturnMPCallPrivilegedErr +; ReturnMPCallInvalidIDErr +; major_0x0b0cc +; ReturnZeroFromMPCall_again +; AlternateMPCallReturnPath +; KCGetCpuCount +; MPCall_6 +; KCYieldWithHint +; KCCpuPlugin +; NKPrintHex +; NKPrintDecimal +; MPCall_11 +; MPCall_12 +; KCGetPageSizeClasses +; KCGetPageSize +; MPCall_70 +; KCCurrentAddressSpace +; KCHomeAddressSpace +; MPCall_72 +; MPCall_73 +; MPCall_84 +; KCGetFreePageCount +; KCGetUnheldFreePageCount +; major_0x16b80 + +CommonMPCallReturnPath ; OUTSIDE REFERER + crset cr2_eq + +TrulyCommonMPCallReturnPath ; OUTSIDE REFERER + mfsprg r8, 0 + lwz r9, 0x0134(r6) + stw r9, 0x0018(r8) + + bne- cr2, @do_the_other_thing_instead + bl Restore_r14_r31 + b skeleton_key +@do_the_other_thing_instead + + b major_0x142dc + + + +; MPCall_0 + + DeclareMPCall 0, MPCall_0 + +MPCall_0 ; OUTSIDE REFERER + andi. r16, r3, 0xfff + mr r30, r7 + mr r29, r6 + bne+ ReturnMPCallOOM + rlwinm. r4, r3, 20, 12, 31 + lwz r9, 0x06a8(r1) + beq+ ReturnMPCallOOM + cmplw r4, r9 + bge+ ReturnMPCallOOM + + _Lock PSA.HTABLock, scratch1=r17, scratch2=r18 + + bl VeryPopularFunction + bge- cr4, MPCall_0_0xd8 + bgt- cr5, MPCall_0_0xd8 + bns- cr7, MPCall_0_0xd8 + bgt- cr7, MPCall_0_0xd8 + bltl+ cr5, VMDoSomethingWithTLB + bgel+ cr5, VMSecondLastExportedFunc + ori r16, r16, 0x404 + li r31, 0x03 + rlwimi r9, r31, 0, 30, 31 + bl VMDoSomeIO + mr r7, r30 + mr r6, r29 + sync + lwz r16, -0x0b90(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + bne+ cr1, MPCall_0_0x8c + mflr r16 + bl panic + +MPCall_0_0x8c + stw r16, -0x0b90(r1) + + _Lock PSA.PoolLock, scratch1=r16, scratch2=r17 + + rlwinm r8, r9, 0, 0, 19 + mr r9, r3 + +; r1 = kdp +; r8 = anywhere in new page (phys) +; r9 = page_virt + bl ExtendPool + sync + lwz r16, -0x0ad0(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + bne+ cr1, MPCall_0_0xd0 + mflr r16 + bl panic + +MPCall_0_0xd0 + stw r16, -0x0ad0(r1) + b ReturnZeroFromMPCall + +MPCall_0_0xd8 + mr r7, r30 + mr r6, r29 + sync + lwz r16, -0x0b90(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + bne+ cr1, MPCall_0_0xfc + mflr r16 + bl panic + +MPCall_0_0xfc + stw r16, -0x0b90(r1) + b ReturnMPCallOOM + + + +; MPCall_1 + + DeclareMPCall 1, MPCall_1 + +MPCall_1 ; OUTSIDE REFERER + b ReturnZeroFromMPCall_again + + + +; KCRegisterCpuPlugin + + + DeclareMPCall 2, KCRegisterCpuPlugin + +KCRegisterCpuPlugin ; OUTSIDE REFERER + mfsprg r14, 0 + lwz r15, EWA.PA_CurTask(r14) + lwz r16, ContextBlock.r6(r6) + + andi. r8, r4, 0xfff ; page alignment? + bne+ ReturnMPCallOOM + + andi. r8, r5, 0xfff ; r5 page aligned and nonzero? + cmpwi cr1, r5, 0 + bne+ ReturnMPCallOOM + beq+ cr1, ReturnMPCallOOM + + _Lock PSA.SchLock, scratch1=r18, scratch2=r19 + + mr. r8, r3 + bne- KCRegisterCpuPlugin_0x50 + mfsprg r15, 0 + lwz r14, -0x0338(r15) + b KCRegisterCpuPlugin_0x60 + +KCRegisterCpuPlugin_0x50 +; r8 = id + bl LookupID + cmpwi r9, CoherenceGroup.kIDClass + + mr r14, r8 + bne+ ReturnMPCallInvalidIDErr + +KCRegisterCpuPlugin_0x60 + cmpwi r16, 0x00 + bne- KCRegisterCpuPlugin_0x74 + stw r16, 0x0038(r14) + stw r16, 0x0034(r14) + b ReleaseAndReturnMPCallInvalidIDErr + +KCRegisterCpuPlugin_0x74 + add r17, r4, r5 + cmplw r16, r4 + cmplw cr1, r16, r17 + blt+ ReleaseAndReturnMPCallOOM + bge+ cr1, ReleaseAndReturnMPCallOOM + lwz r19, 0x0038(r14) + mr. r19, r19 + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r27, r4 + addi r29, r1, 800 + bl PagingFunc3 + beq+ ReleaseAndReturnMPCallOOM + rlwinm r18, r31, 0, 0, 19 + mr r27, r16 + mr r19, r16 + addi r29, r1, 800 + bl PagingFunc3 + beq+ ReleaseAndReturnMPCallOOM + rlwimi r19, r31, 0, 0, 19 + stw r4, 0x0028(r14) + stw r18, 0x002c(r14) + stw r5, 0x0030(r14) + stw r16, 0x0034(r14) + stw r19, 0x0038(r14) + lwz r27, 0x0000(r19) + addi r29, r1, 800 + bl PagingFunc3 + beq+ ReleaseAndReturnMPCallOOM + rlwimi r27, r31, 0, 0, 19 + stw r27, 0x0040(r14) + mfsprg r16, 0 + lwz r17, -0x001c(r16) + stw r17, 0x004c(r14) + addi r16, r19, 0x20 + stw r16, 0x003c(r14) + subi r16, r16, 4 + lwz r17, 0x001c(r19) + cmplwi r17, 0x40 + stw r17, 0x0044(r14) + bgt+ ReleaseAndReturnMPCallOOM + +KCRegisterCpuPlugin_0x114 + lwzu r27, 0x0004(r16) + addi r29, r1, 800 + bl PagingFunc3 + beq+ ReleaseAndReturnMPCallOOM + addi r17, r17, -0x01 + rlwimi r27, r31, 0, 0, 19 + cmpwi r17, 0x00 + stw r27, 0x0000(r16) + bgt+ KCRegisterCpuPlugin_0x114 + _log 'CPU plugin registered^n' + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + +; KCGetCpuCount + +; Called by MPProcessors and MPProcessorsScheduled + +; > r3 = 0:all, 1:scheduled + +; < r3 = cpu_count + + DeclareMPCall 3, KCGetCpuCount + +KCGetCpuCount ; OUTSIDE REFERER + + mfsprg r15, 0 + lwz r14, EWA.CPUBase + CPU.CgrpList + LLL.Freeform(r15) + mr. r8, r3 + + lwz r3, CoherenceGroup.CpuCount(r14) + beq+ CommonMPCallReturnPath + + lwz r3, CoherenceGroup.ScheduledCpuCount(r14) + b CommonMPCallReturnPath + + + +; ARG AddressSpaceID r3 +; RET AddressSpaceID r3, ??? r4, ProcessStructID r5 + + DeclareMPCall 4, KCCreateProcess + +KCCreateProcess ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr. r8, r3 + bne- @spac_id_supplied + lwz r3, PSA.SystemAddressSpaceID(r1) + mr r8, r3 +@spac_id_supplied + + bl LookupID +; r8 = something not sure what +; r9 = 0:inval, 1:proc, 2:task, 3:timer, 4:q, 5:sema, 6:cr, 7:cpu, 8:addrspc, 9:evtg, 10:cohg, 11:area, 12:not, 13:log + + cmpwi r9, AddressSpace.kIDClass + mr r30, r8 + bne+ ReleaseAndReturnMPCallInvalidIDErr + + li r8, 0x20 ;Process.Size + bl PoolAlloc + + mr. r31, r8 + beq+ major_0x0af60 + + li r9, Process.kIDClass + bl MakeID + + cmpwi r8, 0x00 + bne- @did_not_fail + mr r8, r31 + bl PoolFree + b major_0x0af60 +@did_not_fail + + stw r8, Process.ID(r31) + + lisori r16, Process.kSignature + stw r16, Process.Signature(r31) + + stw r3, Process.SystemAddressSpaceID(r31) ; NOT SYSTEM -- fix struct + stw r30, Process.SystemAddressSpacePtr(r31) + + lwz r17, Process.AddressSpaceCount(r31) + addi r17, r17, 1 + stw r17, Process.AddressSpaceCount(r31) + + mr r5, r8 + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 5, MPCall_5 + +MPCall_5 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Process.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + lwz r16, 0x0008(r31) + rlwinm. r17, r16, 0, 30, 30 + bne+ ReleaseAndReturnMPCallOOM + ori r16, r16, 0x02 + stw r16, 0x0008(r31) + mr r8, r3 + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + +; MPCall_6 + +; Xrefs: +; kcMPDispatch +; KCStopScheduling +; MPCall_9 +; KCThrowException + + DeclareMPCall 6, MPCall_6 + +MPCall_6 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Process.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + lwz r16, 0x0008(r31) + lwz r17, 0x0010(r31) + rlwinm. r8, r16, 0, 30, 30 + cmpwi cr1, r17, 0x00 + beq+ ReleaseAndReturnMPCallOOM + bne+ cr1, ReleaseAndReturnMPCallOOM + mr r8, r3 + bl DeleteID + sync + lwz r16, PSA.SchLock + Lock.Count(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + bne+ cr1, MPCall_6_0x68 + mflr r16 + bl panic + +MPCall_6_0x68 + stw r16, PSA.SchLock + Lock.Count(r1) + mr r8, r31 + bl PoolFree + b ReturnZeroFromMPCall + +MPCall_6_0x78 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mfsprg r16, 0 + rlwinm. r8, r7, 0, 10, 10 + lwz r17, 0x0658(r1) + lwz r31, -0x0008(r16) + beq- MPCall_6_0xb4 + lwz r8, 0x00cc(r17) + rlwinm r8, r8, 0, 24, 21 + oris r8, r8, 0x8000 + stw r8, 0x00cc(r17) + +MPCall_6_0xb4 + mr r8, r31 + bl major_0x13e4c + li r16, 0x02 + stb r16, 0x0019(r31) + bl TaskReadyAsPrev + mr r8, r31 + bl major_0x14af8 + sync + lwz r16, PSA.SchLock + Lock.Count(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + bne+ cr1, MPCall_6_0xec + mflr r16 + bl panic + +MPCall_6_0xec + stw r16, PSA.SchLock + Lock.Count(r1) + b CommonMPCallReturnPath + + + +; KCYieldWithHint + + + DeclareMPCall 13, KCYieldWithHint + +KCYieldWithHint ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mfsprg r16, 0 + rlwinm. r8, r7, 0, 10, 10 + lwz r17, 0x0658(r1) + lwz r31, -0x0008(r16) + beq- KCYieldWithHint_0x68 + clrlwi. r8, r3, 0x1f + lwz r8, 0x00cc(r17) + rlwinm r8, r8, 0, 24, 21 + oris r8, r8, 0x8000 + stw r8, 0x00cc(r17) + beq- KCYieldWithHint_0x68 + lbz r16, 0x0019(r31) + cmpwi r16, 0x02 + bge- KCYieldWithHint_0x7c + mr r8, r31 + bl major_0x13e4c + li r16, 0x02 + stb r16, 0x0019(r31) + bl TaskReadyAsNext + b KCYieldWithHint_0x7c + +KCYieldWithHint_0x68 + mr r8, r31 + bl major_0x13e4c + li r16, 0x02 + stb r16, 0x0019(r31) + bl TaskReadyAsPrev + +KCYieldWithHint_0x7c + mr r8, r31 + bl major_0x14af8 + sync + lwz r16, PSA.SchLock + Lock.Count(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + bne+ cr1, KCYieldWithHint_0xa0 + mflr r16 + bl panic + +KCYieldWithHint_0xa0 + stw r16, PSA.SchLock + Lock.Count(r1) + b CommonMPCallReturnPath + + + + DeclareMPCall 33, MPCall_33 + +MPCall_33 ; OUTSIDE REFERER + rlwinm. r8, r7, 0, 10, 10 + bne+ ReturnMPCallBlueBlocking + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + b MPCall_55_0x60 + + + +; MPCall_55 + +; Xrefs: +; kcMPDispatch +; MPCall_33 + + DeclareMPCall 55, MPCall_55 + +MPCall_55 ; OUTSIDE REFERER + rlwinm. r8, r7, 0, 10, 10 + lwz r16, 0x0e80(r1) + beq- MPCall_55_0x60 + lwz r17, -0x08e4(r1) + lwz r18, 0x0658(r1) + cmpw r16, r17 + stw r16, -0x08e4(r1) + bne+ ReturnZeroFromMPCall + lwz r8, 0x00cc(r18) + rlwinm r8, r8, 0, 24, 21 + oris r8, r8, 0x8000 + stw r8, 0x00cc(r18) + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + lwz r16, -0x0410(r1) + cmpwi r16, -0x01 + li r16, 0x00 + bne- MPCall_55_0x60 + stw r16, -0x0410(r1) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_55_0x60 ; OUTSIDE REFERER + mfsprg r16, 0 + li r17, 0x01 + lwz r31, -0x0008(r16) + addi r16, r31, 0x20 + stb r17, 0x0014(r16) + clrlwi r3, r3, 0x01 + stw r3, 0x0038(r16) + stw r4, 0x003c(r16) + stw r31, 0x0018(r16) + mr r8, r16 + bl called_by_init_tmrqs + mr r8, r31 + bl major_0x13e4c + addi r16, r1, -0xa44 + addi r17, r31, 0x08 + stw r16, 0x0000(r17) + stw r16, 0x0008(r17) + lwz r18, 0x000c(r16) + stw r18, 0x000c(r17) + stw r17, 0x0008(r18) + stw r17, 0x000c(r16) + li r3, 0x00 + b AlternateMPCallReturnPath + + + + DeclareMPCall 34, MPCall_34 + +MPCall_34 ; OUTSIDE REFERER + mr r8, r3 + mr r9, r4 + +; r1 = kdp +; r9 = kind + bl MakeID + cmpwi r8, 0x00 + beq+ major_0x0af60_0x20 + mr r5, r8 + b ReturnZeroFromMPCall + + + + DeclareMPCall 35, MPCall_35 + +MPCall_35 ; OUTSIDE REFERER + mr r8, r3 + bl DeleteID + cmpwi r8, 0x01 + beq+ ReturnZeroFromMPCall + b ReturnMPCallInvalidIDErr + + + + DeclareMPCall 36, MPCall_36 + +MPCall_36 ; OUTSIDE REFERER + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, 0 ; invalid + + mr r4, r9 + mr r5, r8 + bne+ ReturnZeroFromMPCall + b ReturnMPCallInvalidIDErr + + + +; Replace the provided process/coherence/console ID with +; the "next" one. IDs were opaque but were only longs. +; Wrapped by MPGetNext*ID, which indirects the opaque ID +; structure. +; From MP docs: A coherence group is the set of processors +; and other bus controllers that have cache-coherent +; access to memory. Mac OS 9 defines only one coherence +; group, which is all the processors that can access +; internal memory (RAM). Other coherence groups are +; possible; for example, a PCI card with its own memory +; and processors can comprise a coherence group. + +; > r3 = kind (process=1,coherence=10,console=13) +; > r4 = prev_id + +; < r3 = MP result code +; < r4 = next_id + + DeclareMPCall 37, KCGetNextID + +KCGetNextID ; OUTSIDE REFERER + mr r8, r4 + mr r9, r3 + bl GetNextIDOfClass + cmpwi r8, 0x00 + mr r4, r8 + bne+ ReturnZeroFromMPCall + b ReturnMPCallInvalidIDErr + + + +; Replace the provided address +; space/task/queue/semaphore/critical +; region/timer/event/notification ID with the "next" one. +; IDs were opaque but were only longs. Wrapped by +; MPGetNext*ID, which indirects the opaque ID structure. +; Differs from KCGetNextID because it deals in +; objects owned by a particular process. + +; Useful info about some poorly understood structures + +; ARG ProcessID r3, IDClass r4, ID r5 +; RET MPErr r3, IDClass r4, ID r5 + + DeclareMPCall 116, KCGetNextIDOwnedByProcess + +KCGetNextIDOwnedByProcess ; OUTSIDE REFERER + + ; Confirm that owner ID in r3 is a Process + + mr r8, r3 + bl LookupID + cmpwi r9, Process.kIDClass + bne+ ReturnMPCallInvalidIDErr + + + ; Loop over IDs (and resolve them) until one is owned by the Process + +@try_another_id + mr r8, r5 + mr r9, r4 + +; ARG ID r8, IDClass r9 + bl GetNextIDOfClass +; RET ID r8 + + mr. r5, r8 + beq+ ReturnMPCallInvalidIDErr + +; ARG ID r8 + bl LookupID +; RET Ptr r8, IDClass r9 + + cmpwi r4, Task.kIDClass + cmpwi cr1, r4, Timer.kIDClass + beq- @task + beq- cr1, @timer + + cmpwi r4, Queue.kIDClass + cmpwi cr1, r4, Semaphore.kIDClass + beq- @queue + beq- cr1, @semaphore + + cmpwi r4, CriticalRegion.kIDClass + cmpwi cr1, r4, AddressSpace.kIDClass + beq- @critical_region + beq- cr1, @address_space + + cmpwi r4, EventGroup.kIDClass + cmpwi cr1, r4, Area.kIDClass + beq- @event_group + beq- cr1, @area + + cmpwi r4, Notification.kIDClass + cmpwi cr1, r4, ConsoleLog.kIDClass + beq- @notification + beq- cr1, @console_log + + b ReturnParamErrFromMPCall + +@task + lwz r17, Task.ThingThatAlignVecHits(r8) + lwz r9, Task.ProcessID(r8) + + rlwinm. r17, r17, 0, 15, 15 + beq- @not_owned_by_blue_process + lwz r9, PSA.blueProcessPtr(r1) + lwz r9, Task.ID(r9) +@not_owned_by_blue_process + + cmpw r9, r3 + bne+ @try_another_id + b ReturnZeroFromMPCall + +@timer + lwz r9, Timer.ProcessID(r8) + cmpw r9, r3 + bne+ @try_another_id + b ReturnZeroFromMPCall + +@queue + lwz r9, Queue.ProcessID(r8) + cmpw r9, r3 + bne+ @try_another_id + b ReturnZeroFromMPCall + +@semaphore + lwz r9, Semaphore.ProcessID(r8) + cmpw r9, r3 + bne+ @try_another_id + b ReturnZeroFromMPCall + +@critical_region + lwz r9, CriticalRegion.ProcessID(r8) + cmpw r9, r3 + bne+ @try_another_id + b ReturnZeroFromMPCall + +@address_space + lwz r9, AddressSpace.ProcessID(r8) + cmpw r9, r3 + bne+ @try_another_id + b ReturnZeroFromMPCall + +@event_group + lwz r9, EventGroup.ProcessID(r8) + cmpw r9, r3 + bne+ @try_another_id + b ReturnZeroFromMPCall + +@area + lwz r9, Area.ProcessID(r8) + cmpw r9, r3 + bne+ @try_another_id + b ReturnZeroFromMPCall + +@notification + lwz r9, Notification.ProcessID(r8) + cmpw r9, r3 + bne+ @try_another_id + b ReturnZeroFromMPCall + +@console_log + lwz r9, ConsoleLog.ProcessID(r8) + cmpw r9, r3 + bne+ @try_another_id + b ReturnZeroFromMPCall + + + + DeclareMPCall 38, MPCall_38 + +MPCall_38 ; OUTSIDE REFERER + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Process.kIDClass + + bne+ ReturnMPCallInvalidIDErr + mr r31, r8 + +MPCall_38_0x14 + mr r8, r4 + li r9, 0x02 + bl GetNextIDOfClass + cmpwi r8, 0x00 + beq+ ReturnMPCallInvalidIDErr + mr r4, r8 + +; r8 = id + bl LookupID +; r8 = something not sure what +; r9 = 0:inval, 1:proc, 2:task, 3:timer, 4:q, 5:sema, 6:cr, 7:cpu, 8:addrspc, 9:evtg, 10:cohg, 11:area, 12:not, 13:log + + lwz r17, 0x0064(r8) + lwz r16, 0x0060(r8) + rlwinm. r17, r17, 0, 15, 15 + beq- MPCall_38_0x48 + lwz r16, -0x041c(r1) + lwz r16, 0x0000(r16) + +MPCall_38_0x48 + cmpw r16, r3 + beq+ ReturnZeroFromMPCall + b MPCall_38_0x14 + + + + DeclareMPCall 62, MPCall_62 + +MPCall_62 ; OUTSIDE REFERER + mr. r8, r3 + bne- MPCall_62_0x18 + mfsprg r15, 0 + lwz r31, -0x0338(r15) + lwz r3, 0x0000(r31) + b MPCall_62_0x24 + +MPCall_62_0x18 +; r8 = id + bl LookupID + cmpwi r9, CoherenceGroup.kIDClass + + bne+ ReturnMPCallInvalidIDErr + +MPCall_62_0x24 + mr r8, r4 + li r9, 0x07 + bl GetNextIDOfClass + cmpwi r8, 0x00 + beq+ ReturnMPCallInvalidIDErr + mr r4, r8 + +; r8 = id + bl LookupID +; r8 = something not sure what +; r9 = 0:inval, 1:proc, 2:task, 3:timer, 4:q, 5:sema, 6:cr, 7:cpu, 8:addrspc, 9:evtg, 10:cohg, 11:area, 12:not, 13:log + + lwz r16, 0x0008(r8) + lwz r17, 0x0000(r16) + cmpw r17, r3 + bne+ MPCall_62_0x24 + b ReturnZeroFromMPCall + + + + DeclareMPCall 42, KCCreateCpuStruct + +KCCreateCpuStruct ; OUTSIDE REFERER + mr. r8, r3 + bne- KCCreateCpuStruct_0x14 + mfsprg r15, 0 + lwz r30, EWA.CPUBase + CPU.CgrpList + LLL.Freeform(r15) + b KCCreateCpuStruct_0x24 + +KCCreateCpuStruct_0x14 +; r8 = id + bl LookupID + cmpwi r9, CoherenceGroup.kIDClass + + mr r30, r8 + bne+ ReturnMPCallInvalidIDErr + +KCCreateCpuStruct_0x24 + li r8, 960 + +; r1 = kdp +; r8 = size + bl PoolAlloc +; r8 = ptr + + mr. r31, r8 + beq+ major_0x0af60_0x20 + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + li r9, 0x07 + +; r1 = kdp +; r9 = kind + bl MakeID + cmpwi r8, 0x00 + bne+ KCCreateCpuStruct_0x68 + mr r8, r31 + bl PoolFree + b major_0x0af60 +KCCreateCpuStruct_0x68 + + + stw r8, CPU.ID(r31) + + lisori r16, CPU.kSignature + + stw r8, ContextBlock.r6(r6) ; return ID in r6 + + stw r16, CPU.Signature(r31) + + lwz r17, 0x0020(r30) + addi r17, r17, 0x01 + stw r17, 0x0020(r30) + addi r16, r31, 0x08 + stw r30, 0x0000(r16) + stw r30, 0x0008(r16) + lwz r17, 0x000c(r30) + stw r17, 0x000c(r16) + stw r16, 0x0008(r17) + stw r16, 0x000c(r30) + + lisori r8, 11 + lisori r8, 6 + stw r8, CPU.Eff(r31) + + + + + addi r30, r31, CPU.EWABase + + + addi r8, r1, PSA.Base + stw r8, EWA.PA_PSA - EWA.Base(r30) + + stw r1, EWA.PA_KDP - EWA.Base(r30) + + li r8, 0 + stw r8, EWA.PA_CurTask - EWA.Base(r30) + + + ; Matches code in Init.s quite closely + + li r8, -0x01 + sth r4, 0x020a(r30) + stb r8, 0x0209(r30) ; interesting... + + lwz r8, EWA.PA_IRP(r1) + stw r8, EWA.PA_IRP - EWA.Base(r30) + + lisori r8, 'time' + stw r8, EWA.TimeList - EWA.Base + LLL.Signature(r30) + + li r8, 0x04 + stb r8, 0x0014(r30) + + li r8, 0x01 + stb r8, 0x0016(r30) + + li r8, 0x00 + stb r8, 0x0017(r30) + + lisori r8, 0x7fffffff + stw r8, 0x0038(r30) + + oris r8, r8, 0xffff + stw r8, 0x003c(r30) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 43, MPCall_43 + +MPCall_43 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, CPU.kIDClass + + mr r31, r8 + bne+ ReleaseAndReturnMPCallInvalidIDErr + lwz r16, 0x0018(r31) + lis r17, 0x00 + ori r17, r17, 0x09 + and. r17, r17, r16 + bne+ ReleaseAndReturnMPCallOOM + mfsprg r15, 0 + li r16, 0x04 + stw r16, -0x0238(r15) + lhz r16, 0x022a(r31) + stw r16, -0x0234(r15) + li r8, 0x02 + +; r7 = flags +; r8 = usually 2? + bl SIGP + lwz r17, 0x0008(r31) + addi r16, r31, 0x08 + lwz r18, 0x0020(r17) + addi r18, r18, -0x01 + stw r18, 0x0020(r17) + lwz r17, 0x0008(r16) + lwz r18, 0x000c(r16) + stw r17, 0x0008(r18) + stw r18, 0x000c(r17) + li r17, 0x00 + stw r17, 0x0008(r16) + stw r17, 0x000c(r16) + mr r8, r31 + bl PoolFree + mr r8, r3 + bl DeleteID + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 44, KCStartCPU + +; ARG CpuID r3 + +KCStartCPU ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + bl LookupID + cmpwi r9, CPU.kIDClass + bne+ ReleaseAndReturnMPCallInvalidIDErr + + mr r30, r8 + lwz r16, CPU.Eff(r30) + rlwinm. r8, r16, 0, 28, 28 + bne+ ReleaseAndReturnZeroFromMPCall + + mfsprg r15, 0 + li r16, 0x04 + stw r16, -0x0238(r15) + lhz r16, 0x022a(r30) + stw r16, -0x0234(r15) + + +; Put the boots in? + + _log 'SIGP kResetProcessor^n' + li r8, 2 + bl SIGP + cmpwi r8, -0x7264 + cmpwi cr1, r8, 0 + beq+ ReleaseAndReturnMPCallOOM + bne+ cr1, ReleaseAndReturnMPCallOOM + + +; Every CPU gets an idle task + + _log 'Creating idle task^n' + mr r31, r7 + rlwinm r7, r7, 0, 13, 11 + lwz r8, PSA.blueProcessPtr(r1) + +; ARG EmpiricalCpuFeatures r7, Process *r8 + bl CreateTask +; RET Task *r8 + + mr r7, r31 + mr. r31, r8 + beq+ major_0x0af60 + + stw r31, CPU.IdleTaskPtr(r30) + + lisori r8, 'idle' + stw r8, Task.Name(r31) + + lisori r8, 0x00080040 ; clearly flags + stw r8, Task.ThingThatAlignVecHits(r31) + + li r8, 1 + stw r8, Task.Weight(r31) + + li r8, Task.kIdlePriority + stb r8, Task.Priority(r31) + + ; whoa -- cpu structs arent this big? + lhz r8, 0x022a(r30) + sth r8, Task.MysteryHalf(r31) + + lwz r8, Task.ContextBlock + ContextBlock.EmpiricalCpuFeatures(r31) + _bset r8, r8, 9 + stw r8, Task.ContextBlock + ContextBlock.EmpiricalCpuFeatures(r31) + + + lwz r8, KDP.PA_NanoKernelCode(r1) + llabel r26, IdleCode + add r8, r8, r26 + stw r8, Task.ContextBlock + ContextBlock.CodePtr(r31) + + ; better compare this with init code idle task + lwz r8, Task.ContextBlock + ContextBlock.MSR(r31) + andi. r8, r8, 0xbfcf + stw r8, Task.ContextBlock + ContextBlock.MSR(r31) + + sync ; flush pending lwarxen? + + +; This feels like cheating with the Sch lock + + lwz r16, PSA.SchLock + Lock.Count(r1) + cmpwi cr1, r16, 0 + li r16, 0 + + bne+ cr1, @do_not_panic + mflr r16 + bl panic +@do_not_panic + + stw r16, PSA.SchLock + Lock.Count(r1) + + + ; Some EWA/KDP stuff I do not understand + mfsprg r15, 0 + li r16, 0x08 + stw r16, -0x0238(r15) + lhz r16, 0x022a(r30) + stw r16, -0x0234(r15) + +MPCall_44_0x15c + _log 'SIGP kSynchClock^n' + li r8, 0x02 + +; r7 = flags +; r8 = usually 2? + bl SIGP + cmpwi r8, -0x7264 + cmpwi cr1, r8, 0x00 + beq+ MPCall_44_0x15c + + + bne- cr1, MPCall_Panic + mfsprg r15, 0 + li r16, 0x01 + stw r16, -0x0238(r15) + lhz r16, 0x022a(r30) + stw r16, -0x0234(r15) + lwz r16, 0x064c(r1) + llabel r17, major_0x14bcc + add r16, r16, r17 + stw r16, -0x0230(r15) + stw r30, -0x022c(r15) + +MPCall_44_0x1c0 + _log 'SIGP kStartProcessor^n' + li r8, 0x04 + +; r7 = flags +; r8 = usually 2? + bl SIGP + cmpwi r8, -0x7264 + cmpwi cr1, r8, 0x00 + beq+ MPCall_44_0x1c0 + bne- cr1, MPCall_Panic + _log 'Processor scheduled^n' + b ReturnZeroFromMPCall + + + +; KCStopScheduling + + + DeclareMPCall 45, KCStopScheduling + +KCStopScheduling ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, CPU.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r30, r8 + lwz r16, 0x0018(r30) + rlwinm. r8, r16, 0, 28, 28 + +; r1 = kdp + beq+ ReleaseAndReturnZeroFromMPCall + lwz r31, 0x001c(r30) + clrlwi. r8, r16, 0x1f + bne+ ReleaseAndReturnMPCallOOM + lbz r17, 0x0019(r31) + cmpwi r17, 0x00 + beq- KCStopScheduling_0x94 + lwz r17, 0x0064(r31) + oris r17, r17, 0x80 + stw r17, 0x0064(r31) + mr r8, r31 + bl major_0x13e4c + li r17, 0x00 + stb r17, 0x0019(r31) + mr r8, r31 + bl TaskReadyAsNext + bl CalculateTimeslice + mr r8, r31 + bl major_0x14af8_0xa0 + lwz r8, 0x064c(r1) + llabel r9, StopProcessor + add r8, r8, r9 + stw r8, 0x01fc(r31) + +KCStopScheduling_0x94 + sync + lwz r16, PSA.SchLock + Lock.Count(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + bne+ cr1, KCStopScheduling_0xb0 + mflr r16 + bl panic + +KCStopScheduling_0xb0 + stw r16, PSA.SchLock + Lock.Count(r1) + b MPCall_6_0x78 + + + +; KCCpuPlugin + + + DeclareMPCall 46, KCCpuPlugin + +KCCpuPlugin ; OUTSIDE REFERER + li r8, 0x00 + +; r7 = flags +; r8 = usually 2? + bl SIGP + mr r3, r8 + mr r4, r9 + b CommonMPCallReturnPath + + + + DeclareMPCall 47, MPCall_47 + +MPCall_47 ; OUTSIDE REFERER + rlwinm. r8, r7, 0, 12, 12 + lwz r15, 0x00d8(r6) + beq+ ReturnMPCallOOM + cmpwi r15, 0x00 + mr r16, r2 + beq+ ReturnMPCallOOM + mr r17, r3 + mr r18, r4 + mr r19, r5 + bl Save_v0_v31 + mr r2, r16 + mr r3, r17 + mr r4, r18 + mr r5, r19 + b ReturnZeroFromMPCall + + + +; MPCall_48_Bad + + + DeclareMPCall 48, MPCall_48_Bad + +MPCall_48_Bad ; OUTSIDE REFERER + b MPCallBad + + + +; NKxprintf + + + DeclareMPCall 96, NKxprintf + +NKxprintf ; OUTSIDE REFERER + rlwinm. r9, r11, 0, 27, 27 + mr r8, r3 + beq- NKxprintf_0x1c + li r9, 0x00 + bl V2P + beq- NKxprintf_0x24 + rlwimi r8, r17, 0, 0, 19 + +NKxprintf_0x1c + bl PrintS + b ReturnZeroFromMPCall + +NKxprintf_0x24 + _log 'NKxprintf (V->P translation error)^n' + b ReturnMPCallOOM + + + +; ARG long r3, int r4 size (1:byte, 2:half, else:word) + + DeclareMPCall 97, NKPrintHex + +NKPrintHex + mr r8, r3 + + cmpwi r4, 1 + cmpwi cr1, r4, 2 + + beq- @byte + beq- cr1, @half + + + bl Printw + b CommonMPCallReturnPath + +@half + bl Printh + b CommonMPCallReturnPath + +@byte + bl Printb + b CommonMPCallReturnPath + + + + DeclareMPCall 124, NKPrintDecimal + +NKPrintDecimal ; OUTSIDE REFERER + mr r8, r3 + bl Printd + b CommonMPCallReturnPath + + + +; KCSetBlueProcessID + + + DeclareMPCall 99, KCSetBlueProcessID + +KCSetBlueProcessID ; OUTSIDE REFERER + mfsprg r16, 0 + rlwinm. r8, r7, 0, 10, 10 + lwz r31, EWA.PA_CurTask(r16) + beq+ ReturnMPCallOOM + mr r8, r3 + +; r8 = id + bl LookupID +; r8 = something not sure what +; r9 = 0:inval, 1:proc, 2:task, 3:timer, 4:q, 5:sema, 6:cr, 7:cpu, 8:addrspc, 9:evtg, 10:cohg, 11:area, 12:not, 13:log + + cmpwi r9, Process.kIDClass + bne+ ReturnMPCallInvalidIDErr + stw r3, Task.ProcessID(r31) + stw r4, 0x00ec(r31) + b ReturnZeroFromMPCall + + + +; KCRegisterThermalHandler + + + DeclareMPCall 104, KCRegisterThermalHandler + +KCRegisterThermalHandler ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr. r8, r3 + beq- @is_zero + bl LookupID + cmpwi r9, Notification.kIDClass + bne+ ReleaseAndReturnMPCallInvalidIDErr +@is_zero + + stw r3, PSA.ThermalHandlerID(r1) + + b ReleaseAndReturnZeroFromMPCall + + + +; KCRegisterPMFHandler + + + DeclareMPCall 105, KCRegisterPMFHandler + +KCRegisterPMFHandler ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr. r8, r3 + beq- @is_zero + bl LookupID + cmpwi r9, Notification.kIDClass + bne+ ReleaseAndReturnMPCallInvalidIDErr +@is_zero + + stw r3, PSA.PMFHandlerID(r1) + + b ReleaseAndReturnZeroFromMPCall + + + +; KCMarkPMFTask + + + DeclareMPCall 106, KCMarkPMFTask + +KCMarkPMFTask ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mfsprg r30, 0 + mr. r8, r3 + lwz r31, EWA.PA_CurTask(r30) + + beq- @use_blue_task_instead + bl LookupID + cmpwi r9, Task.kIDClass + mr r31, r8 + bne+ ReleaseAndReturnMPCallInvalidIDErr +@use_blue_task_instead + +; Insert bit 31 of r4 into bit 21 of these flags + lwz r17, Task.ThingThatAlignVecHits(r31) + rlwimi r17, r4, 10, 21, 21 + stw r17, Task.ThingThatAlignVecHits(r31) + + +; Don't know what this does! + mr r8, r31 + bl major_0x14af8_0xa0 + + b ReleaseAndReturnZeroFromMPCall + + + +; ARG int r6: +; 2: SystemInfo +; 3: DiagInfo +; 4: NanoKernelInfo +; 5: ProcessorInfo +; 6: HWInfo +; 7: ProcessorState + +; RET Ptr r4, short r5 ver, short r6 len + + DeclareMPCall 107, NKLocateInfoRecord + +NKLocateInfoRecord + + cmpwi r3, 5 + cmpwi cr1, r3, 2 + beq- @ProcessorInfo + beq- cr1, @SystemInfo + + cmpwi r3, 3 + cmpwi cr1, r3, 4 + beq- @DiagInfo + beq- cr1, @NanoKernelInfo + + cmpwi r3, 7 + cmpwi cr1, r3, 6 + beq- @ProcessorState + bne+ cr1, ReturnParamErrFromMPCall + + lwz r4, KDP.InfoRecord + InfoRecord.NKHWInfoPtr(r1) + lhz r16, KDP.InfoRecord + InfoRecord.NKHWInfoLen(r1) + lhz r5, KDP.InfoRecord + InfoRecord.NKHWInfoVer(r1) + stw r16, ContextBlock.r6(r6) + b ReturnZeroFromMPCall + +@ProcessorState + lwz r4, KDP.InfoRecord + InfoRecord.NKProcessorStatePtr(r1) + lhz r16, KDP.InfoRecord + InfoRecord.NKProcessorStateLen(r1) + lhz r5, KDP.InfoRecord + InfoRecord.NKProcessorStateVer(r1) + stw r16, ContextBlock.r6(r6) + b ReturnZeroFromMPCall + +@ProcessorInfo + lwz r4, KDP.InfoRecord + InfoRecord.NKProcessorInfoPtr(r1) + lhz r16, KDP.InfoRecord + InfoRecord.NKProcessorInfoLen(r1) + lhz r5, KDP.InfoRecord + InfoRecord.NKProcessorInfoVer(r1) + stw r16, ContextBlock.r6(r6) + b ReturnZeroFromMPCall + +@NanoKernelInfo + lwz r4, KDP.InfoRecord + InfoRecord.NKNanoKernelInfoPtr(r1) + lhz r16, KDP.InfoRecord + InfoRecord.NKNanoKernelInfoLen(r1) + lhz r5, KDP.InfoRecord + InfoRecord.NKNanoKernelInfoVer(r1) + stw r16, ContextBlock.r6(r6) + b ReturnZeroFromMPCall + +@DiagInfo + lwz r4, KDP.InfoRecord + InfoRecord.NKDiagInfoPtr(r1) + lhz r16, KDP.InfoRecord + InfoRecord.NKDiagInfoLen(r1) + lhz r5, KDP.InfoRecord + InfoRecord.NKDiagInfoVer(r1) + stw r16, ContextBlock.r6(r6) + b ReturnZeroFromMPCall + +@SystemInfo + lwz r4, KDP.InfoRecord + InfoRecord.NKSystemInfoPtr(r1) + lhz r16, KDP.InfoRecord + InfoRecord.NKSystemInfoLen(r1) + lhz r5, KDP.InfoRecord + InfoRecord.NKSystemInfoVer(r1) + stw r16, ContextBlock.r6(r6) + b ReturnZeroFromMPCall + + + + DeclareMPCall 108, MPCall_108 + +MPCall_108 ; OUTSIDE REFERER + cmplwi r3, 0x02 + bge+ ReturnParamErrFromMPCall + mulli r17, r3, 0x10 + addi r18, r1, 0xf80 + add r18, r17, r18 + lwz r16, 0x0134(r6) + stw r4, 0x0000(r18) + stw r5, 0x0004(r18) + stw r16, 0x0008(r18) + _log 'Clock rates for step ' + mr r8, r3 + bl Printd + _log '- Cpu ' + mr r8, r4 + bl Printd + _log '- Bus ' + mr r8, r5 + bl Printd + _log '- Dec ' + mr r8, r16 + bl Printd + _log 'Hz^n' + b ReturnZeroFromMPCall + + + +; NKSetClockStep + +; Debug string matches MPLibrary! +; 0xf7e(r1) = clock_step (half-word) + +; > r3 = new_clock_step # (half-word) + + DeclareMPCall 131, NKSetClockStep + +NKSetClockStep ; OUTSIDE REFERER + mfsprg r9, 0 + lwz r8, -0x0338(r9) + lwz r9, 0x0024(r8) + cmpwi r9, 0x01 + bgt+ ReturnMPCallOOM + lhz r19, 0x0f7e(r1) + _log 'NKSetClockStep - current ' + mr r8, r19 + bl Printd + _log ' new ' + mr r8, r3 + bl Printd + _log '^n' + cmplwi r3, 0x02 + cmpw cr1, r3, r19 + bge+ ReturnParamErrFromMPCall + beq+ cr1, ReturnMPCallOOM + mulli r17, r3, 0x10 + addi r18, r1, 0xf80 + sth r17, 0x0f7e(r1) + add r18, r17, r18 + lwz r16, 0x0000(r18) + lwz r17, 0x0004(r18) + stw r16, 0x0f24(r1) + stw r17, 0x0f28(r1) + lwz r16, 0x0f88(r1) + stw r16, 0x0f2c(r1) + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + lwz r16, 0x0008(r18) + stw r16, -0x0438(r1) + bgt- cr1, NKSetClockStep_0xec + lwz r31, -0x0434(r1) + lbz r18, 0x0017(r31) + cmpwi r18, 0x00 + +; r1 = kdp + beq+ ReleaseAndReturnZeroFromMPCall + mr r8, r31 + bl major_0x136c8 + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +NKSetClockStep_0xec + lwz r31, -0x0434(r1) + lbz r18, 0x0017(r31) + cmpwi r18, 0x01 + +; r1 = kdp + beq+ ReleaseAndReturnZeroFromMPCall + bl GetTime + stw r8, 0x0038(r31) + stw r9, 0x003c(r31) + mr r8, r31 + bl called_by_init_tmrqs + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + +; NKSetClockDriftCorrection + +; There's a one-billion constant in here, for fractional +; expression. +; -0x36c(r1) = tb_drift_numerator +; -0x368(r1) = tb_drift_denominator + +; > r3 = to + + DeclareMPCall 132, NKSetClockDriftCorrection + +NKSetClockDriftCorrection ; OUTSIDE REFERER + lwz r31, -0x0364(r1) + mfsprg r9, 0 + cmpwi r31, 0x00 + beq+ ReturnMPCallOOM + lwz r8, -0x0338(r9) + lwz r9, 0x0024(r8) + cmpwi r9, 0x01 + bgt+ ReturnMPCallOOM + lwz r19, 0x0fa0(r1) + cmpwi r3, 0x00 + cmpw cr1, r3, r19 + stw r3, 0x0fa0(r1) + beq- NKSetClockDriftCorrection_0x12c + beq+ cr1, ReturnZeroFromMPCall + lis r16, 0x3b9a + ori r16, r16, 0xca00 + lwz r17, 0x0f88(r1) + srwi r17, r17, 7 + divw r18, r16, r3 + cmpw r18, r17 + bge- NKSetClockDriftCorrection_0x64 + divw r16, r16, r17 + mr r18, r17 + divw r17, r3, r16 + b NKSetClockDriftCorrection_0x6c + +NKSetClockDriftCorrection_0x64 + rlwinm r17, r3, 2, 30, 30 + addi r17, r17, 0x01 + +NKSetClockDriftCorrection_0x6c + stw r17, -0x036c(r1) + stw r18, -0x0368(r1) + _log 'TB drift adjusted to ' + mr r8, r3 + bl Printd + _log ' ppb ( ' + mr r8, r17 + bl Printd + _log '/ ' + mr r8, r18 + bl Printd + _log ')^n' + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + lwz r31, -0x0364(r1) + lbz r18, 0x0017(r31) + cmpwi r18, 0x01 + +; r1 = kdp + beq+ ReleaseAndReturnZeroFromMPCall + bl GetTime + stw r8, 0x0038(r31) + stw r9, 0x003c(r31) + mr r8, r31 + bl called_by_init_tmrqs + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +NKSetClockDriftCorrection_0x12c + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + li r17, 0x00 + stw r17, -0x036c(r1) + stw r17, -0x0368(r1) + lwz r31, -0x0364(r1) + lbz r18, 0x0017(r31) + cmpwi r18, 0x00 + +; r1 = kdp + beq+ ReleaseAndReturnZeroFromMPCall + mr r8, r31 + bl major_0x136c8 + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 115, MPCall_115 + +MPCall_115 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, ConsoleLog.kIDClass + + mr r31, r8 + bne+ ReleaseAndReturnMPCallInvalidIDErr + lwz r30, 0x000c(r31) + cmpwi r30, 0x00 + bne- MPCall_115_0x94 + + _Lock PSA.DbugLock, scratch1=r16, scratch2=r17 + + lwz r30, -0x0404(r1) + +MPCall_115_0x54 + addi r30, r30, 0x01 + andi. r29, r30, 0xfff + bne- MPCall_115_0x64 + lwz r30, -0x1000(r30) + +MPCall_115_0x64 + lbz r16, 0x0000(r30) + cmpwi r16, 0x00 + beq+ MPCall_115_0x54 + stw r30, 0x000c(r31) + sync + lwz r16, -0x0af0(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + bne+ cr1, MPCall_115_0x90 + mflr r16 + bl panic + +MPCall_115_0x90 + stw r16, -0x0af0(r1) + +MPCall_115_0x94 + cmpwi r5, 0x00 + ble+ ReleaseAndReturnMPCallOOM + rlwinm. r9, r11, 0, 27, 27 + mr r8, r4 + crmove 30, 2 + beq- MPCall_115_0xd0 + li r9, 0x00 + bl MPCall_95_0x45c + beq+ ReleaseAndReturnMPCallOOM + add r8, r4, r5 + li r9, 0x00 + addi r8, r8, -0x01 + mr r30, r8 + bl MPCall_95_0x45c + beq+ ReleaseAndReturnMPCallOOM + +MPCall_115_0xd0 + lwz r28, -0x0404(r1) + lwz r29, 0x000c(r31) + li r5, 0x00 + not r27, r4 + +MPCall_115_0xe0 + cmpw r28, r29 + cmplw cr1, r4, r30 + beq- MPCall_115_0x144 + bgt- cr1, MPCall_115_0x144 + rlwinm r16, r4, 0, 0, 19 + mr r8, r4 + beq- cr7, MPCall_115_0x11c + cmpw r16, r27 + mr r17, r26 + beq- MPCall_115_0x11c + mr r27, r16 + li r9, 0x00 + bl MPCall_95_0x45c + beq+ ReleaseAndReturnMPCallOOM + mr r26, r17 + +MPCall_115_0x11c + rlwimi r17, r4, 0, 20, 31 + lbz r8, 0x0000(r29) + addi r29, r29, 0x01 + andi. r16, r29, 0xfff + bne+ MPCall_115_0x134 + lwz r29, -0x1000(r29) + +MPCall_115_0x134 + stb r8, 0x0000(r17) + addi r5, r5, 0x01 + addi r4, r4, 0x01 + b MPCall_115_0xe0 + +MPCall_115_0x144 + stw r29, 0x000c(r31) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + +; KCRegisterExternalHandler + +; Point external interrupts (thing PIHes) towards this notification + + + DeclareMPCall 121, KCRegisterExternalHandler + +KCRegisterExternalHandler + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr. r8, r3 + beq- @zero + bl LookupID + cmpwi r9, Notification.kIDClass + bne+ ReleaseAndReturnMPCallInvalidIDErr +@zero + + stw r3, PSA.ExternalHandlerID(r1) + + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 133, MPCall_133 + +MPCall_133 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + cmpw r3, r0 + lwz r16, 0x0edc(r1) + li r17, 0x0b + blt- MPCall_133_0x34 + and r3, r3, r17 + or r16, r16, r3 + b MPCall_133_0x3c + +MPCall_133_0x34 + orc r3, r3, r17 + and r16, r16, r3 + +MPCall_133_0x3c + stw r16, 0x0edc(r1) + srawi r16, r4, 16 + extsh r17, r4 + cmpwi r16, -0x01 + cmpwi cr1, r17, -0x01 + beq- MPCall_133_0x60 + bgt- MPCall_133_0x5c + li r16, 0x00 + +MPCall_133_0x5c + sth r16, -0x0360(r1) + +MPCall_133_0x60 + beq- cr1, MPCall_133_0x70 + bgt- cr1, MPCall_133_0x6c + li r17, 0x00 + +MPCall_133_0x6c + sth r17, -0x035e(r1) + +MPCall_133_0x70 + srawi r16, r5, 16 + extsh r17, r5 + cmpwi r16, -0x01 + cmpwi cr1, r17, -0x01 + beq- MPCall_133_0x90 + bgt- MPCall_133_0x8c + li r16, 0x00 + +MPCall_133_0x8c + sth r16, -0x035c(r1) + +MPCall_133_0x90 + beq- cr1, MPCall_133_0xa0 + bgt- cr1, MPCall_133_0x9c + li r17, 0x00 + +MPCall_133_0x9c + sth r17, -0x035a(r1) + +MPCall_133_0xa0 +; r1 = kdp + bl ScreenConsole_redraw + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + +; MPCall_Panic + +; Xrefs: +; KCStartCPU + +MPCall_Panic + b panic diff --git a/NanoKernel/NKMacros.s b/NanoKernel/NKMacros.s new file mode 100644 index 0000000..5886507 --- /dev/null +++ b/NanoKernel/NKMacros.s @@ -0,0 +1,192 @@ + MACRO + _log &s + BL @paststring + STRING AsIs + DC.B &s, 0, 0 + ALIGN 2 +@paststring + mflr r8 + BL PrintS + ENDM + + ; Cool macro for one-line debug calls + MACRO + _wlog &s1, ®, &s2, &scratch==r8 + + if &TYPE('ExtraNKLogging') != 'UNDEFINED' + mr &scratch, r8 + + _log &s1 + _log '[ ' + + mr r8, ® + bl PrintW + + _log ']' + _log &s2 + + mr r8, &scratch + endif + + ENDM + + MACRO + _wlogh &s1, ®, &s2, &scratch==r8 + + if &TYPE('ExtraNKLogging') != 'UNDEFINED' + mr &scratch, r8 + + _log &s1 + _log '[ ' + + mr r8, ® + bl PrintH + + _log ']' + _log &s2 + + mr r8, &scratch + endif + + ENDM + + MACRO + _clog &s + + if &TYPE('ExtraNKLogging') != 'UNDEFINED' + _log &s + endif + + ENDM + + + MACRO + LHHI ®, &val + lis (®), ((&val) >> 16) & 0xffff + ENDM + + + MACRO + LLHI ®, &val + ori (®), (®), (&val) & 0xffff + ENDM + + + MACRO + lisori ®, &val + lis ®, ((&val) >> 16) & 0xffff + ori ®, ®, (&val) & 0xffff + ENDM + + MACRO + llabel ®, &val + lisori ®, &val - NKTop + ENDM + + + + MACRO + StartLoadingWord ®, &val + LHHI (®), (&val) +HalfLoadedWord set (&val) +HalfLoadedReg set (®) + ENDM + + + MACRO + FinishLoadingWord + LLHI HalfLoadedReg, HalfLoadedWord + ENDM + + + MACRO + InitList &ptr, &sig, &scratch==r8 + StartLoadingWord &scratch, &sig + stw &ptr, LLL.Next(&ptr) + FinishLoadingWord + stw &ptr, LLL.Prev(&ptr) + stw &scratch, LLL.Signature(&ptr) + ENDM + + + ; Next is 8, Prev is C + + MACRO + InsertAsPrev &el, &next, &scratch==r18 + + stw &next, LLL.Next(&el) + lwz &scratch, LLL.Prev(&next) + stw &scratch, LLL.Prev(&el) + stw &el, LLL.Next(&scratch) + stw &el, LLL.Prev(&next) + + ENDM + + + MACRO + InsertAsNext &el, &prev, &scratch==r18 + + stw &prev, LLL.Prev(&el) + lwz &scratch, LLL.Next(&prev) + stw &scratch, LLL.Next(&el) + stw &el, LLL.Prev(&scratch) + stw &el, LLL.Next(&prev) + + ENDM + + + MACRO + RemoveFromList &el, &scratch1==r17, &scratch2==r18 + + ; Point neighbours of el up and down at each other + lwz &scratch1, 8(&el) + lwz &scratch2, 12(&el) + stw &scratch1, 8(&scratch2) + stw &scratch2, 12(&scratch1) + + ; Zero out the pointers in el + li &scratch1, 0 + stw &scratch1, 8(&el) + stw &scratch1, 12(&el) + + ENDM + + + MACRO + _Lock &lockoffset, &scratch1==r17, &scratch2==r18 + mr &scratch1, r8 + mr &scratch2, r9 + addi r8, r1, &lockoffset + bl AcquireLock + mr r8, &scratch1 + mr r9, &scratch2 + ENDM + + MACRO + _bset &dest, &src, &bit + + IF &bit < 16 + oris&dot &dest, &src, 1 << (15 - (&bit)) + ELSE + ori&dot &dest, &src, 1 << (31 - (&bit)) + ENDIF + + ENDM + + MACRO + _bclr &dest, &src, &bit + + rlwinm&dot &dest, &src, 0, (&bit)+1, (&bit)-1 + + ENDM + + MACRO + _band &dest, &src, &bit + + IF &bit < 16 + andis&dot &dest, &src, 1 << (15 - (&bit)) + ELSE + andi&dot &dest, &src, 1 << (31 - (&bit)) + ENDIF + + ENDM diff --git a/NanoKernel/NKPaging.s b/NanoKernel/NKPaging.s new file mode 100644 index 0000000..7694d9b --- /dev/null +++ b/NanoKernel/NKPaging.s @@ -0,0 +1,753 @@ +Local_Panic set * + b panic + + + +; PagingFunc1 + +; Xrefs: +; setup +; IntDSIOtherOther +; IntISI +; IntDSIOther +; kcVMDispatch +; print_memory_logical + + align 5 + +PagingFunc1 ; OUTSIDE REFERER + mfsprg r29, 0 + mflr r28 + stw r8, -0x00dc(r29) + mfcr r8 + stw r9, -0x00d8(r29) + stw r8, -0x00a4(r29) + stw r14, -0x00d4(r29) + stw r15, -0x00d0(r29) + stw r16, -0x00cc(r29) + stw r17, -0x00c8(r29) + stw r18, -0x00c4(r29) + stw r19, -0x00c0(r29) + stw r20, -0x00bc(r29) + stw r21, -0x00b8(r29) + stw r22, -0x00b4(r29) + stw r28, -0x00e0(r29) + b @_88 + +@_44 + mfsprg r29, 0 + lwz r8, -0x00a4(r29) + lwz r28, -0x00e0(r29) + mtcrf 0x7f, r8 + lwz r8, -0x00dc(r29) + mtlr r28 + lwz r9, -0x00d8(r29) + lwz r14, -0x00d4(r29) + lwz r15, -0x00d0(r29) + lwz r16, -0x00cc(r29) + lwz r17, -0x00c8(r29) + lwz r18, -0x00c4(r29) + lwz r19, -0x00c0(r29) + lwz r20, -0x00bc(r29) + lwz r21, -0x00b8(r29) + lwz r22, -0x00b4(r29) + blr + +@_88 + mfsprg r30, 0 + mr r9, r27 + lwz r8, -0x001c(r30) + bl FindAreaAbove + mr r31, r8 + stw r8, -0x00e4(r30) + stw r27, -0x00e8(r30) + lwz r16, 0x0024(r31) + lwz r17, 0x0020(r31) + cmplw r16, r27 + lwz r18, 0x007c(r31) + bgt- @_1a0 + bgt+ @_44 + and r28, r27, r18 + rlwinm. r26, r17, 0, 16, 16 + lwz r17, 0x0038(r31) + beq- @_fc + lwz r18, 0x0070(r31) + subf r19, r16, r28 + clrlwi r31, r18, 0x1e + cmpwi cr7, r17, -0x01 + cmpwi cr6, r31, 0x00 + beq- cr7, @_1a0 + beq+ cr6, @_44 + cmpwi r17, 0x01 + add r31, r18, r19 + blt+ @_44 + li r26, 0x00 + b @_208 + +@_fc + mr r8, r27 + bl MPCall_95_0x1e4 + lwz r28, 0x0000(r30) + mr r26, r30 + mr r8, r27 + bl MPCall_95_0x254 + beq- @_12c + lhz r16, 0x0000(r30) + rlwinm. r8, r16, 0, 16, 16 + bne- @_12c + srwi r16, r16, 1 + sth r16, 0x0000(r30) + +@_12c + lwz r8, 0x0024(r31) + lwz r9, 0x06b4(r1) + cmpwi r8, 0x00 + cmpwi cr6, r9, 0x00 + li r8, 0x801 + li r9, 0x01 + bne- @_154 + beq- cr6, @_154 + li r8, 0x881 + li r9, 0x81 + +@_154 + lwz r31, 0x0688(r1) + and. r30, r28, r8 + rlwimi r31, r28, 0, 0, 19 + cmplwi cr6, r30, 0x800 + cmplwi r30, 0x01 + bge- cr6, @_2ec + cmplw cr7, r30, r9 + ori r31, r31, 0x100 + rlwimi r31, r28, 28, 28, 28 + rlwimi r31, r28, 3, 24, 24 + rlwimi r31, r28, 31, 26, 26 + rlwimi r31, r28, 1, 25, 25 + xori r31, r31, 0x40 + rlwimi r31, r28, 30, 31, 31 + rlwimi r31, r28, 0, 30, 30 + xori r31, r31, 0x02 + beq- @_208 + blt+ cr7, @_44 + bl Local_Panic + +@_1a0 + lwz r29, 0x05e8(r1) + rlwinm r28, r27, 7, 25, 28 + lwzx r29, r29, r28 + rlwinm r28, r27, 20, 16, 31 + lhz r30, 0x0000(r29) + b @_1bc + +@_1b8 + lhzu r30, 0x0008(r29) + +@_1bc + lhz r31, 0x0002(r29) + subf r30, r30, r28 + cmplw cr7, r30, r31 + bgt+ cr7, @_1b8 + lwz r28, 0x0690(r1) + lwz r31, 0x0004(r29) + cmpwi cr7, r28, 0x00 + bnel- cr7, @_314 + rlwinm. r26, r31, 23, 29, 30 + cmplwi cr7, r26, 0x06 + beq- @_200 + cmplwi cr6, r26, 0x02 + beq- cr7, @_368 + beq- cr6, @_3b8 + b @_44 + dc.l 0x41800168 + dc.l 0x418101bc + +@_200 + slwi r28, r30, 12 + add r31, r31, r28 + +@_208 + mfsrin r30, r27 + rlwinm r28, r27, 26, 10, 25 + rlwinm r30, r30, 6, 7, 25 + xor r28, r28, r30 + lwz r30, KDP.PTEGMask(r1) + lwz r29, KDP.HTABORG(r1) + and r28, r28, r30 + or. r29, r29, r28 + +@_228 + lwz r30, 0x0000(r29) + lwz r28, 0x0008(r29) + cmpwi cr6, r30, 0x00 + lwz r30, 0x0010(r29) + cmpwi cr7, r28, 0x00 + lwzu r28, 0x0018(r29) + bge- cr6, @_298 + cmpwi cr6, r30, 0x00 + lwzu r30, 0x0008(r29) + bge- cr7, @_298 + cmpwi cr7, r28, 0x00 + lwzu r28, 0x0008(r29) + bge- cr6, @_298 + cmpwi cr6, r30, 0x00 + lwzu r30, 0x0008(r29) + bge- cr7, @_298 + cmpwi cr7, r28, 0x00 + lwzu r28, 0x0008(r29) + bge- cr6, @_298 + cmpwi cr6, r30, 0x00 + addi r29, r29, 0x08 + bge- cr7, @_298 + cmpwi cr7, r28, 0x00 + addi r29, r29, 0x08 + bge- cr6, @_298 + rlwinm r28, r31, 0, 26, 26 + addi r29, r29, 0x08 + blt- cr7, @_3e0 + +@_298 + cmpwi r26, 0x00 + mfsrin r28, r27 + rlwinm r30, r27, 10, 26, 31 + stw r27, 0x0694(r1) + oris r30, r30, 0x8000 + ori r31, r31, 0x100 + rlwimi r30, r31, 27, 25, 25 + rlwinm r31, r31, 0, 21, 19 + rlwimi r30, r28, 7, 1, 24 + stw r31, -0x0014(r29) + eieio + stwu r30, -0x0018(r29) + sync + lwz r28, 0x0e94(r1) + stw r29, 0x0698(r1) + addi r28, r28, 0x01 + stw r28, 0x0e94(r1) + beq+ @_44 + cmpwi r26, 0x5a5a + bne- @_2f4 + stw r29, 0x0690(r1) + +@_2ec + cmpw r29, r29 + b @_44 + +@_2f4 + lwz r28, 0x0000(r26) + lwz r30, KDP.HTABORG(r1) + ori r28, r28, 0x800 + subf r30, r30, r29 + cmpw r29, r29 + rlwimi r28, r30, 9, 0, 19 + stw r28, 0x0000(r26) + b @_44 + +@_314 + lwz r28, 0x0e98(r1) + lwz r29, 0x0690(r1) + addi r28, r28, 0x01 + stw r28, 0x0e98(r1) + li r28, 0x00 + stw r28, 0x0000(r29) + lwz r29, 0x068c(r1) + stw r28, 0x068c(r1) + stw r28, 0x0690(r1) + mfspr r28, pvr + rlwinm. r28, r28, 0, 0, 14 + sync + tlbie r29 + beq- @_354 + sync + tlbsync + +@_354 + sync + isync + blr + dc.l 0x57fca803 + dc.l 0x40800068 + +@_368 + slwi r28, r30, 2 + rlwinm r26, r31, 22, 0, 29 + lwzux r28, r26, r28 + lwz r31, 0x0688(r1) + andi. r30, r28, 0x881 + rlwimi r31, r28, 0, 0, 19 + cmplwi cr6, r30, 0x800 + cmplwi cr7, r30, 0x81 + cmplwi r30, 0x01 + bge+ cr6, @_2ec + cmplwi cr7, r30, 0x81 + ori r31, r31, 0x100 + rlwimi r31, r28, 3, 24, 24 + rlwimi r31, r28, 31, 26, 26 + rlwimi r31, r28, 1, 25, 25 + xori r31, r31, 0x40 + rlwimi r31, r28, 30, 31, 31 + beq+ @_208 + blt+ cr7, @_44 + bl Local_Panic + +@_3b8 + ori r28, r27, 0xfff + stw r28, 0x068c(r1) + rlwinm r31, r31, 0, 22, 19 + li r26, 0x5a5a + b @_208 + dc.l 0x4181fc78 + dc.l 0x4bfffc11 + dc.l 0x3ba105c8 + dc.l 0x48000281 + dc.l 0x4bfffc68 + +@_3e0 + cmplw cr6, r28, r26 + addi r29, r29, -0x50 + ble- cr6, @_400 + crnot 2, 2 + lwz r30, KDP.PTEGMask(r1) + xori r31, r31, 0x800 + xor r29, r29, r30 + beq+ @_228 + +@_400 + lwz r26, 0x069c(r1) + crclr cr6_eq + rlwimi r26, r29, 0, 0, 25 + li r9, 0x08 + addi r29, r26, 0x08 + b @_428 + dc.l 0x409a0008 + dc.l 0x7fbaeb78 + +@_420 + cmpw cr6, r29, r26 + addi r29, r29, 0x08 + +@_428 + rlwimi r29, r26, 0, 0, 25 + lwz r31, 0x0004(r29) + lwz r30, 0x0000(r29) + beq- cr6, @_444 + rlwinm r28, r31, 30, 25, 25 + andc. r28, r28, r30 + bne+ @_420 + +@_444 + addi r9, r9, -0x01 + cmpwi cr7, r9, 0x00 + rlwinm r31, r30, 0, 25, 25 + blel+ cr7, Local_Panic + rlwinm r28, r30, 1, 0, 3 + neg r31, r31 + rlwimi r28, r30, 22, 4, 9 + xor r31, r31, r29 + rlwimi r28, r30, 5, 10, 19 + rlwinm r31, r31, 6, 10, 19 + xor r28, r28, r31 + xoris r30, r30, 0x8000 + lwz r31, 0x0e9c(r1) + stw r29, 0x069c(r1) + addi r31, r31, 0x01 + stw r31, 0x0e9c(r1) + lwz r31, 0x0e98(r1) + stw r30, 0x0000(r29) + addi r31, r31, 0x01 + stw r31, 0x0e98(r1) + sync + mfspr r31, pvr + rlwinm. r31, r31, 0, 0, 14 + tlbie r28 + beq- @_4b0 + sync + tlbsync + +@_4b0 + sync + isync + li r8, -0x01 + stw r8, 0x0340(r1) + stw r8, 0x0348(r1) + stw r8, 0x0350(r1) + stw r8, 0x0358(r1) + mfsprg r8, 0 + mr r9, r28 + lwz r8, -0x001c(r8) + bl FindAreaAbove + lwz r16, 0x0024(r8) + mr r31, r8 + cmplw r16, r28 + mr r8, r28 + bgt- @_600 + bgt+ Local_Panic + bl MPCall_95_0x1e4 + mr r26, r30 + beql+ @_88 + +@_500 + lwz r28, 0x0000(r26) + lwz r31, 0x0004(r29) + andi. r30, r28, 0x800 + rlwinm r30, r28, 23, 9, 28 + xor r30, r30, r29 + beq+ Local_Panic + andi. r30, r30, 0xffff + xori r28, r28, 0x800 + bne+ Local_Panic + rlwimi r28, r31, 0, 0, 19 + rlwimi r28, r31, 29, 27, 27 + rlwimi r28, r31, 27, 28, 28 + stw r28, 0x0000(r26) + bl @_88 + _log 'PTEG overflow: EA ' + mr r8, r27 + bl Printw + _log 'Victim EA: ' + mr r8, r28 + bl Printw + _log 'MapInfo: ' + mr r8, r29 + bl Printw + lwz r16, 0x0000(r26) + mr r8, r26 + bl Printw + mr r8, r16 + bl Printw + _log ' PTE: ' + lwz r16, 0x0000(r29) + lwz r17, 0x0004(r29) + mr r8, r29 + bl Printw + mr r8, r16 + bl Printw + mr r8, r17 + bl Printw + _log '^n' + bl @_88 + +@_600 + lwz r26, 0x05e8(r1) + rlwinm r30, r28, 7, 25, 28 + lwzx r26, r26, r30 + +@_60c + lhz r30, 0x0000(r26) + rlwinm r31, r28, 20, 16, 31 + subf r30, r30, r31 + lhz r31, 0x0002(r26) + addi r26, r26, 0x08 + cmplw cr7, r30, r31 + lwz r31, -0x0004(r26) + andi. r31, r31, 0xe01 + cmpwi r31, 0xa01 + bgt+ cr7, @_60c + beq+ @_60c + lwz r26, -0x0004(r26) + slwi r30, r30, 2 + rlwinm r31, r26, 22, 30, 31 + cmpwi cr7, r31, 0x03 + rlwinm r26, r26, 22, 0, 29 + add r26, r26, r30 + bnel+ cr7, @_88 + b @_500 + + + +; PagingFunc2 + +; Xrefs: +; setup + +PagingFunc2 ; OUTSIDE REFERER + sync + isync + lwz r28, 0x0000(r29) + stw r28, 0x05e8(r1) + addi r28, r28, 0x84 + lis r31, 0x00 + +@_18 + lwzu r30, -0x0008(r28) + addis r31, r31, -0x1000 + mr. r31, r31 + mtsrin r30, r31 + bne+ @_18 + isync + +PagingFunc2AndAHalf + lwz r28, 0x0004(r29) + mfspr r31, pvr + rlwinm. r31, r31, 0, 0, 14 + addi r29, r1, 0x00 + stw r28, 0x05ec(r1) + beq- @_168 + li r30, 0x00 + mtspr ibat0u, r30 + mtspr ibat1u, r30 + mtspr ibat2u, r30 + mtspr ibat3u, r30 + mtspr dbat0u, r30 + mtspr dbat1u, r30 + mtspr dbat2u, r30 + mtspr dbat3u, r30 + rlwimi r29, r28, 7, 25, 28 + lwz r31, 0x0284(r29) + lwz r30, 0x0280(r29) + rlwinm r31, r31, 0, 29, 27 + mtspr ibat0l, r31 + mtspr ibat0u, r30 + stw r31, 0x0304(r1) + stw r30, 0x0300(r1) + rlwimi r29, r28, 11, 25, 28 + lwz r31, 0x0284(r29) + lwz r30, 0x0280(r29) + rlwinm r31, r31, 0, 29, 27 + mtspr ibat1l, r31 + mtspr ibat1u, r30 + stw r31, 0x030c(r1) + stw r30, 0x0308(r1) + rlwimi r29, r28, 15, 25, 28 + lwz r31, 0x0284(r29) + lwz r30, 0x0280(r29) + rlwinm r31, r31, 0, 29, 27 + mtspr ibat2l, r31 + mtspr ibat2u, r30 + stw r31, 0x0314(r1) + stw r30, 0x0310(r1) + rlwimi r29, r28, 19, 25, 28 + lwz r31, 0x0284(r29) + lwz r30, 0x0280(r29) + rlwinm r31, r31, 0, 29, 27 + mtspr ibat3l, r31 + mtspr ibat3u, r30 + stw r31, 0x031c(r1) + stw r30, 0x0318(r1) + rlwimi r29, r28, 23, 25, 28 + lwz r31, 0x0284(r29) + lwz r30, 0x0280(r29) + mtspr dbat0l, r31 + mtspr dbat0u, r30 + stw r31, 0x0324(r1) + stw r30, 0x0320(r1) + rlwimi r29, r28, 27, 25, 28 + lwz r31, 0x0284(r29) + lwz r30, 0x0280(r29) + mtspr dbat1l, r31 + mtspr dbat1u, r30 + stw r31, 0x032c(r1) + stw r30, 0x0328(r1) + rlwimi r29, r28, 31, 25, 28 + lwz r31, 0x0284(r29) + lwz r30, 0x0280(r29) + mtspr dbat2l, r31 + mtspr dbat2u, r30 + stw r31, 0x0334(r1) + stw r30, 0x0330(r1) + rlwimi r29, r28, 3, 25, 28 + lwz r31, 0x0284(r29) + lwz r30, 0x0280(r29) + mtspr dbat3l, r31 + mtspr dbat3u, r30 + stw r31, 0x033c(r1) + stw r30, 0x0338(r1) + isync + cmpw r29, r29 + blr + +@_168 + rlwimi r29, r28, 7, 25, 28 + lwz r30, 0x0280(r29) + lwz r31, 0x0284(r29) + stw r30, 0x0300(r1) + stw r31, 0x0304(r1) + stw r30, 0x0320(r1) + stw r31, 0x0324(r1) + rlwimi r30, r31, 0, 25, 31 + mtspr ibat0u, r30 + lwz r30, 0x0280(r29) + rlwimi r31, r30, 30, 26, 31 + rlwimi r31, r30, 6, 25, 25 + mtspr ibat0l, r31 + rlwimi r29, r28, 11, 25, 28 + lwz r30, 0x0280(r29) + lwz r31, 0x0284(r29) + stw r30, 0x0308(r1) + stw r31, 0x030c(r1) + stw r30, 0x0328(r1) + stw r31, 0x032c(r1) + rlwimi r30, r31, 0, 25, 31 + mtspr ibat1u, r30 + lwz r30, 0x0280(r29) + rlwimi r31, r30, 30, 26, 31 + rlwimi r31, r30, 6, 25, 25 + mtspr ibat1l, r31 + rlwimi r29, r28, 15, 25, 28 + lwz r30, 0x0280(r29) + lwz r31, 0x0284(r29) + stw r30, 0x0310(r1) + stw r31, 0x0314(r1) + stw r30, 0x0330(r1) + stw r31, 0x0334(r1) + rlwimi r30, r31, 0, 25, 31 + mtspr ibat2u, r30 + lwz r30, 0x0280(r29) + rlwimi r31, r30, 30, 26, 31 + rlwimi r31, r30, 6, 25, 25 + mtspr ibat2l, r31 + rlwimi r29, r28, 19, 25, 28 + lwz r30, 0x0280(r29) + lwz r31, 0x0284(r29) + stw r30, 0x0318(r1) + stw r31, 0x031c(r1) + stw r30, 0x0338(r1) + stw r31, 0x033c(r1) + rlwimi r30, r31, 0, 25, 31 + mtspr ibat3u, r30 + lwz r30, 0x0280(r29) + rlwimi r31, r30, 30, 26, 31 + rlwimi r31, r30, 6, 25, 25 + mtspr ibat3l, r31 + cmpw r29, r29 + blr + + + +; PagingFunc3 + +; Xrefs: +; IntDSIOtherOther +; kcRunAlternateContext +; kcRTASDispatch +; KCRegisterCpuPlugin +; MPCall_103 + +PagingFunc3 ; OUTSIDE REFERER + lwz r30, 0x0000(r29) + li r28, -0x01 + rlwimi r28, r30, 15, 0, 14 + xor r31, r27, r30 + andc. r31, r31, r28 + beq- @_54 + lwzu r30, 0x0008(r29) + rlwimi r28, r30, 15, 0, 14 + xor r31, r27, r30 + andc. r31, r31, r28 + beq- @_54 + lwzu r30, 0x0008(r29) + rlwimi r28, r30, 15, 0, 14 + xor r31, r27, r30 + andc. r31, r31, r28 + beq- @_54 + lwzu r30, 0x0008(r29) + rlwimi r28, r30, 15, 0, 14 + xor r31, r27, r30 + andc. r31, r31, r28 + bne- PagingFunc4 + +@_54 + andi. r31, r30, 0x01 + rlwinm r28, r28, 0, 8, 19 + lwzu r31, 0x0004(r29) + and r28, r27, r28 + or r31, r31, r28 + bnelr- + + + +; PagingFunc4 + +; Xrefs: +; setup +; PagingFunc3 +; print_memory_logical +; major_0x18c08 + +PagingFunc4 ; OUTSIDE REFERER + mfsrin r31, r27 + rlwinm r30, r27, 10, 26, 31 + rlwimi r30, r31, 7, 1, 24 + rlwinm r28, r27, 26, 10, 25 + oris r30, r30, 0x8000 + rlwinm r31, r31, 6, 7, 25 + xor r28, r28, r31 + lwz r31, KDP.PTEGMask(r1) + lwz r29, KDP.HTABORG(r1) + and r28, r28, r31 + or. r29, r29, r28 + +@_2c + lwz r31, 0x0000(r29) + lwz r28, 0x0008(r29) + cmpw cr6, r30, r31 + lwz r31, 0x0010(r29) + cmpw cr7, r30, r28 + lwzu r28, 0x0018(r29) + bne- cr6, @_50 + +@_48 + lwzu r31, -0x0014(r29) + blr + +@_50 + cmpw cr6, r30, r31 + lwzu r31, 0x0008(r29) + beq+ cr7, @_48 + cmpw cr7, r30, r28 + lwzu r28, 0x0008(r29) + beq+ cr6, @_48 + cmpw cr6, r30, r31 + lwzu r31, 0x0008(r29) + beq+ cr7, @_48 + cmpw cr7, r30, r28 + lwzu r28, 0x0008(r29) + beq+ cr6, @_48 + cmpw cr6, r30, r31 + lwzu r31, -0x000c(r29) + beqlr- cr7 + cmpw cr7, r30, r28 + lwzu r31, 0x0008(r29) + beqlr- cr6 + lwzu r31, 0x0008(r29) + beqlr- cr7 + lwz r31, KDP.PTEGMask(r1) + xori r30, r30, 0x40 + andi. r28, r30, 0x40 + addi r29, r29, -0x3c + xor r29, r29, r31 + bne+ @_2c + blr + + + +; PagingFlushTLB + +; Xrefs: +; setup +; major_0x14bcc +; MPCall_103 + +pb equ 12 + +PagingFlushTLB ; OUTSIDE REFERER + lhz r29, KDP.ProcessorInfo + NKProcessorInfo.TransCacheTotalSize(r1) + slwi r29, r29, pb + +@loop + subi r29, r29, 1 << pb + cmpwi r29, 0 + tlbie r29 + bgt+ @loop + + mfspr r29, pvr + rlwinm. r29, r29, 0, 0, 14 + + ; All cpus + sync + beqlr- + + ; Non-601 stuff + tlbsync + sync + isync + blr diff --git a/NanoKernel/NKPoolAllocator.s b/NanoKernel/NKPoolAllocator.s new file mode 100644 index 0000000..d55f0ac --- /dev/null +++ b/NanoKernel/NKPoolAllocator.s @@ -0,0 +1,530 @@ +Local_Panic set * + b panic + + + +; InitPool + +; Allocate one page for the kernel pool. Same layout at +; Memtop starts at 7 pages below KDP. +; Take note of the structure from kdp-ab0 to kdp-aa0 + +; Xrefs: +; setup + +; > r1 = kdp + +InitPool ; OUTSIDE REFERER + + ; r9 = LA_KD - 7 pages + lwz r8, KDP.PA_ConfigInfo(r1) + lwz r8, NKConfigurationInfo.LA_KernelData(r8) + lisori r9, 0x7000 + subf r9, r9, r8 + stw r9, -0x0a9c(r1) + + lisori r9, -0x7000 + add r9, r9, r1 + stw r9, -0x0aa0(r1) + +; bit of a mystery + lisori r8, 0x00006458 + add r23, r8, r9 + stw r8, 0x0000(r9) + + lisori r8, '‡BGN' + stw r8, 0x0004(r9) + + addi r9, r9, 0x08 + lisori r8, 0x00006450 + stw r8, 0x0000(r9) + + lisori r8, 'free' + stw r8, 0x0004(r9) + + li r8, 0x00 + stw r8, 0x0000(r23) + + lisori r8, '‡END' + stw r8, 0x0004(r23) + +; set up linked list + addi r8, r1, PSA.FreePool + + stw r9, LLL.Next(r8) + stw r9, LLL.Prev(r8) + stw r8, LLL.Next(r9) + stw r8, LLL.Prev(r9) + + lisori r9, 'POOL' + stw r9, LLL.Signature(r8) + + + blr + + + +; PoolAlloc + +; Easy to use! 0xfd8 (a page minus 10 words) is the +; largest request that can be satisfied. + +; Xrefs: +; setup +; major_0x02ccc +; KCCreateProcess +; KCCreateCpuStruct +; MPCall_15 +; MPCall_39 +; MPCall_17 +; MPCall_20 +; MPCall_25 +; MPCall_49 +; MPCall_40 +; MPCall_31 +; MPCall_64 +; major_0x0db04 +; CreateTask +; MPCall_58 +; convert_pmdts_to_areas +; NKCreateAddressSpaceSub +; MPCall_72 +; createarea +; MPCall_73 +; MPCall_130 +; InitTMRQs +; InitIDIndex +; MakeID + +; > r1 = kdp +; > r8 = size + +; < r8 = ptr + +PoolAlloc ; OUTSIDE REFERER + crclr cr7_eq + b PoolAllocCommon + +PoolAlloc_with_crset ; OUTSIDE REFERER + crset cr7_eq + +PoolAllocCommon + + ; Save LR and arg to EWA. Get lock. + mflr r17 + mfsprg r18, 0 + + _Lock PSA.PoolLock, scratch1=r15, scratch2=r16 + + ; These saves are my first real hint at the contents of that + ; large unexplored area of the EWA. This file, then, owns + ; part of the EWA, for its CPU-scoped globals. Because the + ; kernel runs stackless. + stw r17, EWA.PoolSavedLR(r18) + stw r8, EWA.PoolSavedSizeArg(r18) + +@try_again + ; Check that requested allocation is in the doable size range. + cmpwi r8, 0 + cmpwi cr1, r8, 0xfd8 + ble+ Local_Panic ; zero-byte request => thud + bgt- cr1, @request_too_large + + addi r8, r8, 39 + rlwinm r8, r8, 0, 0, 26 + + ; Check that the pool has any pages in it. + addi r14, r1, PSA.FreePool + lwz r15, LLL.Next(r14) +@try_different_page + cmpw r14, r15 + + bne+ @pool_has_page + + ; No? Then claim a page from the system free list for the pool? + + ; Got a free page in the system free list? It's ours. + li r8, 0 ; return zero if there is no page at all + li r9, 1 ; number of pages to grab + + lwz r16, PSA.FreePageCount(r1) + lwz r17, PSA.UnheldFreePageCount(r1) + subf. r16, r9, r16 + subf r17, r9, r17 + blt- PoolCommonReturn + + stw r16, PSA.FreePageCount(r1) + stw r17, PSA.UnheldFreePageCount(r1) + + ; Get that page, mofo. Macros FTW. + lwz r8, PSA.FreeList + LLL.Next(r1) + RemoveFromList r8, scratch1=r17, scratch2=r18 + + ; There was probably once a mechanism for virtual addressing of the pool! + li r9, 0 + bl ExtendPool ; r8=page, r9=virt=0 + + ; Now that the pool is not empty, start over. + mfsprg r18, 0 + lwz r8, EWA.PoolSavedSizeArg(r18) + b @try_again + +@request_too_large + li r8, 0 + b PoolCommonReturn + +@pool_has_page + ; We have a page (r15) that might have room in it. + ; r8 contains the size describing our actual demand on the page! + + lwz r16, PoolPage.FreeBytes(r15) + cmplw r16, r8 + + lis r20, 'fr' + bgt- @fits_with_leftover_space + beq- @fits_perfectly + ori r20, r20, 'ee' + + lwz r16, PoolPage.FreeBytes(r15) + add r18, r16, r15 ; r18 = ??? + lwz r19, 0x0004(r18) + cmplw cr1, r18, r15 + cmpw r19, r20 + ble+ cr1, Local_Panic + bne- @_118 + lwz r17, 0x0000(r18) + rotlwi r19, r19, 0x08 + add r17, r17, r16 + stw r17, 0x0000(r15) + stw r19, 0x0004(r18) + lwz r17, 0x000c(r18) + lwz r16, LLL.Next(r18) + stw r16, LLL.Next(r17) + stw r17, 0x000c(r16) + b @pool_has_page + +@_118 + lwz r15, LLL.Next(r15) + b @try_different_page + +@fits_with_leftover_space + subf r16, r8, r16 + cmpwi r16, 0x28 + blt- @fits_perfectly + stw r16, 0x0000(r15) + add r15, r15, r16 + stw r8, 0x0000(r15) + b @_14c + +@fits_perfectly + lwz r14, 0x000c(r15) + lwz r16, LLL.Next(r15) + stw r16, LLL.Next(r14) + stw r14, 0x000c(r16) + +@_14c + lisori r8, '‡loc' + stw r8, 0x0004(r15) + addi r8, r15, 0x08 + + beq- cr7, PoolCommonReturn + lwz r16, 0x0000(r15) + addi r16, r16, -0x08 + li r14, 0x00 + add r16, r16, r15 + addi r15, r15, 0x04 + +@_174 + stwu r14, 0x0004(r15) + cmpw r15, r16 + ble+ @_174 + b PoolCommonReturn + + + +; PoolFree + +; ARG void *r8 + +PoolFree ; OUTSIDE REFERER + mflr r17 + mfsprg r18, 0 + + _Lock PSA.PoolLock, scratch1=r15, scratch2=r16 + + stw r17, EWA.PoolSavedLR(r18) + bl major_0x129fc + bl major_0x12a34 + + + +; File-internal + +; Return path of most of these functions? +; Releases Pool lock and Returns to the link +; address saved in EWA. + +PoolCommonReturn ; OUTSIDE REFERER + mfsprg r18, 0 + sync + + lwz r15, PSA.PoolLock + Lock.Count(r1) + cmpwi cr1, r15, 0 + li r15, 0 + bne+ cr1, @no_panic + mflr r15 + bl panic +@no_panic + + stw r15, PSA.PoolLock + Lock.Count(r1) + + lwz r17, EWA.PoolSavedLR(r18) + mtlr r17 + blr + + + +; major_0x129fc + +; Xrefs: +; PoolFree +; ExtendPool + +; ARG Area *r8 + +major_0x129fc ; OUTSIDE REFERER + subi r15, r8, 8 + + lis r20, 'fr' + lhz r16, 4(r15) + ori r20, r20, 'ee' + cmplwi r16, 0x876c + bne+ Local_Panic + stw r20, 4(r15) + + addi r16, r1, PSA.FreePool + + InsertAsPrev r15, r16, scratch=r17 + + blr + + + +; major_0x12a34 + +; Xrefs: +; PoolFree +; ExtendPool + +major_0x12a34 ; OUTSIDE REFERER + lis r20, 0x6672 + lwz r16, 0x0000(r15) + ori r20, r20, 0x6565 + add r18, r16, r15 + lwz r19, 0x0004(r18) + cmplw cr1, r18, r15 + cmpw r19, r20 + ble+ cr1, Local_Panic + bnelr- + lwz r17, 0x0000(r18) + rotlwi r19, r19, 0x08 + add r17, r17, r16 + stw r17, 0x0000(r15) + stw r19, 0x0004(r18) + lwz r17, 0x000c(r18) + lwz r16, LLL.Next(r18) + stw r16, LLL.Next(r17) + stw r17, 0x000c(r16) + b major_0x12a34 + + + +; ExtendPool + +; 0xed0(r1) = pool extends (I increment) +; -0xa9c(r1) = virt last page (I update) +; -0xaa0(r1) = phys last page (I update) +; Assumes that cache blocks are 32 bytes! Uh-oh. +; Page gets decorated like this: +; 000: 00 00 0f e8 +; 004: 87 'B 'G 'N +; 008: 00 00 0f e8 +; 00c: 87 'l 'o 'c +; ... zeros << r8 passes ptr to here +; fe8: phys offset from here to prev page +; fec: 87 'E 'N 'D +; ff0: logical abs address of prev page +; ff4: 00 00 00 00 +; ff8: 00 00 00 00 +; ffc: 00 00 00 00 + +; Xrefs: +; MPCall_0 +; PoolAlloc + +; > r1 = kdp +; > r8 = anywhere in new page (phys) +; > r9 = page_virt + +ExtendPool ; OUTSIDE REFERER + mflr r14 + rlwinm r17, r8, 0, 0, 19 + + lwz r16, KDP.NanoKernelInfo + NKNanoKernelInfo.FreePoolExtendCount(r1) + addi r16, r16, 1 + stw r16, KDP.NanoKernelInfo + NKNanoKernelInfo.FreePoolExtendCount(r1) + + _log 'Extend free pool: phys 0x' + mr r8, r17 + bl Printw + _log ' virt 0x' + mr r8, r9 + bl Printw + _log ' count: ' + mr r8, r16 + bl Printd + _log '^n' + li r16, 0x1000 + +@zeroloop + subi r16, r16, 32 + cmpwi r16, 0 + dcbz r16, r17 + bgt+ @zeroloop + +; Put the funny stuff in + li r16, 0xfe8 + stw r16, 0x0000(r17) + lisori r16, '‡BGN' + stw r16, 0x0004(r17) + addi r15, r17, 0x08 + li r16, 0xfe0 + stw r16, 0x0000(r15) + lisori r16, '‡loc' + stw r16, 0x0004(r15) + addi r15, r17, 0xfe8 + lwz r18, -0x0aa0(r1) + subf r18, r15, r18 + stw r18, 0x0000(r15) + lisori r16, '‡END' + stw r16, 0x0004(r15) + lwz r16, -0x0a9c(r1) + stw r16, LLL.Next(r15) + +; Update globals + stw r9, -0x0a9c(r1) + stw r17, -0x0aa0(r1) + +; Unknown func calls + addi r8, r17, 0x10 + bl major_0x129fc + bl major_0x12a34 + mtlr r14 + blr + + + +; major_0x12b94 + +; Xrefs: +; "HeapSegCorrupt" + + mflr r19 + lwz r20, -0x0aa0(r1) + +major_0x12b94_0x8 + addi r8, r20, 0x08 + bl major_0x12b94_0x30 + lwz r17, 0x0000(r20) + add r17, r17, r20 + lwz r18, 0x0000(r17) + cmpwi r18, 0x00 + add r20, r18, r17 + bne+ major_0x12b94_0x8 + mtlr r19 + blr + +major_0x12b94_0x30 + mflr r14 + addi r16, r8, -0x08 + +major_0x12b94_0x38 + lwz r17, 0x0004(r16) + lis r18, -0x78bb + ori r18, r18, 0x4e44 + cmpw r17, r18 + li r9, 0x00 + beq- major_0x12b94_0x1a4 + lis r18, -0x7894 + ori r18, r18, 0x6f63 + cmpw r17, r18 + beq- major_0x12b94_0x94 + lis r18, 0x6672 + ori r18, r18, 0x6565 + li r9, 0x04 + cmpw r17, r18 + bne- major_0x12b94_0xa8 + lwz r17, 0x000c(r16) + cmpwi r17, 0x00 + li r9, 0x05 + beq- major_0x12b94_0xa8 + lwz r17, LLL.Next(r16) + cmpwi r17, 0x00 + li r9, 0x06 + beq- major_0x12b94_0xa8 + +major_0x12b94_0x94 + lwz r17, 0x0000(r16) + add r16, r16, r17 + cmpwi r17, 0x00 + li r9, 0x07 + bgt+ major_0x12b94_0x38 + +major_0x12b94_0xa8 + mr r18, r8 + _log 'Heap segment corrupt ' + mr r8, r9 + bl Printd + _log 'at ' + mr r8, r16 + bl Printw + _log '^n' + addi r16, r16, -0x40 + li r17, 0x08 + +major_0x12b94_0x10c + mr r8, r16 + bl Printw + _log ' ' + lwz r8, 0x0000(r16) + bl Printw + lwz r8, 0x0004(r16) + bl Printw + lwz r8, LLL.Next(r16) + bl Printw + lwz r8, 0x000c(r16) + bl Printw + _log ' *' + li r8, 0x10 + addi r16, r16, -0x01 + mtctr r8 + +major_0x12b94_0x164 + lbzu r8, 0x0001(r16) + cmpwi r8, 0x20 + bgt- major_0x12b94_0x174 + li r8, 0x20 + +major_0x12b94_0x174 + bl Printc + bdnz+ major_0x12b94_0x164 + _log '*^n' + addi r17, r17, -0x01 + addi r16, r16, 0x01 + cmpwi r17, 0x00 + bne+ major_0x12b94_0x10c + mr r8, r18 + +major_0x12b94_0x1a4 + mtlr r14 + blr diff --git a/NanoKernel/NKPowerCalls.s b/NanoKernel/NKPowerCalls.s new file mode 100644 index 0000000..c9c461a --- /dev/null +++ b/NanoKernel/NKPowerCalls.s @@ -0,0 +1,579 @@ +; FillIndigo + +; Xrefs: +; setup + + align kIntAlign + +FillIndigo ; EXPORTED + mflr r9 + llabel r23, panic + add r23, r23, r25 + addi r8, r1, PSA.IndigoVecBase + li r22, 192 ;VecTable.Size + bl wordfill + mtlr r9 + llabel r23, IntIndigo + add r23, r23, r25 + stw r23, VecTable.SystemResetVector(r8) + stw r23, VecTable.ExternalIntVector(r8) + stw r23, VecTable.DecrementerVector(r8) + blr + + + +; kcPowerDispatch + +; NB: I was probably wrong about this. +; Contains a (very rare) mtsprg0 instruction. + +; Xrefs: +; "sup" + + align kIntAlign + +kcPowerDispatch ; EXPORTED ; OUTSIDE REFERER + mtcr r7 + lwz r4, 0x0670(r1) + cmplwi cr7, r3, 0x0b + mr r9, r13 + blt- cr2, kcPowerDispatch_0x18 + lwz r9, -0x0440(r1) + +kcPowerDispatch_0x18 + and. r8, r4, r9 + bgt- cr7, major_0x09e28_0x34 + bne- major_0x09e28_0x2c + cmplwi cr7, r3, 0x0b + beq- cr7, major_0x0a600_0x1c + cmplwi cr7, r3, 0x08 + beq- cr7, major_0x09e28_0x3c + cmplwi cr7, r3, 0x09 + beq- cr7, major_0x0a600_0x10 + stw r26, 0x01d4(r6) + stw r27, 0x01dc(r6) + stw r28, 0x01e4(r6) + stw r29, 0x01ec(r6) + stw r30, 0x01f4(r6) + stw r31, 0x01fc(r6) + mfsprg r31, 3 + addi r8, r1, -0x810 + mtsprg 3, r8 + rlwinm r26, r3, 0, 29, 29 + clrlwi r3, r3, 0x1e + lbz r8, 0x06b8(r1) + slwi r3, r3, 1 + addi r3, r3, 0x1a + rlwnm r3, r8, r3, 0x1e, 0x1f + cmpwi r3, 0x00 + beq- major_0x09e28_0x24 + lbz r9, 0x06b9(r1) + cmpwi r9, 0x00 + beq- kcPowerDispatch_0xb0 + mfspr r27, hid0 + mr r8, r27 + cmpwi r9, 0x01 + beq- kcPowerDispatch_0xa8 + oris r9, r3, 0x100 + srw r9, r9, r9 + rlwimi r8, r9, 0, 8, 10 + +kcPowerDispatch_0xa8 + oris r8, r8, 0x01 + mtspr hid0, r8 + +kcPowerDispatch_0xb0 + cmplwi r26, 0x04 + beql- kcCacheDispatch_0x258 + mfmsr r8 + ori r8, r8, 0x8002 + cmplwi r3, 0x00 + beq- kcPowerDispatch_0xcc + oris r8, r8, 0x04 + +kcPowerDispatch_0xcc + sync + mtmsr r8 + isync + +kcPowerDispatch_0xd8 + b kcPowerDispatch_0xd8 + + + +; IntIndigo + +; Odd that this is unaligned + +IntIndigo + lbz r8, 0x06b9(r1) + cmpwi r8, 0x00 + beq- IntIndigo_0x10 + mtspr hid0, r27 + +IntIndigo_0x10 + mfsprg r1, 2 + mtlr r1 + mfsprg r1, 1 + lis r9, 0x7fff + mfspr r8, dec + mtspr dec, r9 + mtspr dec, r8 + + + +; major_0x09e28 + +; Xrefs: +; kcPowerDispatch +; IntIndigo + + li r3, 0x00 + +major_0x09e28_0x4 + mtsprg 3, r31 + lwz r26, 0x01d4(r6) + lwz r27, 0x01dc(r6) + lwz r28, 0x01e4(r6) + lwz r29, 0x01ec(r6) + lwz r30, 0x01f4(r6) + lwz r31, 0x01fc(r6) + b skeleton_key + +major_0x09e28_0x24 ; OUTSIDE REFERER + li r3, -0x7267 + b major_0x09e28_0x4 + +major_0x09e28_0x2c ; OUTSIDE REFERER + li r3, 0x00 + b skeleton_key + +major_0x09e28_0x34 ; OUTSIDE REFERER + li r3, -0x01 + b skeleton_key + +major_0x09e28_0x3c ; OUTSIDE REFERER + mfsprg r9, 0 + lwz r8, -0x0338(r9) + lwz r9, 0x0024(r8) + cmpwi r9, 0x01 + li r3, -0x7267 + bgt+ skeleton_key + stw r26, 0x01d4(r6) + stw r27, 0x01dc(r6) + stw r28, 0x01e4(r6) + stw r29, 0x01ec(r6) + stw r30, 0x01f4(r6) + stw r31, 0x01fc(r6) + bl kcCacheDispatch_0x258 + mfspr r9, hid0 + rlwinm r9, r9, 0, 18, 16 + rlwinm r9, r9, 0, 17, 15 + mtspr hid0, r9 + sync + isync + lwz r26, 0x0f68(r1) + andi. r26, r26, 0x01 + beq- major_0x09e28_0xb0 + mfspr r9, l2cr + clrlwi r9, r9, 0x01 + mtspr l2cr, r9 + sync + isync + addi r8, r1, -0x4d0 + stw r9, 0x0050(r8) + +major_0x09e28_0xb0 + stw r7, 0x0000(r6) + stw r2, 0x0114(r6) + stw r3, 0x011c(r6) + stw r4, 0x0124(r6) + stw r5, 0x012c(r6) + stw r14, 0x0174(r6) + stw r15, 0x017c(r6) + stw r16, 0x0184(r6) + stw r17, 0x018c(r6) + stw r18, 0x0194(r6) + stw r19, 0x019c(r6) + stw r20, 0x01a4(r6) + stw r21, 0x01ac(r6) + stw r22, 0x01b4(r6) + stw r23, 0x01bc(r6) + stw r24, 0x01c4(r6) + stw r25, 0x01cc(r6) + stw r13, 0x00dc(r6) + andi. r8, r11, 0x2000 + beq- major_0x09e28_0x198 + mfmsr r8 + ori r8, r8, 0x2000 + mtmsr r8 + isync + stfd f0, 0x0200(r6) + stfd f1, 0x0208(r6) + stfd f2, 0x0210(r6) + stfd f3, 0x0218(r6) + stfd f4, 0x0220(r6) + stfd f5, 0x0228(r6) + stfd f6, 0x0230(r6) + stfd f7, 0x0238(r6) + stfd f8, 0x0240(r6) + stfd f9, 0x0248(r6) + stfd f10, 0x0250(r6) + stfd f11, 0x0258(r6) + stfd f12, 0x0260(r6) + stfd f13, 0x0268(r6) + stfd f14, 0x0270(r6) + stfd f15, 0x0278(r6) + stfd f16, 0x0280(r6) + mffs f0 + stfd f17, 0x0288(r6) + stfd f18, 0x0290(r6) + stfd f19, 0x0298(r6) + stfd f20, 0x02a0(r6) + stfd f21, 0x02a8(r6) + stfd f22, 0x02b0(r6) + stfd f23, 0x02b8(r6) + stfd f24, 0x02c0(r6) + stfd f25, 0x02c8(r6) + stfd f26, 0x02d0(r6) + stfd f27, 0x02d8(r6) + stfd f28, 0x02e0(r6) + stfd f29, 0x02e8(r6) + stfd f30, 0x02f0(r6) + stfd f31, 0x02f8(r6) + stfd f0, 0x00e0(r6) + +major_0x09e28_0x198 + mfxer r9 + addi r16, r1, -0x4d0 + stw r9, 0x00d4(r6) + mfctr r9 + stw r9, 0x00f0(r6) + stw r12, 0x00e8(r6) + stw r10, 0x0054(r16) + stw r11, 0x0058(r16) + mfspr r9, hid0 + stw r9, 0x0064(r16) + +major_0x09e28_0x1c0 + mftbu r9 + stw r9, 0x005c(r16) + mftb r9 + stw r9, 0x0060(r16) + mftbu r8 + lwz r9, 0x005c(r16) + cmpw r8, r9 + bne+ major_0x09e28_0x1c0 + mfmsr r9 + stw r9, 0x006c(r16) + mfspr r9, sdr1 + stw r9, 0x0070(r16) + mfspr r9, dbat0u + stw r9, 0x0000(r16) + mfspr r9, dbat0l + stw r9, 0x0004(r16) + mfspr r9, dbat1u + stw r9, 0x0008(r16) + mfspr r9, dbat1l + stw r9, 0x000c(r16) + mfspr r9, dbat2u + stw r9, 0x0010(r16) + mfspr r9, dbat2l + stw r9, 0x0014(r16) + mfspr r9, dbat3u + stw r9, 0x0018(r16) + mfspr r9, dbat3l + stw r9, 0x001c(r16) + mfspr r9, ibat0u + stw r9, 0x0020(r16) + mfspr r9, ibat0l + stw r9, 0x0024(r16) + mfspr r9, ibat1u + stw r9, 0x0028(r16) + mfspr r9, ibat1l + stw r9, 0x002c(r16) + mfspr r9, ibat2u + stw r9, 0x0030(r16) + mfspr r9, ibat2l + stw r9, 0x0034(r16) + mfspr r9, ibat3u + stw r9, 0x0038(r16) + mfspr r9, ibat3l + stw r9, 0x003c(r16) + mfsprg r9, 0 + stw r9, 0x0040(r16) + mfsprg r9, 1 + stw r9, 0x0044(r16) + mfsprg r9, 2 + stw r9, 0x0048(r16) + mfsprg r9, 3 + stw r9, 0x004c(r16) + stw r6, 0x007c(r16) + bl major_0x09e28_0x59c + lwz r1, 0x0004(r1) + addi r16, r1, -0x4d0 + lis r8, 0x100 + ori r8, r8, 0x00 + lis r9, 0x00 + +major_0x09e28_0x2ac + addis r9, r9, -0x1000 + addis r8, r8, -0x10 + mr. r9, r9 + mtsrin r8, r9 + bne+ major_0x09e28_0x2ac + isync + mfspr r9, hid0 + li r8, 0x800 + ori r8, r8, 0x200 + or r9, r9, r8 + mtspr hid0, r9 + isync + andc r9, r9, r8 + mtspr hid0, r9 + isync + ori r9, r9, 0x8000 + ori r9, r9, 0x4000 + mtspr hid0, r9 + isync + lwz r26, 0x0f68(r1) + andi. r26, r26, 0x01 + beq- major_0x09e28_0x38c + lwz r8, 0x0f54(r1) + mr. r8, r8 + beq- major_0x09e28_0x38c + mfspr r9, hid0 + rlwinm r9, r9, 0, 12, 10 + mtspr hid0, r9 + isync + lwz r9, 0x0050(r16) + mtspr l2cr, r9 + sync + isync + lis r8, 0x20 + or r8, r9, r8 + mtspr l2cr, r8 + sync + isync + +major_0x09e28_0x344 + mfspr r8, l2cr + rlwinm. r8, r8, 31, 0, 0 + bne+ major_0x09e28_0x344 + mfspr r8, l2cr + lis r9, -0x21 + ori r9, r9, 0xffff + and r8, r8, r9 + mtspr l2cr, r8 + sync + mfspr r8, hid0 + oris r8, r8, 0x10 + mtspr hid0, r8 + isync + mfspr r8, l2cr + oris r8, r8, 0x8000 + mtspr l2cr, r8 + sync + isync + +major_0x09e28_0x38c + lwz r6, 0x007c(r16) + lwz r7, 0x0000(r6) + lwz r13, 0x00dc(r6) + lwz r9, 0x00f0(r6) + mtctr r9 + lwz r12, 0x00e8(r6) + lwz r9, 0x00d4(r6) + mtxer r9 + lwz r10, 0x0054(r16) + lwz r11, 0x0058(r16) + lwz r2, 0x0114(r6) + lwz r3, 0x011c(r6) + lwz r4, 0x0124(r6) + lwz r5, 0x012c(r6) + lwz r14, 0x0174(r6) + lwz r15, 0x017c(r6) + lwz r17, 0x018c(r6) + lwz r18, 0x0194(r6) + lwz r19, 0x019c(r6) + lwz r20, 0x01a4(r6) + lwz r21, 0x01ac(r6) + lwz r22, 0x01b4(r6) + lwz r23, 0x01bc(r6) + lwz r24, 0x01c4(r6) + lwz r25, 0x01cc(r6) + lwz r26, 0x01d4(r6) + lwz r27, 0x01dc(r6) + lwz r28, 0x01e4(r6) + lwz r29, 0x01ec(r6) + lwz r30, 0x01f4(r6) + lwz r31, 0x01fc(r6) + andi. r8, r11, 0x2000 + beq- major_0x09e28_0x4a8 + mfmsr r8 + ori r8, r8, 0x2000 + mtmsr r8 + isync + lfd f31, 0x00e0(r6) + lfd f0, 0x0200(r6) + lfd f1, 0x0208(r6) + lfd f2, 0x0210(r6) + lfd f3, 0x0218(r6) + lfd f4, 0x0220(r6) + lfd f5, 0x0228(r6) + lfd f6, 0x0230(r6) + lfd f7, 0x0238(r6) + lfd f8, 0x0240(r6) + mtfsf 0xff, f31 + lfd f9, 0x0248(r6) + lfd f10, 0x0250(r6) + lfd f11, 0x0258(r6) + lfd f12, 0x0260(r6) + lfd f13, 0x0268(r6) + lfd f14, 0x0270(r6) + lfd f15, 0x0278(r6) + lfd f16, 0x0280(r6) + lfd f17, 0x0288(r6) + lfd f18, 0x0290(r6) + lfd f19, 0x0298(r6) + lfd f20, 0x02a0(r6) + lfd f21, 0x02a8(r6) + lfd f22, 0x02b0(r6) + lfd f23, 0x02b8(r6) + lfd f24, 0x02c0(r6) + lfd f25, 0x02c8(r6) + lfd f26, 0x02d0(r6) + lfd f27, 0x02d8(r6) + lfd f28, 0x02e0(r6) + lfd f29, 0x02e8(r6) + lfd f30, 0x02f0(r6) + lfd f31, 0x02f8(r6) + +major_0x09e28_0x4a8 + lwz r9, 0x0064(r16) + ori r9, r9, 0x8000 + ori r9, r9, 0x4000 + mtspr hid0, r9 + sync + isync + lwz r9, 0x005c(r16) + mtspr tbu, r9 + lwz r9, 0x0060(r16) + mtspr tbl, r9 + li r9, 0x01 + mtspr dec, r9 + lwz r9, 0x006c(r16) + mtmsr r9 + sync + isync + lwz r9, 0x0070(r16) + mtspr sdr1, r9 + lwz r9, 0x0040(r16) + mtsprg 0, r9 + lwz r9, 0x0044(r16) + mtsprg 1, r9 + lwz r9, 0x0048(r16) + mtsprg 2, r9 + lwz r9, 0x004c(r16) + mtsprg 3, r9 + lwz r9, 0x0000(r16) + mtspr dbat0u, r9 + lwz r9, 0x0004(r16) + mtspr dbat0l, r9 + lwz r9, 0x0008(r16) + mtspr dbat1u, r9 + lwz r9, 0x000c(r16) + mtspr dbat1l, r9 + lwz r9, 0x0010(r16) + mtspr dbat2u, r9 + lwz r9, 0x0014(r16) + mtspr dbat2l, r9 + lwz r9, 0x0018(r16) + mtspr dbat3u, r9 + lwz r9, 0x001c(r16) + mtspr dbat3l, r9 + lwz r9, 0x0020(r16) + mtspr ibat0u, r9 + lwz r9, 0x0024(r16) + mtspr ibat0l, r9 + lwz r9, 0x0028(r16) + mtspr ibat1u, r9 + lwz r9, 0x002c(r16) + mtspr ibat1l, r9 + lwz r9, 0x0030(r16) + mtspr ibat2u, r9 + lwz r9, 0x0034(r16) + mtspr ibat2l, r9 + lwz r9, 0x0038(r16) + mtspr ibat3u, r9 + lwz r9, 0x003c(r16) + mtspr ibat3l, r9 + lwz r16, 0x0184(r6) + li r3, 0x00 + b skeleton_key + +major_0x09e28_0x59c + mflr r9 + stw r9, 0x0074(r16) + stw r1, 0x0078(r16) + addi r9, r16, 0x74 + li r0, 0x00 + stw r9, 0x0000(0) + lis r9, 0x4c61 + ori r9, r9, 0x7273 + stw r9, 0x0004(0) + mfspr r9, hid0 + andis. r9, r9, 0x20 + mtspr hid0, r9 + mfmsr r8 + oris r8, r8, 0x04 + mfspr r9, hid0 + ori r9, r9, 0x8000 + mtspr hid0, r9 + bl * + 4 + mflr r9 + addi r9, r9, major_0x0a600 - (* - 4) + lisori r1, 0xcafebabe + b major_0x0a500 + + + align 8 + + +; major_0x0a500 + +; Xrefs: +; major_0x09e28 + +major_0x0a500 ; OUTSIDE REFERER + sync + mtmsr r8 + isync + cmpwi r1, 0x00 + beq+ major_0x0a500 + lwz r0, 0x0000(r9) + andi. r1, r1, 0x00 + b major_0x0a500 + + + align 8 + + +; major_0x0a600 + +; Xrefs: +; kcPowerDispatch + +major_0x0a600 ; OUTSIDE REFERER + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + +major_0x0a600_0x10 ; OUTSIDE REFERER + mtspr 1019, r5 + li r3, 0x00 + b skeleton_key + +major_0x0a600_0x1c ; OUTSIDE REFERER + b major_0x0a600_0x1c diff --git a/NanoKernel/NKPrimaryIntHandlers.s b/NanoKernel/NKPrimaryIntHandlers.s new file mode 100644 index 0000000..6ab6f0c --- /dev/null +++ b/NanoKernel/NKPrimaryIntHandlers.s @@ -0,0 +1,1268 @@ +; LookupInterruptHandler + +; Called at init time to get the (64b-aligned) physical address +; off the primary interrupt handler ("PIH") for this platform. +; The interrupt handler kind is specified in a one-byte field in +; ConfigInfo, and is an index into the below macro-populated +; table. + +; ARG NKConfigurationInfo *r3 +; RET PIHPtr r7 +; CLOB r12 + + + +MaxPIHCount equ 12 + + + + MACRO + DeclarePIH &n, &code + +@h + org PIHTableStart + &n * 2 + dc.w &code - PIHTableStart + org @h + + ENDM + + + +LookupInterruptHandler ; OUTSIDE REFERER + mflr r12 + bl PIHTableEnd + +PIHTableStart + dcb.w MaxPIHCount, 0 +PIHTableEnd + + mflr r7 + mtlr r12 + lbz r12, NKConfigurationInfo.InterruptHandlerKind(r3) + slwi r12, r12, 1 + lhzx r12, r7, r12 + add r7, r7, r12 + blr + + + +; CommonPIHPath + +; At least I think so. + +; Xrefs: +; KCPropogateExternalInterrupt +; PDM_PIH +; PBX_PIH +; GazellePIH +; TNT_PIH +; GossamerPIH +; NewWorldPowerBookPIH +; CordycepsPIH +; NewWorldPIH +; UnknownPIH + +; > r1 = kdp + +; Alignment probably to fit a cache block (very oft-run code). + align 5 + +CommonPIHPath ; OUTSIDE REFERER + mtsprg 3, r30 + lwz r23, KDP.PA_EmulatorIplValue(r1) + lwz r27, -0x0428(r1) + +CommonPIHPath_0xc ; OUTSIDE REFERER + cmpwi cr7, r28, 0 + li r31, 0x00 + blt- cr7, @negative + + beq- cr7, @zero_rupt + ori r28, r28, 0x8000 + lwz r31, KDP.PostIntMaskInit(r1) +@zero_rupt + + andis. r8, r11, 0x8000 >> 14 ; some kind of perfmon bit + cmpwi cr1, r27, 0x00 + lwz r29, KDP.ClearIntMaskInit(r1) + + bne- @noperf + bne- cr1, CommonPIHPath_0x78 +@noperf + + rlwinm. r8, r7, 0, 10, 10 + beq- CommonPIHPath_0x14c + sth r28, 0x0000(r23) + or r13, r13, r31 + bgt- cr7, @negative + and r13, r13, r29 + +@negative + sync + lwz r8, PSA.PIHLock(r1) + cmpwi cr1, r8, 0 + li r8, 0 + + bne+ cr1, @pih_unlocked + mflr r8 + bl panic +@pih_unlocked + + stw r8, PSA.PIHLock(r1) ; redundant + bl Restore_r20_r31 + b skeleton_key + +CommonPIHPath_0x78 + sync + lwz r8, -0x0b70(r1) + cmpwi cr1, r8, 0x00 + li r8, 0x00 + bne+ cr1, CommonPIHPath_0x94 + mflr r8 + bl panic + +CommonPIHPath_0x94 + stw r8, -0x0b70(r1) + bl Save_r14_r19 + + _Lock PSA.SchLock, scratch1=r8, scratch2=r9 + + mr r8, r27 + +; r8 = id + bl LookupID + cmpwi r9, Notification.kIDClass + + mr r30, r8 + bne- CommonPIHPath_0x100 + clrlwi r9, r28, 0x11 + stw r9, 0x0010(r30) + stw r22, 0x0014(r30) + bl major_0x0db04 + sync + lwz r8, PSA.SchLock + Lock.Count(r1) + cmpwi cr1, r8, 0x00 + li r8, 0x00 + bne+ cr1, CommonPIHPath_0xf4 + mflr r8 + bl panic + +CommonPIHPath_0xf4 + stw r8, PSA.SchLock + Lock.Count(r1) + +; r6 = ewa + bl Restore_r14_r31 + b skeleton_key + +CommonPIHPath_0x100 + li r27, 0x00 + lwz r23, 0x067c(r1) + stw r27, -0x0428(r1) + sync + lwz r8, PSA.SchLock + Lock.Count(r1) + cmpwi cr1, r8, 0x00 + li r8, 0x00 + bne+ cr1, CommonPIHPath_0x128 + mflr r8 + bl panic + +CommonPIHPath_0x128 + stw r8, PSA.SchLock + Lock.Count(r1) + bl Restore_r14_r19 + + _Lock PSA.PIHLock, scratch1=r8, scratch2=r9 + + b CommonPIHPath_0xc + +CommonPIHPath_0x14c + sync + lwz r8, -0x0b70(r1) + cmpwi cr1, r8, 0x00 + li r8, 0x00 + bne+ cr1, CommonPIHPath_0x168 + mflr r8 + bl panic + +CommonPIHPath_0x168 + + ; This is where we have some real fun... + stw r8, -0x0b70(r1) + bl Save_r14_r19 + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + lwz r30, -0x0440(r1) + or r31, r31, r30 + stw r31, -0x0440(r1) + sth r28, -0x043c(r1) + lwz r31, -0x08f0(r1) + mfsprg r30, 0 + lwz r28, 0x0064(r31) + lbz r29, 0x0018(r31) + ori r28, r28, 0x10 + stw r28, 0x0064(r31) + cmpwi r29, 0x00 + lhz r16, 0x001a(r31) + beq- CommonPIHPath_0x1dc + lhz r17, -0x0116(r30) + cmpw cr1, r16, r17 + rlwinm. r8, r28, 0, 26, 26 + beq- cr1, CommonPIHPath_0x1d0 + bne- CommonPIHPath_0x230 + +CommonPIHPath_0x1d0 + mr r8, r31 + bl major_0x13e4c + b CommonPIHPath_0x218 + +CommonPIHPath_0x1dc + addi r16, r31, 0x08 + lwz r17, 0x0008(r16) + lwz r18, 0x000c(r16) + stw r17, 0x0008(r18) + stw r18, 0x000c(r17) + li r17, 0x00 + stw r17, 0x0008(r16) + stw r17, 0x000c(r16) + lbz r17, 0x0037(r31) + cmpwi r17, 0x01 + bne- CommonPIHPath_0x210 + addi r8, r31, 0x20 + bl major_0x136c8 + +CommonPIHPath_0x210 + lwz r16, 0x0e80(r1) + stw r16, -0x08e4(r1) + +CommonPIHPath_0x218 + li r16, 0x00 + stb r16, 0x0019(r31) + mr r8, r31 + bl TaskReadyAsNext + mr r8, r31 + bl CalculateTimeslice + +CommonPIHPath_0x230 + mr r8, r31 + bl major_0x14af8 + sync + lwz r16, PSA.SchLock + Lock.Count(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + bne+ cr1, CommonPIHPath_0x254 + mflr r16 + bl panic + +CommonPIHPath_0x254 + stw r16, PSA.SchLock + Lock.Count(r1) + +; r6 = ewa + bl Restore_r14_r31 + b skeleton_key + + + +; KCPropogateExternalInterrupt + + + DeclareMPCall 122, KCPropogateExternalInterrupt + +KCPropogateExternalInterrupt ; OUTSIDE REFERER + rlwinm. r8, r7, 0, 10, 10 + cmplwi cr1, r3, 7 + bne- @notthegumdropbuttons + bgt- cr1, @too_high + + _Lock PSA.PIHLock, scratch1=r8, scratch2=r9 + + ; Get current interrupt level + lwz r23, KDP.PA_EmulatorIplValue(r1) + lbz r28, 1(r23) + + ; r28 = max(current level, desired level) + cmpw r3, r28 + ble- @desired_is_lower + mr r28, r3 +@desired_is_lower + + li r27, 0x00 + li r3, 0x00 + bl Restore_r14_r19 + b CommonPIHPath_0xc + +@notthegumdropbuttons + b ReturnMPCallOOM + +@too_high + b ReturnParamErrFromMPCall + + + +Save_r14_r19 ; OUTSIDE REFERER + stw r14, ContextBlock.r14(r6) + stw r15, ContextBlock.r15(r6) + stw r16, ContextBlock.r16(r6) + stw r17, ContextBlock.r17(r6) + stw r18, ContextBlock.r18(r6) + stw r19, ContextBlock.r19(r6) + blr + + + +Restore_r14_r19 ; OUTSIDE REFERER + lwz r14, ContextBlock.r14(r6) + lwz r15, ContextBlock.r15(r6) + lwz r16, ContextBlock.r16(r6) + lwz r17, ContextBlock.r17(r6) + lwz r18, ContextBlock.r18(r6) + lwz r19, ContextBlock.r19(r6) + blr + + + +; PDM68kInterruptTable + +; The (byte-sized) entries in the table are 68k rupt numbers. + +; Strictly unnecessary considering indexing method, +; but might speed it up? + align 6 + +PDM68kInterruptTable ; OUTSIDE REFERER + dc.l 0x00010202 + dc.l 0x04040404 + dc.l 0x03030303 + dc.l 0x04040404 + dc.l 0x04040404 + dc.l 0x04040404 + dc.l 0x04040404 + dc.l 0x04040404 + dc.l 0x07070707 + dc.l 0x07070707 + dc.l 0x07070707 + dc.l 0x07070707 + dc.l 0x07070707 + dc.l 0x07070707 + dc.l 0x07070707 + dc.l 0x07070707 + + + +; PDM (Piltdown Man) Primary Interrupt Handler + +; = first ("G1") Power Macs. NuBus. Models +; 61xx, 71xx, 81xx. + + DeclarePIH 1, PDM_PIH + + align 6 + +PDM_PIH + + _Lock PSA.PIHLock, scratch1=r8, scratch2=r9 + + bl Save_r20_r31 + + addi r9, r1, PSA.BlueVecBase + andis. r8, r11, 0x8000 >> 14 ; SRR1 mystery bit + + mfsprg r30, 3 + + bne- @nocount + lwz r21, KDP.NanoKernelInfo + NKNanoKernelInfo.ExternalIntCount(r1) + addi r21, r21, 0x01 + stw r21, KDP.NanoKernelInfo + NKNanoKernelInfo.ExternalIntCount(r1) +@nocount + + ; Switch to Blue vector table + mtsprg 3, r9 + + ; Do the bare minimum to access the device at 0x50f30000 + + ; Hardcoded address is hardcoded + lis r22, 0x50f3;0000 + + ; *Prepare* to enable data paging + mfmsr r23 + _bset r20, r23, MSR_DRbit + ;ori r20, r23, 0x80000000 >> MSR_DRbit + + ; Find a SPAC to set sr5 from + lwz r25, PSA.OtherSystemAddrSpcPtr(r1) + rlwinm r24, r22, 6, 26, 29 + addi r25, r25, AddressSpace.SRs + + ; Save sr5 in r21, load new value from SPAC, isync + mfsrin r21, r22 + lwzx r24, r25, r24 + mtsrin r24, r22 + isync + + ; Turn on data paging, isync + mtmsr r20 + isync + + ; Ask (the PIC?) something + li r20, 0xc0 + stb r20, -0x6000(r22) + eieio + lbz r20, -0x6000(r22) + + ; Turn data paging back off, isync + mtmsr r23 + isync + + ; Lookup a 68k int number using this 6-bit thing from the PIC + lwz r23, KDP.PA_NanoKernelCode(r1) + rlwimi r23, r20, 0, 26, 31 + llabel r28, PDM68kInterruptTable + lbzx r28, r28, r23 + + ; Restore sr5, isync + mtsrin r21, r22 + isync + + b CommonPIHPath + + + +; PBX Primary Interrupt Handler + +; = pre-PCI PowerPC 'Books. Possibly not including the 5300? + + DeclarePIH 3, PBX_PIH + + align 6 + +PBX_PIH + + _Lock PSA.PIHLock, scratch1=r8, scratch2=r9 + +; r6 = ewa + bl Save_r20_r31 +; r8 = sprg0 (not used by me) + + addi r9, r1, -0x750 + andis. r8, r11, 0x02 + mfsprg r30, 3 + bne- PBX_PIH_0x38 + lwz r21, 0x0e80(r1) + addi r21, r21, 0x01 + stw r21, 0x0e80(r1) + +PBX_PIH_0x38 + mtsprg 3, r9 + lis r22, 0x50f3 + mfmsr r23 + lwz r25, -0x03fc(r1) + rlwinm r24, r22, 6, 26, 29 + addi r25, r25, 0x30 + mfsrin r21, r22 + lwzx r24, r25, r24 + mtsrin r24, r22 + isync + ori r20, r23, 0x10 + mtmsr r20 + isync + lwz r20, -0x6000(r22) + ori r20, r20, 0x80 + stw r20, -0x6000(r22) + eieio + lwz r20, -0x6000(r22) + rlwimi r20, r20, 3, 26, 28 + stw r20, -0x6000(r22) + eieio + mr r28, r20 + mtmsr r23 + isync + mtsrin r21, r22 + isync + clrlwi r28, r28, 0x1d + +; r1 = kdp + b CommonPIHPath + + + +; Gazelle Primary Interrupt Handler + +; = later low-end "G2" Power Macs. 603 series +; processors. PCI. Models 54xx-55xx, 64xx-65xx. +; The 54xx/64xx ROM actually identifies as Alchemy, not +; Gazelle, and SheepShaver considers this difference when +; patching the ROM Nanokernels. But, Wikipedia describes +; these machines as minor upgrades, EveryMac calls them +; Gazelle, and they use the same PIH type. + + DeclarePIH 5, GazellePIH + + align 6 + +GazellePIH + + _Lock PSA.PIHLock, scratch1=r8, scratch2=r9 + +; r6 = ewa + bl Save_r20_r31 +; r8 = sprg0 (not used by me) + + addi r9, r1, -0x750 + andis. r8, r11, 0x02 + mfsprg r30, 3 + bne- GazellePIH_0x38 + lwz r21, 0x0e80(r1) + addi r21, r21, 0x01 + stw r21, 0x0e80(r1) + +GazellePIH_0x38 + mtsprg 3, r9 + lis r22, -0xd00 + mfmsr r20 + ori r23, r20, 0x10 + lwz r25, -0x03fc(r1) + rlwinm r24, r22, 6, 26, 29 + addi r25, r25, 0x30 + mfsrin r21, r22 + lwzx r24, r25, r24 + mtsrin r24, r22 + isync + mtmsr r23 + isync + li r26, 0x20 + lwbrx r27, r26, r22 + rlwinm r27, r27, 1, 1, 1 + eieio + lis r23, -0x8000 + li r26, 0x28 + stwbrx r23, r26, r22 + eieio + li r26, 0x24 + lwbrx r23, r26, r22 + eieio + rlwinm r28, r23, 1, 1, 1 + and r28, r27, r28 + or r23, r28, r23 + stwbrx r23, r26, r22 + eieio + li r26, 0x2c + lwbrx r26, r26, r22 + eieio + rlwimi r26, r23, 0, 1, 1 + and r23, r26, r23 + mtmsr r20 + isync + andis. r28, r23, 0x10 + li r28, 0x07 + bne- GazellePIH_0x104 + rlwinm r28, r23, 0, 15, 16 + rlwimi. r28, r23, 0, 22, 31 + li r28, 0x04 + bne- GazellePIH_0x104 + andis. r28, r23, 0x5fca + rlwimi. r28, r23, 0, 17, 20 + li r28, 0x02 + bne- GazellePIH_0x104 + andis. r28, r23, 0x04 + li r28, 0x01 + bne- GazellePIH_0x104 + li r28, 0x00 + +GazellePIH_0x104 + mtsrin r21, r22 + isync + +; r1 = kdp + b CommonPIHPath + + + +; TNT (The New Tesseract) Primary Interrupt Handler + +; = High-end and mid-range "G2" Power Macs. PCI. 603 +; and 604 series processors. Models 7200-7600, 8500-8600, +; 9500-9600. + + DeclarePIH 2, TNT_PIH + + align 6 + +TNT_PIH + + _Lock PSA.PIHLock, scratch1=r8, scratch2=r9 + +; r6 = ewa + bl Save_r20_r31 +; r8 = sprg0 (not used by me) + + addi r9, r1, -0x750 + andis. r8, r11, 0x02 + mfsprg r30, 3 + bne- TNT_PIH_0x38 + lwz r21, 0x0e80(r1) + addi r21, r21, 0x01 + stw r21, 0x0e80(r1) + +TNT_PIH_0x38 + mtsprg 3, r9 + lis r22, -0xd00 + mfmsr r20 + ori r23, r20, 0x10 + lwz r25, -0x03fc(r1) + rlwinm r24, r22, 6, 26, 29 + addi r25, r25, 0x30 + mfsrin r21, r22 + lwzx r24, r25, r24 + mtsrin r24, r22 + isync + mtmsr r23 + isync + lis r23, -0x8000 + li r26, 0x28 + stwbrx r23, r26, r22 + eieio + li r26, 0x24 + lwbrx r23, r26, r22 + li r26, 0x2c + lwbrx r26, r26, r22 + and r23, r26, r23 + eieio + mtmsr r20 + isync + rlwinm. r28, r23, 0, 11, 11 + li r28, 0x07 + bne- TNT_PIH_0xd8 + rlwinm r28, r23, 0, 15, 16 + rlwimi. r28, r23, 0, 21, 31 + li r28, 0x04 + bne- TNT_PIH_0xd8 + rlwinm. r28, r23, 0, 17, 17 + li r28, 0x03 + bne- TNT_PIH_0xd8 + andis. r28, r23, 0x7fea + rlwimi. r28, r23, 0, 18, 19 + li r28, 0x02 + bne- TNT_PIH_0xd8 + rlwinm. r28, r23, 14, 31, 31 + +TNT_PIH_0xd8 + mtsrin r21, r22 + isync + +; r1 = kdp + b CommonPIHPath + + + +; Gossamer (and GRX) Primary Interrupt Handler + +; = beige (pre-iMac) G3s. PIH 07 also used for GRX = OldWorld +; PowerBook G3 Series. + + DeclarePIH 7, GossamerPIH + + align 6 + +GossamerPIH + + _Lock PSA.PIHLock, scratch1=r8, scratch2=r9 + +; r6 = ewa + bl Save_r20_r31 +; r8 = sprg0 (not used by me) + + addi r9, r1, -0x750 + andis. r8, r11, 0x02 + mfsprg r30, 3 + bne- GossamerPIH_0x38 + lwz r21, 0x0e80(r1) + addi r21, r21, 0x01 + stw r21, 0x0e80(r1) + +GossamerPIH_0x38 + mtsprg 3, r9 + mfmsr r20 + ori r23, r20, 0x10 + lis r22, -0xd00 + lwz r25, -0x03fc(r1) + rlwinm r24, r22, 6, 26, 29 + addi r25, r25, 0x30 + mfsrin r21, r22 + lwzx r24, r25, r24 + mtsrin r24, r22 + isync + mtmsr r23 + isync + lis r23, -0x8000 + li r25, 0x28 + stwbrx r23, r25, r22 + eieio + li r25, 0x24 + lwbrx r23, r25, r22 + li r25, 0x2c + lwbrx r25, r25, r22 + and r23, r25, r23 + eieio + lis r24, -0x8000 + li r25, 0x18 + stwbrx r24, r25, r22 + eieio + li r25, 0x14 + lwbrx r24, r25, r22 + li r25, 0x1c + lwbrx r25, r25, r22 + and r24, r25, r24 + eieio + mtmsr r20 + isync + rlwinm. r28, r23, 0, 11, 11 + li r28, 0x07 + bne- GossamerPIH_0x118 + rlwinm r28, r23, 0, 15, 16 + rlwimi. r28, r23, 0, 22, 31 + li r28, 0x04 + bne- GossamerPIH_0x118 + clrlwi. r28, r24, 0x1e + li r28, 0x04 + bne- GossamerPIH_0x118 + rlwinm. r28, r24, 0, 21, 21 + li r28, 0x03 + bne- GossamerPIH_0x118 + andis. r28, r23, 0x3fea + rlwimi. r28, r23, 0, 17, 20 + li r28, 0x02 + bne- GossamerPIH_0x118 + rlwinm. r28, r24, 0, 20, 20 + li r28, 0x01 + bne- GossamerPIH_0x118 + rlwinm. r28, r23, 14, 31, 31 + +GossamerPIH_0x118 + mtsrin r21, r22 + isync + +; r1 = kdp + b CommonPIHPath + + + +; NewWorld PowerBook Primary Interrupt Handler + +; Only ever seen this on Mikey's (NewWorld) Lombard. So +; apparently the Trampoline can also change the ROM's +; default PIH. + + DeclarePIH 10, NewWorldPowerBookPIH ; logged as 'kind 0a' + + align 6 + +NewWorldPowerBookPIH + + _Lock PSA.PIHLock, scratch1=r8, scratch2=r9 + +; r6 = ewa + bl Save_r20_r31 +; r8 = sprg0 (not used by me) + + addi r9, r1, -0x750 + andis. r8, r11, 0x02 + mfsprg r30, 3 + bne- NewWorldPowerBookPIH_0x38 + lwz r21, 0x0e80(r1) + addi r21, r21, 0x01 + stw r21, 0x0e80(r1) + +NewWorldPowerBookPIH_0x38 + mtsprg 3, r9 + lwz r26, -0x0020(r1) + mfmsr r20 + ori r23, r20, 0x10 + lwz r22, 0x0ec0(r26) + lwz r25, -0x03fc(r1) + rlwinm r24, r22, 6, 26, 29 + addi r25, r25, 0x30 + mfsrin r21, r22 + lwzx r24, r25, r24 + mtsrin r24, r22 + isync + mtmsr r23 + isync + li r23, 0x80 + stw r23, 0x0018(r22) + eieio + lwz r23, 0x0014(r22) + lwz r25, 0x001c(r22) + and r23, r25, r23 + lwz r24, 0x0004(r22) + lwz r25, 0x000c(r22) + and r24, r25, r24 + mtmsr r20 + isync + stw r23, 0x0f28(r26) + stw r24, 0x0f2c(r26) + lis r25, 0x00 + ori r25, r25, 0x3f60 + li r28, 0x07 + +NewWorldPowerBookPIH_0xb0 + lwz r26, 0x001c(r25) + and. r26, r24, r26 + bne- NewWorldPowerBookPIH_0xd4 + lwzu r26, -0x0004(r25) + and. r26, r23, r26 + bne- NewWorldPowerBookPIH_0xd4 + addi r28, r28, -0x01 + cmplwi r28, 0x00 + bne+ NewWorldPowerBookPIH_0xb0 + +NewWorldPowerBookPIH_0xd4 + mtsrin r21, r22 + isync + +; r1 = kdp + b CommonPIHPath + + + +; Cordyceps Primary Interrupt Handler + +; = early low-end "G2" Power Macs. 603 series +; processors. PCI. Models 52xx-53xx, 62xx-63xx. + + DeclarePIH 4, CordycepsPIH + + align 6 + +CordycepsPIH + + _Lock PSA.PIHLock, scratch1=r8, scratch2=r9 + +; r6 = ewa + bl Save_r20_r31 +; r8 = sprg0 (not used by me) + + addi r9, r1, -0x750 + andis. r8, r11, 0x02 + mfsprg r30, 3 + bne- CordycepsPIH_0x38 + lwz r21, 0x0e80(r1) + addi r21, r21, 0x01 + stw r21, 0x0e80(r1) + +CordycepsPIH_0x38 + mtsprg 3, r9 + lis r22, 0x5300 + mfmsr r23 + mfspr r26, dbat0u + mfspr r27, dbat0l + ori r20, r22, 0x03 + mtspr dbat0u, r20 + ori r20, r22, 0x2a + mtspr dbat0l, r20 + isync + ori r20, r23, 0x10 + mtmsr r20 + isync + lwz r20, 0x001c(r22) + sync + lis r20, 0x00 + stw r20, 0x001c(r22) + eieio + lwz r20, 0x001c(r22) + lwz r20, 0x001c(r22) + sync + lwz r28, 0x0024(r22) + sync + xori r28, r28, 0x07 + mtmsr r23 + isync + mtspr dbat0l, r27 + mtspr dbat0u, r26 + clrlwi r28, r28, 0x1d + +; r1 = kdp + b CommonPIHPath + + + +; NewWorld Primary Interrupt Handler + +; (At least most NewWorld machines.) +; The '06' in the NewWorld ROM ConfigInfo seems to +; be left alone by the Trampoline on most machines. + +; This ID was reused from, of all things, the Pippin. + + DeclarePIH 6, NewWorldPIH + + align 6 + +NewWorldPIH + + _Lock PSA.PIHLock, scratch1=r8, scratch2=r9 + +; r6 = ewa + bl Save_r20_r31 +; r8 = sprg0 (not used by me) + + addi r9, r1, -0x750 + andis. r8, r11, 0x02 + mfsprg r30, 3 + bne- NewWorldPIH_0x38 + lwz r21, 0x0e80(r1) + addi r21, r21, 0x01 + stw r21, 0x0e80(r1) + +NewWorldPIH_0x38 + mtsprg 3, r9 + mfmsr r23 + lwz r20, -0x0020(r1) + lhz r27, 0x0910(r1) + lwz r22, 0x0f18(r20) + li r28, 0x00 + lwz r25, -0x03fc(r1) + rlwinm r24, r22, 6, 26, 29 + addi r25, r25, 0x30 + mfsrin r21, r22 + lwzx r24, r25, r24 + mtsrin r24, r22 + isync + cmpwi cr1, r27, 0x00 + andis. r26, r11, 0x02 + beq- cr1, NewWorldPIH_0x23c + beq- NewWorldPIH_0x150 + lbz r29, 0x0f93(r20) + stb r28, 0x0f93(r20) + addi r26, r1, 0x912 + cmpwi cr1, r29, 0x07 + cmplwi r27, 0x01 + bne+ cr1, NewWorldPIH_0xa8 + addi r27, r27, -0x01 + ble- NewWorldPIH_0x1fc + lbzx r26, r26, r27 + lbz r28, 0x3f00(r26) + b NewWorldPIH_0x1fc + +NewWorldPIH_0xa8 + cmplwi r27, 0x01 + addi r27, r27, -0x01 + ble- NewWorldPIH_0x1fc + add r26, r26, r27 + addi r27, r20, 0xf93 + lbz r24, 0x0000(r26) + +NewWorldPIH_0xc0 + lbzu r28, -0x0001(r27) + cmpw r24, r28 + cmpwi cr1, r28, 0xfe + beq- NewWorldPIH_0xdc + bne+ cr1, NewWorldPIH_0xc0 + li r28, -0x01 + b NewWorldPIH_0x1fc + +NewWorldPIH_0xdc + li r28, 0xff + stb r28, 0x0000(r27) + addi r27, r20, 0xf28 + rlwinm r20, r24, 29, 29, 29 + clrlwi r24, r24, 0x1b + lis r28, -0x8000 + add r27, r27, r20 + srw r28, r28, r24 + lwz r24, 0x0000(r27) + andc r24, r24, r28 + addi r26, r26, -0x01 + stw r24, 0x0000(r27) + lbz r26, 0x0000(r26) + li r28, 0x00 + ori r29, r23, 0x10 + lis r27, 0x02 + ori r27, r27, 0xb0 + mtmsr r29 + isync + stwx r28, r22, r27 + mtmsr r23 + isync + lhz r27, 0x0910(r1) + cmpwi r26, 0xff + addi r27, r27, -0x01 + beq+ NewWorldPIH_0x148 + lbz r28, 0x3f00(r26) + +NewWorldPIH_0x148 + sth r27, 0x0910(r1) + b NewWorldPIH_0x1fc + +NewWorldPIH_0x150 + lhz r27, 0x0f88(r20) + ori r20, r23, 0x10 + lis r26, 0x02 + ori r26, r26, 160 + mtmsr r20 + isync + lwbrx r26, r22, r26 + clrlwi r26, r26, 0x14 + cmplwi r26, 0x40 + cmplwi cr1, r26, 0x41 + li r29, 0x00 + beq- NewWorldPIH_0x208 + bge- cr1, NewWorldPIH_0x218 + cmplw r26, r27 + lis r27, 0x02 + ori r27, r27, 0xb0 + bne+ NewWorldPIH_0x198 + stwx r29, r22, r27 + +NewWorldPIH_0x198 + mtmsr r23 + isync + lwz r20, -0x0020(r1) + lbz r28, 0x3f00(r26) + cmpwi r28, 0x07 + bne+ NewWorldPIH_0x1b8 + stb r28, 0x0f93(r20) + b NewWorldPIH_0x1fc + +NewWorldPIH_0x1b8 + lhz r27, 0x0910(r1) + add r24, r27, r1 + addi r27, r27, 0x01 + stb r26, 0x0912(r24) + rlwinm r25, r26, 29, 29, 29 + clrlwi r26, r26, 0x1b + lis r24, -0x8000 + sth r27, 0x0910(r1) + addi r27, r20, 0xf28 + add r27, r27, r25 + lwz r25, 0x0000(r27) + srw r24, r24, r26 + or r25, r25, r24 + li r24, 0xff + stw r25, 0x0000(r27) + addi r27, r20, 0xf8c + stbx r24, r28, r27 + +NewWorldPIH_0x1fc + mtsrin r21, r22 + isync + +; r1 = kdp + b CommonPIHPath + +NewWorldPIH_0x208 + mtmsr r23 + isync + li r28, -0x01 + b NewWorldPIH_0x1fc + +NewWorldPIH_0x218 + lis r27, 0x02 + ori r27, r27, 0xb0 + li r29, 0x00 + stwx r29, r22, r27 + eieio + mtmsr r23 + isync + li r28, -0x01 + b NewWorldPIH_0x1fc + +NewWorldPIH_0x23c + addi r27, r27, 0x01 + li r28, -0x01 + sth r27, 0x0910(r1) + stw r28, 0x0912(r1) + stw r28, 0x0f90(r20) + xoris r28, r28, 0x100 + stw r28, 0x0f8c(r20) + li r28, 0x00 + b NewWorldPIH_0x1fc + + + +; Primary Interrupt Handler for a mystery machine + + DeclarePIH 8, UnknownPIH + + align 6 + +UnknownPIH + + _Lock PSA.PIHLock, scratch1=r8, scratch2=r9 + +; r6 = ewa + bl Save_r20_r31 +; r8 = sprg0 (not used by me) + + addi r9, r1, -0x750 + andis. r8, r11, 0x02 + mfsprg r30, 3 + bne- UnknownPIH_0x38 + lwz r21, 0x0e80(r1) + addi r21, r21, 0x01 + stw r21, 0x0e80(r1) + +UnknownPIH_0x38 + mtsprg 3, r9 + mfmsr r23 + lwz r20, -0x0020(r1) + lhz r27, 0x0910(r1) + lwz r22, 0x0f18(r20) + li r28, 0x00 + lwz r25, -0x03fc(r1) + rlwinm r24, r22, 6, 26, 29 + addi r25, r25, 0x30 + mfsrin r21, r22 + lwzx r24, r25, r24 + mtsrin r24, r22 + isync + cmpwi cr1, r27, 0x00 + andis. r26, r11, 0x02 + beq- cr1, UnknownPIH_0x23c + beq- UnknownPIH_0x170 + cmplwi r27, 0x01 + ble- UnknownPIH_0x1f8 + addi r27, r27, -0x01 + addi r26, r1, 0x912 + add r26, r26, r27 + addi r27, r20, 0xee0 + lbz r24, 0x0000(r26) + mr r29, r24 + cmpwi r24, 0x20 + blt+ UnknownPIH_0xac + addi r27, r27, 0x04 + addi r24, r24, -0x20 + +UnknownPIH_0xac + lwz r27, 0x0000(r27) + lis r28, -0x8000 + srw r28, r28, r24 + and. r27, r27, r28 + bne- UnknownPIH_0xc8 + li r28, -0x01 + b UnknownPIH_0x1f8 + +UnknownPIH_0xc8 + addi r27, r20, 0xec4 + cmpwi r29, 0x20 + blt+ UnknownPIH_0xd8 + addi r27, r27, 0x04 + +UnknownPIH_0xd8 + lwz r24, 0x0000(r27) + andc r24, r24, r28 + stw r24, 0x0000(r27) + addi r27, r20, 0xee0 + cmpwi r29, 0x20 + blt+ UnknownPIH_0xf4 + addi r27, r27, 0x04 + +UnknownPIH_0xf4 + lwz r29, 0x0000(r27) + andc r29, r29, r28 + stw r29, 0x0000(r27) + addi r26, r26, -0x01 + lbz r26, 0x0000(r26) + cmpwi r26, 0xff + beq- UnknownPIH_0x114 + b UnknownPIH_0x118 + +UnknownPIH_0x114 + li r26, 0x800 + +UnknownPIH_0x118 + ori r28, r23, 0x10 + lis r27, 0x02 + ori r27, r27, 0xb0 + mtmsr r28 + isync + li r28, 0x00 + stwx r28, r22, r27 + eieio + cmpwi r26, 0x800 + beq- UnknownPIH_0x158 + lis r28, 0x01 + ori r28, r28, 0x00 + rlwinm r27, r26, 5, 16, 31 + add r28, r28, r27 + lwbrx r28, r22, r28 + rlwinm r28, r28, 16, 28, 31 + +UnknownPIH_0x158 + mtmsr r23 + isync + lhz r27, 0x0910(r1) + addi r27, r27, -0x01 + sth r27, 0x0910(r1) + b UnknownPIH_0x1f8 + +UnknownPIH_0x170 + ori r27, r23, 0x10 + lis r26, 0x02 + ori r26, r26, 160 + lis r28, 0x01 + ori r28, r28, 0x00 + mtmsr r27 + isync + lwbrx r26, r22, r26 + clrlwi r26, r26, 0x14 + cmplwi r26, 0x31 + cmplwi cr1, r26, 0x28 + beq- UnknownPIH_0x204 + bge- cr1, UnknownPIH_0x214 + rlwinm r27, r26, 5, 16, 31 + add r28, r28, r27 + lwbrx r28, r22, r28 + rlwinm r28, r28, 16, 28, 31 + mtmsr r23 + isync + lhz r27, 0x0910(r1) + add r24, r27, r1 + addi r27, r27, 0x01 + stb r26, 0x0912(r24) + sth r27, 0x0910(r1) + addi r27, r20, 0xec4 + cmpwi r26, 0x20 + blt+ UnknownPIH_0x1e4 + addi r27, r27, 0x04 + addi r26, r26, -0x20 + +UnknownPIH_0x1e4 + lwz r25, 0x0000(r27) + lis r24, -0x8000 + srw r24, r24, r26 + or r25, r25, r24 + stw r25, 0x0000(r27) + +UnknownPIH_0x1f8 + mtsrin r21, r22 + isync + +; r1 = kdp + b CommonPIHPath + +UnknownPIH_0x204 + mtmsr r23 + isync + li r28, -0x01 + b UnknownPIH_0x1f8 + +UnknownPIH_0x214 + lis r27, 0x02 + ori r27, r27, 0xb0 + li r29, 0x00 + stwx r29, r22, r27 + eieio + mtmsr r23 + isync + li r28, 0x06 + li r28, -0x01 + b UnknownPIH_0x1f8 + +UnknownPIH_0x23c + addi r27, r27, 0x01 + li r28, -0x01 + sth r27, 0x0910(r1) + stw r28, 0x0912(r1) + li r28, 0x00 + stw r28, 0x0ee4(r20) + stw r28, 0x0ee0(r20) + b UnknownPIH_0x1f8 diff --git a/NanoKernel/NKProcFlagsTbl.s b/NanoKernel/NKProcFlagsTbl.s new file mode 100644 index 0000000..df6e201 --- /dev/null +++ b/NanoKernel/NKProcFlagsTbl.s @@ -0,0 +1,72 @@ +; Contains the table used by Init.s:SetProcessorFlags, and a label to find it with. +; +; Using this table, three fields in KDP are set: +; KDP.CpuSpecificByte1 +; KDP.CpuSpecificByte2 (immediately follows Byte1) +; KDP.ProcessorInfo.ProcessorFlags + +ProcessorFlagsTable + dcb.b 32 * (1 + 1 + 4), 0 +ProcessorFlagsTableEnd + + + +PflgTblCtr set 0 + + macro + PflgTblEnt &CpuSpecificByte1, &CpuSpecificByte2, &ProcessorFlags + +@fb + org ProcessorFlagsTable + PflgTblCtr + dc.b &CpuSpecificByte1 + org ProcessorFlagsTable + 32 + PflgTblCtr + dc.b &CpuSpecificByte2 + org ProcessorFlagsTable + 64 + 4*PflgTblCtr + dc.l &ProcessorFlags + org @fb +PflgTblCtr set PflgTblCtr + 1 + + endm + + + + with NKProcessorInfo + + ; CpuSpecificByte + ; 1 2 ProcessorFlags CPU + ; ---- - ------------------------------------------------------------------------ ----------------------- + PflgTblEnt 0x03, 1, 0 ; 0**0 + PflgTblEnt 0x00, 0, 0 ; 0**1 = 601 + PflgTblEnt 0x03, 1, 0 ; 0**2 + PflgTblEnt 0x1b, 2, 0 ; 0**3 = 603 + PflgTblEnt 0x0a, 1, 0 ; 0**4 = 604 + PflgTblEnt 0x1b, 2, 0 ; 0**5 + PflgTblEnt 0x1b, 2, 0 ; 0**6 = 603e + PflgTblEnt 0x1b, 2, 0 ; 0**7 = 750FX + PflgTblEnt 0x1b, 2, 1<< hasL2CR | 1<< hasPLRUL1 | 1<< hasTAU ; 0**8 = 750 + PflgTblEnt 0x0a, 1, 0 ; 0**9 + PflgTblEnt 0x0a, 1, 0 ; 0**a + PflgTblEnt 0x03, 1, 0 ; 0**b + PflgTblEnt 0x1b, 2, 1<< hasL2CR | 1<< hasPLRUL1 | 1<< hasTAU | 1<< hasVMX | 1<< unknownFlag ; 0**c = 7400 + PflgTblEnt 0x0b, 2, 0 ; 0**d + PflgTblEnt 0x03, 2, 0 ; 0**e + PflgTblEnt 0x03, 2, 0 ; 0**f + + PflgTblEnt 0x03, 2, 1<< hasL2CR | 1<< hasPLRUL1 | 1<< hasTAU | 1<< hasVMX | 1<< unknownFlag ; 8**0 = 7450 + PflgTblEnt 0x1b, 2, 1<< hasL2CR | 1<< hasPLRUL1 | 1<< hasTAU | 1<< hasVMX | 1<< unknownFlag ; 8**1 = 7445/55 + PflgTblEnt 0x03, 2, 0 ; 8**2 = 7447 (OS X only) + PflgTblEnt 0x03, 2, 0 ; 8**3 + PflgTblEnt 0x03, 1, 0 ; 8**4 + PflgTblEnt 0x03, 2, 0 ; 8**5 + PflgTblEnt 0x03, 2, 0 ; 8**6 + PflgTblEnt 0x03, 2, 0 ; 8**7 + PflgTblEnt 0x03, 2, 0 ; 8**8 + PflgTblEnt 0x03, 2, 0 ; 8**9 + PflgTblEnt 0x03, 2, 0 ; 8**a + PflgTblEnt 0x03, 2, 0 ; 8**b + PflgTblEnt 0x1b, 2, 1<< hasL2CR | 1<< hasPLRUL1 | 1<< hasTAU | 1<< hasVMX | 1<< unknownFlag ; 8**c = 7410 + PflgTblEnt 0x03, 2, 0 ; 8**d + PflgTblEnt 0x03, 2, 0 ; 8**e + PflgTblEnt 0x03, 2, 0 ; 8**f + + endwith diff --git a/NanoKernel/NKProcInfoTbl.s b/NanoKernel/NKProcInfoTbl.s new file mode 100644 index 0000000..a47fbb0 --- /dev/null +++ b/NanoKernel/NKProcInfoTbl.s @@ -0,0 +1,52 @@ +; Contains the table used by InitBuiltin.s:OverrideProcessorInfo +; +; If the Trampoline fails to pass in a signed HardwareInfo struct, +; this is our first choice for populating ProcessorInfo. +; +; Also contains a 'function' that will do the populating +; (not very clever), and fall through to the end of the file, +; where we expect to find Init.s:FinishInitBuiltin. + + macro ; just to make the table below look nicer... + PnfoTblEnt &a, &b, &c, &d, &e, &f, &g, &h, &i, &j, &k, &l, &m, &n, &o + dc.l &a * 1024, &b * 1024, &c * 1024 + dc.w &d, &e, &f, &g, &h, &i, &j, &k, &l, &m, &n, &o + endm + +ProcessorInfoTable + +; - PageSize, KB +; | - DataCacheTotalSize, KB +; | | - InstCacheTotalSize, KB +; | | | - CoherencyBlockSize +; | | | | - ReservationGranuleSize +; | | | | | - CombinedCaches +; | | | | | | - InstCacheLineSize +; | | | | | | | - DataCacheLineSize +; | | | | | | | | - DataCacheBlockSizeTouch +; | | | | | | | | | - InstCacheBlockSize +; | | | | | | | | | | - DataCacheBlockSize +; | | | | | | | | | | | - InstCacheAssociativity +; | | | | | | | | | | | | - DataCacheAssociativity +; | | | | | | | | | | | | | - TransCacheTotalSize +; | | | | | | | | | | | | | | - TransCacheAssociativity + + PnfoTblEnt 4, 32, 32, 32, 32, 1, 64, 64, 32, 32, 32, 8, 8, 256, 2 ; 0001 = 601 + PnfoTblEnt 4, 8, 8, 32, 32, 0, 32, 32, 32, 32, 32, 2, 2, 64, 2 ; 0003 = 603 + PnfoTblEnt 4, 16, 16, 32, 32, 0, 32, 32, 32, 32, 32, 4, 4, 128, 2 ; 0004 = 604 + PnfoTblEnt 4, 16, 16, 32, 32, 0, 32, 32, 32, 32, 32, 4, 4, 64, 2 ; 0006 = 603e + PnfoTblEnt 4, 16, 16, 32, 32, 0, 32, 32, 32, 32, 32, 4, 4, 64, 2 ; 0007 = 750FX + PnfoTblEnt 4, 32, 32, 32, 32, 0, 32, 32, 32, 32, 32, 8, 8, 128, 2 ; 0008 = 750 + PnfoTblEnt 4, 32, 32, 32, 32, 0, 32, 32, 32, 32, 32, 4, 4, 128, 2 ; 0009/a = ??? + PnfoTblEnt 4, 32, 32, 32, 32, 0, 32, 32, 32, 32, 32, 8, 8, 128, 2 ; 000c = 7400 + PnfoTblEnt 4, 32, 32, 32, 32, 0, 32, 32, 32, 32, 32, 8, 8, 256, 4 ; 000d = ??? + + + +OverrideProcessorInfo + +@loop + subic. r9, r9, 4 + lwzx r12, r11, r9 + stwx r12, r10, r9 + bgt+ @loop diff --git a/NanoKernel/NKQueues.s b/NanoKernel/NKQueues.s new file mode 100644 index 0000000..d4d842e --- /dev/null +++ b/NanoKernel/NKQueues.s @@ -0,0 +1,2526 @@ + DeclareMPCall 15, MPCall_15 + +MPCall_15 ; OUTSIDE REFERER + li r8, 0x34 + bl PoolAlloc_with_crset + mr. r31, r8 + beq+ major_0x0af60_0x20 + lis r16, 'MS' + stw r8, 0x0008(r8) + ori r16, r16, 'GQ' + stw r8, 0x000c(r8) + stw r16, 0x0004(r8) + addi r9, r8, 0x10 + lis r16, 'NO' + stw r9, 0x0008(r9) + ori r16, r16, 'TQ' + stw r9, 0x000c(r9) + stw r16, 0x0004(r9) + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + li r9, 0x04 + +; r1 = kdp +; r9 = kind + bl MakeID + cmpwi r8, 0x00 + bne+ MPCall_15_0x70 + mr r8, r31 + bl PoolFree + b major_0x0af60 + +MPCall_15_0x70 + mfsprg r30, 0 + lwz r30, -0x0008(r30) + stw r8, 0x0000(r31) + lwz r17, 0x0060(r30) + stw r17, 0x0020(r31) + mr r4, r8 + li r17, 0x00 + stw r17, 0x0024(r31) + stw r17, 0x0028(r31) + stw r17, 0x002c(r31) + stw r17, 0x0030(r31) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 16, MPCall_16 + +MPCall_16 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Queue.kIDClass + + mr r31, r8 + bne+ ReleaseAndReturnMPCallInvalidIDErr + +MPCall_16_0x2c + addi r30, r31, 0x10 + lwz r8, 0x0018(r31) + cmpw r8, r30 + beq- MPCall_16_0x60 + lwz r16, 0x0008(r8) + lwz r17, 0x000c(r8) + stw r16, 0x0008(r17) + stw r17, 0x000c(r16) + li r16, 0x00 + stw r16, 0x0008(r8) + stw r16, 0x000c(r8) + bl PoolFree + b MPCall_16_0x2c + +MPCall_16_0x60 + lwz r30, 0x0028(r31) + +MPCall_16_0x64 + mr. r8, r30 + beq- MPCall_16_0x78 + lwz r30, 0x0008(r30) + bl PoolFree + b MPCall_16_0x64 + +MPCall_16_0x78 + mr r8, r3 + bl major_0x0dce8 + +MPCall_16_0x80 + addi r30, r31, 0x00 + lwz r16, 0x0008(r31) + cmpw r16, r30 + addi r8, r16, -0x08 + beq- MPCall_16_0xe4 + lwz r17, 0x0088(r8) + li r18, -0x726f + stw r18, 0x011c(r17) + lbz r17, 0x0037(r8) + cmpwi r17, 0x01 + bne- MPCall_16_0xb4 + addi r8, r8, 0x20 + bl major_0x136c8 + +MPCall_16_0xb4 + lwz r16, 0x0008(r31) + lwz r17, 0x0008(r16) + lwz r18, 0x000c(r16) + stw r17, 0x0008(r18) + stw r18, 0x000c(r17) + li r17, 0x00 + stw r17, 0x0008(r16) + stw r17, 0x000c(r16) + addi r8, r16, -0x08 + bl TaskReadyAsPrev + bl major_0x14af8 + b MPCall_16_0x80 + +MPCall_16_0xe4 + mr r8, r31 + bl PoolFree + mr r8, r3 + bl DeleteID + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 39, MPCall_39 + +MPCall_39 ; OUTSIDE REFERER + cmpwi r4, 0x00 + blt+ ReturnMPCallOOM + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Queue.kIDClass + + mr r31, r8 + bne+ ReleaseAndReturnMPCallInvalidIDErr + lwz r29, 0x0024(r31) + lwz r30, 0x0028(r31) + cmpw r29, r4 + +; r1 = kdp + beq+ ReleaseAndReturnZeroFromMPCall + blt- MPCall_39_0x7c + +MPCall_39_0x48 + mr. r8, r30 + beq- MPCall_39_0x70 + addi r29, r29, -0x01 + lwz r30, 0x0008(r30) + bl PoolFree + cmpw r29, r4 + bgt+ MPCall_39_0x48 + stw r4, 0x0024(r31) + stw r30, 0x0028(r31) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_39_0x70 + stw r29, 0x0024(r31) + stw r30, 0x0028(r31) + b ReleaseAndReturnMPCallOOM + +MPCall_39_0x7c + li r8, 0x1c + bl PoolAlloc_with_crset + cmpwi r8, 0x00 + beq+ major_0x0af60 + addi r29, r29, 0x01 + lis r17, 0x6e6f + ori r17, r17, 0x7472 + stw r17, 0x0004(r8) + stw r30, 0x0008(r8) + stw r29, 0x0024(r31) + cmpw r29, r4 + stw r8, 0x0028(r31) + mr r30, r8 + blt+ MPCall_39_0x7c + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 17, MPCall_17 + +MPCall_17 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Queue.kIDClass + + mr r31, r8 + bne+ ReleaseAndReturnMPCallInvalidIDErr + lwz r16, 0x0024(r31) + li r8, 0x1c + cmpwi r16, 0x00 + bne- MPCall_17_0x58 + bl PoolAlloc_with_crset + cmpwi r8, 0x00 + beq+ major_0x0af60 + lis r17, 0x6e6f + ori r17, r17, 0x7465 + stw r17, 0x0004(r8) + b MPCall_17_0x6c + +MPCall_17_0x58 + lwz r17, 0x0028(r31) + mr. r8, r17 + beq+ ReleaseAndReturnMPCallOOM + lwz r17, 0x0008(r17) + stw r17, 0x0028(r31) + +MPCall_17_0x6c + lwz r16, 0x0134(r6) + stw r4, 0x0010(r8) + stw r5, 0x0014(r8) + stw r16, 0x0018(r8) + bl major_0x0c8b4 + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + +; major_0x0c8b4 + +; Xrefs: +; major_0x02ccc +; MPCall_17 +; major_0x0db04 +; MPCall_9 +; MPCall_58 + +major_0x0c8b4 ; OUTSIDE REFERER + addi r17, r31, 0x10 + stw r17, 0x0000(r8) + stw r17, 0x0008(r8) + lwz r16, 0x000c(r17) + stw r16, 0x000c(r8) + stw r8, 0x0008(r16) + stw r8, 0x000c(r17) + lwz r18, 0x0030(r31) + addi r18, r18, 0x01 + stw r18, 0x0030(r31) + mflr r27 + lwz r8, 0x0000(r31) + bl major_0x0dce8 + lwz r16, 0x0008(r31) + cmpw r16, r31 + addi r8, r16, -0x08 + beq- major_0x0c8b4_0xac + lwz r17, 0x0088(r8) + lwz r18, 0x00fc(r17) + subi r18, r18, 4 + stw r18, 0x00fc(r17) + lbz r17, 0x0037(r8) + cmpwi r17, 0x01 + bne- major_0x0c8b4_0x68 + addi r8, r8, 0x20 + bl major_0x136c8 + +major_0x0c8b4_0x68 + lwz r16, 0x0008(r31) + lwz r17, 0x0008(r16) + lwz r18, 0x000c(r16) + stw r17, 0x0008(r18) + stw r18, 0x000c(r17) + li r17, 0x00 + stw r17, 0x0008(r16) + stw r17, 0x000c(r16) + lwz r18, 0x002c(r31) + addi r18, r18, -0x01 + stw r18, 0x002c(r31) + addi r8, r16, -0x08 + li r17, 0x01 + stb r17, 0x0019(r8) + bl TaskReadyAsPrev + bl CalculateTimeslice + bl major_0x14af8 + +major_0x0c8b4_0xac + mtlr r27 + blr + + + + DeclareMPCall 18, MPCall_18 + +MPCall_18 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Queue.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + lwz r16, 0x0018(r31) + addi r17, r31, 0x10 + cmpw r16, r17 + beq- MPCall_18_0x9c + lwz r4, 0x0010(r16) + lwz r5, 0x0014(r16) + lwz r17, 0x0018(r16) + stw r17, 0x0134(r6) + lwz r17, 0x0008(r16) + lwz r18, 0x000c(r16) + stw r17, 0x0008(r18) + stw r18, 0x000c(r17) + li r17, 0x00 + stw r17, 0x0008(r16) + stw r17, 0x000c(r16) + lwz r18, 0x0030(r31) + addi r18, r18, -0x01 + stw r18, 0x0030(r31) + lbz r17, 0x0007(r16) + mr r8, r16 + cmpwi r17, 0x72 + beq- MPCall_18_0x8c + bl PoolFree + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_18_0x8c + lwz r17, 0x0028(r31) + stw r16, 0x0028(r31) + stw r17, 0x0008(r16) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_18_0x9c + lwz r17, 0x013c(r6) + mfsprg r30, 0 + cmpwi r17, 0x00 + lwz r19, -0x0008(r30) + beq+ ReleaseAndTimeoutMPCall + lwz r16, 0x0064(r19) + rlwinm. r16, r16, 0, 15, 15 + beq- MPCall_18_0xc4 + stw r3, -0x0410(r1) + b ReleaseAndReturnMPCallBlueBlocking + +MPCall_18_0xc4 + mr r8, r19 + bl major_0x13e4c + lwz r19, -0x0008(r30) + addi r16, r31, 0x00 + addi r17, r19, 0x08 + stw r16, 0x0000(r17) + stw r16, 0x0008(r17) + lwz r18, 0x000c(r16) + stw r18, 0x000c(r17) + stw r17, 0x0008(r18) + stw r17, 0x000c(r16) + lwz r18, 0x002c(r31) + addi r18, r18, 0x01 + stw r18, 0x002c(r31) + lis r16, 0x7fff + lwz r17, 0x013c(r6) + ori r16, r16, 0xffff + addi r30, r19, 0x20 + cmpw r17, r16 + li r16, 0x02 + beq- MPCall_18_0x154 + stb r16, 0x0014(r30) + stw r19, 0x0018(r30) + mr r8, r17 + +; r1 = kdp +; r8 = multiple (pos: /250; neg: /250000) + bl TimebaseTicksPerPeriod +; r8 = hi +; r9 = lo + + mr r27, r8 + mr r28, r9 + bl GetTime + mfxer r16 + addc r9, r9, r28 + adde r8, r8, r27 + mtxer r16 + stw r8, 0x0038(r30) + stw r9, 0x003c(r30) + mr r8, r30 + bl called_by_init_tmrqs + +MPCall_18_0x154 + b AlternateMPCallReturnPath + + + + DeclareMPCall 19, MPCall_19 + +MPCall_19 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Queue.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + lwz r16, 0x0018(r31) + addi r17, r31, 0x10 + cmpw r16, r17 + beq+ ReleaseAndTimeoutMPCall + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 20, MPCall_20 + +MPCall_20 ; OUTSIDE REFERER + cmpw r4, r3 + bgt+ ReturnMPCallOOM + li r8, 0x20 + bl PoolAlloc_with_crset + mr. r31, r8 + beq+ major_0x0af60_0x20 + lis r16, 0x5345 + stw r31, 0x0008(r31) + ori r16, r16, 0x4d41 + stw r31, 0x000c(r31) + stw r16, 0x0004(r31) + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + li r9, 0x05 + +; r1 = kdp +; r9 = kind + bl MakeID + cmpwi r8, 0x00 + bne+ MPCall_20_0x60 + mr r8, r31 + bl PoolFree + b major_0x0af60 + +MPCall_20_0x60 + li r18, 0x00 + stw r8, 0x0000(r31) + mfsprg r30, 0 + lwz r30, -0x0008(r30) + stw r3, 0x0014(r31) + stw r4, 0x0010(r31) + lwz r17, 0x0060(r30) + stw r18, 0x001c(r31) + stw r17, 0x0018(r31) + mr r5, r8 + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 23, MPCall_23 + +MPCall_23 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Semaphore.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + lwz r16, 0x0010(r31) + cmpwi r16, 0x00 + addi r16, r16, -0x01 + ble- MPCall_23_0x44 + stw r16, 0x0010(r31) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_23_0x44 + cmpwi r4, 0x00 + mfsprg r30, 0 + beq+ ReleaseAndTimeoutMPCall + lwz r8, -0x0008(r30) + lwz r16, 0x0064(r8) + rlwinm. r16, r16, 0, 15, 15 + beq- MPCall_23_0x68 + stw r3, -0x0410(r1) + b ReleaseAndReturnMPCallBlueBlocking + +MPCall_23_0x68 + bl major_0x13e4c + addi r16, r31, 0x00 + addi r17, r8, 0x08 + stw r16, 0x0000(r17) + stw r16, 0x0008(r17) + lwz r18, 0x000c(r16) + stw r18, 0x000c(r17) + stw r17, 0x0008(r18) + stw r17, 0x000c(r16) + lwz r18, 0x001c(r31) + addi r18, r18, 0x01 + stw r18, 0x001c(r31) + lis r16, 0x7fff + addi r30, r8, 0x20 + ori r16, r16, 0xffff + cmpw r4, r16 + li r17, 0x02 + beq- MPCall_23_0xec + stb r17, 0x0014(r30) + stw r8, 0x0018(r30) + mr r8, r4 + +; r1 = kdp +; r8 = multiple (pos: /250; neg: /250000) + bl TimebaseTicksPerPeriod +; r8 = hi +; r9 = lo + + mr r27, r8 + mr r28, r9 + bl GetTime + mfxer r16 + addc r9, r9, r28 + adde r8, r8, r27 + mtxer r16 + stw r8, 0x0038(r30) + stw r9, 0x003c(r30) + mr r8, r30 + bl called_by_init_tmrqs + +MPCall_23_0xec + li r3, 0x00 + b AlternateMPCallReturnPath + + + + DeclareMPCall 24, MPCall_24 + +MPCall_24 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Semaphore.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + lwz r16, 0x0010(r31) + cmpwi r16, 0x00 + ble+ ReleaseAndTimeoutMPCall + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 22, MPCall_22 + +MPCall_22 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Semaphore.kIDClass + + mr r31, r8 + bne+ ReleaseAndReturnMPCallInvalidIDErr + bl major_0x0ccf4 + mr r3, r8 + b ReleaseAndReturnMPCall + + + +; major_0x0ccf4 + +; Xrefs: +; MPCall_22 +; major_0x0db04 + +major_0x0ccf4 ; OUTSIDE REFERER + mflr r27 + lwz r8, 0x0000(r31) + bl major_0x0dce8 + lwz r16, 0x0008(r31) + cmpw r16, r31 + beq- major_0x0ccf4_0x80 + addi r8, r16, -0x08 + lbz r17, 0x0037(r8) + cmpwi r17, 0x01 + bne- major_0x0ccf4_0x30 + addi r8, r8, 0x20 + bl major_0x136c8 + +major_0x0ccf4_0x30 + lwz r16, 0x0008(r31) + lwz r17, 0x0008(r16) + lwz r18, 0x000c(r16) + stw r17, 0x0008(r18) + stw r18, 0x000c(r17) + li r17, 0x00 + stw r17, 0x0008(r16) + stw r17, 0x000c(r16) + lwz r18, 0x001c(r31) + addi r18, r18, -0x01 + stw r18, 0x001c(r31) + addi r8, r16, -0x08 + li r17, 0x01 + stb r17, 0x0019(r8) + bl TaskReadyAsPrev + bl CalculateTimeslice + bl major_0x14af8 + mtlr r27 + li r8, 0x00 + blr + +major_0x0ccf4_0x80 + mtlr r27 + lwz r16, 0x0010(r31) + lwz r17, 0x0014(r31) + cmpw r16, r17 + addi r16, r16, 0x01 + li r8, -0x7272 + bgelr- + stw r16, 0x0010(r31) + li r8, 0x00 + blr + + + + DeclareMPCall 21, MPCall_21 + +MPCall_21 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Semaphore.kIDClass + + mr r31, r8 + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r8, r3 + bl major_0x0dce8 + +MPCall_21_0x34 + addi r30, r31, 0x00 + lwz r16, 0x0008(r31) + cmpw r16, r30 + addi r8, r16, -0x08 + beq- MPCall_21_0x98 + lwz r17, 0x0088(r8) + li r18, -0x726f + stw r18, 0x011c(r17) + lbz r17, 0x0037(r8) + cmpwi r17, 0x01 + bne- MPCall_21_0x68 + addi r8, r8, 0x20 + bl major_0x136c8 + +MPCall_21_0x68 + lwz r16, 0x0008(r31) + lwz r17, 0x0008(r16) + lwz r18, 0x000c(r16) + stw r17, 0x0008(r18) + stw r18, 0x000c(r17) + li r17, 0x00 + stw r17, 0x0008(r16) + stw r17, 0x000c(r16) + addi r8, r16, -0x08 + bl TaskReadyAsPrev + bl major_0x14af8 + b MPCall_21_0x34 + +MPCall_21_0x98 + mr r8, r31 + bl PoolFree + mr r8, r3 + bl DeleteID + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 25, MPCall_25 + +MPCall_25 ; OUTSIDE REFERER + li r8, 0x24 + bl PoolAlloc_with_crset + mr. r31, r8 + beq+ major_0x0af60_0x20 + lis r16, 0x4352 + stw r31, 0x0008(r31) + ori r16, r16, 0x474e + stw r31, 0x000c(r31) + stw r16, 0x0004(r31) + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + li r9, 0x06 + +; r1 = kdp +; r9 = kind + bl MakeID + cmpwi r8, 0x00 + bne+ MPCall_25_0x58 + mr r8, r31 + bl PoolFree + b major_0x0af60 + +MPCall_25_0x58 + li r18, 0x00 + mfsprg r30, 0 + lwz r30, -0x0008(r30) + li r16, 0x00 + stw r8, 0x0000(r31) + stw r16, 0x0014(r31) + stw r16, 0x001c(r31) + stw r16, 0x0018(r31) + lwz r17, 0x0060(r30) + stw r18, 0x0020(r31) + stw r17, 0x0010(r31) + mr r4, r8 + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 27, MPCall_27 + +MPCall_27 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, CriticalRegion.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + mfsprg r17, 0 + lwz r18, 0x0014(r31) + lwz r30, -0x0008(r17) + cmpwi r18, 0x00 + lwz r16, 0x0018(r31) + beq- MPCall_27_0x64 + lwz r17, 0x001c(r31) + cmpw r16, r30 + cmpw cr1, r17, r5 + bne- MPCall_27_0x78 + bne- cr1, MPCall_27_0x78 + addi r18, r18, 0x01 + stw r18, 0x0014(r31) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_27_0x64 + addi r18, r18, 0x01 + stw r30, 0x0018(r31) + stw r5, 0x001c(r31) + stw r18, 0x0014(r31) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_27_0x78 + lwz r8, 0x0000(r16) + +; r8 = id + bl LookupID + cmpwi r9, Task.kIDClass + + bne+ ReleaseAndReturnMPCallTaskAborted + lwz r8, 0x001c(r31) + +; r8 = id + bl LookupID + cmpwi r9, Process.kIDClass + + bne+ ReleaseAndReturnMPCallTaskAborted + cmpwi r4, 0x00 + lwz r16, 0x0064(r30) + beq+ ReleaseAndTimeoutMPCall + rlwinm. r16, r16, 0, 15, 15 + beq- MPCall_27_0xb4 + stw r3, -0x0410(r1) + b ReleaseAndReturnMPCallBlueBlocking + +MPCall_27_0xb4 + mr r8, r30 + bl major_0x13e4c + lis r16, 0x7fff + addi r18, r30, 0x08 + ori r16, r16, 0xffff + stw r31, 0x0000(r18) + stw r31, 0x0008(r18) + lwz r19, 0x000c(r31) + stw r19, 0x000c(r18) + stw r18, 0x0008(r19) + stw r18, 0x000c(r31) + lwz r18, 0x0020(r31) + addi r18, r18, 0x01 + stw r18, 0x0020(r31) + cmpw r4, r16 + beq- MPCall_27_0x138 + addi r29, r30, 0x20 + li r8, 0x02 + stw r30, 0x0018(r29) + stb r8, 0x0014(r29) + mr r8, r4 + +; r1 = kdp +; r8 = multiple (pos: /250; neg: /250000) + bl TimebaseTicksPerPeriod +; r8 = hi +; r9 = lo + + mr r27, r8 + mr r28, r9 + bl GetTime + mfxer r16 + addc r9, r9, r28 + adde r8, r8, r27 + mtxer r16 + stw r8, 0x0038(r29) + stw r9, 0x003c(r29) + mr r8, r29 + bl called_by_init_tmrqs + +MPCall_27_0x138 + b AlternateMPCallReturnPath + + + + DeclareMPCall 29, MPCall_29 + +MPCall_29 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, CriticalRegion.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + mfsprg r17, 0 + lwz r18, 0x0014(r31) + cmpwi r18, 0x00 + +; r1 = kdp + beq+ ReleaseAndReturnZeroFromMPCall + lwz r30, -0x0008(r17) + lwz r16, 0x0018(r31) + lwz r17, 0x001c(r31) + cmpw r16, r30 + cmpw cr1, r17, r4 + bne+ ReleaseAndTimeoutMPCall + bne+ cr1, ReleaseAndTimeoutMPCall + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 28, MPCall_28 + +MPCall_28 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, CriticalRegion.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + mfsprg r17, 0 + lwz r16, 0x0018(r31) + lwz r30, -0x0008(r17) + lwz r18, 0x0014(r31) + lwz r17, 0x001c(r31) + cmpw r16, r30 + cmpw cr1, r17, r4 + bne+ ReleaseAndReturnMPCallOOM + bne+ cr1, ReleaseAndReturnMPCallOOM + addi r18, r18, -0x01 + cmpwi r18, 0x00 + stw r18, 0x0014(r31) + +; r1 = kdp + bne+ ReleaseAndReturnZeroFromMPCall + stw r18, 0x0018(r31) + stw r18, 0x001c(r31) + mr r8, r3 + bl major_0x0dce8 + lwz r16, 0x0008(r31) + cmpw r16, r31 + +; r1 = kdp + beq+ ReleaseAndReturnZeroFromMPCall + addi r8, r16, -0x08 + lbz r17, 0x0037(r8) + cmpwi r17, 0x01 + bne- MPCall_28_0x94 + addi r8, r8, 0x20 + bl major_0x136c8 + +MPCall_28_0x94 + lwz r16, 0x0008(r31) + lwz r17, 0x0008(r16) + lwz r18, 0x000c(r16) + stw r17, 0x0008(r18) + stw r18, 0x000c(r17) + li r17, 0x00 + stw r17, 0x0008(r16) + stw r17, 0x000c(r16) + lwz r18, 0x0020(r31) + addi r18, r18, -0x01 + stw r18, 0x0020(r31) + addi r8, r16, -0x08 + lwz r17, 0x0088(r8) + lwz r18, 0x00fc(r17) + subi r18, r18, 4 + stw r18, 0x00fc(r17) + li r17, 0x01 + stb r17, 0x0019(r8) + bl TaskReadyAsPrev + bl CalculateTimeslice + bl major_0x14af8 + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 26, MPCall_26 + +MPCall_26 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, CriticalRegion.kIDClass + + mr r31, r8 + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r8, r3 + bl major_0x0dce8 + +MPCall_26_0x34 + addi r30, r31, 0x00 + lwz r16, 0x0008(r31) + cmpw r16, r30 + addi r8, r16, -0x08 + beq- MPCall_26_0x98 + lwz r17, 0x0088(r8) + li r18, -0x726f + stw r18, 0x011c(r17) + lbz r17, 0x0037(r8) + cmpwi r17, 0x01 + bne- MPCall_26_0x68 + addi r8, r8, 0x20 + bl major_0x136c8 + +MPCall_26_0x68 + lwz r16, 0x0008(r31) + lwz r17, 0x0008(r16) + lwz r18, 0x000c(r16) + stw r17, 0x0008(r18) + stw r18, 0x000c(r17) + li r17, 0x00 + stw r17, 0x0008(r16) + stw r17, 0x000c(r16) + addi r8, r16, -0x08 + bl TaskReadyAsPrev + bl major_0x14af8 + b MPCall_26_0x34 + +MPCall_26_0x98 + mr r8, r31 + bl PoolFree + mr r8, r3 + bl DeleteID + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 49, NKCreateEventGroupForThisTask + +NKCreateEventGroupForThisTask + + li r8, EventGroup.Size + bl PoolAlloc + mr. r31, r8 + beq+ major_0x0af60_0x20 + + InitList r8, EventGroup.kSignature, scratch=r16 + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + li r9, EventGroup.kIDClass + bl MakeID + cmpwi r8, 0 + bne+ @success + + mr r8, r31 + bl PoolFree + b major_0x0af60 + +@success + mfsprg r30, 0 + lwz r30, EWA.PA_CurTask(r30) + + stw r8, EventGroup.LLL + LLL.Freeform(r31) + + lwz r17, Task.ProcessID(r30) + stw r17, EventGroup.ProcessID(r31) + + mr r4, r8 + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 50, MPCall_50 + +MPCall_50 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, EventGroup.kIDClass + + mr r31, r8 + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r8, r3 + bl major_0x0dce8 + +MPCall_50_0x34 + addi r30, r31, 0x00 + lwz r16, 0x0008(r31) + cmpw r16, r30 + addi r8, r16, -0x08 + beq- MPCall_50_0x98 + lwz r17, 0x0088(r8) + li r18, -0x726f + stw r18, 0x011c(r17) + lbz r17, 0x0037(r8) + cmpwi r17, 0x01 + bne- MPCall_50_0x68 + addi r8, r8, 0x20 + bl major_0x136c8 + +MPCall_50_0x68 + lwz r16, 0x0008(r31) + lwz r17, 0x0008(r16) + lwz r18, 0x000c(r16) + stw r17, 0x0008(r18) + stw r18, 0x000c(r17) + li r17, 0x00 + stw r17, 0x0008(r16) + stw r17, 0x000c(r16) + addi r8, r16, -0x08 + bl TaskReadyAsPrev + bl major_0x14af8 + b MPCall_50_0x34 + +MPCall_50_0x98 + mr r8, r31 + bl PoolFree + mr r8, r3 + bl DeleteID + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 51, MPCall_51 + +MPCall_51 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, EventGroup.kIDClass + + mr r31, r8 + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r8, r4 + bl major_0x0d35c + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + +; major_0x0d35c + +; Xrefs: +; MPCall_51 +; major_0x0db04 +; MPCall_83 + +major_0x0d35c ; OUTSIDE REFERER + lwz r16, 0x0010(r31) + or r16, r16, r8 + stw r16, 0x0010(r31) + mflr r27 + lwz r8, 0x0000(r31) + bl major_0x0dce8 + lwz r16, 0x0008(r31) + cmpw r16, r31 + addi r8, r16, -0x08 + beq- major_0x0d35c_0x90 + lwz r17, 0x0088(r8) + lwz r18, 0x00fc(r17) + subi r18, r18, 4 + stw r18, 0x00fc(r17) + lbz r17, 0x0037(r8) + cmpwi r17, 0x01 + bne- major_0x0d35c_0x4c + addi r8, r8, 0x20 + bl major_0x136c8 + +major_0x0d35c_0x4c + lwz r16, 0x0008(r31) + lwz r17, 0x0008(r16) + lwz r18, 0x000c(r16) + stw r17, 0x0008(r18) + stw r18, 0x000c(r17) + li r17, 0x00 + stw r17, 0x0008(r16) + stw r17, 0x000c(r16) + lwz r18, 0x001c(r31) + addi r18, r18, -0x01 + stw r18, 0x001c(r31) + addi r8, r16, -0x08 + li r17, 0x01 + stb r17, 0x0019(r8) + bl TaskReadyAsPrev + bl CalculateTimeslice + bl major_0x14af8 + +major_0x0d35c_0x90 + lwz r16, 0x0018(r31) + rlwinm. r17, r16, 0, 27, 27 + beq- major_0x0d35c_0x1a0 + lwz r17, 0x0658(r1) + lwz r26, -0x08f0(r1) + lwz r18, 0x00c8(r17) + lwz r19, 0x00d0(r17) + cmpwi cr1, r18, 0x00 + cmpwi r19, 0x00 + bne- cr1, major_0x0d35c_0xc8 + bne- major_0x0d35c_0x1a0 + lwz r8, 0x0000(r31) + stw r8, 0x00d0(r17) + b major_0x0d35c_0x118 + +major_0x0d35c_0xc8 + lwz r9, 0x0634(r1) + rlwinm r16, r16, 2, 26, 29 + add r18, r18, r9 + lwzx r19, r16, r18 + cmpwi r19, 0x00 + bne- major_0x0d35c_0x1a0 + lwz r8, 0x0000(r31) + stwx r8, r16, r18 + li r19, 0x1c + li r9, 0x04 + +major_0x0d35c_0xf0 + lwzx r8, r19, r18 + cmpwi r8, 0x00 + bne- major_0x0d35c_0x108 + subf. r19, r9, r19 + bgt+ major_0x0d35c_0xf0 + bl panic + +major_0x0d35c_0x108 + cmplw r16, r19 + srwi r16, r16, 2 + blt- major_0x0d35c_0x1a0 + stw r16, 0x00d0(r17) + +major_0x0d35c_0x118 + lwz r16, 0x0064(r26) + lbz r19, 0x0018(r26) + ori r16, r16, 0x10 + stw r16, 0x0064(r26) + lwz r17, -0x0440(r1) + lwz r16, 0x0674(r1) + lwz r8, 0x0678(r1) + and r16, r16, r8 + or r17, r17, r16 + stw r17, -0x0440(r1) + cmpwi r19, 0x00 + addi r16, r26, 0x08 + bne- major_0x0d35c_0x198 + lwz r17, 0x0008(r16) + lwz r18, 0x000c(r16) + stw r17, 0x0008(r18) + stw r18, 0x000c(r17) + li r17, 0x00 + stw r17, 0x0008(r16) + stw r17, 0x000c(r16) + lbz r17, 0x0037(r26) + cmpwi r17, 0x01 + bne- major_0x0d35c_0x17c + addi r8, r26, 0x20 + bl major_0x136c8 + +major_0x0d35c_0x17c + lwz r18, -0x08f0(r1) + li r16, 0x00 + stb r16, 0x0019(r26) + mr r8, r26 + bl TaskReadyAsNext + mr r8, r26 + bl CalculateTimeslice + +major_0x0d35c_0x198 + mr r8, r26 + bl major_0x14af8 + +major_0x0d35c_0x1a0 + mtlr r27 + blr + + + + DeclareMPCall 52, MPCall_52 + +MPCall_52 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, EventGroup.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + lwz r16, 0x0010(r31) + cmpwi r16, 0x00 + beq- MPCall_52_0xc0 + mr r4, r16 + li r16, 0x00 + stw r16, 0x0010(r31) + lwz r16, 0x0018(r31) + lwz r17, 0x0658(r1) + rlwinm. r18, r16, 0, 27, 27 + rlwinm r16, r16, 2, 26, 29 + +; r1 = kdp + beq+ ReleaseAndReturnZeroFromMPCall + lwz r18, 0x00c8(r17) + lwz r9, 0x0634(r1) + cmpwi r18, 0x00 + add r18, r18, r9 + bne- MPCall_52_0x84 + lwz r18, 0x00d0(r17) + cmpw r18, r3 + li r18, 0x00 + +; r1 = kdp + bne+ ReleaseAndReturnZeroFromMPCall + stw r18, 0x00d0(r17) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_52_0x84 + lwzx r19, r16, r18 + cmpw r19, r3 + li r19, 0x00 + +; r1 = kdp + bne+ ReleaseAndReturnZeroFromMPCall + stwx r19, r16, r18 + li r19, 0x1c + li r9, 0x04 + +MPCall_52_0xa0 + lwzx r8, r19, r18 + cmpwi r8, 0x00 + bne- MPCall_52_0xb4 + subf. r19, r9, r19 + bgt+ MPCall_52_0xa0 + +MPCall_52_0xb4 + srwi r19, r19, 2 + stw r19, 0x00d0(r17) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_52_0xc0 + mfsprg r30, 0 + cmpwi r5, 0x00 + lwz r19, -0x0008(r30) + beq+ ReleaseAndTimeoutMPCall + lwz r16, 0x0064(r19) + rlwinm. r16, r16, 0, 15, 15 + beq- MPCall_52_0xe4 + stw r3, -0x0410(r1) + b ReleaseAndReturnMPCallBlueBlocking + +MPCall_52_0xe4 + mr r8, r19 + bl major_0x13e4c + lwz r19, -0x0008(r30) + addi r16, r31, 0x00 + addi r17, r19, 0x08 + stw r16, 0x0000(r17) + stw r16, 0x0008(r17) + lwz r18, 0x000c(r16) + stw r18, 0x000c(r17) + stw r17, 0x0008(r18) + stw r17, 0x000c(r16) + lwz r18, 0x001c(r31) + addi r18, r18, 0x01 + stw r18, 0x001c(r31) + lis r16, 0x7fff + ori r16, r16, 0xffff + addi r30, r19, 0x20 + cmpw r5, r16 + li r16, 0x02 + beq- MPCall_52_0x170 + stb r16, 0x0014(r30) + stw r19, 0x0018(r30) + mr r8, r5 + +; r1 = kdp +; r8 = multiple (pos: /250; neg: /250000) + bl TimebaseTicksPerPeriod +; r8 = hi +; r9 = lo + + mr r27, r8 + mr r28, r9 + bl GetTime + mfxer r16 + addc r9, r9, r28 + adde r8, r8, r27 + mtxer r16 + stw r8, 0x0038(r30) + stw r9, 0x003c(r30) + mr r8, r30 + bl called_by_init_tmrqs + +MPCall_52_0x170 + b AlternateMPCallReturnPath + + + + DeclareMPCall 53, MPCall_53 + +MPCall_53 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, EventGroup.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + lwz r16, 0x0010(r31) + cmpwi r16, 0x00 + beq+ ReleaseAndTimeoutMPCall + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 54, MPCall_54 + +MPCall_54 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + bl LookupID + cmpwi r9, EventGroup.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + + mr r31, r8 + li r17, 1 + + cmpwi r4, 0 + cmplwi cr1, r4, 8 + + lwz r16, 0x0018(r31) + + beq- @use_1 + bgt- cr1, @use_1 + + mr r17, r4 +@use_1 + + ; r17 = 1 if outside 1-8 (inc) range + + ori r16, r16, 0x10 + rlwimi r16, r17, 0, 28, 31 + stw r16, 0x0018(r31) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 40, MPCall_40 + +MPCall_40 ; OUTSIDE REFERER + li r8, 0x40 + +; r1 = kdp +; r8 = size + bl PoolAlloc +; r8 = ptr + + mr. r31, r8 + beq+ major_0x0af60_0x20 + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r31 + li r9, 0x03 + +; r1 = kdp +; r9 = kind + bl MakeID + cmpwi r8, 0x00 + bne- MPCall_40_0x48 + mr r8, r31 + bl PoolFree + b major_0x0af60 + +MPCall_40_0x48 + mfsprg r30, 0 + stw r8, 0x0000(r31) + lwz r30, -0x0008(r30) + mr r4, r8 + lwz r17, 0x0060(r30) + stw r17, 0x0010(r31) + bl GetTime + stw r8, 0x0038(r31) + stw r9, 0x003c(r31) + lis r17, 0x5449 + ori r17, r17, 0x4d45 + stw r17, 0x0004(r31) + li r17, 0x03 + stb r17, 0x0014(r31) + li r17, 0x00 + stb r17, 0x0016(r31) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 41, MPCall_41 + +MPCall_41 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Timer.kIDClass + + mr r31, r8 + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r8, r3 + bl DeleteID + lwz r16, 0x0008(r31) + cmpwi r16, 0x00 + beq- MPCall_41_0x48 + mr r8, r31 + bl major_0x136c8 + +MPCall_41_0x48 + sync + lwz r16, PSA.SchLock + Lock.Count(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + bne+ cr1, MPCall_41_0x64 + mflr r16 + bl panic + +MPCall_41_0x64 + stw r16, PSA.SchLock + Lock.Count(r1) + lwz r8, 0x001c(r31) + cmpwi r8, 0x00 + bnel- PoolFree + mr r8, r31 + bl PoolFree + b ReturnZeroFromMPCall + + + + DeclareMPCall 30, MPCall_30 + +MPCall_30 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Timer.kIDClass + + mr r31, r8 + bne+ ReleaseAndReturnMPCallInvalidIDErr + lbz r16, 0x0014(r31) + cmpwi r16, 0x03 + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r8, r4 + +; r8 = id + bl LookupID + cmpwi r9, Semaphore.kIDClass + + cmpwi cr2, r9, 0x04 + beq- MPCall_30_0x80 + cmpwi r9, 0x09 + beq- cr2, MPCall_30_0x64 + bne+ ReleaseAndReturnMPCallInvalidIDErr + stw r4, 0x002c(r31) + stw r5, 0x0030(r31) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_30_0x64 + stw r4, 0x0018(r31) + lwz r16, 0x0134(r6) + lwz r17, 0x013c(r6) + stw r5, 0x0020(r31) + stw r16, 0x0024(r31) + stw r17, 0x0028(r31) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_30_0x80 + stw r4, 0x0034(r31) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 31, MPCall_31 + +MPCall_31 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Timer.kIDClass + + mr r31, r8 + bne+ ReleaseAndReturnMPCallInvalidIDErr + lbz r16, 0x0014(r31) + cmpwi r16, 0x03 + bne+ ReleaseAndReturnMPCallInvalidIDErr + lwz r16, 0x0008(r31) + cmpwi r16, 0x00 + mr r8, r31 + beq- MPCall_31_0x4c + bl major_0x136c8 + +MPCall_31_0x4c + lwz r9, 0x001c(r31) + lwz r8, 0x0018(r31) + cmpwi r9, 0x00 + cmpwi cr1, r8, 0x00 + bne- MPCall_31_0x9c + beq- cr1, MPCall_31_0x9c + +; r8 = id + bl LookupID + cmpwi r9, Queue.kIDClass + + bne- MPCall_31_0x9c + lwz r9, 0x0024(r8) + li r8, 0x1c + cmpwi r9, 0x00 + bne- MPCall_31_0x9c + +; r1 = kdp +; r8 = size + bl PoolAlloc +; r8 = ptr + + mr. r30, r8 + beq+ major_0x0af60 + lis r8, 0x6e6f + ori r8, r8, 0x7465 + stw r8, 0x0004(r30) + stw r30, 0x001c(r31) + +MPCall_31_0x9c + lwz r16, 0x0134(r6) + rlwinm. r9, r16, 0, 29, 29 + mr r8, r4 + beq- MPCall_31_0xb8 + +; r1 = kdp +; r8 = multiple (pos: /250; neg: /250000) + bl TimebaseTicksPerPeriod +; r8 = hi +; r9 = lo + + mr r4, r8 + mr r5, r9 + +MPCall_31_0xb8 + lwz r16, 0x0134(r6) + rlwinm. r8, r16, 0, 30, 30 + mfxer r17 + beq- MPCall_31_0xdc + lwz r19, 0x003c(r31) + lwz r18, 0x0038(r31) + addc r5, r5, r19 + adde r4, r4, r18 + mtxer r17 + +MPCall_31_0xdc + stw r4, 0x0038(r31) + stw r5, 0x003c(r31) + lwz r16, 0x0134(r6) + clrlwi. r16, r16, 0x1f + li r17, 0x00 + beq- MPCall_31_0xf8 + li r17, 0x01 + +MPCall_31_0xf8 + stb r17, 0x0016(r31) + mr r8, r31 + bl called_by_init_tmrqs + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 32, MPCall_32 + +MPCall_32 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Timer.kIDClass + + mr r31, r8 + bne+ ReleaseAndReturnMPCallInvalidIDErr + lbz r16, 0x0017(r31) + cmpwi r16, 0x01 + bne- MPCall_32_0x58 + lwz r4, 0x0038(r31) + lwz r5, 0x003c(r31) + bl GetTime + mfxer r16 + subfc r5, r9, r5 + subfe. r4, r8, r4 + mtxer r16 + bge+ MPCall_32_0x60 + +MPCall_32_0x58 + li r4, 0x00 + li r5, 0x00 + +MPCall_32_0x60 + lwz r16, 0x0008(r31) + cmpwi r16, 0x00 + mr r8, r31 + beq- MPCall_32_0x74 + bl major_0x136c8 + +MPCall_32_0x74 +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 64, MPCall_64 + +MPCall_64 ; OUTSIDE REFERER + li r8, 0x28 + +; r1 = kdp +; r8 = size + bl PoolAlloc +; r8 = ptr + + mr. r31, r8 + beq+ major_0x0af60_0x20 + lis r16, 0x4b4e + ori r16, r16, 0x4f54 + stw r16, 0x0004(r31) + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + li r9, 0x0c + +; r1 = kdp +; r9 = kind + bl MakeID + cmpwi r8, 0x00 + bne+ MPCall_64_0x50 + mr r8, r31 + bl PoolFree + b major_0x0af60 + +MPCall_64_0x50 + mfsprg r30, 0 + lwz r30, -0x0008(r30) + stw r8, 0x0000(r31) + lwz r17, 0x0060(r30) + stw r17, 0x0008(r31) + mr r4, r8 + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 65, MPCall_65 + +MPCall_65 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Notification.kIDClass + + mr r31, r8 + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r8, r31 + bl PoolFree + mr r8, r3 + bl DeleteID + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 67, MPCall_67 + +MPCall_67 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Notification.kIDClass + + mr r30, r8 + bne+ ReleaseAndReturnMPCallInvalidIDErr + bl major_0x0db04 + mr r3, r8 + b ReleaseAndReturnMPCall + + + +; major_0x0db04 + +; Xrefs: +; major_0x02ccc +; IntPerfMonitor +; IntThermalEvent +; MPCall_67 +; major_0x102c8 +; CommonPIHPath + +major_0x0db04 ; OUTSIDE REFERER + mflr r29 + lwz r16, 0x000c(r30) + lwz r17, 0x0024(r30) + cmplwi r16, 0x00 + cmplwi cr1, r17, 0x00 + bne- major_0x0db04_0x28 + bne- cr1, major_0x0db04_0x28 + lwz r18, 0x001c(r30) + cmplwi r18, 0x00 + beq- major_0x0db04_0xf0 + +major_0x0db04_0x28 + lwz r8, 0x000c(r30) + cmplwi r8, 0x00 + beq- major_0x0db04_0x94 + +; r8 = id + bl LookupID + cmpwi r9, Queue.kIDClass + + mr r31, r8 + bne- major_0x0db04_0xfc + lwz r16, 0x0024(r31) + cmpwi r16, 0x00 + lwz r17, 0x0028(r31) + beq- major_0x0db04_0x68 + mr. r8, r17 + lwz r17, 0x0008(r17) + beq- major_0x0db04_0xf0 + stw r17, 0x0028(r31) + b major_0x0db04_0x78 + +major_0x0db04_0x68 + li r8, 0x1c + bl PoolAlloc_with_crset + cmpwi r8, 0x00 + beq- major_0x0db04_0xe4 + +major_0x0db04_0x78 + lwz r16, 0x0010(r30) + lwz r17, 0x0014(r30) + lwz r18, 0x0018(r30) + stw r16, 0x0010(r8) + stw r17, 0x0014(r8) + stw r18, 0x0018(r8) + bl major_0x0c8b4 + +major_0x0db04_0x94 + lwz r8, 0x0024(r30) + cmplwi r8, 0x00 + beq- major_0x0db04_0xb4 + +; r8 = id + bl LookupID + cmpwi r9, Semaphore.kIDClass + + mr r31, r8 + bne- major_0x0db04_0xfc + bl major_0x0ccf4 + +major_0x0db04_0xb4 + lwz r8, 0x001c(r30) + cmplwi r8, 0x00 + beq- major_0x0db04_0xd8 + +; r8 = id + bl LookupID + cmpwi r9, EventGroup.kIDClass + + mr r31, r8 + bne- major_0x0db04_0xfc + lwz r8, 0x0020(r30) + bl major_0x0d35c + +major_0x0db04_0xd8 + mtlr r29 + li r8, 0x00 + blr + +major_0x0db04_0xe4 + mtlr r29 + li r8, -0x726e + blr + +major_0x0db04_0xf0 + mtlr r29 + li r8, -0x7272 + blr + +major_0x0db04_0xfc + mtlr r29 + li r8, -0x7273 + blr + + + + DeclareMPCall 66, MPCall_66 + +MPCall_66 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Notification.kIDClass + + mr r31, r8 + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r8, r4 + +; r8 = id + bl LookupID + cmpwi r9, Semaphore.kIDClass + + cmpwi cr2, r9, 0x04 + beq- MPCall_66_0x74 + cmpwi r9, 0x09 + beq- cr2, MPCall_66_0x58 + bne+ ReleaseAndReturnMPCallInvalidIDErr + stw r4, 0x001c(r31) + stw r5, 0x0020(r31) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_66_0x58 + stw r4, 0x000c(r31) + lwz r16, 0x0134(r6) + lwz r17, 0x013c(r6) + stw r5, 0x0010(r31) + stw r16, 0x0014(r31) + stw r17, 0x0018(r31) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_66_0x74 + stw r4, 0x0024(r31) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 128, MPCall_128 + +MPCall_128 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Notification.kIDClass + + mr r31, r8 + bne+ ReleaseAndReturnMPCallInvalidIDErr + cmpwi r4, 0x04 + cmpwi cr1, r4, 0x09 + beq- MPCall_128_0x40 + beq- cr1, MPCall_128_0x58 + b major_0x0b054 + +MPCall_128_0x40 + lwz r16, 0x0134(r6) + lwz r17, 0x013c(r6) + stw r5, 0x0010(r31) + stw r16, 0x0014(r31) + stw r17, 0x0018(r31) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_128_0x58 + stw r5, 0x0020(r31) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + +; major_0x0dce8 + +; Xrefs: +; major_0x02ccc +; MPCall_16 +; major_0x0c8b4 +; major_0x0ccf4 +; MPCall_21 +; MPCall_28 +; MPCall_26 +; MPCall_50 +; major_0x0d35c + +major_0x0dce8 ; OUTSIDE REFERER + lwz r9, -0x0410(r1) + lwz r19, -0x08f0(r1) + cmpw r8, r9 + bnelr- + li r9, -0x01 + mflr r24 + stw r9, -0x0410(r1) + lbz r17, 0x0018(r19) + cmpwi r17, 0x00 + addi r16, r19, 0x08 + bne- major_0x0dce8_0x70 + lwz r17, 0x0008(r16) + lwz r18, 0x000c(r16) + stw r17, 0x0008(r18) + stw r18, 0x000c(r17) + li r17, 0x00 + stw r17, 0x0008(r16) + stw r17, 0x000c(r16) + lbz r17, 0x0037(r19) + cmpwi r17, 0x01 + bne- major_0x0dce8_0x60 + addi r8, r19, 0x20 + bl major_0x136c8 + lwz r19, -0x08f0(r1) + +major_0x0dce8_0x60 + li r16, 0x01 + stb r16, 0x0019(r19) + lwz r8, -0x08f0(r1) + bl TaskReadyAsPrev + +major_0x0dce8_0x70 + lwz r8, -0x08f0(r1) + mtlr r24 + b major_0x14af8 + + + + DeclareMPCall 120, MPCall_120 + +MPCall_120 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID +; r8 = something not sure what +; r9 = 0:inval, 1:proc, 2:task, 3:timer, 4:q, 5:sema, 6:cr, 7:cpu, 8:addrspc, 9:evtg, 10:cohg, 11:area, 12:not, 13:log + + mr r31, r8 + cmpwi r9, 0x05 + cmpwi cr1, r9, 0x04 + beq- MPCall_120_0x33c + beq- cr1, MPCall_120_0x248 + cmpwi r9, 0x09 + cmpwi cr1, r9, 0x06 + beq- MPCall_120_0x1b4 + beq- cr1, MPCall_120_0x10c + cmpwi r9, 0x0c + cmpwi cr1, r9, 0x08 + beq- MPCall_120_0x58 + beq- cr1, MPCall_120_0x3d8 + b major_0x0b054 + +MPCall_120_0x58 + lis r8, 0x0c + ori r8, r8, 0x01 + cmpw r8, r4 + bne+ major_0x0b054 + cmplwi r5, 0x00 + bne- MPCall_120_0xa0 + lis r16, 0x0c + ori r16, r16, 0x01 + stw r16, 0x0134(r6) + lwz r16, 0x0008(r31) + stw r16, 0x013c(r6) + lwz r16, 0x0004(r31) + stw r16, 0x0144(r6) + lwz r16, 0x000c(r31) + stw r16, 0x014c(r6) + li r16, 0x10 + stw r16, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_120_0xa0 + cmplwi r5, 0x10 + bne- MPCall_120_0xd4 + lwz r16, 0x0010(r31) + stw r16, 0x0134(r6) + lwz r16, 0x0014(r31) + stw r16, 0x013c(r6) + lwz r16, 0x0018(r31) + stw r16, 0x0144(r6) + lwz r16, 0x001c(r31) + stw r16, 0x014c(r6) + li r16, 0x10 + stw r16, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_120_0xd4 + cmplwi r5, 0x20 + bne- MPCall_120_0xf8 + lwz r16, 0x0020(r31) + stw r16, 0x0134(r6) + lwz r16, 0x0024(r31) + stw r16, 0x013c(r6) + li r16, 0x08 + stw r16, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_120_0xf8 + cmpwi r5, 0x28 + bne+ major_0x0b054 + li r16, 0x00 + stw r16, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_120_0x10c + lis r8, 0x06 + ori r8, r8, 0x01 + cmpw r8, r4 + bne+ major_0x0b054 + cmplwi r5, 0x00 + bne- MPCall_120_0x154 + lis r16, 0x06 + ori r16, r16, 0x01 + stw r16, 0x0134(r6) + lwz r16, 0x0010(r31) + stw r16, 0x013c(r6) + lwz r16, 0x0004(r31) + stw r16, 0x0144(r6) + lwz r16, 0x0020(r31) + stw r16, 0x014c(r6) + li r16, 0x10 + stw r16, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_120_0x154 + cmplwi r5, 0x10 + bne- MPCall_120_0x1a0 + addi r17, r31, 0x00 + lwz r18, 0x0008(r31) + li r16, 0x00 + cmpw r17, r18 + beq- MPCall_120_0x174 + lwz r16, -0x0008(r18) + +MPCall_120_0x174 + stw r16, 0x0134(r6) + lwz r16, 0x0018(r31) + cmpwi r16, 0x00 + beq- MPCall_120_0x188 + lwz r16, 0x0000(r16) + +MPCall_120_0x188 + stw r16, 0x013c(r6) + lwz r16, 0x0014(r31) + stw r16, 0x0144(r6) + li r16, 0x0c + stw r16, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_120_0x1a0 + cmpwi r5, 0x1c + bne+ major_0x0b054 + li r16, 0x00 + stw r16, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_120_0x1b4 + lis r8, 0x09 + ori r8, r8, 0x01 + cmpw r8, r4 + bne+ major_0x0b054 + cmplwi r5, 0x00 + bne- MPCall_120_0x1fc + lis r16, 0x09 + ori r16, r16, 0x01 + stw r16, 0x0134(r6) + lwz r16, 0x0014(r31) + stw r16, 0x013c(r6) + lwz r16, 0x0004(r31) + stw r16, 0x0144(r6) + lwz r16, 0x001c(r31) + stw r16, 0x014c(r6) + li r16, 0x10 + stw r16, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_120_0x1fc + cmplwi r5, 0x10 + bne- MPCall_120_0x234 + addi r17, r31, 0x00 + lwz r18, 0x0008(r31) + li r16, 0x00 + cmpw r17, r18 + beq- MPCall_120_0x21c + lwz r16, -0x0008(r18) + +MPCall_120_0x21c + stw r16, 0x0134(r6) + lwz r16, 0x0010(r31) + stw r16, 0x013c(r6) + li r16, 0x08 + stw r16, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_120_0x234 + cmpwi r5, 0x18 + bne+ major_0x0b054 + li r16, 0x00 + stw r16, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_120_0x248 + lis r8, 0x04 + ori r8, r8, 0x01 + cmpw r8, r4 + bne+ major_0x0b054 + cmplwi r5, 0x00 + bne- MPCall_120_0x290 + lis r16, 0x04 + ori r16, r16, 0x01 + stw r16, 0x0134(r6) + lwz r16, 0x0020(r31) + stw r16, 0x013c(r6) + lwz r16, 0x0004(r31) + stw r16, 0x0144(r6) + lwz r16, 0x002c(r31) + stw r16, 0x014c(r6) + li r16, 0x10 + stw r16, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_120_0x290 + cmplwi r5, 0x10 + bne- MPCall_120_0x2ec + addi r17, r31, 0x00 + lwz r18, 0x0008(r31) + li r16, 0x00 + cmpw r17, r18 + beq- MPCall_120_0x2b0 + lwz r16, -0x0008(r18) + +MPCall_120_0x2b0 + stw r16, 0x0134(r6) + lwz r16, 0x0030(r31) + stw r16, 0x013c(r6) + lwz r16, 0x0024(r31) + stw r16, 0x0144(r6) + lwz r18, 0x0018(r31) + addi r17, r31, 0x10 + li r16, 0x00 + cmpw r17, r18 + beq- MPCall_120_0x2dc + lwz r16, 0x0010(r18) + +MPCall_120_0x2dc + stw r16, 0x014c(r6) + li r16, 0x10 + stw r16, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_120_0x2ec + cmplwi r5, 0x20 + bne- MPCall_120_0x328 + lwz r18, 0x0018(r31) + addi r17, r31, 0x10 + li r16, 0x00 + cmpw r17, r18 + li r17, 0x00 + beq- MPCall_120_0x314 + lwz r16, 0x0014(r18) + lwz r17, 0x0018(r18) + +MPCall_120_0x314 + stw r16, 0x0134(r6) + stw r17, 0x013c(r6) + li r16, 0x08 + stw r16, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_120_0x328 + cmpwi r5, 0x28 + bne+ major_0x0b054 + li r16, 0x00 + stw r16, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_120_0x33c + lis r8, 0x05 + ori r8, r8, 0x01 + cmpw r8, r4 + bne+ major_0x0b054 + cmplwi r5, 0x00 + bne- MPCall_120_0x384 + lis r16, 0x05 + ori r16, r16, 0x01 + stw r16, 0x0134(r6) + lwz r16, 0x0018(r31) + stw r16, 0x013c(r6) + lwz r16, 0x0004(r31) + stw r16, 0x0144(r6) + lwz r16, 0x001c(r31) + stw r16, 0x014c(r6) + li r16, 0x10 + stw r16, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_120_0x384 + cmplwi r5, 0x10 + bne- MPCall_120_0x3c4 + addi r17, r31, 0x00 + lwz r18, 0x0008(r31) + li r16, 0x00 + cmpw r17, r18 + beq- MPCall_120_0x3a4 + lwz r16, -0x0008(r18) + +MPCall_120_0x3a4 + stw r16, 0x0134(r6) + lwz r16, 0x0014(r31) + stw r16, 0x013c(r6) + lwz r16, 0x0010(r31) + stw r16, 0x0144(r6) + li r16, 0x0c + stw r16, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_120_0x3c4 + cmpwi r5, 0x1c + bne+ major_0x0b054 + li r16, 0x00 + stw r16, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_120_0x3d8 + lis r8, 0x08 + ori r8, r8, 0x01 + cmpw r8, r4 + bne+ major_0x0b054 + cmplwi r5, 0x00 + bne- MPCall_120_0x420 + lis r16, 0x08 + ori r16, r16, 0x01 + stw r16, 0x0134(r6) + lwz r16, 0x0074(r31) + stw r16, 0x013c(r6) + lwz r16, 0x0070(r31) + stw r16, 0x0144(r6) + lwz r16, 0x000c(r31) + stw r16, 0x014c(r6) + li r16, 0x10 + stw r16, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_120_0x420 + cmplwi r5, 0x10 + bne- MPCall_120_0x454 + lwz r16, 0x0030(r31) + stw r16, 0x0134(r6) + lwz r16, 0x0034(r31) + stw r16, 0x013c(r6) + lwz r16, 0x0038(r31) + stw r16, 0x0144(r6) + lwz r16, 0x003c(r31) + stw r16, 0x014c(r6) + li r16, 0x10 + stw r16, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_120_0x454 + cmplwi r5, 0x20 + bne- MPCall_120_0x488 + lwz r16, 0x0040(r31) + stw r16, 0x0134(r6) + lwz r16, 0x0044(r31) + stw r16, 0x013c(r6) + lwz r16, 0x0048(r31) + stw r16, 0x0144(r6) + lwz r16, 0x004c(r31) + stw r16, 0x014c(r6) + li r16, 0x10 + stw r16, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_120_0x488 + cmplwi r5, 0x30 + bne- MPCall_120_0x4bc + lwz r16, 0x0050(r31) + stw r16, 0x0134(r6) + lwz r16, 0x0054(r31) + stw r16, 0x013c(r6) + lwz r16, 0x0058(r31) + stw r16, 0x0144(r6) + lwz r16, 0x005c(r31) + stw r16, 0x014c(r6) + li r16, 0x10 + stw r16, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_120_0x4bc + cmplwi r5, 0x40 + bne- MPCall_120_0x4f0 + lwz r16, 0x0060(r31) + stw r16, 0x0134(r6) + lwz r16, 0x0064(r31) + stw r16, 0x013c(r6) + lwz r16, 0x0068(r31) + stw r16, 0x0144(r6) + lwz r16, 0x006c(r31) + stw r16, 0x014c(r6) + li r16, 0x10 + stw r16, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_120_0x4f0 + cmpwi r5, 0x50 + bne+ major_0x0b054 + li r16, 0x00 + stw r16, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall diff --git a/NanoKernel/NKRTASCalls.s b/NanoKernel/NKRTASCalls.s new file mode 100644 index 0000000..8cca070 --- /dev/null +++ b/NanoKernel/NKRTASCalls.s @@ -0,0 +1,190 @@ +Local_Panic set * + b panic + + + +; kcRTASDispatch + +; Only major that hits the RTAS globals. +; RTAS requires some specific context stuff. + +; Xrefs: +; "sup" + +; > r1 = kdp +; > r6 = some kind of place +; > r7 = some kind of flags + + align 5 + +kcRTASDispatch ; OUTSIDE REFERER + lwz r8, 0x0908(r1) + cmpwi r8, 0x00 + bne- rtas_is_available + li r3, -0x01 + b skeleton_key + +rtas_is_available + + _Lock PSA.RTASLock, scratch1=r8, scratch2=r9 + + mtcrf 0x3f, r7 + lwz r9, 0x0658(r1) + lwz r8, -0x000c(r1) + stw r7, 0x0000(r6) + stw r8, 0x0004(r6) + bns- cr6, kcRTASDispatch_0x5c + stw r17, 0x0024(r6) + stw r20, 0x0028(r6) + stw r21, 0x002c(r6) + stw r19, 0x0034(r6) + stw r18, 0x003c(r6) + lmw r14, 0x0038(r1) + +kcRTASDispatch_0x5c + mfxer r8 + stw r13, 0x00dc(r6) + stw r8, 0x00d4(r6) + stw r12, 0x00ec(r6) + mfctr r8 + stw r10, 0x00fc(r6) + stw r8, 0x00f4(r6) + ble- cr3, kcRTASDispatch_0x8c + lwz r8, 0x00c4(r9) + mfspr r12, mq + mtspr mq, r8 + stw r12, 0x00c4(r6) + +kcRTASDispatch_0x8c + lwz r8, 0x0004(r1) + stw r8, 0x010c(r6) + stw r2, 0x0114(r6) + stw r3, 0x011c(r6) + stw r4, 0x0124(r6) + lwz r8, 0x0018(r1) + stw r5, 0x012c(r6) + stw r8, 0x0134(r6) + andi. r8, r11, 0x2000 + stw r14, 0x0174(r6) + stw r15, 0x017c(r6) + stw r16, 0x0184(r6) + stw r17, 0x018c(r6) + stw r18, 0x0194(r6) + stw r19, 0x019c(r6) + stw r20, 0x01a4(r6) + stw r21, 0x01ac(r6) + stw r22, 0x01b4(r6) + stw r23, 0x01bc(r6) + stw r24, 0x01c4(r6) + stw r25, 0x01cc(r6) + stw r26, 0x01d4(r6) + stw r27, 0x01dc(r6) + stw r28, 0x01e4(r6) + stw r29, 0x01ec(r6) + stw r30, 0x01f4(r6) + stw r31, 0x01fc(r6) + bnel+ major_0x03e18_0xb4 + stw r11, 0x00a4(r6) + mr r27, r3 + addi r29, r1, 800 + bl PagingFunc3 + beql+ Local_Panic + rlwimi r3, r31, 0, 0, 19 + lhz r8, 0x0004(r3) + cmpwi r8, 0x00 + beq- kcRTASDispatch_0x14c + slwi r8, r8, 2 + lwzx r27, r8, r3 + addi r29, r1, 800 + bl PagingFunc3 + beql+ Local_Panic + lwzx r9, r8, r3 + rlwimi r9, r31, 0, 0, 19 + stwx r9, r8, r3 + li r9, 0x00 + sth r9, 0x0004(r3) + dcbf r8, r3 + +kcRTASDispatch_0x14c + li r9, 0x04 + dcbf r9, r3 + sync + isync + lwz r4, 0x090c(r1) + mfmsr r8 + andi. r8, r8, 0x10cf + mtmsr r8 + isync + mr r28, r3 + lwz r9, 0x0908(r1) + bl rtas_make_actual_call + mfsprg r1, 0 + lwz r6, -0x0014(r1) + clrlwi r29, r28, 0x14 + subfic r29, r29, 0x1000 + lhz r27, 0x0f4a(r1) + +kcRTASDispatch_0x190 + subf. r29, r27, r29 + dcbf r29, r28 + sync + icbi r29, r28 + bge+ kcRTASDispatch_0x190 + sync + isync + lwz r8, 0x0000(r6) + lwz r11, 0x00a4(r6) + mr r7, r8 + andi. r8, r11, 0x900 + lwz r8, 0x0004(r6) + lwz r13, 0x00dc(r6) + stw r8, -0x000c(r1) + lwz r8, 0x00d4(r6) + lwz r12, 0x00ec(r6) + mtxer r8 + lwz r8, 0x00f4(r6) + lwz r10, 0x00fc(r6) + mtctr r8 + bnel+ major_0x03e18_0x8 + lwz r8, 0x010c(r6) + stw r8, 0x0004(r1) + lwz r2, 0x0114(r6) + lwz r3, 0x011c(r6) + lwz r4, 0x0124(r6) + lwz r8, 0x0134(r6) + lwz r5, 0x012c(r6) + stw r8, 0x0018(r1) + lwz r14, 0x0174(r6) + lwz r15, 0x017c(r6) + lwz r16, 0x0184(r6) + lwz r17, 0x018c(r6) + lwz r18, 0x0194(r6) + lwz r19, 0x019c(r6) + lwz r20, 0x01a4(r6) + lwz r21, 0x01ac(r6) + lwz r22, 0x01b4(r6) + lwz r23, 0x01bc(r6) + lwz r24, 0x01c4(r6) + lwz r25, 0x01cc(r6) + lwz r26, 0x01d4(r6) + lwz r27, 0x01dc(r6) + lwz r28, 0x01e4(r6) + lwz r29, 0x01ec(r6) + lwz r30, 0x01f4(r6) + lwz r31, 0x01fc(r6) + sync + lwz r8, -0x0b10(r1) + cmpwi cr1, r8, 0x00 + li r8, 0x00 + bne+ cr1, kcRTASDispatch_0x268 + mflr r8 + bl panic + +kcRTASDispatch_0x268 + stw r8, -0x0b10(r1) + li r3, 0x00 + b skeleton_key + +rtas_make_actual_call + mtctr r9 + bctr diff --git a/NanoKernel/NKReplacementInit.s b/NanoKernel/NKReplacementInit.s new file mode 100644 index 0000000..2d173be --- /dev/null +++ b/NanoKernel/NKReplacementInit.s @@ -0,0 +1,480 @@ +; sprg0 = old KDP/EWA/r1 ptr +; r3 = PA_NanoKernelCode +; r4 = physical base of our global area +; r5 = NoIdeaR23 +; r6 = PA_EDP or zero? +; r7 = probably ROMHeader.ROMRelease ('rom vers', e.g. 0x10B5 is 1.0§5) + + +InitReplacement + + crset cr5_eq + + + li r0, 0 + + + +; Position and initialise the kernel globals, IRP to KDP inclusive. +; (subset of builtin kernel) + + ; Zero from IRP (r4) to KDP (r4 + 10 pages) + + lisori r12, kKDPfromIRP + mr r13, r4 +@wipeloop + subic. r12, r12, 4 + stwx r0, r13, r12 + bgt+ @wipeloop + + + ; Copy the old KDP to r4 + 10 pages. + ; (r1 becomes our main ptr and r4 is discarded) + + mfsprg r11, 0 + lisori r1, kKDPfromIRP + add r1, r1, r4 + + li r12, 4096 +@kdp_copyloop + subic. r12, r12, 4 + lwzx r10, r11, r12 + stwx r10, r1, r12 + bgt+ @kdp_copyloop + + + ; IRP goes at the base of the area we were given. + ; Fill with repeating pattern and point EWA at it. + + lisori r12, -kKDPfromIRP + add r12, r12, r1 + stw r12, EWA.PA_IRP(r1) + bl InitIRP ; clobbers r10 and r12 + + + +; Play with some of the other values we were given + + ; Leave ROMRelease in r23. + + mr r23, r7 + + ; If no EDP (Emulator Data Page) pointer was provided, + ; then put the EDP above our new KDP. + + cmpwi r6, 0 + stw r11, KDP.OldKDP(r1) + stw r9, 0x05a4(r1) + + + ; discarded + + bne- @emulatordata_ptr_provided + addi r6, r1, 0x1000 +@emulatordata_ptr_provided + + + + ; Save a few bits + + stw r6, 0x05a8(r1) + stw r3, KDP.PA_NanoKernelCode(r1) + stw r5, PSA.NoIdeaR23(r1) + stw r1, EWA.PA_KDP(r1) + + addi r12, r1, -0x340 ; get the base of the main CPU struct + li r10, -1 + stw r10, CPU.ID(r12) + + lwz r3, KDP.PA_ConfigInfo(r1) + + bl LookupInterruptHandler + stw r7, KDP.PA_InterruptHandler(r1) + + + +; Clearly changed our mind about where we might be. + + bl @x +@x mflr r12 + subi r12, r12, @x - NKTop + + stw r12, KDP.PA_NanoKernelCode(r1) + + +; FDP + + llabel r10, FDP + add r12, r10, r12 + stw r12, KDP.PA_FDP(r1) + + +; Do something terrible with the CPU features + + lwz r12, -0x0010(r1) + li r10, 0x00 + rlwimi r10, r12, 0, 12, 15 + rlwimi r10, r12, 0, 28, 30 + stw r10, -0x0968(r1) + + +; Cook up a MSR: +; MSR_EE = 1 +; MSR_PR = 1 +; MSR_FP = 0 +; MSR_ME = 0 +; MSR_FE0 = 0 +; MSR_SE = 0 +; MSR_BE = 0 +; MSR_FE1 = 0 +; MSR_IP = preserved +; MSR_IR = 1 +; MSR_DR = 1 +; MSR_RI = 0 +; MSR_LE = 0 + + mfmsr r12 + andi. r12, r12, 0x0040 + ori r12, r12, 0xd032 + stw r12, PSA.UserModeMSR(r1) + + + +; Set SPRG0 (for this CPU at least) + + mtsprg 0, r1 + + +; r11 still contains the OLD EWA ptr (which is also KDP/PSA ptr?) + + lhz r12, KDP.InfoRecord + InfoRecord.NKNanoKernelInfoVer(r11) + cmpwi r12, 0x0101 + + bgt- @replaces_later_than_0101 + + ; + lwz r12, KDP.PA_ECB_Old(r1) + stw r12, EWA.PA_ContextBlock(r1) + + lwz r12, 0x660(r1) + oris r12, r12, 0x20 + stw r12, EWA.Flags(r1) + + lwz r12, 0x0664(r1) + stw r12, -0x000c(r1) ; boy, better figure out what this is + + b @endif +@replaces_later_than_0101 + + ; Obviously cannot replace a v2 NanoKernel like myself + cmpwi r12, 0x0200 + bge- CancelReplacement + + lwz r12, EWA.PA_ContextBlock(r11) + stw r12, EWA.PA_ContextBlock(r1) + + lwz r12, EWA.Flags(r11) + oris r12, r12, 0x20 + stw r12, EWA.Flags(r1) + + lwz r12, -0x000c(r11) + stw r12, -0x000c(r1) + +@endif + + + + lwz r12, 0x0340(r11) + lwz r10, 0x05b4(r11) + cmpw r12, r10 + + beq- replace_old_kernel_0x198 + stw r12, 0x05b4(r1) + stw r0, 0x06b4(r1) + lwz r10, 0x05b0(r11) + stw r10, 0x06c0(r1) + lwz r10, 0x05b4(r11) + stw r10, 0x06c4(r1) + lwz r10, 0x05b8(r11) + stw r10, 0x06c8(r1) + lwz r10, 0x05bc(r11) + stw r10, 0x06cc(r1) + stw r0, 0x06d0(r1) + stw r0, 0x06d4(r1) + stw r0, 0x06d8(r1) + stw r0, 0x06dc(r1) + stw r0, 0x06e0(r1) + stw r0, 0x06e4(r1) + stw r0, 0x06e8(r1) + stw r0, 0x06ec(r1) + stw r0, 0x06f0(r1) + stw r0, 0x06f4(r1) + stw r0, 0x06f8(r1) + stw r0, 0x06fc(r1) +replace_old_kernel_0x198 + + + +; Adjust a few KDP pointers to point into the new KDP + + lwz r12, KDP.PA_PageMapStart(r1) + subf r12, r11, r12 + add r12, r12, r1 + stw r12, KDP.PA_PageMapStart(r1) + + lwz r12, KDP.PA_PageMapEnd(r1) + subf r12, r11, r12 + add r12, r12, r1 + stw r12, KDP.PA_PageMapEnd(r1) + + lwz r12, 0x05e8(r1) + subf r12, r11, r12 + add r12, r12, r1 + stw r12, 0x05e8(r1) + + + +; Wipe KDP's NKInfo and ProcessorInfo + + li r12, 0x200 + addi r10, r1, KDP.NanoKernelInfo + +@wipeloop + subic. r12, r12, 4 + stwx r0, r10, r12 + bgt+ @wipeloop + + + + + ; r9 = physical base of kernel + li r12, 0 + addi r10, r1, KDP.InfoRecord + + bl MoveRecord ; (NanoKernelCode, NewKDPInfoRecord, OldKDP, 0) + + stw r10, KDP.InfoRecord + InfoRecord.InfoRecordPtr(r1) + stw r0, KDP.InfoRecord + InfoRecord.Zero(r1) + + + + lhz r12, KDP.InfoRecord + InfoRecord.NKProcessorStateLen(r1) + addi r10, r1, PSA.ProcessorState + lwz r9, KDP.InfoRecord + InfoRecord.NKProcessorStatePtr(r1) + + bl MoveRecord ; (OldProcessorState, NewPSAProcessorState, OldKDP, ProcessorStateLen) + + stw r10, KDP.InfoRecord + InfoRecord.NKProcessorStatePtr(r1) + + + + lhz r12, KDP.InfoRecord + InfoRecord.NKHWInfoLen(r1) + lwz r10, EWA.PA_IRP(r1) + addi r10, r10, IRP.HWInfo + lwz r9, KDP.InfoRecord + InfoRecord.NKHWInfoPtr(r1) + + bl MoveRecord ; (OldHWInfo, NewIRPHWInfo, OldKDP, HWInfoLen) + + stw r10, KDP.InfoRecord + InfoRecord.NKHWInfoPtr(r1) + + + + lhz r12, KDP.InfoRecord + InfoRecord.NKProcessorInfoLen(r1) + addi r10, r1, KDP.ProcessorInfo + lwz r9, KDP.InfoRecord + InfoRecord.NKProcessorInfoPtr(r1) + + bl MoveRecord ; (OldProcessorInfo, NewKDPProcessorInfo, OldKDP, ProcessorInfoLen) + + stw r10, KDP.InfoRecord + InfoRecord.NKProcessorInfoPtr(r1) + stw r10, KDP.InfoRecord + InfoRecord.NKProcessorInfoPtr2(r1) + + + + lhz r10, KDP.InfoRecord + InfoRecord.NKProcessorInfoVer(r1) + cmplwi r10, 0x0112 + bge- @ProcessorInfo_version_already_current + + li r12, 160 + li r10, 0x0112 + sth r12, KDP.InfoRecord + InfoRecord.NKProcessorInfoLen(r1) + sth r12, KDP.InfoRecord + InfoRecord.NKProcessorInfoLen2(r1) + sth r10, KDP.InfoRecord + InfoRecord.NKProcessorInfoVer(r1) + sth r10, KDP.InfoRecord + InfoRecord.NKProcessorInfoVer2(r1) +@ProcessorInfo_version_already_current + + + + lhz r12, KDP.InfoRecord + InfoRecord.NKDiagInfoLen(r1) + addi r10, r1, PSA.DiagInfo + lwz r9, KDP.InfoRecord + InfoRecord.NKDiagInfoPtr(r1) + + bl MoveRecord ; (OldDiagInfo, NewPSADiagInfo, OldKDP, DiagInfoLen) + + stw r10, KDP.InfoRecord + InfoRecord.NKDiagInfoPtr(r1) + + + + lhz r12, KDP.InfoRecord + InfoRecord.NKSystemInfoLen(r1) + lwz r10, EWA.PA_IRP(r1) + addi r10, r10, IRP.SystemInfo + lwz r9, KDP.InfoRecord + InfoRecord.NKSystemInfoPtr(r1) + + bl MoveRecord ; (OldSystemInfo, NewIRPSystemInfo, OldKDP, SystemInfoLen) + + stw r10, KDP.InfoRecord + InfoRecord.NKSystemInfoPtr(r1) + + + + lhz r12, KDP.InfoRecord + InfoRecord.NKNanoKernelInfoLen(r1) + addi r10, r1, KDP.NanoKernelInfo + lwz r9, KDP.InfoRecord + InfoRecord.NKNanoKernelInfoPtr(r1) + + bl MoveRecord ; (OldNanoKernelInfo, NewKDPNanoKernelInfo, OldKDP, NanoKernelInfoLen) + + stw r10, KDP.InfoRecord + InfoRecord.NKNanoKernelInfoPtr(r1) + + + + li r12, 0x160 + sth r12, KDP.InfoRecord + InfoRecord.NKNanoKernelInfoLen(r1) + + + li r12, kNanoKernelVersion + sth r12, KDP.InfoRecord + InfoRecord.NKNanoKernelInfoVer(r1) + + + lwz r8, KDP.ProcessorInfo + NKProcessorInfo.DecClockRateHz(r1) + stw r8, PSA.DecClockRateHzCopy(r1) + + + +; Play with ConfigFlags + + lwz r8, KDP.NanoKernelInfo + NKNanoKernelInfo.ConfigFlags(r1) + + _bset r8, r8, 31 ; always set bit 31 + + if &TYPE('NKShowLog') != 'UNDEFINED' + _bset r8, r8, 28 ; see if someone can test this + endif + + cmplwi r23, 0x27f3 ; set bit 27 on ROM 2.7f3 or later + blt- @oldrom ; means later than PDM and Cordyceps + _bset r8, r8, 27 +@oldrom + + stw r8, KDP.NanoKernelInfo + NKNanoKernelInfo.ConfigFlags(r1) + + + +; Say hello. + + bl InitScreenConsole + + _log 'Hello from the replacement multitasking NanoKernel. Version: ' + + mr r8, r12 + bl printh + + + _log '^n Old KDP: ' + + mr r8, r11 + bl printw + + + _log ' new KDP: ' + + mr r8, r1 + bl printw + + + _log ' new irp: ' + + lwz r8, EWA.PA_IRP(r1) + mr r8, r8 + bl printw + + + _log 'ROM vers: ' + + mr r8, r23 + bl printh + + _log '^n' + + + +; Jump back into the common code path of Init.s + + ; The Emulator ContextBlock is expected in r6. + lwz r6, KDP.PA_ECB(r1) + + b InitHighLevel + + + +; MoveRecord + +; Xrefs: +; replace_old_kernel +; r9 = base of kernel??? + +; Seems to be code to relocate some old structures. + +MoveRecord ; OUTSIDE REFERER + + ; Check whether the old structure is in KDP + ; + lwz r22, KDP.PA_ConfigInfo(r1) + lwz r22, NKConfigurationInfo.LA_InfoRecord(r22) + + subf r9, r22, r9 ; r9 = offset of old address in irp + cmplwi r9, 0x1000 + bge- @kdp + + add r21, r9, r11 ; r21 = the old address if it had been in KDP instead? + + +@0x18 + + ; r9 = offset of old structure in old parent page + ; r10 = destination + ; r12 = length + + + ; +@loop + subic. r12, r12, 4 + blt- @exit_loop + lwzx r9, r21, r12 + stwx r9, r10, r12 + bgt+ @loop +@exit_loop + + lwz r22, KDP.PA_ConfigInfo(r1) + lwz r22, NKConfigurationInfo.LA_KernelData(r22) + + subf r10, r1, r10 + lisori r21, -9 * 4096 + cmpw r10, r21 ; if dest is nearer than 9 pages below kdp... + blt- @0x50 + add r10, r10, r22 + blr +@0x50 + + lwz r22, KDP.PA_ConfigInfo(r1) + lwz r22, NKConfigurationInfo.LA_InfoRecord(r22) + lwz r21, EWA.PA_IRP(r1) + add r10, r10, r1 + subf r10, r21, r10 + add r10, r10, r22 + blr + +@kdp + add r9, r9, r22 + lwz r22, KDP.PA_ConfigInfo(r1) + lwz r22, NKConfigurationInfo.LA_KernelData(r22) + subf r9, r22, r9 ; r9 now equals an offset from old_kdp + add r21, r9, r11 ; r21 = address in new_kdp + b @0x18 \ No newline at end of file diff --git a/NanoKernel/NKScheduler.s b/NanoKernel/NKScheduler.s new file mode 100644 index 0000000..4af8f19 --- /dev/null +++ b/NanoKernel/NKScheduler.s @@ -0,0 +1,2192 @@ +Local_Panic set * + b panic + + + +; Called by setup only +; Each queue has a 64-bit time value (measured in implementation-dependent ticks). +; Critical queue has ~1ms, other queues increase this by 8x. + +InitRDYQs + + li r16, 0 + stw r16, KDP.NanoKernelInfo + NKNanoKernelInfo.TaskCount(r1) + + + ; Get a time doubleword approximating 1ms (for critical priority) + mflr r20 + + li r8, -1042 ; negative args are in usec + bl TimebaseTicksPerPeriod + mr r16, r8 ; hi + mr r17, r9 ; lo + + mtlr r20 + + + ; Zero out the KDP priority flags (a full value would be 0xf0000000) + li r23, 0 + stw r23, PSA.PriorityFlags(r1) + addi r9, r1, PSA.ReadyQueues + + + +; Populate one RDYQ for each of the four task priorities + +@loop + lisori r8, ReadyQueue.kSignature + stw r8, LLL.Signature(r9) + + stw r9, LLL.Next(r9) + stw r9, LLL.Prev(r9) + + + ; Set one word in the structure in the format of KDP PriorityFlags, + ; with the bit SET that corresponds with this queue + lis r8, 0x8000 ; ...0000 + srw r8, r8, r23 + stw r8, LLL.Freeform(r9) + + + ; Zero some shit + li r8, 0 + stw r8, ReadyQueue.Counter(r9) ; incremented by TaskReadyAsNext + stw r8, ReadyQueue.TotalWeight(r9) + + + ; Save the doubleword (1ms, 8ms...) for this priority + stw r16, ReadyQueue.Timecake(r9) + stw r17, ReadyQueue.Timecake + 4(r9) + + + ; Show off a bit + mflr r20 + + _log 'Init ready queue ' + + mr r8, r23 ; the priority (1,2,3,4) + bl printw + + mr r8, r16 ; the Timeslice + bl printw + + mr r8, r17 + bl printw + + _log '^n' + + mtlr r20 + + + ; Multiply Timeslice by 8 for the next iteration + slwi r16, r16, 3 + rlwimi r16, r17, 3, 29, 31 + slwi r17, r17, 3 + + ; Only do four of these + addi r23, r23, 1 + cmpwi r23, 4 + addi r9, r9, 32 ;ReadyQueue.Size + blt+ @loop + + + ; If the low nybble is empty, set ContextBlock.PriorityShifty to 2. + lwz r16, KDP.PA_ECB(r1) + lwz r17, ContextBlock.PriorityShifty(r16) + andi. r9, r17, (1<<4)-1 + li r17, 2 + bnelr- + + stw r17, ContextBlock.PriorityShifty(r16) + blr + + + +; ...to (ECB *)r6 +; (and also copy SPRG0 to r8) + +Save_r14_r31 + li r8, ContextBlock.r16 & -32 + dcbtst r8, r6 + stw r14, ContextBlock.r14(r6) + stw r15, ContextBlock.r15(r6) + +Save_r16_r31 + li r8, ContextBlock.r20 & -32 + stw r16, ContextBlock.r16(r6) + dcbtst r8, r6 + stw r17, ContextBlock.r17(r6) + stw r18, ContextBlock.r18(r6) + stw r19, ContextBlock.r19(r6) + +Save_r20_r31 + li r8, ContextBlock.r24 & -32 + stw r20, ContextBlock.r20(r6) + dcbtst r8, r6 + stw r21, ContextBlock.r21(r6) + stw r22, ContextBlock.r22(r6) + stw r23, ContextBlock.r23(r6) + +Save_r24_r31 + li r8, ContextBlock.r28 & -32 + stw r24, ContextBlock.r24(r6) + dcbtst r8, r6 + stw r25, ContextBlock.r25(r6) + stw r26, ContextBlock.r26(r6) + stw r27, ContextBlock.r27(r6) + stw r28, ContextBlock.r28(r6) + stw r29, ContextBlock.r29(r6) + stw r30, ContextBlock.r30(r6) + stw r31, ContextBlock.r31(r6) + + mfsprg r8, 0 + blr + + + +; ...from (ECB *)r6 + +Restore_r14_r31 + li r31, ContextBlock.r16 & -32 + dcbt r31, r6 + lwz r14, ContextBlock.r14(r6) + lwz r15, ContextBlock.r15(r6) + +Restore_r16_r31 + li r31, ContextBlock.r20 & -32 + lwz r16, ContextBlock.r16(r6) + dcbt r31, r6 + lwz r17, ContextBlock.r17(r6) + lwz r18, ContextBlock.r18(r6) + lwz r19, ContextBlock.r19(r6) + +Restore_r20_r31 + li r31, ContextBlock.r24 & -32 + lwz r20, ContextBlock.r20(r6) + dcbt r31, r6 + lwz r21, ContextBlock.r21(r6) + lwz r22, ContextBlock.r22(r6) + lwz r23, ContextBlock.r23(r6) + +Restore_r24_r31 + li r31, ContextBlock.r28 & -32 + lwz r24, ContextBlock.r24(r6) + dcbt r31, r6 + lwz r25, ContextBlock.r25(r6) + lwz r26, ContextBlock.r26(r6) + lwz r27, ContextBlock.r27(r6) + lwz r28, ContextBlock.r28(r6) + lwz r29, ContextBlock.r29(r6) + lwz r30, ContextBlock.r30(r6) + lwz r31, ContextBlock.r31(r6) + + blr + + + +; ...to (ECB *)r6 +; (but first set the MSR_FP bit in MSR, but *unset* it in r11) + +Save_f0_f31 + mfmsr r8 + rlwinm r11, r11, 0, MSR_FPbit+1, MSR_FPbit-1 + _bset r8, r8, MSR_FPbit + mtmsr r8 + isync + + li r8, 0x220 + stfd f0, 0x0200(r6) + dcbtst r8, r6 + stfd f1, 0x0208(r6) + stfd f2, 0x0210(r6) + stfd f3, 0x0218(r6) + li r8, 0x240 + stfd f4, 0x0220(r6) + dcbtst r8, r6 + stfd f5, 0x0228(r6) + stfd f6, 0x0230(r6) + stfd f7, 0x0238(r6) + li r8, 0x260 + stfd f8, 0x0240(r6) + dcbtst r8, r6 + stfd f9, 0x0248(r6) + stfd f10, 0x0250(r6) + stfd f11, 0x0258(r6) + li r8, 640 + stfd f12, 0x0260(r6) + dcbtst r8, r6 + stfd f13, 0x0268(r6) + stfd f14, 0x0270(r6) + stfd f15, 0x0278(r6) + li r8, 0x2a0 + stfd f16, 0x0280(r6) + dcbtst r8, r6 + stfd f17, 0x0288(r6) + stfd f18, 0x0290(r6) + stfd f19, 0x0298(r6) + li r8, 0x2c0 + stfd f20, 0x02a0(r6) + dcbtst r8, r6 + stfd f21, 0x02a8(r6) + stfd f22, 0x02b0(r6) + stfd f23, 0x02b8(r6) + li r8, 0x2e0 + stfd f24, 0x02c0(r6) + dcbtst r8, r6 + stfd f25, 0x02c8(r6) + stfd f26, 0x02d0(r6) + stfd f27, 0x02d8(r6) + mffs f0 + stfd f28, 0x02e0(r6) + stfd f29, 0x02e8(r6) + stfd f30, 0x02f0(r6) + stfd f31, 0x02f8(r6) + stfd f0, 0x00e0(r6) + blr + + + + +Restore_v0_v31 ; OUTSIDE REFERER + li r8, 0x200 + mfspr r11, vrsave + lvxl v0, r8, r10 + mtcr r11 + mtvscr v0 + lwz r8, -0x0004(r1) + li r9, -0x8e0 + lvx v31, r8, r9 + vor v0, v31, v31 + bge- major_0x13988_0x108 + li r8, 0x00 + lvx v0, r8, r10 + +major_0x13988_0x108 + vor v1, v31, v31 + ble- major_0x13988_0x118 + li r9, 0x10 + lvx v1, r9, r10 + +major_0x13988_0x118 + vor v2, v31, v31 + bne- major_0x13988_0x128 + li r8, 0x20 + lvx v2, r8, r10 + +major_0x13988_0x128 + vor v3, v31, v31 + bns- major_0x13988_0x138 + li r9, 0x30 + lvx v3, r9, r10 + +major_0x13988_0x138 + vor v4, v31, v31 + bge- cr1, major_0x13988_0x148 + li r8, 0x40 + lvx v4, r8, r10 + +major_0x13988_0x148 + vor v5, v31, v31 + ble- cr1, major_0x13988_0x158 + li r9, 0x50 + lvx v5, r9, r10 + +major_0x13988_0x158 + vor v6, v31, v31 + bne- cr1, major_0x13988_0x168 + li r8, 0x60 + lvx v6, r8, r10 + +major_0x13988_0x168 + vor v7, v31, v31 + bns- cr1, major_0x13988_0x178 + li r9, 0x70 + lvx v7, r9, r10 + +major_0x13988_0x178 + vor v8, v31, v31 + bge- cr2, major_0x13988_0x188 + li r8, 0x80 + lvx v8, r8, r10 + +major_0x13988_0x188 + vor v9, v31, v31 + ble- cr2, major_0x13988_0x198 + li r9, 0x90 + lvx v9, r9, r10 + +major_0x13988_0x198 + vor v10, v31, v31 + bne- cr2, major_0x13988_0x1a8 + li r8, 160 + lvx v10, r8, r10 + +major_0x13988_0x1a8 + vor v11, v31, v31 + bns- cr2, major_0x13988_0x1b8 + li r9, 0xb0 + lvx v11, r9, r10 + +major_0x13988_0x1b8 + vor v12, v31, v31 + bge- cr3, major_0x13988_0x1c8 + li r8, 0xc0 + lvx v12, r8, r10 + +major_0x13988_0x1c8 + vor v13, v31, v31 + ble- cr3, major_0x13988_0x1d8 + li r9, 0xd0 + lvx v13, r9, r10 + +major_0x13988_0x1d8 + vor v14, v31, v31 + bne- cr3, major_0x13988_0x1e8 + li r8, 0xe0 + lvx v14, r8, r10 + +major_0x13988_0x1e8 + vor v15, v31, v31 + bns- cr3, major_0x13988_0x1f8 + li r9, 240 + lvx v15, r9, r10 + +major_0x13988_0x1f8 + vor v16, v31, v31 + bge- cr4, major_0x13988_0x208 + li r8, 0x100 + lvx v16, r8, r10 + +major_0x13988_0x208 + vor v17, v31, v31 + ble- cr4, major_0x13988_0x218 + li r9, 0x110 + lvx v17, r9, r10 + +major_0x13988_0x218 + vor v18, v31, v31 + bne- cr4, major_0x13988_0x228 + li r8, 0x120 + lvx v18, r8, r10 + +major_0x13988_0x228 + vor v19, v31, v31 + bns- cr4, major_0x13988_0x238 + li r9, 0x130 + lvx v19, r9, r10 + +major_0x13988_0x238 + vor v20, v31, v31 + bge- cr5, major_0x13988_0x248 + li r8, 320 + lvx v20, r8, r10 + +major_0x13988_0x248 + vor v21, v31, v31 + ble- cr5, major_0x13988_0x258 + li r9, 0x150 + lvx v21, r9, r10 + +major_0x13988_0x258 + vor v22, v31, v31 + bne- cr5, major_0x13988_0x268 + li r8, 0x160 + lvx v22, r8, r10 + +major_0x13988_0x268 + vor v23, v31, v31 + bns- cr5, major_0x13988_0x278 + li r9, 0x170 + lvx v23, r9, r10 + +major_0x13988_0x278 + vor v24, v31, v31 + bge- cr6, major_0x13988_0x288 + li r8, 0x180 + lvx v24, r8, r10 + +major_0x13988_0x288 + vor v25, v31, v31 + ble- cr6, major_0x13988_0x298 + li r9, 400 + lvx v25, r9, r10 + +major_0x13988_0x298 + vor v26, v31, v31 + bne- cr6, major_0x13988_0x2a8 + li r8, 0x1a0 + lvx v26, r8, r10 + +major_0x13988_0x2a8 + vor v27, v31, v31 + bns- cr6, major_0x13988_0x2b8 + li r9, 0x1b0 + lvx v27, r9, r10 + +major_0x13988_0x2b8 + vor v28, v31, v31 + bge- cr7, major_0x13988_0x2c8 + li r8, 0x1c0 + lvx v28, r8, r10 + +major_0x13988_0x2c8 + vor v29, v31, v31 + ble- cr7, major_0x13988_0x2d8 + li r9, 0x1d0 + lvx v29, r9, r10 + +major_0x13988_0x2d8 + vor v30, v31, v31 + bne- cr7, major_0x13988_0x2e8 + li r8, 480 + lvx v30, r8, r10 + +major_0x13988_0x2e8 + vor v31, v31, v31 + bns- cr7, major_0x13988_0x2f8 + li r9, 0x1f0 + lvx v31, r9, r10 + +major_0x13988_0x2f8 + blr + + + +; Save_v0_v31 + +; Xrefs: +; major_0x02980 +; MPCall_47 +; major_0x14548 +; MPCall_103 + + align 4 ; ???? + +Save_v0_v31 ; OUTSIDE REFERER + mfspr r5, vrsave + lwz r2, 0x00d8(r6) + cmplwi r2, 0x00 + beqlr- + andis. r3, r11, 0x200 + stw r5, 0x0210(r2) + beqlr- + mfmsr r3 + rlwinm r11, r11, 0, 7, 5 + oris r3, r3, 0x200 + mtmsr r3 + isync + li r3, 0x00 + li r4, 0x10 + mtcr r5 + stvx v0, r3, r2 + stvxl v1, r4, r2 + mfvscr v0 + li r3, 0x200 + stvx v0, r3, r2 + bne- Save_v0_v31_0x5c + li r3, 0x20 + stvx v2, r3, r2 + +Save_v0_v31_0x5c + bns- Save_v0_v31_0x68 + li r4, 0x30 + stvx v3, r4, r2 + +Save_v0_v31_0x68 + bge- cr1, Save_v0_v31_0x74 + li r3, 0x40 + stvx v4, r3, r2 + +Save_v0_v31_0x74 + ble- cr1, Save_v0_v31_0x80 + li r4, 0x50 + stvx v5, r4, r2 + +Save_v0_v31_0x80 + bne- cr1, Save_v0_v31_0x8c + li r3, 0x60 + stvx v6, r3, r2 + +Save_v0_v31_0x8c + bns- cr1, Save_v0_v31_0x98 + li r4, 0x70 + stvx v7, r4, r2 + +Save_v0_v31_0x98 + bge- cr2, Save_v0_v31_0xa4 + li r3, 0x80 + stvx v8, r3, r2 + +Save_v0_v31_0xa4 + ble- cr2, Save_v0_v31_0xb0 + li r4, 0x90 + stvx v9, r4, r2 + +Save_v0_v31_0xb0 + bne- cr2, Save_v0_v31_0xbc + li r3, 160 + stvx v10, r3, r2 + +Save_v0_v31_0xbc + bns- cr2, Save_v0_v31_0xc8 + li r4, 0xb0 + stvx v11, r4, r2 + +Save_v0_v31_0xc8 + bge- cr3, Save_v0_v31_0xd4 + li r3, 0xc0 + stvx v12, r3, r2 + +Save_v0_v31_0xd4 + ble- cr3, Save_v0_v31_0xe0 + li r4, 0xd0 + stvx v13, r4, r2 + +Save_v0_v31_0xe0 + bne- cr3, Save_v0_v31_0xec + li r3, 0xe0 + stvx v14, r3, r2 + +Save_v0_v31_0xec + bns- cr3, Save_v0_v31_0xf8 + li r4, 240 + stvx v15, r4, r2 + +Save_v0_v31_0xf8 + bge- cr4, Save_v0_v31_0x104 + li r3, 0x100 + stvx v16, r3, r2 + +Save_v0_v31_0x104 + ble- cr4, Save_v0_v31_0x110 + li r4, 0x110 + stvx v17, r4, r2 + +Save_v0_v31_0x110 + bne- cr4, Save_v0_v31_0x11c + li r3, 0x120 + stvx v18, r3, r2 + +Save_v0_v31_0x11c + bns- cr4, Save_v0_v31_0x128 + li r4, 0x130 + stvx v19, r4, r2 + +Save_v0_v31_0x128 + bge- cr5, Save_v0_v31_0x134 + li r3, 320 + stvx v20, r3, r2 + +Save_v0_v31_0x134 + ble- cr5, Save_v0_v31_0x140 + li r4, 0x150 + stvx v21, r4, r2 + +Save_v0_v31_0x140 + bne- cr5, Save_v0_v31_0x14c + li r3, 0x160 + stvx v22, r3, r2 + +Save_v0_v31_0x14c + bns- cr5, Save_v0_v31_0x158 + li r4, 0x170 + stvx v23, r4, r2 + +Save_v0_v31_0x158 + bge- cr6, Save_v0_v31_0x164 + li r3, 0x180 + stvx v24, r3, r2 + +Save_v0_v31_0x164 + ble- cr6, Save_v0_v31_0x170 + li r4, 400 + stvx v25, r4, r2 + +Save_v0_v31_0x170 + bne- cr6, Save_v0_v31_0x17c + li r3, 0x1a0 + stvx v26, r3, r2 + +Save_v0_v31_0x17c + bns- cr6, Save_v0_v31_0x188 + li r4, 0x1b0 + stvx v27, r4, r2 + +Save_v0_v31_0x188 + bge- cr7, Save_v0_v31_0x194 + li r3, 0x1c0 + stvx v28, r3, r2 + +Save_v0_v31_0x194 + ble- cr7, Save_v0_v31_0x1a0 + li r4, 0x1d0 + stvx v29, r4, r2 + +Save_v0_v31_0x1a0 + bne- cr7, Save_v0_v31_0x1ac + li r3, 480 + stvx v30, r3, r2 + +Save_v0_v31_0x1ac + bns- cr7, Save_v0_v31_0x1b8 + li r4, 0x1f0 + stvx v31, r4, r2 + +Save_v0_v31_0x1b8 + blr + + + + +major_0x13e4c + lwz r17, 0x0010( r8) + lbz r18, 0x0018( r8) + addi r16, r8, 0x08 + cmpwi cr1, r18, 0x00 + cmpwi r17, 0x00 + beq+ cr1, Local_Panic + beq- major_0x13e4c_0x74 + lwz r17, 0x0008(r16) + lwz r18, 0x000c(r16) + stw r17, 0x0008(r18) + stw r18, 0x000c(r17) + li r17, 0x00 + stw r17, 0x0008(r16) + stw r17, 0x000c(r16) + lwz r17, 0x0000(r16) + lwz r16, 0x001c( r8) + lwz r18, 0x0014(r17) + subf r18, r16, r18 + stw r18, 0x0014(r17) + lwz r18, 0x0010(r17) + addi r18, r18, -0x01 + stw r18, 0x0010(r17) + cmpwi r18, 0x00 + lwz r16, -0x0970( r1) + blt+ Local_Panic + bne- major_0x13e4c_0x74 + lwz r18, 0x0000(r17) + andc r16, r16, r18 + stw r16, -0x0970( r1) + +major_0x13e4c_0x74 + li r16, 0x00 + stb r16, 0x0018( r8) + mfsprg r17, 0 + li r16, 0x01 + stb r16, -0x0118(r17) + blr + + + + + +; TaskReadyAsNext + +; Xrefs: +; major_0x02ccc +; MPCall_6 +; KCYieldWithHint +; MPCall_55 +; KCStopScheduling +; MPCall_18 +; MPCall_23 +; MPCall_27 +; MPCall_52 +; MPCall_9 +; KCThrowException +; MPCall_114 +; major_0x130f0 +; major_0x142dc +; CommonPIHPath + + +; These two entry cases specify different directions of queue insertion + +; ARG Task *r8 +; CLOB r16, r17, r18 + +TaskReadyAsNext + crclr cr1_eq + b TaskReadyCommonPath + +TaskReadyAsPrev + crset cr1_eq + +TaskReadyCommonPath + + lwz r16, Task.QueueMember + LLL.Next(r8) + lis r17, 0x8000 ; ...0000 + cmpwi r16, 0 + lbz r18, Task.Priority(r8) + bne+ Local_Panic + + + ; Set the KDP priority flag for this task. + ; Leave pointer to target RDYQ in r17. + + lwz r16, PSA.PriorityFlags(r1) + srw r17, r17, r18 + mulli r18, r18, 32 ;ReadyQueue.Size + or r16, r16, r17 + addi r17, r1, PSA.ReadyQueues + stw r16, PSA.PriorityFlags(r1) + add r17, r17, r18 + + + ; What decrements this counter? + lwz r18, ReadyQueue.Counter(r17) + addi r18, r18, 1 + stw r18, ReadyQueue.Counter(r17) + + + lwz r16, Task.Weight(r8) + lwz r18, ReadyQueue.TotalWeight(r17) + add r18, r18, r16 + stw r18, ReadyQueue.TotalWeight(r17) + + + addi r16, r8, Task.QueueMember + + bne- cr1, @as_next + + + stw r17, LLL.Freeform(r16) + InsertAsPrev r16, r17, scratch=r18 + + + b @endif +@as_next + + stw r17, LLL.Freeform(r16) + InsertAsNext r16, r17, scratch=r18 + +@endif + + + li r16, 1 + stb r16, Task.MysteryByte1(r8) + blr + + + + +; Set the segment and block allocation table registers according to the +; SPAC structure passed in. On non-601 machines, unset the "guarded" bit +; of the WIMG field of each lower BAT register. +; +; And apparently there is a second, undocumented batch of BAT registers! + +; ARG AddressSpace *r8, AddressSpace *r9 (can be zero?) + +SetAddrSpcRegisters + + ; This is the only function that hits this counter + lwz r17, KDP.NanoKernelInfo + NKNanoKernelInfo.AddrSpcSetCtr(r1) + addi r17, r17, 1 + stw r17, KDP.NanoKernelInfo + NKNanoKernelInfo.AddrSpcSetCtr(r1) + + ; Check that we have the right guy (a 'SPAC') + lwz r16, AddressSpace.Signature(r8) + lisori r17, AddressSpace.kSignature + cmpw r16, r17 + bne+ Local_Panic + + ; Intend to skip the dssall instruction if Altivec is... present? absent? + rlwinm. r16, r7, 0, 12, 12 ; seems to be leftover from Init.s Altivec testing + + ; Apply the address space to the segment registers + isync + lwz r16, AddressSpace.SRs + 0(r8) + lwz r17, AddressSpace.SRs + 4(r8) + mtsr 0, r16 + mtsr 1, r17 + lwz r16, AddressSpace.SRs + 8(r8) + lwz r17, AddressSpace.SRs + 12(r8) + mtsr 2, r16 + mtsr 3, r17 + lwz r16, AddressSpace.SRs + 16(r8) + lwz r17, AddressSpace.SRs + 20(r8) + mtsr 4, r16 + mtsr 5, r17 + lwz r16, AddressSpace.SRs + 24(r8) + lwz r17, AddressSpace.SRs + 28(r8) + mtsr 6, r16 + mtsr 7, r17 + lwz r16, AddressSpace.SRs + 32(r8) + lwz r17, AddressSpace.SRs + 36(r8) + mtsr 8, r16 + mtsr 9, r17 + lwz r16, AddressSpace.SRs + 40(r8) + lwz r17, AddressSpace.SRs + 44(r8) + mtsr 10, r16 + mtsr 11, r17 + lwz r16, AddressSpace.SRs + 48(r8) + lwz r17, AddressSpace.SRs + 52(r8) + mtsr 12, r16 + mtsr 13, r17 + lwz r16, AddressSpace.SRs + 56(r8) + lwz r17, AddressSpace.SRs + 60(r8) + mtsr 14, r16 + mtsr 15, r17 + + beq- @skip_dssall + dssall ; flush pending vector ops? +@skip_dssall + + ; Point KDP at this SPAC + mfsprg r16, 0 ; paranoid + isync + stw r8, EWA.PA_CurAddressSpace(r16) + + + ; The 601 has a special code path for populating the BATs + mfpvr r16 + rlwinm. r16, r16, 0, 0, 14 + cmpwi cr1, r9, 0 ; arg r9 is 0 when called from Init.s + beq- @is_601 + + + ; Fill the BATs on "real" PowerPC CPUs + + lwz r16, AddressSpace.BAT0U(r8) + lwz r17, AddressSpace.BAT0U(r9) + cmplw r16, r17 + + lwz r17, AddressSpace.BAT0L(r8) + beq- cr1, @definitely_set_BAT0 + beq- @skip_setting_BAT0 + +@definitely_set_BAT0 ; r9 is zero or the addrspc bats match low physical memory + mtspr dbat0u, r0 + mtspr dbat0l, r17 + rlwinm r17, r17, 0, 29, 27 + mtspr dbat0u, r16 + mtspr ibat0u, r0 + mtspr ibat0l, r17 + mtspr ibat0u, r16 +@skip_setting_BAT0 + + + lwz r16, AddressSpace.BAT1U(r8) + lwz r17, AddressSpace.BAT1U(r9) + cmplw r16, r17 + lwz r17, AddressSpace.BAT1L(r8) + beq- cr1, @definitely_set_BAT1 + beq- @skip_setting_BAT1 + +@definitely_set_BAT1 + mtspr dbat1u, r0 + mtspr dbat1l, r17 + rlwinm r17, r17, 0, 29, 27 + mtspr dbat1u, r16 + mtspr ibat1u, r0 + mtspr ibat1l, r17 + mtspr ibat1u, r16 +@skip_setting_BAT1 + + + lwz r16, AddressSpace.BAT2U(r8) + lwz r17, AddressSpace.BAT2U(r9) + cmplw r16, r17 + lwz r17, AddressSpace.BAT2L(r8) + beq- cr1, @definitely_set_BAT2 + beq- @skip_setting_BAT2 + +@definitely_set_BAT2 + mtspr dbat2u, r0 + mtspr dbat2l, r17 + rlwinm r17, r17, 0, 29, 27 + mtspr dbat2u, r16 + mtspr ibat2u, r0 + mtspr ibat2l, r17 + mtspr ibat2u, r16 +@skip_setting_BAT2 + + + lwz r16, AddressSpace.BAT3U(r8) + lwz r17, AddressSpace.BAT3U(r9) + cmplw r16, r17 + lwz r17, AddressSpace.BAT3L(r8) + beq- cr1, @definitely_set_BAT3 + beq- @skip_setting_BAT3 +@definitely_set_BAT3 + + mtspr dbat3u, r0 + mtspr dbat3l, r17 + rlwinm r17, r17, 0, 29, 27 + mtspr dbat3u, r16 + mtspr ibat3u, r0 + mtspr ibat3l, r17 + mtspr ibat3u, r16 +@skip_setting_BAT3 + + + ; This is weird. If the hasExtraBATs flag (my name) is set in ProcessorInfo, + ; populate a second (undocumented?) set of BATs from the same struct. + + lwz r17, KDP.ProcessorInfo + NKProcessorInfo.ProcessorFlags(r1) + lwz r16, AddressSpace.ExtraBAT0U(r8) + rlwinm. r17, r17, 0, 31-NKProcessorInfo.hasExtraBATs, 31-NKProcessorInfo.hasExtraBATs + lwz r17, AddressSpace.ExtraBAT0U(r9) + beq- @return + cmplw r16, r17 + lwz r17, AddressSpace.ExtraBAT0L(r8) + beq- cr1, @definitely_set_ExtraBAT0 + beq- @skip_setting_ExtraBAT0 + +@definitely_set_ExtraBAT0 + mtspr 0x238, r0 + mtspr 0x239, r17 + mtspr 0x238, r16 + mtspr 0x230, r0 + mtspr 0x231, r17 + mtspr 0x230, r16 +@skip_setting_ExtraBAT0 + + + lwz r16, AddressSpace.ExtraBAT1U(r8) + lwz r17, AddressSpace.ExtraBAT1U(r9) + cmplw r16, r17 + lwz r17, AddressSpace.ExtraBAT1L(r8) + beq- cr1, @definitely_set_ExtraBAT1 + beq- @skip_setting_ExtraBAT1 + +@definitely_set_ExtraBAT1 + mtspr 0x23a, r0 + mtspr 0x23b, r17 + mtspr 0x23a, r16 + mtspr 0x232, r0 + mtspr 0x233, r17 + mtspr 0x232, r16 +@skip_setting_ExtraBAT1 + + + lwz r16, AddressSpace.ExtraBAT2U(r8) + lwz r17, AddressSpace.ExtraBAT2U(r9) + cmplw r16, r17 + lwz r17, AddressSpace.ExtraBAT2L(r8) + beq- cr1, @definitely_set_ExtraBAT2 + beq- @skip_setting_ExtraBAT2 + +@definitely_set_ExtraBAT2 + mtspr 0x23c, r0 + mtspr 0x23d, r17 + mtspr 0x23c, r16 + mtspr 0x234, r0 + mtspr 0x235, r17 + mtspr 0x234, r16 +@skip_setting_ExtraBAT2 + + + lwz r16, AddressSpace.ExtraBAT3U(r8) + lwz r17, AddressSpace.ExtraBAT3U(r9) + cmplw r16, r17 + lwz r17, AddressSpace.ExtraBAT3L(r8) + beq- cr1, @definitely_set_ExtraBAT3 + beq- @skip_setting_ExtraBAT3 + +@definitely_set_ExtraBAT3 + mtspr 0x23e, r0 + mtspr 0x23f, r17 + mtspr 0x23e, r16 + mtspr 0x236, r0 + mtspr 0x237, r17 + mtspr 0x236, r16 +@skip_setting_ExtraBAT3 + + +@return + blr + + ; This is the crazy cpu case +@is_601 + lwz r16, 0x0080(r8) + lwz r17, 0x0080(r9) + cmplw r16, r17 + lwz r17, 0x0084(r8) + beq- cr1, SetAddrSpcRegisters_0x284 + beq- SetAddrSpcRegisters_0x29c + +SetAddrSpcRegisters_0x284: + rlwimi r16, r17, 0, 25, 31 + mtspr ibat0u, r16 + lwz r16, 0x0080(r8) + rlwimi r17, r16, 30, 26, 31 + rlwimi r17, r16, 6, 25, 25 + mtspr ibat0l, r17 + +SetAddrSpcRegisters_0x29c: + lwz r16, 0x0088(r8) + lwz r17, 0x0088(r9) + cmplw r16, r17 + lwz r17, 0x008c(r8) + beq- cr1, SetAddrSpcRegisters_0x2b4 + beq- SetAddrSpcRegisters_0x2cc + +SetAddrSpcRegisters_0x2b4: + rlwimi r16, r17, 0, 25, 31 + mtspr ibat1u, r16 + lwz r16, 0x0088(r8) + rlwimi r17, r16, 30, 26, 31 + rlwimi r17, r16, 6, 25, 25 + mtspr ibat1l, r17 + +SetAddrSpcRegisters_0x2cc: + lwz r16, 0x0090(r8) + lwz r17, 0x0090(r9) + cmplw r16, r17 + lwz r17, 0x0094(r8) + beq- cr1, SetAddrSpcRegisters_0x2e4 + beq- SetAddrSpcRegisters_0x2fc + +SetAddrSpcRegisters_0x2e4: + rlwimi r16, r17, 0, 25, 31 + mtspr ibat2u, r16 + lwz r16, 0x0090(r8) + rlwimi r17, r16, 30, 26, 31 + rlwimi r17, r16, 6, 25, 25 + mtspr ibat2l, r17 + +SetAddrSpcRegisters_0x2fc: + lwz r16, 0x0098(r8) + lwz r17, 0x0098(r9) + cmplw r16, r17 + lwz r17, 0x009c(r8) + beq- cr1, SetAddrSpcRegisters_0x314 + beqlr- + +SetAddrSpcRegisters_0x314: + rlwimi r16, r17, 0, 25, 31 + mtspr ibat3u, r16 + lwz r16, 0x0098(r8) + rlwimi r17, r16, 30, 26, 31 + rlwimi r17, r16, 6, 25, 25 + mtspr ibat3l, r17 + blr + + + +; major_0x142a8 + +; Xrefs: +; skeleton_key + +major_0x142a8 ; OUTSIDE REFERER + lbz r8, -0x0118(r1) + rlwinm. r9, r7, 0, 16, 16 + lwz r1, -0x0004(r1) + cmpwi cr1, r8, 0x00 + +; sprg0 = for r1 and r6 +; r1 = kdp +; r6 = register restore area +; r7 = flag to insert into XER +; r10 = new srr0 (return location) +; r11 = new srr1 +; r12 = lr restore +; r13 = cr restore + bne- int_teardown + +; sprg0 = for r1 and r6 +; r1 = kdp +; r6 = register restore area +; r7 = flag to insert into XER +; r10 = new srr0 (return location) +; r11 = new srr1 +; r12 = lr restore +; r13 = cr restore + beq+ cr1, int_teardown + +; r6 = ewa + bl Save_r14_r31 +; r8 = sprg0 (not used by me) + + + _Lock PSA.SchLock, scratch1=r27, scratch2=r28 + + + + +; major_0x142dc + +; Xrefs: +; major_0x02ccc +; CommonMPCallReturnPath +; major_0x142a8 +; major_0x14bcc + +major_0x142dc ; OUTSIDE REFERER + mfsprg r14, 0 + li r8, 0x00 + stb r8, -0x0118(r14) + lwz r31, -0x0008(r14) + lwz r1, -0x0004(r14) + lwz r9, 0x0ee4(r1) + addi r9, r9, 0x01 + stw r9, 0x0ee4(r1) + bl major_0x14a98 + lbz r27, 0x0019(r31) + blt- major_0x142dc_0x58 + li r26, 0x01 + beq- major_0x142dc_0x38 + li r26, 0x00 + +major_0x142dc_0x38 + cmpw r27, r26 + mr r8, r31 + beq- major_0x142dc_0x58 + bl major_0x13e4c + stb r26, 0x0019(r31) + mr r8, r31 + bl TaskReadyAsPrev + bl CalculateTimeslice + +major_0x142dc_0x58 ; OUTSIDE REFERER + lwz r27, -0x0970(r1) + +major_0x142dc_0x5c + mr r30, r31 + cmpwi r27, 0x00 + cntlzw r26, r27 + beq- major_0x142dc_0x140 + addi r25, r1, -0x9f0 + mulli r26, r26, 0x20 + add r26, r26, r25 + lwz r29, 0x0008(r26) + addi r30, r29, -0x08 + +major_0x142dc_0x80 + lhz r28, -0x0116(r14) + lwz r24, 0x0064(r30) + lhz r25, 0x001a(r30) + rlwinm. r8, r24, 0, 25, 26 + cmpw cr1, r25, r28 + beq- major_0x142dc_0xb8 + beq- cr1, major_0x142dc_0xb8 + lwz r29, 0x0008(r29) + addi r30, r29, -0x08 + cmpw r29, r26 + bne+ major_0x142dc_0x80 + lwz r25, 0x0000(r26) + andc r27, r27, r25 + b major_0x142dc_0x5c + +major_0x142dc_0xb8 + lbz r25, 0x0018(r31) + lbz r28, 0x0019(r30) + lbz r27, 0x0019(r31) + cmpwi cr1, r25, 0x02 + cmpw cr2, r28, r27 + bne- cr1, major_0x142dc_0xd8 + blt- cr2, major_0x142dc_0xd8 + mr r30, r31 + +major_0x142dc_0xd8 ; OUTSIDE REFERER + lwz r28, 0x0010(r30) + addi r29, r30, 0x08 + cmpwi r28, 0x00 + lwz r26, 0x0008(r30) + beq- major_0x142dc_0x140 + lwz r28, 0x0008(r29) + lwz r27, 0x000c(r29) + stw r28, 0x0008(r27) + stw r27, 0x000c(r28) + li r28, 0x00 + stw r28, 0x0008(r29) + stw r28, 0x000c(r29) + lwz r27, 0x001c(r30) + lwz r28, 0x0014(r26) + subf r28, r27, r28 + stw r28, 0x0014(r26) + lwz r28, 0x0010(r26) + lwz r27, -0x0970(r1) + addi r28, r28, -0x01 + cmpwi r28, 0x00 + stw r28, 0x0010(r26) + bltl+ Local_Panic + bne- major_0x142dc_0x140 + lwz r28, 0x0000(r26) + andc r27, r27, r28 + stw r27, -0x0970(r1) + +major_0x142dc_0x140 + lwz r25, 0x0064(r30) + li r26, 0x00 + rlwinm. r8, r25, 0, 21, 22 + andc r27, r25, r8 + beq+ major_0x142dc_0x184 + ori r27, r27, 0x200 + stb r26, 0x0018(r30) + stw r27, 0x0064(r30) + addi r25, r1, -0xa34 + addi r26, r30, 0x08 + stw r25, 0x0000(r26) + stw r25, 0x0008(r26) + lwz r27, 0x000c(r25) + stw r27, 0x000c(r26) + stw r26, 0x0008(r27) + stw r26, 0x000c(r25) + b major_0x142dc_0x58 + +major_0x142dc_0x184 + cmpw cr3, r30, r31 + rlwinm. r8, r25, 0, 27, 27 + bne- cr3, major_0x14548 + bne- major_0x14548 + bl GetTime + bl major_0x148ec + lwz r27, 0x0064(r31) + mfsprg r14, 0 + rlwinm. r8, r27, 0, 8, 8 + rlwimi r11, r27, 24, 29, 29 + beq+ major_0x142dc_0x1bc + lwz r10, 0x00fc(r6) + rlwinm r27, r27, 0, 9, 7 + stw r27, 0x0064(r31) + +major_0x142dc_0x1bc + li r27, 0x02 + lbz r28, 0x0019(r31) + stb r27, 0x0018(r31) + stb r28, -0x0117(r14) + sync + lwz r27, PSA.SchLock + Lock.Count(r1) + cmpwi cr1, r27, 0x00 + li r27, 0x00 + bne+ cr1, major_0x142dc_0x1e8 + mflr r27 + bl panic + +major_0x142dc_0x1e8 + stw r27, PSA.SchLock + Lock.Count(r1) + +; r6 = ewa + bl Restore_r14_r31 + + + +; int_teardown + +; All MPCalls get here? +; r0,7,8,9,10,11,12,13 restored from r6 area +; r1,6 restored from sprg0 area +; Apple used the "reserved" (not first three) bits of XER. +; If bit 27 of 0xedc(r1) is set: +; Bit 22 of XER is cleared +; Bit 10 of r7 is inserted into XER at bit 23 + +; Xrefs: +; non_skeleton_reset_trap +; major_0x142a8 +; major_0x142dc +; major_0x14548 + +; > sprg0 = for r1 and r6 +; > r1 = kdp +; > r6 = register restore area +; > r7 = flag to insert into XER +; > r10 = new srr0 (return location) +; > r11 = new srr1 +; > r12 = lr restore +; > r13 = cr restore + +int_teardown ; OUTSIDE REFERER + lwz r8, 0x0edc(r1) + mfsprg r1, 0 + mtlr r12 + mtspr srr0, r10 + mtspr srr1, r11 + rlwinm. r8, r8, 0, 27, 27 + beq- int_teardown_0x2c + mfxer r8 + rlwinm r8, r8, 0, 23, 21 + rlwimi r8, r7, 19, 23, 23 + mtxer r8 + +int_teardown_0x2c + mtcr r13 + lwz r10, 0x0154(r6) + lwz r11, 0x015c(r6) + lwz r12, 0x0164(r6) + lwz r13, 0x016c(r6) + lwz r7, 0x013c(r6) + lwz r8, 0x0144(r6) + lwz r9, 0x014c(r6) + lwz r0, 0x0104(r6) + lwz r6, 0x0018(r1) + lwz r1, 0x0004(r1) + rfi + dcb.b 32, 0 + + + + +; major_0x14548 + +; Xrefs: +; major_0x142dc + +major_0x14548 ; OUTSIDE REFERER + lwz r16, 0x0064(r31) + stw r30, -0x0260(r14) + rlwinm r16, r16, 0, 27, 25 + stw r6, 0x0088(r31) + mfsprg r8, 3 + stw r16, 0x0064(r31) + stw r8, 0x00f0(r31) + lwz r8, -0x000c(r14) + stw r7, 0x0000(r6) + stw r8, 0x0004(r6) + mfxer r8 + stw r13, 0x00dc(r6) + stw r8, 0x00d4(r6) + stw r12, 0x00ec(r6) + mfctr r8 + stw r10, 0x00fc(r6) + stw r8, 0x00f4(r6) + mfspr r8, pvr + rlwinm. r8, r8, 0, 0, 14 + bne- major_0x14548_0x58 + mfspr r8, mq + stw r8, 0x00c4(r6) + +major_0x14548_0x58 + lwz r8, 0x0004(r14) + stw r8, 0x010c(r6) + stw r2, 0x0114(r6) + stw r3, 0x011c(r6) + andi. r8, r11, 0x2000 + stw r4, 0x0124(r6) + lwz r8, 0x0018(r14) + stw r5, 0x012c(r6) + stw r8, 0x0134(r6) + bnel+ Save_f0_f31 + lwz r31, -0x0008(r14) + lwz r30, -0x0260(r14) + rlwinm. r8, r7, 0, 12, 12 + bnel+ Save_v0_v31 + stw r11, 0x00a4(r6) + lwz r8, 0x00e8(r31) + addi r8, r8, 0x01 + stw r8, 0x00e8(r31) + bl GetTime + bl major_0x148ec + mfsprg r14, 0 + li r27, 0x02 + lbz r28, 0x0019(r30) + stb r27, 0x0018(r30) + stb r28, -0x0117(r14) + cmplw r30, r31 + lwz r16, 0x0010(r31) + beq- major_0x14548_0xd4 + cmpwi r16, 0x00 + mr r8, r31 + beql+ TaskReadyAsPrev + +major_0x14548_0xd4 + mfsprg r19, 0 + li r8, 0x00 + stb r8, -0x0118(r19) + lhz r8, -0x0116(r19) + lwz r6, 0x0088(r30) + lwz r28, -0x0340(r19) + sth r8, 0x001a(r30) + stw r28, 0x0078(r30) + stw r30, -0x0008(r19) + stw r6, -0x0014(r19) + lwz r7, 0x0000(r6) + lwz r28, 0x0004(r6) + stw r7, -0x0010(r19) + stw r28, -0x000c(r19) + lwz r27, 0x0064(r30) + lwz r13, 0x00dc(r6) + ori r27, r27, 0x20 + lwz r11, 0x00a4(r6) + lwz r8, 0x00f0(r30) + rlwimi r11, r27, 24, 29, 29 + rlwinm r27, r27, 0, 9, 7 + mtsprg 3, r8 + stw r27, 0x0064(r30) + lwz r18, 0x0070(r30) + lwz r9, -0x001c(r19) + cmpw r18, r9 + beq- major_0x14548_0x148 + mr r8, r18 + bl SetAddrSpcRegisters + +major_0x14548_0x148 + mfsprg r19, 0 + mtcr r7 + lis r28, 0x00 + ori r28, r28, 0x10 + bne- cr2, major_0x14548_0x20c + and. r28, r28, r27 + li r8, 0x00 + beq- major_0x14548_0x20c + andc r27, r27, r28 + lwz r29, -0x0440(r1) + stw r27, 0x0064(r30) + stw r8, -0x0440(r1) + blt- cr2, major_0x14548_0x1cc + bsol+ cr6, Local_Panic + clrlwi r8, r7, 0x08 + stw r8, 0x0000(r6) + lwz r6, 0x0658(r1) + addi r26, r1, 0x360 + mtsprg 3, r26 + stw r26, 0x00f0(r30) + stw r6, -0x0014(r19) + stw r6, 0x0088(r30) + lwz r7, 0x0000(r6) + lwz r26, 0x0004(r6) + mtcr r7 + stw r26, -0x000c(r19) + lwz r13, 0x00dc(r6) + lwz r11, 0x00a4(r6) + bsol+ cr6, Local_Panic + rlwimi r11, r7, 0, 20, 23 + rlwimi r7, r8, 0, 9, 16 + rlwimi r11, r27, 24, 29, 29 + stw r7, -0x0010(r19) + +major_0x14548_0x1cc + lwz r17, 0x00cc(r6) + ori r17, r17, 0x100 + stw r17, 0x00cc(r6) + lhz r17, -0x043c(r1) + lwz r18, 0x067c(r1) + cmplwi r17, 0xffff + lwz r26, 0x0674(r1) + beq- major_0x14548_0x1f8 + sth r17, 0x0000(r18) + li r17, -0x01 + sth r17, -0x043c(r1) + +major_0x14548_0x1f8 + cmpwi r29, 0x00 + or r13, r13, r29 + bne- major_0x14548_0x20c + lwz r29, 0x0678(r1) + and r13, r13, r29 + +major_0x14548_0x20c + lwz r29, 0x00d8(r6) + cmpwi r29, 0x00 + lwz r8, 0x0210(r29) + beq- major_0x14548_0x220 + mtspr vrsave, r8 + +major_0x14548_0x220 + lwz r8, 0x00d4(r6) + lwz r12, 0x00ec(r6) + mtxer r8 + lwz r8, 0x00f4(r6) + lwz r10, 0x00fc(r6) + mtctr r8 + mfspr r8, pvr + rlwinm. r8, r8, 0, 0, 14 + bne- major_0x14548_0x24c + lwz r8, 0x00c4(r6) + mtspr mq, r8 + +major_0x14548_0x24c + li r9, 0x124 + lwz r8, 0x010c(r6) + dcbt r9, r6 + lwz r2, 0x0114(r6) + stw r8, 0x0004(r19) + lwz r3, 0x011c(r6) + li r9, 0x184 + lwz r4, 0x0124(r6) + dcbt r9, r6 + lwz r8, 0x0134(r6) + lwz r5, 0x012c(r6) + stw r8, 0x0018(r19) + lwz r14, 0x0174(r6) + lwz r15, 0x017c(r6) + li r9, 420 + lwz r16, 0x0184(r6) + dcbt r9, r6 + lwz r17, 0x018c(r6) + lwz r18, 0x0194(r6) + lwz r19, 0x019c(r6) + li r9, 0x1c4 + lwz r20, 0x01a4(r6) + dcbt r9, r6 + lwz r21, 0x01ac(r6) + lwz r22, 0x01b4(r6) + lwz r23, 0x01bc(r6) + li r9, 0x1e4 + lwz r24, 0x01c4(r6) + dcbt r9, r6 + lwz r25, 0x01cc(r6) + lwz r26, 0x01d4(r6) + lwz r27, 0x01dc(r6) + andi. r8, r11, 0x2900 + lwz r28, 0x01e4(r6) + lwz r29, 0x01ec(r6) + lwz r30, 0x01f4(r6) + lwz r31, 0x01fc(r6) + beq- major_0x14548_0x380 + mfmsr r8 + ori r8, r8, 0x2000 + ori r11, r11, 0x2000 + mtmsr r8 + isync + lfd f31, 0x00e0(r6) + lfd f0, 0x0200(r6) + lfd f1, 0x0208(r6) + lfd f2, 0x0210(r6) + lfd f3, 0x0218(r6) + lfd f4, 0x0220(r6) + lfd f5, 0x0228(r6) + lfd f6, 0x0230(r6) + lfd f7, 0x0238(r6) + mtfsf 0xff, f31 + lfd f8, 0x0240(r6) + lfd f9, 0x0248(r6) + lfd f10, 0x0250(r6) + lfd f11, 0x0258(r6) + lfd f12, 0x0260(r6) + lfd f13, 0x0268(r6) + lfd f14, 0x0270(r6) + lfd f15, 0x0278(r6) + lfd f16, 0x0280(r6) + lfd f17, 0x0288(r6) + lfd f18, 0x0290(r6) + lfd f19, 0x0298(r6) + lfd f20, 0x02a0(r6) + lfd f21, 0x02a8(r6) + lfd f22, 0x02b0(r6) + lfd f23, 0x02b8(r6) + lfd f24, 0x02c0(r6) + lfd f25, 0x02c8(r6) + lfd f26, 0x02d0(r6) + lfd f27, 0x02d8(r6) + lfd f28, 0x02e0(r6) + lfd f29, 0x02e8(r6) + lfd f30, 0x02f0(r6) + lfd f31, 0x02f8(r6) + +major_0x14548_0x380 + sync + lwz r8, PSA.SchLock + Lock.Count(r1) + cmpwi cr1, r8, 0x00 + li r8, 0x00 + bne+ cr1, major_0x14548_0x39c + mflr r8 + bl panic + +major_0x14548_0x39c + stw r8, PSA.SchLock + Lock.Count(r1) + +; sprg0 = for r1 and r6 +; r1 = kdp +; r6 = register restore area +; r7 = flag to insert into XER +; r10 = new srr0 (return location) +; r11 = new srr1 +; r12 = lr restore +; r13 = cr restore + b int_teardown + + + +; major_0x148ec + +; Xrefs: +; major_0x142dc +; major_0x14548 + +major_0x148ec ; OUTSIDE REFERER + mfxer r20 + mfsprg r21, 0 + lwz r19, 0x00cc(r31) + lwz r18, 0x00c8(r31) + subfc r19, r19, r9 + subfe r18, r18, r8 + lwz r17, 0x00c4(r31) + lwz r16, 0x00c0(r31) + addc r17, r17, r19 + adde r16, r16, r18 + stw r17, 0x00c4(r31) + stw r16, 0x00c0(r31) + lwz r17, 0x00dc(r31) + lwz r16, 0x00d8(r31) + andi. r22, r17, 0x01 + bne- major_0x148ec_0x58 + subfc r17, r19, r17 + subfe. r16, r18, r16 + bge- major_0x148ec_0x54 + li r16, 0x00 + li r17, 0x00 + +major_0x148ec_0x54 + stw r16, 0x00d8(r31) + +major_0x148ec_0x58 + rlwinm r17, r17, 0, 0, 30 + stw r17, 0x00dc(r31) + lwz r17, 0x00fc(r31) + andi. r22, r17, 0x01 + bne- major_0x148ec_0x78 + subf. r17, r19, r17 + bge- major_0x148ec_0x78 + li r17, 0x00 + +major_0x148ec_0x78 + rlwinm r17, r17, 0, 0, 30 + stw r17, 0x00fc(r31) + stw r8, 0x00c8(r30) + stw r9, 0x00cc(r30) + lwz r18, 0x0008(r30) + lbz r19, 0x0019(r30) + lwz r18, 0x0010(r18) + cmpwi cr1, r19, 0x02 + cmpwi r18, 0x00 + bge- cr1, major_0x148ec_0xb0 + lwz r16, 0x00fc(r30) + lwz r17, 0x00fc(r30) + srawi r16, r16, 31 + b major_0x148ec_0xc8 + +major_0x148ec_0xb0 + lwz r16, 0x00d8(r30) + lwz r17, 0x00dc(r30) + bgt- major_0x148ec_0xc8 + bne- cr1, major_0x148ec_0xc8 + li r16, 0x00 + lwz r17, 0x0f2c(r1) + +major_0x148ec_0xc8 + addc r17, r17, r9 + adde r16, r16, r8 + stw r17, -0x02e4(r21) + stw r16, -0x02e8(r21) + mtxer r20 + li r16, 0x01 + stb r16, -0x0309(r21) + b major_0x13060_0xc + + + +; major_0x149d4 + +; Xrefs: +; setup +; KCStopScheduling +; major_0x0c8b4 +; major_0x0ccf4 +; MPCall_28 +; major_0x0d35c +; MPCall_8 +; major_0x130f0 +; major_0x142dc +; major_0x14bcc +; CommonPIHPath + +; Almost certain this was hand-written. Has a typo, and some +; instructions the compiler rarely touched, and is in hot path. + +major_0x149d4 ; OUTSIDE REFERER + crset cr1_eq + b major_0x149d4_0xc + +CalculateTimeslice ; OUTSIDE REFERER + crclr cr1_eq + +major_0x149d4_0xc: + + + lwz r18, Task.QueueMember + LLL.Next(r8) + lwz r16, Task.QueueMember + LLL.Freeform(r8) ; points to RDYQ + cmpwi r18, 0 + lwz r17, Task.Weight(r8) + beq+ Local_Panic + + + lwz r18, ReadyQueue.TotalWeight(r16) + + lwz r19, ReadyQueue.Timecake(r16) + lwz r20, ReadyQueue.Timecake + 4(r16) + + ; Skip some stuff if this task accounts for all of the weight in this queue + cmpw r18, r17 + rlwinm r17, r17, 10, 0, 22 ; looks like a typo; should multiply wt by 1024 + beq- @is_only_weighted_task + + divw. r18, r17, r18 ; how many slices do I get in 1024? + + ble- @no_time ; fall back on one slice worth of ticks per 1024 slices + + ; r19 || r20 = (r19 || r20) * r18 = ticks owed to this task in 1024 slices + mulhw r17, r20, r18 + mullw r19, r19, r18 + mullw r20, r20, r18 + add r19, r19, r17 +@no_time + + ; Set r19 || r20 to ticks owed to this task per RoundRobinTime + + srwi r20, r20, 10 + rlwimi r20, r19, 22, 0, 9 + srwi r19, r19, 10 +@is_only_weighted_task + + + + ; Now r19 || r20 contains something meaningful + + lbz r18, Task.Priority(r8) + cmpwi r18, Task.kNominalPriority + + ori r20, r20, 1 ; why make this odd? + + bge- @priority_nominal_or_idle + + ; Critical or latency protection: save the low word of (ticks per round) + stw r20, 0x00fc(r8) + blr + +@priority_nominal_or_idle + + lwz r16, 0x00d8(r8) + lwz r17, 0x00dc(r8) + beq- cr1, @definitely_do_the_thing + cmpwi r16, 0 + cmplwi cr2, r17, 0 + blt- @definitely_do_the_thing + bgtlr- + bgtlr- cr2 + +@definitely_do_the_thing + mfxer r18 + addc r20, r20, r17 + adde r19, r19, r16 + mtxer r18 + rlwinm r20, r20, 0, 0, 30 + + li r18, 1 + stw r19, 0x00d8(r8) + stw r20, 0x00dc(r8) + stw r18, 0x00fc(r8) + blr + + + + +; clear_cr0_lt + +; Xrefs: +; major_0x130f0 + +clear_cr0_lt ; OUTSIDE REFERER + crclr cr0_lt + blr + + + +; major_0x14a98 + +; Xrefs: +; IntDecrementer +; major_0x142dc + +major_0x14a98 ; OUTSIDE REFERER + rlwinm r8, r7, 10, 0, 0 + lwz r18, 0x0658(r1) + nand. r8, r8, r8 + lwz r17, 0x00cc(r18) + bltlr- + cmpwi r17, 0x00 + rlwinm r9, r17, 0, 22, 22 + blt- major_0x14a98_0x54 + cmpwi r9, 0x200 + lwz r16, 0x01cc(r18) + beq- major_0x14a98_0x48 + clrlwi r8, r16, 0x1d + clrlwi r9, r17, 0x1c + cmpwi r8, 0x06 + bgt- major_0x14a98_0x48 + cmpw r8, r9 + bltlr- + cmpw r8, r8 + +major_0x14a98_0x48 + ori r17, r17, 0x100 + stw r17, 0x00cc(r18) + blr + +major_0x14a98_0x54 + clrlwi r17, r17, 0x01 + stw r17, 0x00cc(r18) + blr + + + +; major_0x14af8 + +; Xrefs: +; setup +; major_0x02ccc +; MPCall_6 +; KCYieldWithHint +; KCStopScheduling +; KCMarkPMFTask +; MPCall_16 +; major_0x0c8b4 +; major_0x0ccf4 +; MPCall_21 +; MPCall_28 +; MPCall_26 +; MPCall_50 +; major_0x0d35c +; major_0x0dce8 +; MPCall_8 +; MPCall_9 +; MPCall_14 +; KCThrowException +; MPCall_58 +; MPCall_114 +; major_0x130f0 +; CommonPIHPath + +major_0x14af8 ; OUTSIDE REFERER + lwz r16, 0x0064(r8) + mfsprg r15, 0 + rlwinm. r16, r16, 0, 25, 26 + bne- major_0x14af8_0xa0 + addi r16, r15, -0x340 + lbz r17, 0x0019(r8) + lwz r19, 0x0008(r16) + lwz r14, 0x0024(r19) + cmpwi r14, 0x02 + blt- major_0x14af8_0xa0 + lwz r14, 0x0020(r19) + mr r18, r16 + b major_0x14af8_0x3c + +major_0x14af8_0x34 + lwz r16, 0x0008(r19) + +major_0x14af8_0x38 + addi r16, r16, -0x08 + +major_0x14af8_0x3c + addi r14, r14, -0x01 + lbz r20, 0x0229(r16) + lwz r21, 0x0018(r16) + cmpw cr1, r17, r20 + rlwinm. r21, r21, 0, 28, 28 + bge- cr1, major_0x14af8_0x60 + beq- major_0x14af8_0x60 + mr r17, r20 + mr r18, r16 + +major_0x14af8_0x60 + lwz r16, 0x0010(r16) + cmpwi cr1, r14, 0x00 + cmpw r16, r19 + ble- cr1, major_0x14af8_0x78 + beq+ major_0x14af8_0x34 + b major_0x14af8_0x38 + +major_0x14af8_0x78 + lbz r16, 0x0019(r8) + cmpw r17, r16 + blelr- + lhz r17, -0x0116(r15) + lhz r18, 0x022a(r18) + cmpw r18, r17 + bne- major_0x14af8_0xb4 + +major_0x14af8_0x94 + li r16, 0x01 + stb r16, -0x0118(r15) + blr + + +major_0x14af8_0xa0 ; OUTSIDE REFERER + mfsprg r15, 0 + lhz r18, Task.MysteryHalf(r8) + lhz r17, -0x0116(r15) ; somewhere in EWA + cmpw r17, r18 + beq+ major_0x14af8_0x94 + +major_0x14af8_0xb4 + lwz r9, 0x0ee0(r1) + addi r9, r9, 0x01 + stw r9, 0x0ee0(r1) + li r16, 0x05 + stw r16, -0x0238(r15) + stw r18, -0x0234(r15) + li r8, 0x02 + +; r7 = flags +; r8 = usually 2? + b SIGP + + + +; major_0x14bcc + +; Xrefs: +; "EvenMore" +; "SecondCpuCodeViaPtr" + +major_0x14bcc + + ; This func gets passed its CPU struct in r3, + ; which lets us find its real EWA pointer. + addi r1, r3, CPU.EWA + mtsprg 0, r1 + + ; Get KDP + lwz r1, EWA.PA_KDP(r1) + lwz r8, KDP.HTABORG(r1) + lwz r9, KDP.PTEGMask(r1) + + ; Set SDR1 (same as the main ones) + srwi r9, r9, 16 + or r9, r8, r9 + sync + mtspr sdr1, r9 + sync + + _log 'Sch: Symmetric Multiprocessing^n' + _log 'Sch: On CPU ' + lhz r8, 0x022a(r3) + bl Printh + _log ' ID-' + lwz r8, -0x0340(r3) + bl Printw + + _log ' SDR1: ' + mr r8, r9 + bl Printw + + _log ' CpuDescriptor: ' + mr r8, r3 + bl Printw + + _log ' KDP: ' + mr r8, r1 + bl Printw + + _log '^n' + + bl PagingFlushTLB + + _log 'Sch: Starting SMP idle task^n' + + _Lock PSA.SchLock, scratch1=r27, scratch2=r28 + + mfsprg r14, 0 + lwz r31, 0x001c(r3) + li r8, 0x00 + stb r8, -0x0118(r14) + lwz r6, 0x0088(r31) + stw r31, -0x0008(r14) + stw r6, -0x0014(r14) + lwz r7, 0x0000(r6) + lwz r28, 0x0004(r6) + stw r7, -0x0010(r14) + stw r28, -0x000c(r14) + lwz r8, 0x00f0(r31) + mtsprg 3, r8 + lwz r10, 0x00fc(r6) + lwz r11, 0x00a4(r6) + lwz r13, 0x00dc(r6) + lwz r12, 0x00ec(r6) + _log 'EWA ' + mr r8, r14 + bl Printw + _log 'ContextPtr ' + mr r8, r6 + bl Printw + _log 'Flags ' + mr r8, r7 + bl Printw + _log 'Enables ' + mr r8, r28 + bl Printw + _log '^n' + addi r16, r31, 0x08 + lwz r17, 0x0008(r16) + lwz r18, 0x000c(r16) + stw r17, 0x0008(r18) + stw r18, 0x000c(r17) + li r17, 0x00 + stw r17, 0x0008(r16) + stw r17, 0x000c(r16) + li r16, 0x02 + stb r16, 0x0018(r31) + lwz r16, 0x0064(r31) + ori r16, r16, 0x20 + stw r16, 0x0064(r31) + mfsprg r14, 0 + lbz r8, 0x0019(r31) + stb r8, -0x0117(r14) + lwz r8, 0x0070(r31) + li r9, 0x00 + bl SetAddrSpcRegisters + _log 'Adding idle task 0x' + mr r8, r31 + bl Printw + _log 'to the ready queue^n' + mr r8, r31 + bl TaskReadyAsPrev + bl CalculateTimeslice + lwz r16, 0x0018(r3) + ori r16, r16, 0x08 + stw r16, 0x0018(r3) + lwz r17, 0x0008(r3) + lwz r16, 0x0024(r17) + addi r16, r16, 0x01 + stw r16, 0x0024(r17) + li r8, 0x01 + mtspr dec, r8 + _log 'Sch: Going to ' + mr r8, r11 + bl Printw + mr r8, r10 + bl Printw + _log '^n' + mr r30, r31 + b major_0x142dc_0xd8 + b major_0x142dc_0x58 + + + +IdleCode + li r31, 0 + lisori r20, 'idle' + lisori r21, 'task' + lisori r22, 'RenŽ' + lisori r23, 'Alan' + lisori r24, 'Jim ' + lisori r25, 'Alex' + lisori r26, 'Derr' + lisori r27, 'ick ' + +@loop + + ; Kill some time + mr r30, r1 + mr r1, r2 + mr r2, r5 + mr r5, r6 + mr r6, r7 + mr r7, r8 + mr r8, r9 + mr r9, r10 + mr r10, r11 + mr r11, r12 + mr r12, r13 + mr r13, r14 + mr r14, r15 + mr r15, r16 + mr r16, r17 + mr r17, r18 + mr r18, r19 + mr r19, r20 + mr r20, r21 + mr r21, r22 + mr r22, r23 + mr r23, r24 + mr r24, r25 + mr r25, r26 + mr r26, r27 + mr r27, r28 + mr r28, r29 + mr r29, r30 + + ; If the loop started with r31==0, make another round of syscalls + cmpwi r31, 0 + beq- @make_calls + + ; But if we counted down from >=1 to zero, then just do that again + subi r31, r31, 1 + cmplwi r31, 0 + bgt- @startagain + +@make_calls + + ; KCCpuPlugin(12, 1) + li r3, 12 + li r4, 1 + li r0, 46 + sc + cmpwi r3, 0 + beq- @startagain + + li r3, 1 + li r4, 0 + twi 31, r31, 5 ; unconditional + cmpwi r3, 0 + beq- @startagain + + lisori r31, 10*1000000 + +@startagain + b @loop + + + +StopProcessor + mfmsr r30 + andi. r29, r30, 0x7fff + mtmsr r29 + mfsprg r2, 0 + lwz r1, -0x0004(r2) + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + addi r31, r2, -0x340 + lwz r16, 0x0018(r31) + rlwinm r16, r16, 0, 29, 27 + stw r16, 0x0018(r31) + sync + lwz r17, 0x0008(r31) + lwz r16, 0x0024(r17) + addi r16, r16, -0x01 + stw r16, 0x0024(r17) + lwz r8, 0x001c(r31) + li r9, 0x00 + stw r9, 0x001c(r31) + bl major_0x13e4c + addi r16, r1, -0xa44 + addi r17, r8, 0x08 + stw r16, 0x0000(r17) + stw r16, 0x0008(r17) + lwz r18, 0x000c(r16) + stw r18, 0x000c(r17) + stw r17, 0x0008(r18) + stw r17, 0x000c(r16) + bl TasksFuncThatIsNotAMPCall + sync + lwz r16, PSA.SchLock + Lock.Count(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + bne+ cr1, StopProcessor_0xa0 + mflr r16 + bl panic + +StopProcessor_0xa0 + stw r16, PSA.SchLock + Lock.Count(r1) + _log 'SIGP kStopProcessor^n' + li r3, 0x03 + lhz r4, 0x022a(r31) + li r0, 0x2e + twi 31, r31, 0x08 + _log 'Stop didn''t work - going to sleep.^n' + +StopProcessor_0x10c + lis r5, 0x7fff + ori r5, r5, 0xffff + mtdec r5 + li r3, 0x06 + li r4, 0x00 + twi 31, r31, 0x05 + b StopProcessor_0x10c \ No newline at end of file diff --git a/NanoKernel/NKScreenConsole.s b/NanoKernel/NKScreenConsole.s new file mode 100644 index 0000000..21f22f7 --- /dev/null +++ b/NanoKernel/NKScreenConsole.s @@ -0,0 +1,1313 @@ +ScreenConsoleX equ 24 +ScreenConsoleY equ 22 + + + if &TYPE('ExtraNKLogging') != 'UNDEFINED' +ScreenConsoleWidth equ 800-24 +ScreenConsoleHeight equ 900-22 + else +ScreenConsoleWidth equ 588 +ScreenConsoleHeight equ 502 + endif + +ScreenConsoleBG equ 0xfffffeee +ScreenConsoleFG equ 0x44444444 + + + + align 6 ; odd! +; InitScreenConsole + +; Xrefs: +; replace_old_kernel +; new_world +; undo_failed_kernel_replacement + +; > r1 = kdp + +InitScreenConsole ; OUTSIDE REFERER + stmw r29, -0x0110(r1) + lis r30, -0x01 + ori r30, r30, 0x7000 + add r30, r30, r1 + addi r31, r30, 0x2000 + addi r30, r30, 0x04 + +InitScreenConsole_0x18 + cmplw r30, r31 + addi r29, r31, 0x04 + bge- InitScreenConsole_0x2c + stwu r29, -0x1000(r31) + b InitScreenConsole_0x18 + +InitScreenConsole_0x2c + addi r31, r30, 0x1000 + stw r30, -0x0004(r31) + stw r30, -0x0404(r1) + stw r30, -0x0400(r1) + li r29, ScreenConsoleY + sth r29, -0x0360(r1) + li r29, ScreenConsoleX + sth r29, -0x035e(r1) + li r29, ScreenConsoleHeight + sth r29, -0x035c(r1) + li r29, ScreenConsoleWidth + sth r29, -0x035a(r1) + li r29, 0x5e + sth r29, -0x0358(r1) + li r29, 0x30 + sth r29, -0x0356(r1) + lmw r29, -0x0110(r1) + blr + + + +; ScreenConsole_putchar + +; Xrefs: +; PrintS +; Printd +; print_digity_common +; Printc + +; > r1 = kdp + +ScreenConsole_putchar ; OUTSIDE REFERER + lwz r30, -0x0404(r1) + stb r29, 0x0000(r30) + addi r30, r30, 0x01 + andi. r29, r30, 0xfff + stw r30, -0x0404(r1) + bnelr- + lwz r30, -0x1000(r30) + stw r30, -0x0404(r1) + blr + + + +; ScreenConsole_redraw + +; Xrefs: +; MPCall_133 +; PrintS + +; > r1 = kdp + +ScreenConsole_redraw ; OUTSIDE REFERER + stmw r2, -0x03e8(r1) + mflr r14 + mfcr r15 + stw r14, -0x03f0(r1) + stw r15, -0x03ec(r1) + addi r26, r1, -0x690 + mfsprg r2, 3 + mtsprg 3, r26 + lwz r26, 0x0edc(r1) + andi. r26, r26, 0x08 + beq- major_0x18bec + lwz r14, -0x0404(r1) + lwz r15, -0x0400(r1) + cmpw r14, r15 + beq- major_0x18bec + bl major_0x18c18 + +ScreenConsole_redraw_0x40 + li r9, 0x00 + li r10, 0x00 + li r25, 0x20 + bl major_0x18e54 + bl major_0x19018 + mflr r21 + bl major_0x18e24 + bl funny_thing + bl major_0x18e24 + bl funny_thing + lwz r14, -0x0404(r1) + lwz r15, -0x0400(r1) + li r16, 0x00 + +ScreenConsole_redraw_0x74 + cmpw r14, r15 + beq- ScreenConsole_redraw_0x118 + lbz r25, 0x0000(r15) + addi r15, r15, 0x01 + andi. r17, r15, 0xfff + bne+ ScreenConsole_redraw_0x90 + lwz r15, -0x1000(r15) + +ScreenConsole_redraw_0x90 + cmplwi r25, 0x0d + cmplwi cr1, r25, 0x0a + beq+ ScreenConsole_redraw_0x74 + beq- cr1, ScreenConsole_redraw_0xc0 + cmpwi r25, 0x00 + cmpwi cr1, r25, 0x07 + beq+ ScreenConsole_redraw_0x74 + beq- cr1, ScreenConsole_redraw_0xe4 + bl major_0x18e54 + lhz r17, -0x0358(r1) + cmpw r9, r17 + blt+ ScreenConsole_redraw_0x74 + +ScreenConsole_redraw_0xc0 + cmpwi r16, 0x00 + bne- ScreenConsole_redraw_0xcc + mr r16, r15 + +ScreenConsole_redraw_0xcc + bl funny_thing + lhz r17, -0x0356(r1) + cmpw r10, r17 + blt+ ScreenConsole_redraw_0x74 + stw r16, -0x0400(r1) + b ScreenConsole_redraw_0x40 + +ScreenConsole_redraw_0xe4 + lhz r17, -0x0356(r1) + addi r17, r17, -0x01 + cmpw r10, r17 + blt+ ScreenConsole_redraw_0x74 + lwz r17, -0x0438(r1) + slwi r25, r17, 2 + add r25, r25, r17 + mfspr r17, dec + subf r17, r25, r17 + +ScreenConsole_redraw_0x108 + mfspr r25, dec + subf. r25, r17, r25 + bge+ ScreenConsole_redraw_0x108 + b ScreenConsole_redraw_0x74 + +ScreenConsole_redraw_0x118 + bl funny_thing_0x8 + mfspr r31, pvr + rlwinm. r31, r31, 0, 0, 14 + li r31, 0x00 + bne- ScreenConsole_redraw_0x140 + mtspr ibat3l, r31 + isync + mtspr ibat3u, r18 + mtspr ibat3l, r19 + b ScreenConsole_redraw_0x150 + +ScreenConsole_redraw_0x140 + mtspr dbat3u, r31 + isync + mtspr dbat3l, r19 + mtspr dbat3u, r18 + +ScreenConsole_redraw_0x150 + isync + + + +; major_0x18bec + +; Xrefs: +; ScreenConsole_redraw +; major_0x18c18 + +major_0x18bec ; OUTSIDE REFERER + mtsprg 3, r2 + lwz r14, -0x03f0(r1) + lwz r15, -0x03ec(r1) + mtlr r14 + mtcr r15 + lmw r2, -0x03e8(r1) + blr + + + +; major_0x18c08 + +; Xrefs: +; major_0x18c18 + +major_0x18c08 ; OUTSIDE REFERER + mfsrin r31, r27 + cmpwi r31, 0x00 + beqlr- + b PagingFunc4 + + + +; major_0x18c18 + +; Xrefs: +; ScreenConsole_redraw + +major_0x18c18 ; OUTSIDE REFERER + mflr r13 + lwz r27, -0x08f8(r1) + cmpwi r27, 0x00 + bne- major_0x18c18_0x40 + lwz r27, 0x0630(r1) + lhz r31, 0x0378(r27) + cmpwi r31, 0x00 + beq- major_0x18c18_0x40 + lwz r31, 0x037c(r27) + cmpwi r31, 0x00 + beq- major_0x18c18_0x40 + stw r31, -0x08f8(r1) + lhz r31, 0x0384(r27) + sth r31, -0x08f4(r1) + lhz r31, 0x0386(r27) + sth r31, -0x08f2(r1) + +major_0x18c18_0x40 + li r27, 0x8a4 + bl major_0x18c08 + beq- major_0x18c18_0xe0 + rlwimi. r27, r31, 0, 0, 19 + ble- major_0x18c18_0xe0 + lwz r27, 0x0000(r27) + cmpwi r27, 0x00 + ble- major_0x18c18_0xe0 + bl major_0x18c08 + beq- major_0x18c18_0xe0 + rlwimi r27, r31, 0, 0, 19 + lwz r27, 0x0000(r27) + cmpwi r27, 0x00 + ble- major_0x18c18_0xe0 + addi r27, r27, 0x16 + bl major_0x18c08 + beq- major_0x18c18_0xe0 + rlwimi r27, r31, 0, 0, 19 + lwz r27, 0x0000(r27) + cmpwi r27, 0x00 + ble- major_0x18c18_0xe0 + bl major_0x18c08 + beq- major_0x18c18_0xe0 + rlwimi r27, r31, 0, 0, 19 + lwz r27, 0x0000(r27) + cmpwi r27, 0x00 + ble- major_0x18c18_0xe0 + bl major_0x18c08 + beq- major_0x18c18_0xe0 + rlwimi r27, r31, 0, 0, 19 + lwz r3, 0x0000(r27) + lhz r5, 0x0004(r27) + andi. r5, r5, 0x7fff + lhz r6, 0x0020(r27) + srwi r6, r6, 3 + cmplwi r6, 0x08 + bgt- major_0x18c18_0xe0 + stw r3, -0x08f8(r1) + sth r5, -0x08f4(r1) + sth r6, -0x08f2(r1) + +major_0x18c18_0xe0 + lwz r3, -0x08f8(r1) + lhz r5, -0x08f4(r1) + lhz r6, -0x08f2(r1) + cmpwi r3, 0x00 + bne- major_0x18d5c + b major_0x18bec + + + +; major_0x18d10 + + dc.l 0x3c608180 + dc.l 0x60630200 + dc.l 0x38a00340 + dc.l 0x38c00001 + dc.l 0x4800003c + dc.l 0x3c60a600 + dc.l 0x60638000 + dc.l 0x38a00400 + dc.l 0x38c00001 + dc.l 0x48000028 + dc.l 0x3c609600 + dc.l 0x60638000 + dc.l 0x38a00400 + dc.l 0x38c00001 + dc.l 0x48000014 + dc.l 0x3c609600 + dc.l 0x60638000 + dc.l 0x38a00400 + dc.l 0x38c00001 + + + +; major_0x18d5c + +; Xrefs: +; major_0x18c18 + +major_0x18d5c ; OUTSIDE REFERER + cmpwi cr4, r6, 0x02 + bl major_0x19ab0 + blt- cr4, major_0x18d5c_0x18 + bl major_0x19b00 + beq- cr4, major_0x18d5c_0x18 + bl load_log_colours + +major_0x18d5c_0x18 + mflr r24 + mfspr r31, pvr + rlwinm. r31, r31, 0, 0, 14 + li r31, 0x00 + bne- major_0x18d5c_0x3c + mfspr r19, ibat3l + mfspr r18, ibat3u + mtspr ibat3l, r31 + b major_0x18d5c_0x48 + +major_0x18d5c_0x3c + mfspr r18, dbat3u + mfspr r19, dbat3l + mtspr dbat3u, r31 + +major_0x18d5c_0x48 + isync + rlwinm r29, r3, 0, 0, 7 + beq- major_0x18d5c_0x70 + li r30, 0x7e + or r30, r30, r29 + li r31, 0x32 + or r31, r31, r29 + mtspr dbat3l, r31 + mtspr dbat3u, r30 + b major_0x18d5c_0x88 + +major_0x18d5c_0x70 + li r30, 0x32 + or r30, r30, r29 + li r31, 0x5f + or r31, r31, r29 + mtspr ibat3u, r30 + mtspr ibat3l, r31 + +major_0x18d5c_0x88 + isync + mfmsr r22 + lhz r29, -0x0360(r1) + lhz r30, -0x035c(r1) + subf r29, r29, r30 + li r30, 0x0a + divw r29, r29, r30 + sth r29, -0x0356(r1) + lhz r29, -0x035e(r1) + lhz r30, -0x035a(r1) + subf r29, r29, r30 + li r30, 0x06 + divw r29, r29, r30 + sth r29, -0x0358(r1) + mtlr r13 + blr + + + +; major_0x18e24 + +; Xrefs: +; ScreenConsole_redraw + +major_0x18e24 ; OUTSIDE REFERER + mflr r12 + +major_0x18e24_0x4 + lhz r25, -0x0358(r1) + cmpw cr1, r9, r25 + lbz r25, 0x0000(r21) + cmplwi r25, 0x00 + addi r21, r21, 0x01 + beq- major_0x18e24_0x28 + bge+ cr1, major_0x18e24_0x4 + bl major_0x18e54 + b major_0x18e24_0x4 + +major_0x18e24_0x28 + mtlr r12 + blr + + + +; major_0x18e54 + +; Xrefs: +; ScreenConsole_redraw +; major_0x18e24 +; funny_thing + +major_0x18e54 ; OUTSIDE REFERER + mflr r13 + cmpwi cr4, r6, 0x02 + bl load_log_font + mflr r23 + add r23, r25, r23 + mulli r27, r5, 0x0a + mullw r27, r27, r10 + mulli r7, r9, 0x06 + mullw r7, r7, r6 + add r7, r7, r27 + add r7, r7, r3 + lhz r27, -0x0360(r1) + lhz r28, -0x035e(r1) + mullw r27, r5, r27 + mullw r28, r6, r28 + add r7, r7, r27 + add r7, r7, r28 + subf. r27, r3, r7 + blt- major_0x18e54_0x174 + li r8, 0x00 + +major_0x18e54_0x50 + beq- cr4, major_0x18e54_0x9c + bgt- cr4, major_0x18e54_0xe0 + lbz r27, 0x0000(r23) + rlwinm r27, r27, 28, 28, 29 + lwzx r28, r24, r27 + lbz r27, 0x0000(r23) + rlwinm r27, r27, 0, 26, 29 + lwzx r27, r24, r27 + ori r22, r22, 0x10 + mtmsr r22 + isync + sth r28, 0x0000(r7) + sth r27, 0x0004(r7) + srwi r27, r27, 16 + sth r27, 0x0002(r7) + rlwinm r22, r22, 0, 28, 26 + mtmsr r22 + isync + b major_0x18e54_0x160 + +major_0x18e54_0x9c + lbz r28, 0x0000(r23) + rlwinm r27, r28, 28, 28, 29 + lwzx r27, r24, r27 + rlwinm r29, r28, 30, 28, 29 + lwzx r29, r24, r29 + rlwinm r30, r28, 0, 28, 29 + lwzx r30, r24, r30 + ori r22, r22, 0x10 + mtmsr r22 + isync + stw r27, 0x0000(r7) + stw r29, 0x0004(r7) + stw r30, 0x0008(r7) + rlwinm r22, r22, 0, 28, 26 + mtmsr r22 + isync + b major_0x18e54_0x160 + +major_0x18e54_0xe0 + lbz r28, 0x0000(r23) + rlwinm r27, r28, 27, 29, 29 + lwzx r27, r24, r27 + rlwinm r29, r28, 28, 29, 29 + lwzx r29, r24, r29 + rlwinm r30, r28, 29, 29, 29 + lwzx r30, r24, r30 + rlwinm r31, r28, 30, 29, 29 + lwzx r31, r24, r31 + ori r22, r22, 0x10 + mtmsr r22 + isync + stw r27, 0x0000(r7) + stw r29, 0x0004(r7) + stw r30, 0x0008(r7) + stw r31, 0x000c(r7) + rlwinm r22, r22, 0, 28, 26 + mtmsr r22 + isync + rlwinm r27, r28, 31, 29, 29 + lwzx r27, r24, r27 + rlwinm r29, r28, 0, 29, 29 + lwzx r29, r24, r29 + ori r22, r22, 0x10 + mtmsr r22 + isync + stw r27, 0x0010(r7) + stw r29, 0x0014(r7) + rlwinm r22, r22, 0, 28, 26 + mtmsr r22 + isync + b major_0x18e54_0x160 + +major_0x18e54_0x160 + addi r8, r8, 0x01 + cmplwi r8, 0x0a + add r7, r7, r5 + addi r23, r23, 0x100 + blt+ major_0x18e54_0x50 + +major_0x18e54_0x174 + addi r9, r9, 0x01 + mtlr r13 + blr + + + +; funny_thing + +; Xrefs: +; ScreenConsole_redraw + +funny_thing ; OUTSIDE REFERER + crclr cr2_eq + b funny_thing_0xc + +funny_thing_0x8 ; OUTSIDE REFERER + crset cr2_eq + +funny_thing_0xc + mflr r12 + +funny_thing_0x10 + lhz r25, -0x0358(r1) + cmpw r9, r25 + bge- funny_thing_0x28 + li r25, 0x20 + bl major_0x18e54 + b funny_thing_0x10 + +funny_thing_0x28 + beq- cr2, funny_thing_0x3c + li r9, 0x00 + addi r10, r10, 0x01 + li r25, 0x20 + bl major_0x18e54 + +funny_thing_0x3c + mtlr r12 + blr + + + +; Xrefs: +; ScreenConsole_redraw + +major_0x19018 ; OUTSIDE REFERER + + blrl + + string CString + dc.b ' NanoKernel Log ' + dc.b ' -------------- ' + align 2 + + + +; Unfortunately inaccessible + + blrl + + string CString + dc.b ' System Termination ' + dc.b ' ------------------ ' + align 2 + + + +; load_log_font + +; Xrefs: +; major_0x18e54 + +load_log_font ; OUTSIDE REFERER + blrl + dc.l 0x907070f0 + dc.l 0xf0f06000 + dc.l 0xe0008090 + dc.l 0xf0007070 + dc.l 0xe0e0e0e0 + dc.l 0xe09070f0 + dc.l 0x70f070f0 + dc.l 0xf070e090 + dc.l 0 + dc.l 0x20000000 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0x00000008 + dc.l 0x20400000 + dc.l 0x50200010 + dc.l 0x68505000 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0x70000000 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0x00001800 + dc.l 0 + dc.l 0 + dc.l 0x18000000 + dc.l 0x00000040 + dc.l 0x68680000 + dc.l 0 + dc.l 0 + dc.l 0x00500000 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0xd0808080 + dc.l 0x80809000 + dc.l 0x90008090 + dc.l 0x80088080 + dc.l 0x90909090 + dc.l 0x90d08080 + dc.l 0x80808080 + dc.l 0x80809090 + dc.l 0x00205050 + dc.l 0x70786020 + dc.l 0x10200000 + dc.l 0x00000008 + dc.l 0x70207070 + dc.l 0x10f870f8 + dc.l 0x70700000 + dc.l 0x00000070 + dc.l 0x7070f070 + dc.l 0xf0f8f870 + dc.l 0x88700888 + dc.l 0x80888870 + dc.l 0xf070f070 + dc.l 0xf8888888 + dc.l 0x8888f830 + dc.l 0x40302000 + dc.l 0x20008000 + dc.l 0x08001800 + dc.l 0x80202080 + dc.l 0x20000000 + dc.l 0 + dc.l 0x20000000 + dc.l 0x00000010 + dc.l 0x20200000 + dc.l 0x00500020 + dc.l 0xb8000010 + dc.l 0x40200068 + dc.l 0x30001040 + dc.l 0x20001040 + dc.l 0x20006810 + dc.l 0x40200068 + dc.l 0x10402000 + dc.l 0x00300060 + dc.l 0x88007830 + dc.l 0 + dc.l 0 + dc.l 0x00001040 + dc.l 0x880020f8 + dc.l 0xf8002038 + dc.l 0x30700000 + dc.l 0x20200000 + dc.l 0x20000000 + dc.l 0x00000020 + dc.l 0xb0b00000 + dc.l 0x00005050 + dc.l 0x20600000 + dc.l 0x50000000 + dc.l 0x00003030 + dc.l 0 + dc.l 0x40202010 + dc.l 0x00201020 + dc.l 0x00201020 + dc.l 0x30201020 + dc.l 0x20002068 + dc.l 0x70482020 + dc.l 0x00280050 + dc.l 0xb06060e0 + dc.l 0xe0e0f020 + dc.l 0xe0208090 + dc.l 0xe0086060 + dc.l 0x90909090 + dc.l 0x90b060e0 + dc.l 0x80e060e0 + dc.l 0xe0b0e090 + dc.l 0x002050f8 + dc.l 0xa8a89020 + dc.l 0x20102020 + dc.l 0x00000008 + dc.l 0x88608888 + dc.l 0x30808008 + dc.l 0x88880000 + dc.l 0x10004088 + dc.l 0x88888888 + dc.l 0x88808088 + dc.l 0x88200890 + dc.l 0x80d8c888 + dc.l 0x88888888 + dc.l 0x20888888 + dc.l 0x88880820 + dc.l 0x40105000 + dc.l 0x10008000 + dc.l 0x08002000 + dc.l 0x80000080 + dc.l 0x20000000 + dc.l 0 + dc.l 0x20000000 + dc.l 0x00000010 + dc.l 0x20206800 + dc.l 0x702070f8 + dc.l 0x88708820 + dc.l 0x205050b0 + dc.l 0x48002020 + dc.l 0x50502020 + dc.l 0x5050b020 + dc.l 0x205050b0 + dc.l 0x20205050 + dc.l 0x20480090 + dc.l 0x4800a848 + dc.l 0xe0e0f410 + dc.l 0x50007870 + dc.l 0x00202020 + dc.l 0x50001048 + dc.l 0x50002048 + dc.l 0x48880000 + dc.l 0x00000018 + dc.l 0x20082000 + dc.l 0x00000070 + dc.l 0x70707800 + dc.l 0x0000a050 + dc.l 0x40200000 + dc.l 0x00880884 + dc.l 0x00004048 + dc.l 0x20000000 + dc.l 0xa0505020 + dc.l 0x50102050 + dc.l 0x50102050 + dc.l 0x20102050 + dc.l 0x100050b0 + dc.l 0x00300050 + dc.l 0x00500020 + dc.l 0x90101080 + dc.l 0x80809070 + dc.l 0x9030f0a0 + dc.l 0x80281010 + dc.l 0x90909090 + dc.l 0x90901080 + dc.l 0x80801080 + dc.l 0x8090a090 + dc.l 0x00200050 + dc.l 0xa0b0a000 + dc.l 0x4008a820 + dc.l 0x00000010 + dc.l 0x98200808 + dc.l 0x50f0f008 + dc.l 0x88882020 + dc.l 0x20f82008 + dc.l 0xe8888880 + dc.l 0x88808080 + dc.l 0x882008a0 + dc.l 0x80a8a888 + dc.l 0x88888880 + dc.l 0x20888888 + dc.l 0x50881020 + dc.l 0x20108800 + dc.l 0x0078f070 + dc.l 0x78707078 + dc.l 0xf0202090 + dc.l 0x20f0b070 + dc.l 0xf078b078 + dc.l 0x708888a8 + dc.l 0x8888f810 + dc.l 0x2020b000 + dc.l 0x88708880 + dc.l 0xc8888800 + dc.l 0 + dc.l 0x30700000 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0x70482080 + dc.l 0xa000a888 + dc.l 0x10105c20 + dc.l 0x0010a088 + dc.l 0xd8204010 + dc.l 0xf8901820 + dc.l 0x50f82048 + dc.l 0x48887070 + dc.l 0x20200010 + dc.l 0x20702000 + dc.l 0x00000088 + dc.l 0x8888a000 + dc.l 0x0000a0a0 + dc.l 0x60402020 + dc.l 0x88881030 + dc.l 0x0000e8e8 + dc.l 0x70000000 + dc.l 0x40000000 + dc.l 0 + dc.l 0 + dc.l 0x58000000 + dc.l 0x00200000 + dc.l 0x00000020 + dc.l 0 + dc.l 0x90e0e0f0 + dc.l 0xf0f09070 + dc.l 0xe0f80040 + dc.l 0x8068e0e0 + dc.l 0xe0e0e0e0 + dc.l 0xe090e0f0 + dc.l 0x70f0e0f0 + dc.l 0x80609060 + dc.l 0x002000f8 + dc.l 0x70504000 + dc.l 0x400870f8 + dc.l 0x00f80010 + dc.l 0xa8201030 + dc.l 0x90088810 + dc.l 0x70880000 + dc.l 0x40001010 + dc.l 0xa8f8f080 + dc.l 0x88f0f098 + dc.l 0xf82008c0 + dc.l 0x80889888 + dc.l 0xf088f070 + dc.l 0x20888888 + dc.l 0x20502020 + dc.l 0x20100000 + dc.l 0x00888888 + dc.l 0x88882088 + dc.l 0x882020a0 + dc.l 0x20a8c888 + dc.l 0x8888c880 + dc.l 0x208888a8 + dc.l 0x50881020 + dc.l 0x20100000 + dc.l 0x88888080 + dc.l 0xa8888878 + dc.l 0x78787878 + dc.l 0x78887070 + dc.l 0x70702020 + dc.l 0x2020b070 + dc.l 0x70707070 + dc.l 0x88888888 + dc.l 0x203070e0 + dc.l 0x9030a890 + dc.l 0xc8685c00 + dc.l 0x00f8a098 + dc.l 0xa8f82020 + dc.l 0x20902810 + dc.l 0x50502038 + dc.l 0x3088a898 + dc.l 0x4020f820 + dc.l 0x70885048 + dc.l 0x90000088 + dc.l 0x8888a050 + dc.l 0 + dc.l 0x00000050 + dc.l 0x88882048 + dc.l 0x00004848 + dc.l 0x20200000 + dc.l 0x1c70f870 + dc.l 0xf8f87070 + dc.l 0x70707070 + dc.l 0xf0708888 + dc.l 0x88200000 + dc.l 0 + dc.l 0 + dc.l 0x48484848 + dc.l 0x003048f8 + dc.l 0x38307800 + dc.l 0x78f83830 + dc.l 0x00107070 + dc.l 0x10484870 + dc.l 0x00007038 + dc.l 0x38383838 + dc.l 0x00200050 + dc.l 0x2868a800 + dc.l 0x4008a820 + dc.l 0x00000020 + dc.l 0xc8202008 + dc.l 0xf8088820 + dc.l 0x88782000 + dc.l 0x20f82020 + dc.l 0xf0888880 + dc.l 0x88808088 + dc.l 0x882088a0 + dc.l 0x80888888 + dc.l 0x80888808 + dc.l 0x208888a8 + dc.l 0x50204020 + dc.l 0x10100000 + dc.l 0x00888880 + dc.l 0x88f82088 + dc.l 0x882020e0 + dc.l 0x20a88888 + dc.l 0x88888070 + dc.l 0x208888a8 + dc.l 0x20882010 + dc.l 0x20200000 + dc.l 0xf88880f0 + dc.l 0x98888888 + dc.l 0x88888888 + dc.l 0x88808888 + dc.l 0x88882020 + dc.l 0x2020c888 + dc.l 0x88888888 + dc.l 0x88888888 + dc.l 0x2000a880 + dc.l 0x48307890 + dc.l 0xa8880000 + dc.l 0x0020f0a8 + dc.l 0xd8201040 + dc.l 0xf8904820 + dc.l 0x50502000 + dc.l 0x0088b8a8 + dc.l 0x802008a0 + dc.l 0x20705090 + dc.l 0x480000f8 + dc.l 0xf888b0a8 + dc.l 0x70f80000 + dc.l 0x0000f888 + dc.l 0x88504048 + dc.l 0x10404848 + dc.l 0x20000000 + dc.l 0xe0888088 + dc.l 0x80802020 + dc.l 0x20208888 + dc.l 0xf8888888 + dc.l 0x88200000 + dc.l 0 + dc.l 0 + dc.l 0x48484848 + dc.l 0x384850f8 + dc.l 0x40204038 + dc.l 0x40601048 + dc.l 0x40300808 + dc.l 0x30504848 + dc.l 0x48884840 + dc.l 0x40404040 + dc.l 0 + dc.l 0xa8a89000 + dc.l 0x20102020 + dc.l 0x00000020 + dc.l 0x88204088 + dc.l 0x10888820 + dc.l 0x88080000 + dc.l 0x10004000 + dc.l 0x80888888 + dc.l 0x88808088 + dc.l 0x88208890 + dc.l 0x80888888 + dc.l 0x80888888 + dc.l 0x208850d8 + dc.l 0x88208020 + dc.l 0x10100000 + dc.l 0x00988880 + dc.l 0x88802088 + dc.l 0x88202090 + dc.l 0x20a88888 + dc.l 0x88888008 + dc.l 0x209850a8 + dc.l 0x50884010 + dc.l 0x20200000 + dc.l 0x88f88080 + dc.l 0x88888888 + dc.l 0x88888888 + dc.l 0x8880f8f8 + dc.l 0xf8f82020 + dc.l 0x20208888 + dc.l 0x88888888 + dc.l 0x88888888 + dc.l 0x2000a080 + dc.l 0x28002888 + dc.l 0xc8680000 + dc.l 0x00f8a0c8 + dc.l 0x00200000 + dc.l 0x20904848 + dc.l 0x50502078 + dc.l 0x7850a0c8 + dc.l 0x88200840 + dc.l 0x20808890 + dc.l 0x48000088 + dc.l 0x8888a0b8 + dc.l 0 + dc.l 0x00000050 + dc.l 0x88208030 + dc.l 0x20204848 + dc.l 0x20000000 + dc.l 0x00f8f0f8 + dc.l 0xf0f02020 + dc.l 0x20208888 + dc.l 0xf8888888 + dc.l 0x88200000 + dc.l 0 + dc.l 0 + dc.l 0x48783030 + dc.l 0x10487020 + dc.l 0x30007010 + dc.l 0x70201048 + dc.l 0x40101030 + dc.l 0x78703070 + dc.l 0x68d87040 + dc.l 0x30303030 + dc.l 0x00200000 + dc.l 0x70906800 + dc.l 0x10200000 + dc.l 0x20002040 + dc.l 0x7020f870 + dc.l 0x10707020 + dc.l 0x70700020 + dc.l 0x00000020 + dc.l 0x7088f070 + dc.l 0xf0f88070 + dc.l 0x88707088 + dc.l 0xf8888870 + dc.l 0x80708870 + dc.l 0x20702088 + dc.l 0x8820f830 + dc.l 0x083000f8 + dc.l 0x0068f078 + dc.l 0x78782078 + dc.l 0x88202088 + dc.l 0x20a88870 + dc.l 0xf07880f0 + dc.l 0x18682050 + dc.l 0x8878f810 + dc.l 0x20200000 + dc.l 0x88888880 + dc.l 0x88888898 + dc.l 0x98989898 + dc.l 0x98788080 + dc.l 0x80802020 + dc.l 0x20208888 + dc.l 0x88888888 + dc.l 0x98989898 + dc.l 0x0000a888 + dc.l 0x90002888 + dc.l 0xb0100000 + dc.l 0x0040a088 + dc.l 0x00f87070 + dc.l 0x20e830f8 + dc.l 0x50502000 + dc.l 0x00d87870 + dc.l 0x70200040 + dc.l 0x2000f848 + dc.l 0x90a80088 + dc.l 0x8888a0a0 + dc.l 0 + dc.l 0x00002020 + dc.l 0x78200084 + dc.l 0x10404848 + dc.l 0x70002050 + dc.l 0x48888088 + dc.l 0x80802020 + dc.l 0x20208888 + dc.l 0x50888888 + dc.l 0x88200000 + dc.l 0 + dc.l 0x20001000 + dc.l 0x30484848 + dc.l 0x10584800 + dc.l 0x08004010 + dc.l 0x40001048 + dc.l 0x40102008 + dc.l 0x10481048 + dc.l 0x58a84840 + dc.l 0x08080808 + dc.l 0 + dc.l 0x20000000 + dc.l 0 + dc.l 0x20000040 + dc.l 0 + dc.l 0 + dc.l 0x00000020 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0x00080000 + dc.l 0 + dc.l 0 + dc.l 0x08000000 + dc.l 0 + dc.l 0x00000008 + dc.l 0x00002000 + dc.l 0 + dc.l 0x80080000 + dc.l 0 + dc.l 0x00080008 + dc.l 0x20400000 + dc.l 0x888870f8 + dc.l 0x88707068 + dc.l 0x68686868 + dc.l 0x68207878 + dc.l 0x78782020 + dc.l 0x20208870 + dc.l 0x70707070 + dc.l 0x68686868 + dc.l 0x000070f0 + dc.l 0x880028b0 + dc.l 0x00e00000 + dc.l 0x0000b870 + dc.l 0 + dc.l 0x00800000 + dc.l 0x00002000 + dc.l 0 + dc.l 0 + dc.l 0x20000000 + dc.l 0x00000088 + dc.l 0x88707858 + dc.l 0 + dc.l 0 + dc.l 0x08200000 + dc.l 0 + dc.l 0x20002050 + dc.l 0xb488f888 + dc.l 0xf8f87070 + dc.l 0x70708888 + dc.l 0x00887070 + dc.l 0x70000000 + dc.l 0 + dc.l 0x10002000 + dc.l 0x00484848 + dc.l 0x10384800 + dc.l 0x70004010 + dc.l 0x40003830 + dc.l 0x70387870 + dc.l 0x10481070 + dc.l 0x48887038 + dc.l 0x70707070 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0x40000000 + dc.l 0 + dc.l 0 + dc.l 0x00000040 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0x00000070 + dc.l 0x0000c000 + dc.l 0 + dc.l 0x80080000 + dc.l 0 + dc.l 0x00700000 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0x00400000 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0x00002000 + dc.l 0x70000080 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0x00800000 + dc.l 0x0000c000 + dc.l 0 + dc.l 0 + dc.l 0xc0000000 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0 + dc.l 0x70000000 + dc.l 0 + dc.l 0x000040a0 + dc.l 0x48000000 + dc.l 0 + dc.l 0x00007070 + dc.l 0x00700000 + dc.l 0 + dc.l 0 + dc.l 0x30003000 + + + +; major_0x19ab0 + +; Xrefs: +; major_0x18d5c + + align 4 + +major_0x19ab0 ; OUTSIDE REFERER + blrl + dc.l 0x06060606 + dc.l 0x060606ff + dc.l 0x0606ff06 + dc.l 0x0606ffff + dc.l 0x06ff0606 + dc.l 0x06ff06ff + dc.l 0x06ffff06 + dc.l 0x06ffffff + dc.l 0xff060606 + dc.l 0xff0606ff + dc.l 0xff06ff06 + dc.l 0xff06ffff + dc.l 0xffff0606 + dc.l 0xffff06ff + dc.l 0xffffff06 + dc.l 0xffffffff + + + +; major_0x19b00 + +; Xrefs: +; major_0x18d5c + + align 4 + +major_0x19b00 ; OUTSIDE REFERER + blrl + dc.l 0xff7eff7e + dc.l 0xff7e0000 + dc.l 0x0000ff7e + dc.l 0 + + + +; load_log_colours + +; Each word is RGB with the high byte ignored. Background +; and text. + +; Xrefs: +; major_0x18d5c + + align 4 + +load_log_colours ; OUTSIDE REFERER + blrl + dc.l ScreenConsoleBG + dc.l ScreenConsoleFG diff --git a/NanoKernel/NKSleep.s b/NanoKernel/NKSleep.s new file mode 100644 index 0000000..4fc5d61 --- /dev/null +++ b/NanoKernel/NKSleep.s @@ -0,0 +1,598 @@ +; Implements two MPCalls that seem to have something to do with COHGs + + + +; Make conditional calls easier +Local_Panic set * + b panic + +Local_ReturnParamErrFromMPCall + b ReturnParamErrFromMPCall + +Local_ReturnInsufficientResourcesErrFromMPCall + b ReturnMPCallOOM + +Local_CommonMPCallReturnPath + b CommonMPCallReturnPath + + + + DeclareMPCall 102, MPCall_102 + +MPCall_102 ; OUTSIDE REFERER + mfsprg r9, 0 + lwz r8, EWA.CPUBase + CPU.CgrpList + LLL.Freeform(r9) + lwz r9, CoherenceGroup.ScheduledCpuCount(r8) + cmpwi r9, 1 + bgt+ Local_ReturnInsufficientResourcesErrFromMPCall + bl CoherenceFunc + mr r4, r8 + mr r5, r9 + b ReturnZeroFromMPCall + + + + DeclareMPCall 103, MPCall_103 + +MPCall_103 ; OUTSIDE REFERER + mfsprg r9, 0 + lwz r8, EWA.CPUBase + CPU.CgrpList + LLL.Freeform(r9) + lwz r9, CoherenceGroup.ScheduledCpuCount(r8) + cmpwi r9, 1 + bgt+ Local_ReturnInsufficientResourcesErrFromMPCall + + clrlwi. r8, r5, 20 + bne+ Local_ReturnParamErrFromMPCall + bl CoherenceFunc + cmpw r3, r8 + blt+ Local_ReturnParamErrFromMPCall + cmpw r4, r9 + blt+ Local_ReturnParamErrFromMPCall + bl PagingFlushTLB + mfsprg r9, 0 + mfxer r8 + stw r13, 0x00dc(r6) + stw r8, 0x00d4(r6) + stw r12, 0x00ec(r6) + mfctr r8 + stw r10, 0x00fc(r6) + stw r8, 0x00f4(r6) + + mfpvr r8 + rlwinm. r8, r8, 0, 0, 14 + bne- @not_601 + mfspr r8, mq + stw r8, ContextBlock.MQ(r6) +@not_601 + + lwz r8, EWA.r1(r9) + stw r8, ContextBlock.r1(r6) + stw r2, ContextBlock.r2(r6) + stw r3, ContextBlock.r3(r6) + andi. r8, r11, MSR_FP + stw r4, ContextBlock.r4(r6) + lwz r8, EWA.r6(r9) + stw r5, ContextBlock.r5(r6) + stw r8, ContextBlock.r6(r6) + bnel+ Save_f0_f31 + rlwinm. r8, r7, 0, 12, 12 ; flags + bnel+ Save_v0_v31 + + lwz r3, ContextBlock.r3(r6) + lwz r4, ContextBlock.r4(r6) + lwz r5, ContextBlock.r5(r6) + + stw r11,ContextBlock.MSR(r6) + mr r27, r5 + addi r29, r1, 800 + bl PagingFunc3 + beq+ Local_ReturnInsufficientResourcesErrFromMPCall + rlwimi r27, r31, 0, 0, 19 + mr r17, r27 + addi r15, r17, 0x34 + srwi r3, r3, 12 + +MPCall_103_0xc8 + mr r27, r5 + addi r29, r1, 800 + bl PagingFunc3 + beq+ Local_ReturnInsufficientResourcesErrFromMPCall + rlwimi r27, r31, 0, 0, 19 + stwu r27, 0x0004(r15) + addi r3, r3, -0x01 + addi r5, r5, 0x1000 + cmpwi r3, 0x00 + bge+ MPCall_103_0xc8 + addi r15, r15, 0x04 + subf r15, r17, r15 + stw r15, 0x0034(r17) + mfsprg r15, 0 + stw r15, 0x0024(r17) + mfsprg r8, 3 + stw r8, 0x0028(r17) + +MPCall_103_0x10c + mftbu r8 + mftb r9, 0x10c + mftbu r16 + cmpw r16, r8 + bne- MPCall_103_0x10c + stw r8, -0x0278(r15) + stw r9, -0x0274(r15) + mr r29, r17 + li r16, 0x06 + stw r16, -0x0238(r15) + lhz r16, -0x0116(r15) + stw r16, -0x0234(r15) + li r8, 0x02 + +; r7 = flags +; r8 = usually 2? + bl SIGP + mr r17, r29 + mfsdr1 r8 + stw r8, 0x002c(r17) + rlwinm r9, r8, 16, 7, 15 + cntlzw r18, r9 + li r9, -0x01 + srw r9, r9, r18 + addi r9, r9, 0x01 + stw r9, 0x000c(r17) + rlwinm r8, r8, 0, 0, 15 + stw r8, 0x0010(r17) + lis r8, 0x00 + ori r8, r8, 0xc000 + stw r8, 0x0018(r17) + lis r9, 0x00 + ori r9, r9, 0xa000 + subf r8, r9, r1 + stw r8, 0x001c(r17) + addi r9, r1, 120 + lis r31, 0x00 + li r14, 0x00 + lwz r29, 0x0034(r17) + add r29, r29, r17 + +MPCall_103_0x1a0 + lwzu r30, 0x0008(r9) + +MPCall_103_0x1a4 + lwz r18, 0x0004(r30) + lhz r15, 0x0000(r30) + andi. r19, r18, 0xe00 + lhz r16, 0x0002(r30) + cmplwi r19, 0xc00 + bne- MPCall_103_0x1dc + addi r16, r16, 0x01 + slwi r16, r16, 2 + stw r16, 0x0000(r29) + rlwinm r18, r18, 22, 0, 29 + stw r18, 0x0004(r29) + addi r29, r29, 0x0c + addi r14, r14, 0x01 + b MPCall_103_0x1fc + +MPCall_103_0x1dc + cmpwi r15, 0x00 + bne- MPCall_103_0x1fc + cmplwi r16, 0xffff + bne- MPCall_103_0x1fc + addis r31, r31, 0x1000 + cmpwi r31, 0x00 + bne+ MPCall_103_0x1a0 + b MPCall_103_0x204 + +MPCall_103_0x1fc + addi r30, r30, 0x08 + b MPCall_103_0x1a4 + +MPCall_103_0x204 + lwz r16, -0x0aa0(r1) + +MPCall_103_0x208 + lwz r31, 0x0000(r16) + add r18, r31, r16 + lwz r19, 0x0000(r18) + addi r31, r31, 0x18 + stw r31, 0x0000(r29) + stw r16, 0x0004(r29) + addi r29, r29, 0x0c + addi r14, r14, 0x01 + cmpwi r19, 0x00 + beq- MPCall_103_0x238 + add r16, r19, r18 + b MPCall_103_0x208 + +MPCall_103_0x238 + addi r19, r1, -0x450 + lwz r31, -0x0448(r1) + +MPCall_103_0x240 + cmpw r31, r19 + beq- MPCall_103_0x264 + li r18, 0x10 + stw r18, 0x0000(r29) + stw r31, 0x0004(r29) + addi r29, r29, 0x0c + addi r14, r14, 0x01 + lwz r31, 0x0008(r31) + b MPCall_103_0x240 + +MPCall_103_0x264 + stw r14, 0x0030(r17) + lwz r30, 0x0034(r17) + add r30, r30, r17 + +MPCall_103_0x270 + subf r8, r17, r29 + stw r8, 0x0008(r30) + lwz r24, 0x0004(r30) + mr r25, r8 + lwz r26, 0x0000(r30) + add r29, r29, r26 + bl AnotherCoherenceFunc + addi r30, r30, 0x0c + addi r14, r14, -0x01 + cmpwi r14, 0x00 + bne+ MPCall_103_0x270 + subf r8, r17, r29 + stw r8, 0x0020(r17) + lwz r24, 0x001c(r17) + mr r25, r8 + lwz r26, 0x0018(r17) + add r29, r29, r26 + bl AnotherCoherenceFunc + subf r8, r17, r29 + stw r8, 0x0014(r17) + lwz r24, 0x0010(r17) + mr r25, r8 + lwz r26, 0x000c(r17) + add r29, r29, r26 + bl AnotherCoherenceFunc + bl LoadStateRestoreFunc + mflr r9 + stw r9, 0x0000(r17) + lwz r8, -0x0900(r1) + stw r8, 0x0008(r17) + li r8, 0x00 + stw r8, 0x0004(r17) + mfsprg r15, 0 + li r16, 0x11 + stw r16, -0x0238(r15) + lhz r16, -0x0116(r15) + stw r16, -0x0234(r15) + li r8, 0x02 + +; r7 = flags +; r8 = usually 2? + bl SIGP + li r3, 0x00 + b Local_CommonMPCallReturnPath + + + +LoadStateRestoreFunc + blrl + + mr r17, r3 + lwz r24, 0x0014(r17) + lwz r25, 0x0010(r17) + lwz r26, 0x000c(r17) + bl YetAnotherCoherenceFunc + lwz r24, 0x002c(r17) + mtsdr1 r24 + lwz r24, 0x0020(r17) + lwz r25, 0x001c(r17) + lwz r26, 0x0018(r17) + bl YetAnotherCoherenceFunc + lwz r14, 0x0030(r17) + lwz r30, 0x0034(r17) + add r30, r30, r17 + +RestoreKernelState_0x38 + lwz r24, 0x0008(r30) + lwz r25, 0x0004(r30) + lwz r26, 0x0000(r30) + bl YetAnotherCoherenceFunc + addi r30, r30, 0x0c + addi r14, r14, -0x01 + cmpwi r14, 0x00 + bne+ RestoreKernelState_0x38 + lwz r16, 0x0024(r17) + mtsprg 0, r16 + lwz r8, 0x0028(r17) + mtsprg 3, r8 + lwz r1, -0x0004(r16) + lwz r6, -0x0014(r16) + lwz r7, -0x0010(r16) + li r8, -0x01 + stw r8, 0x0004(r17) + lwz r8, -0x0278(r16) + lwz r9, -0x0274(r16) + li r16, 0x01 + mttb r16 + mttbu r8 + mttb r9 + mtdec r16 + _log 'Resuming saved kernel state^n' + lwz r8, 0x00d4(r6) + lwz r13, 0x00dc(r6) + mtxer r8 + lwz r12, 0x00ec(r6) + lwz r8, 0x00f4(r6) + lwz r10, 0x00fc(r6) + mtctr r8 + lwz r11, 0x00a4(r6) + mfpvr r8 + rlwinm. r8, r8, 0, 0, 14 + bne- RestoreKernelState_0xf8 + lwz r8, 0x00c4(r6) + DIALECT POWER + mtmq r8 + DIALECT PowerPC + +RestoreKernelState_0xf8 + lwz r4, -0x0020(r1) + li r2, 0x01 + sth r2, 0x0910(r1) + li r2, -0x01 + stw r2, 0x0912(r1) + stw r2, 0x0f90(r4) + xoris r2, r2, 0x100 + stw r2, 0x0f8c(r4) + li r2, 0x00 + stw r2, 0x0f28(r4) + stw r2, 0x0f2c(r4) + lwz r2, 0x0114(r6) + lwz r4, 0x0124(r6) + lwz r5, 0x012c(r6) + lwz r29, 0x00d8(r6) + cmpwi r29, 0x00 + lwz r8, 0x0210(r29) + beq- RestoreKernelState_0x144 + mtspr vrsave, r8 + +RestoreKernelState_0x144 + bl PagingFlushTLB + addi r29, r1, 0x5e0 + bl PagingFunc2AndAHalf + mfsprg r15, 0 + lwz r8, -0x001c(r15) + li r9, 0x00 + bl SetAddrSpcRegisters + isync + mfsprg r15, 0 + li r16, 0x07 + stw r16, -0x0238(r15) + lhz r16, -0x0116(r15) + stw r16, -0x0234(r15) + li r8, 0x02 + +; r7 = flags +; r8 = usually 2? + bl SIGP + mfsprg r15, 0 + li r16, 0x11 + stw r16, -0x0238(r15) + lhz r16, -0x0116(r15) + stw r16, -0x0234(r15) + li r8, 0x02 + +; r7 = flags +; r8 = usually 2? + bl SIGP + li r3, 0x00 + b Local_CommonMPCallReturnPath + + + +; Xrefs: +; MPCall_102 +; MPCall_103 +; AnotherCoherenceFunc +; YetAnotherCoherenceFunc + +CoherenceFunc ; OUTSIDE REFERER + li r24, 0x00 + mfsdr1 r16 + rlwinm r16, r16, 16, 7, 15 + cntlzw r17, r16 + li r16, -0x01 + srw r16, r16, r17 + addi r8, r16, 0x01 + addi r9, r1, 120 + lis r31, 0x00 + li r19, 0x00 + li r14, 0x00 + +CoherenceFunc_0x2c + lwzu r17, 0x0008(r9) + +CoherenceFunc_0x30 + lwz r18, 0x0004(r17) + lhz r15, 0x0000(r17) + andi. r18, r18, 0xe00 + lhz r16, 0x0002(r17) + cmplwi r18, 0xc00 + bne- CoherenceFunc_0x58 + addi r16, r16, 0x01 + add r19, r19, r16 + addi r14, r14, 0x01 + b CoherenceFunc_0x78 + +CoherenceFunc_0x58 + cmpwi r15, 0x00 + bne- CoherenceFunc_0x78 + cmplwi r16, 0xffff + bne- CoherenceFunc_0x78 + addis r31, r31, 0x1000 + cmpwi r31, 0x00 + bne+ CoherenceFunc_0x2c + b CoherenceFunc_0x80 + +CoherenceFunc_0x78 + addi r17, r17, 0x08 + b CoherenceFunc_0x30 + +CoherenceFunc_0x80 + slwi r19, r19, 2 + add r8, r8, r19 + cmpwi r14, 0x00 + beq+ Local_ReturnInsufficientResourcesErrFromMPCall + mulli r9, r14, 0x0c + add r8, r8, r9 + add r24, r24, r9 + li r9, 0x00 + li r14, 0x00 + lwz r16, -0x0aa0(r1) + +CoherenceFunc_0xa8 + lwz r17, 0x0000(r16) + add r18, r17, r16 + lwz r19, 0x0000(r18) + add r9, r9, r17 + addi r9, r9, 0x18 + addi r14, r14, 0x01 + cmpwi r19, 0x00 + add r16, r19, r18 + beq- CoherenceFunc_0xd0 + b CoherenceFunc_0xa8 + +CoherenceFunc_0xd0 + addi r16, r1, -0x450 + lwz r18, -0x0448(r1) + +CoherenceFunc_0xd8 + cmpw r18, r16 + beq- CoherenceFunc_0xf0 + addi r9, r9, 0x10 + addi r14, r14, 0x01 + lwz r18, 0x0008(r18) + b CoherenceFunc_0xd8 + +CoherenceFunc_0xf0 + add r8, r8, r9 + mulli r9, r14, 0x0c + add r8, r8, r9 + add r24, r24, r9 + lis r9, 0x00 + ori r9, r9, 0xc000 + add r8, r8, r9 + lis r9, 0x00 + ori r9, r9, 0x3c + add r8, r8, r9 + add r24, r24, r9 + srwi r9, r8, 12 + slwi r9, r9, 2 + addi r9, r9, 0x04 + add r8, r8, r9 + add r24, r24, r9 + mr r9, r24 + blr + +CoherenceFunc_0x138 ; OUTSIDE REFERER + srwi r23, r28, 12 + slwi r23, r23, 2 + add r23, r23, r17 + lwz r23, 0x0038(r23) + rlwimi r23, r28, 0, 20, 31 + blr + + + +; Xrefs: +; MPCall_103 + +AnotherCoherenceFunc ; OUTSIDE REFERER + cmpwi r26, 0x00 + beqlr- + mflr r22 + addi r24, r24, -0x01 + mr r28, r25 + +AnotherCoherenceFunc_0x14 + bl CoherenceFunc_0x138 + clrlwi r25, r23, 0x14 + subfic r25, r25, 0x1000 + cmplw r25, r26 + blt- AnotherCoherenceFunc_0x2c + mr r25, r26 + +AnotherCoherenceFunc_0x2c + mr r19, r23 + mr r20, r25 + addi r23, r23, -0x01 + mtctr r25 + +AnotherCoherenceFunc_0x3c + lbzu r27, 0x0001(r24) + stbu r27, 0x0001(r23) + bdnz+ AnotherCoherenceFunc_0x3c + bl YetAnotherCoherenceFunc_0x64 + subf r26, r25, r26 + add r28, r28, r25 + cmpwi r26, 0x00 + bne+ AnotherCoherenceFunc_0x14 + mtlr r22 + blr + + + +; Xrefs: +; RestoreKernelState +; AnotherCoherenceFunc + +YetAnotherCoherenceFunc ; OUTSIDE REFERER + cmpwi r26, 0x00 + beqlr- + mr r19, r25 + mr r20, r26 + mflr r22 + addi r25, r25, -0x01 + mr r28, r24 + +YetAnotherCoherenceFunc_0x1c + bl CoherenceFunc_0x138 + clrlwi r24, r23, 0x14 + subfic r24, r24, 0x1000 + cmplw r24, r26 + blt- YetAnotherCoherenceFunc_0x34 + mr r24, r26 + +YetAnotherCoherenceFunc_0x34 + addi r23, r23, -0x01 + mtctr r24 + +YetAnotherCoherenceFunc_0x3c + lbzu r27, 0x0001(r23) + stbu r27, 0x0001(r25) + bdnz+ YetAnotherCoherenceFunc_0x3c + add r28, r28, r24 + subf r26, r24, r26 + cmpwi r26, 0x00 + bne+ YetAnotherCoherenceFunc_0x1c + bl YetAnotherCoherenceFunc_0x64 + mtlr r22 + blr + +YetAnotherCoherenceFunc_0x64 ; OUTSIDE REFERER + sync + isync + lhz r21, 0x0f4a(r1) + addi r15, r21, -0x01 + add r20, r19, r20 + add r20, r20, r15 + neg r15, r21 + and r19, r19, r15 + and r20, r20, r15 + +YetAnotherCoherenceFunc_0x88 + dcbst 0, r19 + sync + icbi 0, r19 + add r19, r19, r21 + cmpw r19, r20 + blt+ YetAnotherCoherenceFunc_0x88 + sync + isync + blr diff --git a/NanoKernel/NKTasks.s b/NanoKernel/NKTasks.s new file mode 100644 index 0000000..f62ae57 --- /dev/null +++ b/NanoKernel/NKTasks.s @@ -0,0 +1,1569 @@ +; This file mostly provides MPCall implementations related to multitasking. +; We won't understand this very well until someone disassembles MPLibrary. + + + +Local_Panic set * + b panic + + + + DeclareMPCall 7, MPCall_7 + +MPCall_7 ; OUTSIDE REFERER + rlwinm. r8, r5, 0, 31, 28 + bne+ ReturnMPCallOOM + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Process.kIDClass + + mr r30, r8 + bne+ ReleaseAndReturnMPCallInvalidIDErr + lwz r16, 0x0008(r30) + rlwinm. r17, r16, 0, 30, 30 + bne+ ReleaseAndReturnMPCallOOM + bl CreateTask + mr. r31, r8 + beq+ major_0x0af60 + mfsprg r15, 0 + lwz r17, 0x0000(r31) + stw r17, 0x0154(r6) + lhz r16, -0x0116(r15) + sth r16, 0x001a(r31) + addi r16, r31, 0x100 + lwz r17, 0x013c(r6) + stw r17, 0x0164(r16) + lwz r17, 0x0144(r6) + stw r17, 0x00fc(r16) + lwz r17, 0x014c(r6) + stw r17, 0x0114(r16) + stw r4, 0x0098(r31) + lwz r17, 0x0134(r6) + stw r17, 0x00ec(r31) + lwz r16, 0x0064(r28) + rlwinm. r8, r5, 0, 30, 30 + beq- MPCall_7_0x98 + oris r16, r16, 0x40 + +MPCall_7_0x98 + rlwinm. r8, r5, 0, 29, 29 + beq- MPCall_7_0xa4 + oris r16, r16, 0x02 + +MPCall_7_0xa4 + stw r16, 0x0064(r28) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + +;Xrefs: +;setup +;major_0x0bb20 +;major_0x0e284 + + +; ARG EmpiricalCpuFeatures r7, Process *r8 +; RET Task *r8 + + +CreateTask + + ; Save arg and lr for later + mr r27, r8 + mflr r29 + + +; Create the 1k TASK struct in the pool and give it an ID, leave ptr in r28 + + li r8, 0x400 ;Task.Size + bl PoolAlloc + mr. r28, r8 + beq- @fail_oom + + ; Allocate an opaque ID for it + li r9, Task.kIDClass + bl MakeID + cmpwi r8, 0 + beq- @fail_no_id + + ; ID and sign it + stw r8, Task.ID(r28) + + lisori r8, Task.kSignature + stw r8, Task.Signature(r28) + + ; Untitled. Usually set to creator code of owning MacOS process + lisori r8, '----' + stw r8, Task.Name(r28) + + + +; Create a subordinate notification struct -- NOPENOPENOPE + + li r8, 0x1c ;Notification.Size + bl PoolAlloc + cmpwi r8, 0 + stw r8, Task.NotificationPtr(r28) + beq- @fail_note_oom + + lisori r9, 'note' + stw r9, 4(r8) + + + +; Create a semaphore struct inside the task +; (NOT a semaphore queue) + + addi r16, r28, Task.SemaphoreLLL + StartLoadingWord r17, 'SEMA' + stw r16, LLL.Next(r16) + FinishLoadingWord + stw r16, LLL.Prev(r16) + stw r17, LLL.Signature(r16) + + + +; Might be part of the SEMA? + + li r16, 1 + stw r16, Task.One(r28) + li r16, 0 + stw r16, Task.Zero(r28) + + + +; Allocate an ID for the SEMA + + addi r8, r28, Task.SemaphoreLLL + li r9, Semaphore.kIDClass + bl MakeID + cmpwi r8, 0 + beq- @fail_semq_no_id + stw r8, Task.SemaphoreLLL + LLL.Freeform(r28) + + + +; Allocate a vector (i.e. AltiVec) save area + + ; Conditionally, that is + rlwinm. r8, r7, 0, PSA.AVFeatureBit, PSA.AVFeatureBit + beq- @non_altivec_task + + ; Allocate and check + li r8, 0x214 ;VectorSaveArea.Size ; room for v registers plus 20 bytes + bl PoolAlloc + andi. r9, r8, 16-1 ; Sanity check: aligned to size of vector register? + cmpwi cr1, r8, 0 + bne+ Local_Panic + beq- cr1, @fail_altivec_oom + + ; Point to it (from inside and outside the ECB-like area) + stw r8, Task.VectorSaveArea(r28) + stw r8, Task.ContextBlock + ContextBlock.VectorSaveArea(r28) + + ; Fill the actual register parts with 0x7fffffff + li r16, 0x80 ;VectorSaveArea.RegisterAreaSize / 4 + subi r8, r8, 4 + lwz r17, PSA.VectorRegInitWord(r1) +@vectorarea_copyloop + subi r16, r16, 1 + stwu r17, 4(r8) + cmpwi r16, 0 + bgt+ @vectorarea_copyloop +@non_altivec_task + + + ; Some unexplored DLYQ stuff + + addi r16, r1, PSA.DelayQueue + addi r17, r28, 0x08 + stw r16, 0x0000(r17) + stw r16, 0x0008(r17) + lwz r18, 0x000c(r16) + stw r18, 0x000c(r17) + stw r17, 0x0008(r18) + stw r17, 0x000c(r16) + + + + li r16, 0 + stb r16, Task.MysteryByte1(r28) + + li r16, 9 + stw r16, 0x0064(r28) + + lisori r16, 'time' + stw r16, 0x0024(r28) + + li r16, 1 + stb r16, 0x0036(r28) + + li r16, 100 + stw r16, Task.Weight(r28) + + li r16, Task.kNominalPriority + stb r16, Task.Priority(r28) + + + + + addi r16, r28, Task.ContextBlock + stw r16, Task.ContextBlockPtr(r28) ; overridden to real ECB on blue + + lwz r16, PSA.EmpiricalCpuFeatures(r1) + stw r16, Task.ContextBlock + ContextBlock.EmpiricalCpuFeatures(r28) + + lwz r16, PSA.UserModeMSR(r1) + stw r16, Task.ContextBlock + ContextBlock.MSR(r28) + + addi r16, r1, KDP.YellowVecBase + stw r16, Task.YellowVecTblPtr(r28) + + li r16, 0 + lwz r17, Task.NotificationPtr(r28) + stw r16, 0x0010(r17) + stw r16, 0x0014(r17) + li r16, -0x7271 + stw r16, 0x0018(r17) + + li r16, 0 + stw r16, Task.Zero1(r28) + stw r16, Task.Zero2(r28) + stw r16, Task.Zero3(r28) + stw r16, Task.Zero4(r28) + stw r16, Task.Zero5(r28) + + ; Who knows that these are for + bl GetTime + + stw r8, Task.CreateTime1(r28) + stw r9, Task.CreateTime1 + 4(r28) + + stw r8, Task.CreateTime2(r28) + stw r9, Task.CreateTime2 + 4(r28) + + stw r8, Task.CreateTime3(r28) + stw r9, Task.CreateTime3 + 4(r28) + + lwz r16, KDP.NanoKernelInfo + NKNanoKernelInfo.TaskCount(r1) + addi r16, r16, 1 + stw r16, KDP.NanoKernelInfo + NKNanoKernelInfo.TaskCount(r1) + + ; Squeeze some info (including my owning process) out of the passed PROC ptr + stw r27, Task.OwningProcessPtr(r28) + + lwz r16, Process.ID(r27) + stw r16, Task.ProcessID(r28) + + lwz r17, Process.SystemAddressSpacePtr(r27) + stw r17, Task.AddressSpacePtr(r28) + + lwz r16, AddressSpace.TaskCount(r17) + addi r16, r16, 1 + stw r16, AddressSpace.TaskCount(r17) + + lwz r16, Process.TaskCount(r27) + addi r16, r16, 1 + stw r16, Process.TaskCount(r27) + + ; Restore and return + mtlr r29 + mr r8, r28 + blr + +@fail_altivec_oom + lwz r8, 0x00a0(r28) + bl DeleteID + +@fail_semq_no_id: + lwz r8, 0x009c(r28) + bl PoolFree + +@fail_note_oom + lwz r8, 0x0000(r28) + bl DeleteID + +@fail_no_id + mr r8, r28 + bl PoolFree + +@fail_oom + mtlr r29 + li r8, 0 + blr + + + + DeclareMPCall 8, MPCall_8 + +MPCall_8 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Task.kIDClass + + mr r31, r8 + bne+ ReleaseAndReturnMPCallInvalidIDErr + lbz r16, 0x0018(r31) + cmpwi r16, 0x00 + bne+ ReleaseAndReturnMPCallOOM + lwz r8, 0x0060(r31) + +; r8 = id + bl LookupID + cmpwi r9, Process.kIDClass + + bne+ Local_Panic + lwz r16, 0x0008(r8) + rlwinm. r17, r16, 0, 30, 30 + bne+ ReleaseAndReturnMPCallOOM + lwz r30, 0x0088(r31) + stw r4, 0x0074(r31) + stw r5, 0x011c(r30) + lwz r18, 0x009c(r31) + lwz r16, 0x0134(r6) + lwz r17, 0x013c(r6) + stw r16, 0x0010(r18) + stw r17, 0x0014(r18) + lwz r16, 0x0144(r6) + lwz r17, 0x014c(r6) + stw r16, 0x010c(r30) + stw r16, 0x0090(r31) + stw r17, 0x0094(r31) + addi r16, r31, 0x08 + lwz r17, 0x0008(r16) + lwz r18, 0x000c(r16) + stw r17, 0x0008(r18) + stw r18, 0x000c(r17) + li r17, 0x00 + stw r17, 0x0008(r16) + stw r17, 0x000c(r16) + mr r8, r31 + bl TaskReadyAsPrev + bl CalculateTimeslice + bl major_0x14af8 + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + +; MPCall_9 + +; Xrefs: +; kcMPDispatch +; MPCall_58 + + DeclareMPCall 9, MPCall_9 + +MPCall_9 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID +; r8 = something not sure what +; r9 = 0:inval, 1:proc, 2:task, 3:timer, 4:q, 5:sema, 6:cr, 7:cpu, 8:addrspc, 9:evtg, 10:cohg, 11:area, 12:not, 13:log + + mr r31, r8 + cmpwi r9, 0x02 + bne+ ReleaseAndReturnMPCallInvalidIDErr + lwz r16, 0x0064(r31) + lbz r17, 0x0018(r31) + rlwinm. r18, r16, 0, 30, 30 + cmpwi cr1, r17, 0x00 + bne+ ReleaseAndReturnMPCallOOM + beq- cr1, MPCall_9_0xb4 + mfsprg r15, 0 + lhz r18, 0x001a(r31) + lhz r17, -0x0116(r15) + cmpw r18, r17 + beq- MPCall_9_0xe0 + ori r16, r16, 0x400 + stw r16, 0x0064(r31) + li r17, 0x01 + stb r17, 0x0019(r31) + mr r8, r31 + bl major_0x14af8_0xa0 + sync + lwz r16, PSA.SchLock + Lock.Count(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + bne+ cr1, MPCall_9_0x8c + mflr r16 + bl panic + +MPCall_9_0x8c + stw r16, PSA.SchLock + Lock.Count(r1) + subi r10, r10, 4 + b MPCall_6_0x78 + +MPCall_9_0x98 ; OUTSIDE REFERER + lwz r16, 0x0064(r31) + ori r16, r16, 0x02 + stw r16, 0x0064(r31) + lwz r17, 0x009c(r31) + li r16, -0x7271 + stw r16, 0x0018(r17) + b MPCall_9_0xfc + +MPCall_9_0xb4 + ori r16, r16, 0x02 + stw r16, 0x0064(r31) + addi r16, r31, 0x08 + lwz r17, 0x0008(r16) + lwz r18, 0x000c(r16) + stw r17, 0x0008(r18) + stw r18, 0x000c(r17) + li r17, 0x00 + stw r17, 0x0008(r16) + stw r17, 0x000c(r16) + b MPCall_9_0xf0 + +MPCall_9_0xe0 + ori r16, r16, 0x02 + stw r16, 0x0064(r31) + mr r8, r31 + bl major_0x13e4c + +MPCall_9_0xf0 + lwz r17, 0x009c(r31) + li r3, 0x00 + stw r4, 0x0018(r17) + +MPCall_9_0xfc + addi r16, r1, -0xa44 + addi r17, r31, 0x08 + stw r16, 0x0000(r17) + stw r16, 0x0008(r17) + lwz r18, 0x000c(r16) + stw r18, 0x000c(r17) + stw r17, 0x0008(r18) + stw r17, 0x000c(r16) + lbz r8, 0x0037(r31) + cmpwi r8, 0x01 + bne- MPCall_9_0x130 + addi r8, r31, 0x20 + bl major_0x136c8 + +MPCall_9_0x130 + lwz r8, 0x0098(r31) + +; r8 = id + bl LookupID + cmpwi r9, Queue.kIDClass + + li r18, 0x00 + lwz r17, 0x009c(r31) + stw r18, 0x009c(r31) + bne- MPCall_9_0x15c + mr r31, r8 + mr r8, r17 + bl major_0x0c8b4 + b ReleaseAndReturnMPCall + +MPCall_9_0x15c + mr r8, r17 + bl PoolFree + b ReleaseAndReturnMPCall + + + + DeclareMPCall 10, MPCall_10 + +MPCall_10 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Task.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + lbz r16, 0x0018(r31) + cmpwi r16, 0x00 + bne+ ReleaseAndReturnMPCallOOM + lwz r16, 0x0064(r31) + rlwinm. r16, r16, 0, 30, 30 + beq+ ReleaseAndReturnMPCallOOM + mr r8, r31 + bl TasksFuncThatIsNotAMPCall + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + +TasksFuncThatIsNotAMPCall + mflr r27 + mr r26, r8 + addi r16, r26, 0x08 + lwz r17, 0x0008(r16) + lwz r18, 0x000c(r16) + stw r17, 0x0008(r18) + stw r18, 0x000c(r17) + li r17, 0x00 + stw r17, 0x0008(r16) + stw r17, 0x000c(r16) + lwz r8, 0x0000(r26) + bl DeleteID + lwz r8, 0x00a0(r26) + bl DeleteID + lwz r8, 0x009c(r26) + cmpwi r8, 0x00 + beq- @_0x98 + bl PoolFree + +@_0x98 + lwz r8, 0x008c(r26) + cmpwi r8, 0x00 + beq- @_0xa8 + bl PoolFree + +@_0xa8 + lwz r17, 0x006c(r26) + lwz r16, 0x0010(r17) + addi r16, r16, -0x01 + stw r16, 0x0010(r17) + lwz r17, 0x0070(r26) + lwz r16, 0x000c(r17) + addi r16, r16, -0x01 + stw r16, 0x000c(r17) + mr r8, r26 + bl PoolFree + lwz r16, 0x0ecc(r1) + addi r16, r16, -0x01 + stw r16, 0x0ecc(r1) + mtlr r27 + blr + + + + DeclareMPCall 11, MPCall_11 + +MPCall_11 ; OUTSIDE REFERER + mfsprg r16, 0 + cmpwi r3, 0x00 + lwz r17, -0x08f0(r1) + lwz r18, -0x0008(r16) + lwz r19, 0x0000(r17) + bne- MPCall_11_0x1c + lwz r3, 0x0000(r18) + +MPCall_11_0x1c + cmpw r3, r19 + li r3, 0x01 + beq+ CommonMPCallReturnPath + li r3, 0x00 + b CommonMPCallReturnPath + + + + DeclareMPCall 12, MPCall_12 + +MPCall_12 ; OUTSIDE REFERER + mfsprg r14, 0 + lwz r15, -0x0008(r14) + lwz r3, 0x0000(r15) + lwz r4, 0x00ec(r15) + b CommonMPCallReturnPath + + + + DeclareMPCall 14, MPCall_14 + +MPCall_14 ; OUTSIDE REFERER + cmpwi r4, 0x01 + cmpwi cr1, r4, 10000 + blt+ ReturnMPCallInvalidIDErr + bgt+ cr1, ReturnMPCallInvalidIDErr + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Task.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + lbz r16, 0x0018(r31) + cmpwi r16, 0x01 + bne- MPCall_14_0x70 + lwz r16, 0x0008(r31) + lwz r17, 0x001c(r31) + lwz r18, 0x0014(r16) + subf r17, r17, r4 + add r18, r17, r18 + cmpwi r17, 0x00 + stw r18, 0x0014(r16) + beq- MPCall_14_0x70 + mr r8, r31 + bl major_0x14af8_0xa0 + +MPCall_14_0x70 + stw r4, 0x001c(r31) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 56, MPCall_56 + +MPCall_56 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Task.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + mr r8, r4 + +; r8 = id + bl LookupID + cmpwi r9, 0 ; invalid + + cmpwi cr1, r9, 0x04 + beq- MPCall_56_0x44 + bne+ cr1, ReleaseAndReturnMPCallInvalidIDErr + +MPCall_56_0x44 + mr r30, r8 + stw r4, 0x00f4(r31) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + +; KCThrowException + +; Throws an exception to a specified task. + +; > r3 = MPTaskID task +; > r4 = MPExceptionKind kind + +; < r3 = result code + + DeclareMPCall 57, KCThrowException + +KCThrowException ; OUTSIDE REFERER + mfsprg r15, 0 + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Task.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + lwz r16, 0x0064(r31) + mtcr r16 + li r3, -0x7271 + beq+ cr7, ReleaseAndReturnMPCall + li r3, -0x726c + beq+ cr5, ReleaseAndReturnMPCall + beq+ cr3, ReleaseAndReturnMPCallOOM + lbz r17, 0x0018(r31) + lhz r18, 0x001a(r31) + cmpwi cr1, r17, 0x00 + bne- cr1, KCThrowException_0x70 + ori r16, r16, 0x600 + stw r4, 0x00f8(r31) + stw r16, 0x0064(r31) + li r3, -0x726b + b ReleaseAndReturnMPCall + +KCThrowException_0x70 + lhz r19, -0x0116(r15) + cmpw r19, r18 + bne- KCThrowException_0xb8 + ori r16, r16, 0x200 + stw r4, 0x00f8(r31) + stw r16, 0x0064(r31) + mr r8, r31 + bl major_0x13e4c + addi r16, r1, -0xa34 + addi r17, r31, 0x08 + stw r16, 0x0000(r17) + stw r16, 0x0008(r17) + lwz r18, 0x000c(r16) + stw r18, 0x000c(r17) + stw r17, 0x0008(r18) + stw r17, 0x000c(r16) + li r3, -0x726c + b ReleaseAndReturnMPCall + +KCThrowException_0xb8 + lwz r3, 0x0000(r31) + ori r16, r16, 0x400 + stw r16, 0x0064(r31) + li r17, 0x01 + stb r17, 0x0019(r31) + mr r8, r31 + bl major_0x14af8_0xa0 + sync + lwz r16, PSA.SchLock + Lock.Count(r1) + cmpwi cr1, r16, 0x00 + li r16, 0x00 + bne+ cr1, KCThrowException_0xf0 + mflr r16 + bl panic + +KCThrowException_0xf0 + stw r16, PSA.SchLock + Lock.Count(r1) + subi r10, r10, 4 + b MPCall_6_0x78 + + + +; MPCall_58 + +; Xrefs: +; major_0x02ccc +; kcMPDispatch +; MPCall_60 + + DeclareMPCall 58, MPCall_58 + +MPCall_58 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Task.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + lwz r29, 0x0064(r31) + mtcr r29 + li r3, -0x7271 + beq+ cr7, ReleaseAndReturnMPCall + beq- cr4, MPCall_58_0x44 + bne+ cr5, ReleaseAndReturnMPCallOOM + +MPCall_58_0x44 + mtcr r4 + lwz r30, 0x0088(r31) + bns- cr7, MPCall_58_0x68 + li r8, 0x1c + bl PoolAlloc_with_crset + cmpwi r8, 0x00 + beq+ major_0x0af60 + li r3, 0x00 + b MPCall_58_0x114 + +MPCall_58_0x68 + li r17, 0x3800 + rlwinm. r8, r29, 0, 18, 18 + andc r29, r29, r17 + li r17, 0x00 + bne- cr7, MPCall_58_0x80 + ori r17, r17, 0x400 + +MPCall_58_0x80 + ble- cr7, MPCall_58_0x88 + ori r17, r17, 0x200 + +MPCall_58_0x88 + lwz r18, 0x00a4(r30) + rlwimi r18, r17, 0, 21, 22 + stw r18, 0x00a4(r30) + li r19, 0x600 + lwz r17, 0x0008(r31) + addi r18, r1, -0xa34 + andc r29, r29, r19 + cmpw cr1, r17, r18 + stw r29, 0x0064(r31) + bne- MPCall_58_0xb4 + bne- cr1, MPCall_58_0xe0 + +MPCall_58_0xb4 + addi r16, r31, 0x08 + lwz r17, 0x0008(r16) + lwz r18, 0x000c(r16) + stw r17, 0x0008(r18) + stw r18, 0x000c(r17) + li r17, 0x00 + stw r17, 0x0008(r16) + stw r17, 0x000c(r16) + mr r8, r31 + bl TaskReadyAsPrev + bl major_0x14af8 + +MPCall_58_0xe0 +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + +FuncExportedFromTasks ; OUTSIDE REFERER + addi r16, r1, -0xa34 + addi r17, r31, 0x08 + stw r16, 0x0000(r17) + stw r16, 0x0008(r17) + lwz r18, 0x000c(r16) + stw r18, 0x000c(r17) + stw r17, 0x0008(r18) + stw r17, 0x000c(r16) + li r8, 0x1c + bl PoolAlloc_with_crset + lwz r29, 0x0064(r31) + ori r29, r29, 0x200 + +MPCall_58_0x114 + mtcr r29 + mr r28, r8 + beq- cr3, MPCall_58_0x13c + blt- cr5, MPCall_58_0x13c + lwz r8, -0x08e8(r1) + +; r8 = id + bl LookupID + cmpwi r9, Queue.kIDClass + + mr r30, r8 + ori r29, r29, 0x800 + beq- MPCall_58_0x184 + +MPCall_58_0x13c + bso- cr4, MPCall_58_0x158 + lwz r8, 0x00f4(r31) + +; r8 = id + bl LookupID + cmpwi r9, Queue.kIDClass + + mr r30, r8 + ori r29, r29, 0x1000 + beq- MPCall_58_0x184 + +MPCall_58_0x158 + mr. r8, r28 + bnel- PoolFree + addi r16, r31, 0x08 + lwz r17, 0x0008(r16) + lwz r18, 0x000c(r16) + stw r17, 0x0008(r18) + stw r18, 0x000c(r17) + li r17, 0x00 + stw r17, 0x0008(r16) + stw r17, 0x000c(r16) + b MPCall_9_0x98 + +MPCall_58_0x184 + mr. r8, r28 + stw r29, 0x0064(r31) + bne- MPCall_58_0x1a4 + lwz r8, 0x0028(r30) + cmpwi r8, 0x00 + beq+ MPCall_58_0x114 + lwz r17, 0x0008(r8) + stw r17, 0x0028(r30) + +MPCall_58_0x1a4 + bl LoadSomeData + lwz r16, 0x0088(r31) + lwz r17, 0x0000(r31) + mflr r18 + stw r17, 0x0010(r8) + lwz r17, 0x0074(r16) + lbz r19, 0x0040(r16) + lbzx r18, r18, r19 + stw r18, 0x0014(r8) + stw r17, 0x0018(r8) + stw r18, 0x00f8(r31) + mr r31, r30 + bl major_0x0c8b4 + b ReleaseAndReturnMPCall + + + + + + +LoadSomeData ; OUTSIDE REFERER + blrl + dc.l 0x0002020d + dc.l 0x01080003 + dc.l 0x090a0403 + dc.l 0x07000500 + dc.l 0x0b0b0403 + dc.l 0x07060505 + dc.l 0x11000000 + + + + DeclareMPCall 59, MPCall_59 + +MPCall_59 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr. r8, r3 + beq- MPCall_59_0x30 + +; r8 = id + bl LookupID + cmpwi r9, Queue.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + +MPCall_59_0x30 + stw r3, -0x08e8(r1) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 60, MPCall_60 + +MPCall_60 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Task.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + cmpwi r4, 0x05 + beq- MPCall_60_0x288 + lwz r16, 0x0064(r31) + mtcr r16 + li r3, -0x7271 + beq+ cr7, ReleaseAndReturnMPCall + beq- cr4, MPCall_60_0x4c + bne+ cr5, ReleaseAndReturnMPCallOOM + +MPCall_60_0x4c + lbz r16, 0x0018(r31) + cmpwi r16, 0x00 + bne+ ReleaseAndReturnMPCallOOM + cmpwi r4, 0x00 + cmpwi cr1, r4, 0x01 + beq- MPCall_60_0xf8 + beq- cr1, MPCall_60_0x10c + cmpwi r4, 0x02 + cmpwi cr1, r4, 0x03 + beq- MPCall_60_0x150 + beq- cr1, MPCall_60_0x1c0 + cmpwi r4, 0x04 + bne+ ReleaseAndReturnMPCallOOM + lwz r16, 0x0088(r31) + li r17, 0x00 + cmplwi r5, 0x00 + cmplwi cr1, r5, 0x04 + beq- MPCall_60_0xac + beq- cr1, MPCall_60_0xc0 + cmplwi r5, 0x08 + cmplwi cr1, r5, 0x0c + beq- MPCall_60_0xc8 + beq- cr1, MPCall_60_0xd0 + b ReleaseAndReturnMPCallOOM + +MPCall_60_0xac + lwz r8, 0x0070(r31) + lwz r9, 0x0074(r16) + bl FindAreaAbove + lwz r17, 0x0000(r8) + b MPCall_60_0x36c + +MPCall_60_0xc0 + lwz r17, 0x0074(r16) + b MPCall_60_0x36c + +MPCall_60_0xc8 + lwz r17, 0x00f8(r31) + b MPCall_60_0x36c + +MPCall_60_0xd0 + lwz r17, 0x0040(r16) + lwz r18, 0x0064(r16) + rlwinm. r8, r17, 0, 27, 27 + li r17, 0x02 + beq- MPCall_60_0x36c + rlwinm. r8, r18, 0, 1, 1 + li r17, 0x01 + bne- MPCall_60_0x36c + li r17, 0x00 + b MPCall_60_0x36c + +MPCall_60_0xf8 + lwz r16, 0x0088(r31) + cmplwi cr1, r5, 0xf8 + andi. r17, r5, 0x07 + addi r16, r16, 0xfc + b MPCall_60_0x124 + +MPCall_60_0x10c + lwz r16, 0x0088(r31) + cmplwi r5, 0x100 + cmplwi cr1, r5, 0xf8 + beq- MPCall_60_0x144 + andi. r17, r5, 0x07 + addi r16, r16, 0x1fc + +MPCall_60_0x124 + add r16, r16, r5 + bgt+ cr1, ReleaseAndReturnMPCallOOM + bne+ ReleaseAndReturnMPCallOOM + lwzu r17, 0x0004(r16) + lwzu r18, 0x0004(r16) + lwzu r19, 0x0004(r16) + lwzu r20, 0x0004(r16) + b MPCall_60_0x3a8 + +MPCall_60_0x144 + lwz r17, 0x00e4(r16) + li r18, 0x00 + b MPCall_60_0x37c + +MPCall_60_0x150 + lwz r16, 0x0088(r31) + rlwinm. r8, r7, 0, 12, 12 + lwz r16, 0x00d8(r16) + beq+ ReleaseAndReturnMPCallOOM + cmplwi cr3, r16, 0x00 + cmplwi r5, 0x200 + cmplwi cr2, r5, 0x210 + cmplwi cr1, r5, 0x1f0 + beql+ cr3, Local_Panic + beq- MPCall_60_0x1a4 + beq- cr2, MPCall_60_0x1b8 + andi. r8, r5, 0x0f + add r16, r16, r5 + subi r16, r16, 4 + bgt+ cr1, ReleaseAndReturnMPCallOOM + bne+ ReleaseAndReturnMPCallOOM + lwzu r17, 0x0004(r16) + lwzu r18, 0x0004(r16) + lwzu r19, 0x0004(r16) + lwzu r20, 0x0004(r16) + b MPCall_60_0x3a8 + +MPCall_60_0x1a4 + lwz r17, 0x0200(r16) + lwz r18, 0x0204(r16) + lwz r19, 0x0208(r16) + lwz r20, 0x020c(r16) + b MPCall_60_0x3a8 + +MPCall_60_0x1b8 + lwz r17, 0x0210(r16) + b MPCall_60_0x36c + +MPCall_60_0x1c0 + lwz r16, 0x0088(r31) + li r17, 0x00 + cmplwi r5, 0x00 + cmplwi cr1, r5, 0x08 + beq- MPCall_60_0x21c + beq- cr1, MPCall_60_0x228 + cmplwi r5, 0x10 + cmplwi cr1, r5, 0x30 + beq- MPCall_60_0x234 + beq- cr1, MPCall_60_0x240 + cmplwi r5, 0x1c + cmplwi cr1, r5, 0x20 + beq- MPCall_60_0x24c + beq- cr1, MPCall_60_0x254 + cmplwi r5, 0x24 + cmplwi cr1, r5, 0x28 + beq- MPCall_60_0x25c + beq- cr1, MPCall_60_0x264 + cmplwi r5, 0x2c + cmplwi cr1, r5, 0x18 + beq- MPCall_60_0x278 + beq- cr1, MPCall_60_0x280 + b ReleaseAndReturnMPCallOOM + +MPCall_60_0x21c + lwz r17, 0x00f0(r16) + lwz r18, 0x00f4(r16) + b MPCall_60_0x37c + +MPCall_60_0x228 + lwz r17, 0x00e8(r16) + lwz r18, 0x00ec(r16) + b MPCall_60_0x37c + +MPCall_60_0x234 + lwz r17, 0x00f8(r16) + lwz r18, 0x00fc(r16) + b MPCall_60_0x37c + +MPCall_60_0x240 + lwz r17, 0x0070(r16) + lwz r18, 0x0074(r16) + b MPCall_60_0x37c + +MPCall_60_0x24c + lwz r17, 0x00d4(r16) + b MPCall_60_0x36c + +MPCall_60_0x254 + lwz r17, 0x00a4(r16) + b MPCall_60_0x36c + +MPCall_60_0x25c + lwz r17, 0x00c4(r16) + b MPCall_60_0x36c + +MPCall_60_0x264 + lbz r17, 0x0040(r16) + bl LoadSomeData + mflr r18 + lbzx r17, r18, r17 + b MPCall_60_0x36c + +MPCall_60_0x278 + li r17, 0x00 + b MPCall_60_0x36c + +MPCall_60_0x280 + lwz r17, 0x00dc(r16) + b MPCall_60_0x36c + +MPCall_60_0x288 + cmplwi cr1, r5, 0x04 + cmplwi r5, 0x14 + beq- cr1, MPCall_60_0x2c4 + beq- MPCall_60_0x2e4 + cmplwi cr1, r5, 0x20 + cmplwi r5, 0x30 + beq- cr1, MPCall_60_0x2f4 + beq- MPCall_60_0x308 + cmpwi cr1, r5, 0x40 + cmplwi r5, 0x3c + beq- cr1, MPCall_60_0x320 + beq- MPCall_60_0x318 + cmpwi cr1, r5, 0x50 + beq- cr1, MPCall_60_0x34c + b ReleaseAndReturnMPCallOOM + +MPCall_60_0x2c4 + lwz r17, 0x0074(r31) + lwz r18, 0x0008(r31) + lwz r18, 0x0004(r18) + lhz r19, 0x001a(r31) + lbz r20, 0x0018(r31) + rlwimi r19, r20, 16, 8, 15 + lwz r20, 0x001c(r31) + b MPCall_60_0x3a8 + +MPCall_60_0x2e4 + lwz r17, 0x0060(r31) + lwz r18, 0x00c0(r31) + lwz r19, 0x00c4(r31) + b MPCall_60_0x390 + +MPCall_60_0x2f4 + lwz r17, 0x00c8(r31) + lwz r18, 0x00cc(r31) + lwz r19, 0x00d0(r31) + lwz r20, 0x00d4(r31) + b MPCall_60_0x3a8 + +MPCall_60_0x308 + lwz r17, 0x00e0(r31) + lwz r18, 0x00e4(r31) + lwz r19, 0x00e8(r31) + b MPCall_60_0x390 + +MPCall_60_0x318 + lwz r17, 0x0078(r31) + b MPCall_60_0x36c + +MPCall_60_0x320 + lbz r20, 0x0018(r31) + li r17, 0x00 + lwz r16, 0x0008(r31) + lwz r18, 0x0070(r31) + cmpwi r20, 0x00 + lwz r19, 0x0094(r31) + lwz r20, 0x0090(r31) + lwz r18, 0x0000(r18) + bne- MPCall_60_0x3a8 + lwz r17, 0x0000(r16) + b MPCall_60_0x3a8 + +MPCall_60_0x34c + mfsprg r18, 0 + lwz r20, 0x0088(r31) + lwz r19, -0x0008(r18) + cmpw r19, r31 + lwz r17, 0x0004(r18) + beq- MPCall_60_0x36c + lwz r17, 0x010c(r20) + b MPCall_60_0x36c + +MPCall_60_0x36c + li r21, 0x04 + stw r17, 0x0134(r6) + stw r21, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_60_0x37c + li r21, 0x08 + stw r17, 0x0134(r6) + stw r18, 0x013c(r6) + stw r21, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_60_0x390 + li r21, 0x0c + stw r17, 0x0134(r6) + stw r18, 0x013c(r6) + stw r19, 0x0144(r6) + stw r21, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_60_0x3a8 + li r21, 0x10 + stw r17, 0x0134(r6) + stw r18, 0x013c(r6) + stw r19, 0x0144(r6) + stw r20, 0x014c(r6) + stw r21, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 61, MPCall_61 + +MPCall_61 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Task.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r31, r8 + lwz r16, 0x0064(r31) + mtcr r16 + li r3, -0x7271 + beq+ cr7, ReleaseAndReturnMPCall + beq- cr4, MPCall_61_0x44 + bne+ cr5, ReleaseAndReturnMPCallOOM + +MPCall_61_0x44 + lbz r16, 0x0018(r31) + cmpwi r16, 0x00 + bne+ ReleaseAndReturnMPCallOOM + lwz r17, 0x0134(r6) + lwz r18, 0x013c(r6) + lwz r19, 0x0144(r6) + lwz r20, 0x014c(r6) + cmpwi r4, 0x00 + cmpwi cr1, r4, 0x01 + beq- MPCall_61_0x84 + beq- cr1, MPCall_61_0x98 + cmpwi r4, 0x02 + cmpwi cr1, r4, 0x03 + beq- MPCall_61_0xe8 + beq- cr1, MPCall_61_0x170 + b ReleaseAndReturnMPCallOOM + +MPCall_61_0x84 + lwz r16, 0x0088(r31) + cmplwi cr1, r5, 0xf8 + andi. r8, r5, 0x07 + addi r16, r16, 0xfc + b MPCall_61_0xb0 + +MPCall_61_0x98 + lwz r16, 0x0088(r31) + cmplwi r5, 0x100 + cmplwi cr1, r5, 0xf8 + beq- MPCall_61_0xd8 + andi. r8, r5, 0x07 + addi r16, r16, 0x1fc + +MPCall_61_0xb0 + add r16, r16, r5 + bgt+ cr1, ReleaseAndReturnMPCallOOM + bne+ ReleaseAndReturnMPCallOOM + li r21, 0x10 + stwu r17, 0x0004(r16) + stwu r18, 0x0004(r16) + stwu r19, 0x0004(r16) + stwu r20, 0x0004(r16) + stw r21, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_61_0xd8 + li r21, 0x04 + stw r17, 0x00e4(r16) + stw r21, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_61_0xe8 + lwz r16, 0x0088(r31) + rlwinm. r8, r7, 0, 12, 12 + lwz r16, 0x00d8(r16) + beq+ ReleaseAndReturnMPCallOOM + cmplwi cr3, r16, 0x00 + cmplwi r5, 0x200 + cmplwi cr2, r5, 0x210 + cmplwi cr1, r5, 0x1f0 + beql+ cr3, Local_Panic + beq- MPCall_61_0x144 + beq- cr2, MPCall_61_0x160 + andi. r8, r5, 0x0f + add r16, r16, r5 + subi r16, r16, 4 + bgt+ cr1, ReleaseAndReturnMPCallOOM + bne+ ReleaseAndReturnMPCallOOM + li r21, 0x10 + stwu r17, 0x0004(r16) + stwu r18, 0x0004(r16) + stwu r19, 0x0004(r16) + stwu r20, 0x0004(r16) + stw r21, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_61_0x144 + li r21, 0x10 + stw r17, 0x0200(r16) + stw r18, 0x0204(r16) + stw r19, 0x0208(r16) + stw r20, 0x020c(r16) + stw r21, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_61_0x160 + li r21, 0x04 + stw r17, 0x0210(r16) + stw r21, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_61_0x170 + lwz r16, 0x0088(r31) + cmplwi r5, 0x00 + cmplwi cr1, r5, 0x08 + beq- MPCall_61_0x1b0 + beq- cr1, MPCall_61_0x1c4 + cmplwi r5, 0x10 + beq- MPCall_61_0x1d8 + cmplwi r5, 0x1c + cmplwi cr1, r5, 0x20 + beq- MPCall_61_0x1ec + beq- cr1, MPCall_61_0x1fc + cmplwi r5, 0x24 + cmplwi cr1, r5, 0x18 + beq- MPCall_61_0x218 + beq- cr1, MPCall_61_0x228 + b ReleaseAndReturnMPCallOOM + +MPCall_61_0x1b0 + li r21, 0x08 + stw r17, 0x00f0(r16) + stw r18, 0x00f4(r16) + stw r21, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_61_0x1c4 + li r21, 0x08 + stw r17, 0x00e8(r16) + stw r18, 0x00ec(r16) + stw r21, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_61_0x1d8 + li r21, 0x08 + stw r17, 0x00f8(r16) + stw r18, 0x00fc(r16) + stw r21, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_61_0x1ec + li r21, 0x04 + stw r17, 0x00d4(r16) + stw r21, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_61_0x1fc + li r21, 0x04 + lwz r18, 0x00a4(r16) + rlwimi r18, r17, 0, 20, 23 + rlwimi r18, r17, 0, 31, 31 + stw r18, 0x00a4(r16) + stw r21, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_61_0x218 + li r21, 0x04 + stw r17, 0x00c4(r16) + stw r21, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + +MPCall_61_0x228 + li r21, 0x04 + stw r17, 0x00dc(r16) + stw r21, 0x0154(r6) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 63, MPCall_63 + +MPCall_63 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Task.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + stw r4, 0x00ec(r8) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + + DeclareMPCall 114, MPCall_114 + +MPCall_114 ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Task.kIDClass + + mr r31, r8 + bne+ ReleaseAndReturnMPCallInvalidIDErr + mr r8, r4 + +; r8 = id + bl LookupID + cmpwi r9, CPU.kIDClass + + mr r30, r8 + bne+ ReleaseAndReturnMPCallInvalidIDErr + lwz r16, 0x0064(r31) + lwz r17, 0x00e8(r31) + rlwinm. r8, r16, 0, 30, 30 + cmplw cr1, r17, r5 + lwz r18, 0x0018(r30) + bne+ ReleaseAndReturnMPCallOOM + bne+ cr1, ReleaseAndReturnMPCallOOM + rlwinm. r8, r18, 0, 28, 28 + cmplwi cr1, r17, 0x04 + beq+ ReleaseAndReturnMPCallOOM + lwz r16, 0x0064(r31) + lhz r17, 0x022a(r30) + ori r16, r16, 0x40 + stw r16, 0x0064(r31) + sth r17, 0x001a(r31) + rlwinm. r8, r16, 0, 26, 26 + mr r8, r31 + bne- MPCall_114_0x90 + bl major_0x13e4c + bl TaskReadyAsPrev + +MPCall_114_0x90 + bl major_0x14af8 + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall + + + +; KCSetTaskType + + + DeclareMPCall 126, KCSetTaskType + +KCSetTaskType ; OUTSIDE REFERER + + _Lock PSA.SchLock, scratch1=r16, scratch2=r17 + + mr r8, r3 + +; r8 = id + bl LookupID + cmpwi r9, Task.kIDClass + + bne+ ReleaseAndReturnMPCallInvalidIDErr + stw r4, 0x0074(r8) + +; r1 = kdp + b ReleaseAndReturnZeroFromMPCall diff --git a/NanoKernel/NKThud.s b/NanoKernel/NKThud.s new file mode 100644 index 0000000..b592a45 --- /dev/null +++ b/NanoKernel/NKThud.s @@ -0,0 +1,1369 @@ +; panic + +; Xrefs: +; "vec" +; Local_Panic +; Local_Panic +; major_0x02ccc +; IntDecrementer +; IntDSIOtherOther +; IntMachineCheckMemRetry +; IntISI +; IntDSIOther +; IntPerfMonitor +; IntThermalEvent +; Local_Panic +; FDP_1c40 +; Local_Panic +; kcVMDispatch +; Local_Panic +; kcRTASDispatch +; ReleaseAndMPCallWasBad +; ReleaseAndReturnZeroFromMPCall +; major_0x0af60 +; ReleaseAndReturnMPCallBlueBlocking +; major_0x0b054 +; ReleaseAndReturnMPCallPrivilegedErr +; major_0x0b0cc +; AlternateMPCallReturnPath +; MPCall_0 +; MPCall_6 +; KCYieldWithHint +; KCStartCPU +; KCStopScheduling +; MPCall_115 +; Local_Panic +; major_0x0d35c +; MPCall_41 +; Local_Panic +; MPCall_9 +; KCThrowException +; Local_Panic +; MPCall_70 +; MPCall_72 +; createarea +; major_0x102c8 +; MPCall_73 +; MPCall_74 +; MPCall_75 +; MPCall_130 +; KCSetAreaAccess +; MPCall_123 +; MPCall_81 +; MPCall_98 +; MPCall_83 +; MPCall_84 +; KCMapPage +; KCUnmapPages +; KCMakePhysicallyContiguous +; KCLockPages +; KCUnlockPages +; KCHoldPages +; KCUnholdPages +; MPCall_91 +; MPCall_92 +; MPCall_94 +; MPCall_95 +; Local_Panic +; major_0x129cc +; Local_Panic +; Local_Panic +; major_0x142dc +; major_0x14548 +; Local_Panic +; CommonPIHPath +; print_common + + + align 5 + + +panic ; OUTSIDE REFERER + crset cr1_eq + b panic_common + +panic_non_interactive + crclr cr1_eq + +panic_common + mfsprg r1, 0 + stmw r29, EWA.ThudSavedR29(r1) + lwz r1, EWA.PA_KDP(r1) + mflr r29 + + _Lock PSA.ThudLock, scratch1=r30, scratch2=r31 + + stw r29, KDP.ThudSavedLR(r1) + stw r0, KDP.ThudSavedR0(r1) + mfsprg r0, 1 + stw r0, KDP.ThudSavedR1(r1) + stw r2, KDP.ThudSavedR2(r1) + mfsprg r2, 0 + lmw r29, EWA.ThudSavedR29(r2) + stmw r3, KDP.ThudSavedR3(r1) + mfcr r0 + stw r0, KDP.ThudSavedCR(r1) + + +; Save the silly multiply-quotient register + + mfspr r0, pvr + rlwinm. r0, r0, 0, 0, 14 + bne- @no_mq + dialect POWER + mfmq r0 + dialect PowerPC + stw r0, KDP.ThudSavedMQ(r1) +@no_mq + + mfxer r0 + stw r0, KDP.ThudSavedXER(r1) + mfsprg r0, 2 + stw r0, KDP.ThudSavedSPRG2(r1) + mfctr r0 + stw r0, KDP.ThudSavedCTR(r1) + mfspr r0, pvr + stw r0, KDP.ThudSavedPVR(r1) + mfspr r0, dsisr + stw r0, KDP.ThudSavedDSISR(r1) + mfspr r0, dar + stw r0, KDP.ThudSavedDAR(r1) + + +; Save the time + + mfpvr r0 + rlwinm. r0, r0, 0, 0, 14 + bne- @not_601 + +@rtcloop + dialect POWER + mfrtcu r0 + mfrtcl r2 + mfrtcu r3 + dialect PowerPC + cmpw r0, r3 + bne+ @rtcloop + + stw r0, KDP.ThudSavedTBU(r1) + stw r2, KDP.ThudSavedTB(r1) + b @end_if_601 +@not_601 + +@tbloop + mftbu r0 + mftb r2 + mftbu r3 + cmpw r0, r3 + bne+ @tbloop + stw r0, KDP.ThudSavedTBU(r1) + stw r2, KDP.ThudSavedTB(r1) +@end_if_601 + + + mfspr r0, dec + stw r0, 0x07a8(r1) + mfspr r0, hid0 + stw r0, 0x07ac(r1) + mfspr r0, sdr1 + stw r0, 0x07b0(r1) + mfspr r0, srr0 + stw r0, 0x07b4(r1) + mfspr r0, srr1 + stw r0, 0x07b8(r1) + mfmsr r0 + stw r0, 0x07bc(r1) + mfsr r0, 0 + stw r0, 0x07c0(r1) + mfsr r0, 1 + stw r0, 0x07c4(r1) + mfsr r0, 2 + stw r0, 0x07c8(r1) + mfsr r0, 3 + stw r0, 0x07cc(r1) + mfsr r0, 4 + stw r0, 0x07d0(r1) + mfsr r0, 5 + stw r0, 0x07d4(r1) + mfsr r0, 6 + stw r0, 0x07d8(r1) + mfsr r0, 7 + stw r0, 0x07dc(r1) + mfsr r0, 8 + stw r0, 0x07e0(r1) + mfsr r0, 9 + stw r0, 0x07e4(r1) + mfsr r0, 10 + stw r0, 0x07e8(r1) + mfsr r0, 11 + stw r0, 0x07ec(r1) + mfsr r0, 12 + stw r0, 0x07f0(r1) + mfsr r0, 13 + stw r0, 0x07f4(r1) + mfsr r0, 14 + stw r0, 0x07f8(r1) + mfsr r0, 15 + stw r0, 0x07fc(r1) + + + mfmsr r0 + _bset r0, r0, MSR_FPbit + mtmsr r0 + isync + + stfd f0, 0x0800(r1) + stfd f1, 0x0808(r1) + stfd f2, 0x0810(r1) + stfd f3, 0x0818(r1) + stfd f4, 0x0820(r1) + stfd f5, 0x0828(r1) + stfd f6, 0x0830(r1) + stfd f7, 0x0838(r1) + stfd f8, 0x0840(r1) + stfd f9, 0x0848(r1) + stfd f10, 0x0850(r1) + stfd f11, 0x0858(r1) + stfd f12, 0x0860(r1) + stfd f13, 0x0868(r1) + stfd f14, 0x0870(r1) + stfd f15, 0x0878(r1) + stfd f16, 0x0880(r1) + stfd f17, 0x0888(r1) + stfd f18, 0x0890(r1) + stfd f19, 0x0898(r1) + stfd f20, 0x08a0(r1) + stfd f21, 0x08a8(r1) + stfd f22, 0x08b0(r1) + stfd f23, 0x08b8(r1) + stfd f24, 0x08c0(r1) + stfd f25, 0x08c8(r1) + stfd f26, 0x08d0(r1) + stfd f27, 0x08d8(r1) + stfd f28, 0x08e0(r1) + stfd f29, 0x08e8(r1) + stfd f30, 0x08f0(r1) + stfd f31, 0x08f8(r1) + mffs f31 + lwz r0, 0x08fc(r1) + stfd f31, 0x08fc(r1) + stw r0, 0x08fc(r1) + bne- cr1, @0x260 + + if &TYPE('NKDebugShim') != 'UNDEFINED' + b @go_here_to_use_saved_debug_command + endif + +@0x23c + lwz r1, 0(0) + addi r1, r1, 1 + stw r1, 0(0) + + li r1, 0 + dcbst r1, r1 + + bl getchar + +; gets kdp from print!!! + cmpwi r8, -0x01 + bne- @0x260 + b @0x23c + +@0x260 + lwz r8, 0x0edc(r1) + ori r8, r8, 0x02 + stw r8, 0x0edc(r1) + _log '½ NanoKernel debugger^n' + +@prompt + + if &TYPE('NKDebugShim') != 'UNDEFINED' + b @NKDebugShimCode + endif + + _log '½ ' ; thats an omega, btw + li r17, 0x00 ; r17 = charcount + stw r17, -0x08fc(r1) + +@input_busywait + bl getchar + cmpwi r8, -1 + beq+ @input_busywait + + mr r16, r8 + cmpwi r16, 8 ; backspace + cmpwi cr1, r17, 0 + bne- @not_backspace + ble+ cr1, @input_busywait + + + ; Backspace, wipe position, then backspace again! + subi r17, r17, 1 + li r8, 8 + bl Printc + li r8, ' ' + bl Printc + li r8, 8 + bl Printc + + b @input_busywait +@not_backspace + + ; If + cmpwi cr2, r17, 95 + addi r18, r1, -0x960 ; prepare to copy the line! + blt- cr2, @short_line + _log '^b' + b @input_busywait + +@0x30c + addi r17, r17, 1 ; accept the character as an addition to the line + mr r8, r16 + bl Printc + b @input_busywait +@short_line + + cmpwi r16, 13 + stbx r16, r17, r18 + bne+ @0x30c + li r16, 0x00 + stbx r16, r17, r18 + _log '^n' + + +@go_here_to_use_saved_debug_command + + +; Now a line is expected to be committed: + + addi r15, r1, -0x960 + +; r15 = start + bl next_cmd_word +; r15 = ptr +; r16 = char + + cmpwi r16, 0x00 + beq+ @prompt + bl @load_commands + mflr r16 + bl @load_tbl + mflr r17 + +; r16 = command strings +; r17 = lut + bl cmd_lookup +; cr0 = found +; r17 = ptr to lut entry + + bne- @bad_command + bl @load_tbl + mflr r16 + lwz r17, 0x0000(r17) + add r16, r16, r17 + mtlr r16 + + blr + +@bad_command + _log '???^n' + b @prompt + +@load_commands + blrl + string CString + dc.b 'dm' + dc.b 'dml' + dc.b 'g' + dc.b 'id' + dc.b 'kd' + dc.b 'td' + dc.b '?' + dc.b 'help' + dc.b 0xff + align 2 + +@load_tbl + blrl + +@tbl + dc.l @cmd_dumpmem_physical - @tbl + dc.l @cmd_dumpmem_logical - @tbl + dc.l @cmd_goto - @tbl + dc.l @cmd_opaque_id_info - @tbl + dc.l @cmd_display_kern_data - @tbl + dc.l @cmd_dump_registers - @tbl + dc.l @cmd_help - @tbl + dc.l @cmd_help - @tbl + dc.l 0 + +@cmd_help + _log 'Commands:^n' + _log ' dm address [length] -- Display physical^n' + _log ' dml address [length] -- Display logical^n' + _log ' g [address] -- Go resume^n' + _log ' id [-all -p -t -tm -q -s -r -c -sp -e -cg -a -n -nc]^n' + _log ' id idvalue -- Obtain opaque ID info^n' + _log ' kd -- Display kernel data^n' + _log ' td -- Dump registers^n' + b @prompt + +@cmd_dumpmem_physical +; r15 = start + bl next_cmd_word +; r15 = ptr +; r16 = char + + cmpwi r16, 0x00 + beq- @missing_physical_addr + bl major_0x187b0 + bne- @bad_length_1 + mr r30, r16 + li r31, 0x10 + +; r15 = start + bl next_cmd_word +; r15 = ptr +; r16 = char + + cmpwi r16, 0x00 + beq- @0x5e0 + bl major_0x187b0 + bne- @bad_length_1 + mr r31, r16 + +@0x5e0 + addi r31, r31, 0x03 + rlwinm r31, r31, 0, 0, 29 + mr r16, r30 + mr r17, r31 + bl print_memory + b @prompt + +@missing_physical_addr + _log 'Need a physical address^n' + b @prompt + +@bad_length_1 + _log 'Length must be a hexadecimal value^n' + b @prompt + +@cmd_dumpmem_logical + _log 'Logical memory^n' + +; r15 = start + bl next_cmd_word +; r15 = ptr +; r16 = char + + cmpwi r16, 0x00 + beq- @missing_logical_addr + bl major_0x187b0 + bne- @bad_length_2 + mr r30, r16 + li r31, 0x10 + +; r15 = start + bl next_cmd_word +; r15 = ptr +; r16 = char + + cmpwi r16, 0x00 + beq- @0x6b0 + bl major_0x187b0 + bne- @bad_length_2 + mr r31, r16 + +@0x6b0 + addi r31, r31, 0x03 + rlwinm r31, r31, 0, 0, 29 + mr r16, r30 + mr r17, r31 + bl print_memory_logical + b @prompt + +@missing_logical_addr + _log 'Need a logical address^n' + b @prompt + +@bad_length_2 + _log 'Length must be a hexadecimal value^n' + b @prompt + +@cmd_goto +; r15 = start + bl next_cmd_word +; r15 = ptr +; r16 = char + + cmpwi r16, 0x00 + lwz r31, 0x0904(r1) + beq- @0x748 + bl major_0x187b0 + bne- @bad_resume_address + stw r16, 0x0904(r1) + +@0x748 + +@NKDebugShimCode + _log 'Resuming at ' + lwz r31, 0x0904(r1) + mr r8, r31 + bl Printw + _log ' - wish me luck.^n' + bl prereturn + lwz r8, 0x0904(r1) + sync + + lwz r9, PSA.ThudLock + Lock.Count(r1) + cmpwi cr1, r9, 0x00 + li r9, 0x00 + bne+ cr1, @0x7b4 + mflr r9 + bl panic +@0x7b4 + stw r9, PSA.ThudLock + Lock.Count(r1) + mtlr r8 + blr + +@bad_resume_address + _log 'Need hexadecimal value for resume address^n' + b @prompt + +@cmd_opaque_id_info +; r15 = start + bl next_cmd_word +; r15 = ptr +; r16 = char + + cmpwi r16, 0x00 + beq- @missing_opaque_id + bl @load_id_args + mflr r16 + li r17, 0x00 + +; r16 = command strings +; r17 = lut + bl cmd_lookup +; cr0 = found +; r17 = ptr to lut entry + + bne- @0x884 + li r29, 0x00 + li r30, 0x00 + srwi r31, r17, 2 + +@0x82c + mr r8, r30 + mr r9, r31 + bl GetNextIDOfClass + mr. r30, r8 + beq- @0x868 + mr r8, r8 + bl Printw + addi r29, r29, 0x01 + andi. r29, r29, 0x07 + bne+ @0x82c + _log '^n' + b @0x82c + +@0x868 + cmpwi r29, 0x00 + beq+ @prompt + _log '^n' + b @prompt + +@0x884 + bl major_0x187b0 + bne- @bad_opaque_id + mr r30, r16 + mr r8, r16 + +; r8 = id + bl LookupID +; r8 = something not sure what +; r9 = 0:inval, 1:proc, 2:task, 3:timer, 4:q, 5:sema, 6:cr, 7:cpu, 8:addrspc, 9:evtg, 10:cohg, 11:area, 12:not, 13:log + + mr r31, r8 + _log 'ID ' + mr r8, r30 + bl Printw + bl @load_id_kind_strings + mflr r17 + slwi r18, r9, 4 + add r8, r17, r18 + bl PrintS + cmpwi r9, 0x00 + beq- @0x978 + _log ' at ' + mr r8, r31 + bl Printw + _log '^n' + mr r16, r31 + bl @load_more_jumps + mflr r17 + slwi r18, r9, 2 + lwzx r17, r17, r18 + bl print_memory + b @prompt + +@missing_opaque_id + _log 'Need an opaque ID^n' + b @prompt + +@bad_opaque_id + _log 'ID must be a hexadecimal value^n' + b @prompt + +@0x978 + _log '^n' + b @prompt + +@load_id_kind_strings + blrl + string CString + dc.b 'is invalid. ' + dc.b 'Process ' + dc.b 'Task ' + dc.b 'Timer ' + dc.b 'Queue ' + dc.b 'Semaphore ' + dc.b 'Critical Region' + dc.b 'Cpu ' + dc.b 'Address Space ' + dc.b 'Event Group ' + dc.b 'Coherence Group' + dc.b 'Area ' + dc.b 'Notification ' + dc.b 'Console Log ' + align 2 + +@load_more_jumps + blrl + dc.l 0 + dc.l Process.Size + dc.l Task.Size + dc.l Timer.Size + dc.l Queue.Size + dc.l Semaphore.Size + dc.l CriticalRegion.Size + dc.l CPU.Size + dc.l AddressSpace.Size + dc.l EventGroup.Size + dc.l CoherenceGroup.Size + dc.l Area.Size + dc.l Notification.Size + dc.l ConsoleLog.Size + +@load_id_args + blrl + dc.b '-all' + dc.b '-p' + dc.b '-t' + dc.b '-tm' + dc.b '-q' + dc.b '-s' + dc.b '-r' + dc.b '-c' + dc.b '-sp' + dc.b '-e' + dc.b '-cg' + dc.b '-a' + dc.b '-n' + dc.b '-nc' + dc.b 0xff + align 2 + +@cmd_display_kern_data + mfsprg r17, 0 + + _log 'Kernel version ' + lhz r8, KDP.InfoRecord + InfoRecord.NKNanoKernelInfoVer(r1) + bl Printh + + _log 'Code base ' + lwz r8, KDP.PA_NanoKernelCode(r1) + bl Printw + + _log 'PSA ' + addi r8, r17, PSA.Base + bl Printw + + _log 'KDP ' + mr r8, r1 + bl Printw + + _log 'EDP ' + lwz r8, KDP.PA_EmulatorData(r1) + bl Printw + + _log '^nCurrent EWA ' + mr r8, r17 + bl Printw + + _log ' is CPU ' + lhz r8, -0x0116(r17) + bl Printh + + _log ' ID-' + lwz r8, -0x0340(r17) + bl Printw + + lwz r18, EWA.PA_CurTask(r17) + _log '^nCurrent task ' + mr r8, r18 + bl Printw + + _log 'ID-' + lwz r8, Task.ID(r18) + bl Printw + + _log 'name \"' + lwz r8, Task.Name(r18) + rotlwi r8, r8, 8 + bl Printc + rotlwi r8, r8, 8 + bl Printc + rotlwi r8, r8, 8 + bl Printc + rotlwi r8, r8, 8 + bl Printc + + _log '\" Owning process ' + lwz r8, 0x006c(r18) + bl Printw + + _log ' ID-' + lwz r8, 0x0060(r18) + bl Printw + + _log '^nAddress Space ' + lwz r18, -0x001c(r17) + mr r8, r18 + bl Printw + + _log ' ID-' + lwz r8, 0x0000(r18) + bl Printw + + _log '^n' + + bl print_xpt_info + b @prompt + +@cmd_dump_registers + _log 'Kernel registers:^n' + bl print_sprgs + bl print_sprs + _log '^n' + bl print_segment_registers + _log '^n' + bl print_gprs + b @prompt + + + +; major_0x18040 + +; Xrefs: +; "EightyForty" + + mflr r16 + lwz r17, 0x07b4(r1) + rlwinm r17, r17, 16, 16, 27 + cmpwi r17, 0x6800 + bne- major_0x18040_0x100 + lwz r17, 0x071c(r1) + srwi r17, r17, 16 + andi. r17, r17, 0xffa0 + cmpwi r17, 0x2a0 + bne- major_0x18040_0x64 + _log 'Caused by emulator termination request^n' + b major_0x18040_0x9c + +major_0x18040_0x64 + _log 'Caused by unhandled emulator exception^n' + +major_0x18040_0x9c + lwz r17, 0x079c(r1) + lwz r18, 0x0704(r1) + subf r17, r18, r17 + cmpwi r17, 0x100 + cmpwi cr1, r17, -0x100 + bgt- major_0x18040_0x100 + blt- cr1, major_0x18040_0x100 + _log 'Looks like interrupt stack overflow by os or application^n' + +major_0x18040_0x100 + mtlr r16 + blr + + + +; print_xpt_info + +; Xrefs: +; panic + +print_xpt_info ; OUTSIDE REFERER + mflr r16 + lwz r18, 0x064c(r1) + llabel r18, NKBtm + add r19, r18, r19 + _log 'Termination caller ' + lwz r20, 0x0904(r1) + mr r8, r20 + bl Printw + subf. r21, r18, r20 + cmplw cr1, r20, r19 + blt- print_xpt_info_0x84 + bge- cr1, print_xpt_info_0x84 + _log '( NK+' + mr r8, r21 + bl Printw + _log ')^n' + +print_xpt_info_0x84 + _log ' Last exception at ' + mfspr r8, srr1 + bl Printw + mfspr r8, srr0 + bl Printw + mfspr r8, srr0 + subf. r21, r18, r8 + cmplw cr1, r8, r19 + blt- print_xpt_info_0xf8 + bge- cr1, print_xpt_info_0xf8 + _log '( NK+' + mr r8, r21 + bl Printw + _log ')' + +print_xpt_info_0xf8 + _log '^n' + mtlr r16 + blr + + + +; print_sprgs + +; Goldmine. Tells me what the SPRGs do! + +; Xrefs: +; panic + +print_sprgs ; OUTSIDE REFERER + mflr r16 + _log 'SPRGs ewa: ' + mfsprg r8, 0 + bl Printw + _log ' r1: ' + mfsprg r8, 1 + bl Printw + _log ' lr: ' + mfsprg r8, 2 + bl Printw + _log ' vecBase: ' + mfsprg r8, 3 + bl Printw + _log '^n' + mtlr r16 + blr + + + +; print_sprs + +; Both user-mode and supervisor-only + +; Xrefs: +; panic + +print_sprs ; OUTSIDE REFERER + mflr r16 + _log ' cr: ' + lwz r8, 0x0780(r1) + bl Printw + _log 'xer: ' + lwz r8, 0x0788(r1) + bl Printw + _log 'ctr: ' + lwz r8, 0x0790(r1) + bl Printw + _log 'lr: ' + lwz r8, 0x078c(r1) + bl Printw + _log '^n dsisr: ' + lwz r8, 0x0798(r1) + bl Printw + _log 'dar:' + lwz r8, 0x079c(r1) + bl Printw + _log 'pvr: ' + lwz r8, 0x0794(r1) + bl Printw + _log '^n' + mtlr r16 + blr + + + +; print_segment_registers + +; Xrefs: +; panic + +print_segment_registers ; OUTSIDE REFERER + mflr r16 + _log ' sr0-sr7 ' + li r17, 0x08 + mtctr r17 + li r18, 0x00 + +print_segment_registers_0x28 + mfsrin r8, r18 + addis r18, r18, 0x1000 + bl Printw + bdnz+ print_segment_registers_0x28 + _log '^n sr8-sr15 ' + li r17, 0x08 + mtctr r17 + +print_segment_registers_0x5c + mfsrin r8, r18 + addis r18, r18, 0x1000 + bl Printw + bdnz+ print_segment_registers_0x5c + _log '^n' + mtlr r16 + blr + + + +; print_gprs + +; Xrefs: +; panic + +print_gprs ; OUTSIDE REFERER + mflr r16 + addi r17, r1, 0x6fc + _log ' r0-r7 ' + li r18, 0x08 + mtctr r18 + +print_gprs_0x28 + lwzu r8, 0x0004(r17) + bl Printw + bdnz+ print_gprs_0x28 + _log '^n r8-r15 ' + li r18, 0x08 + mtctr r18 + +print_gprs_0x58 + lwzu r8, 0x0004(r17) + bl Printw + bdnz+ print_gprs_0x58 + _log '^n r16-r23 ' + li r18, 0x08 + mtctr r18 + +print_gprs_0x88 + lwzu r8, 0x0004(r17) + bl Printw + bdnz+ print_gprs_0x88 + _log '^n r24-r31 ' + li r18, 0x08 + mtctr r18 + +print_gprs_0xb8 + lwzu r8, 0x0004(r17) + bl Printw + bdnz+ print_gprs_0xb8 + _log '^n' + mtlr r16 + blr + + + +; print_memory + +; Xrefs: +; panic + +print_memory ; OUTSIDE REFERER + mflr r18 + srwi r17, r17, 4 + +print_memory_0x8 + mr r8, r16 + bl Printw + _log ' ' + lwz r8, 0x0000(r16) + bl Printw + lwz r8, 0x0004(r16) + bl Printw + lwz r8, 0x0008(r16) + bl Printw + lwz r8, 0x000c(r16) + bl Printw + _log ' *' + li r8, 0x10 + addi r16, r16, -0x01 + mtctr r8 + +print_memory_0x60 + lbzu r8, 0x0001(r16) + cmpwi r8, 0xff + beq- print_memory_0x74 + cmpwi r8, 0x20 + bgt- print_memory_0x78 + +print_memory_0x74 + li r8, 0x20 + +print_memory_0x78 + bl Printc + bdnz+ print_memory_0x60 + _log '*^n' + addi r16, r16, 0x01 + addi r17, r17, -0x01 + bl getchar + cmpwi r8, -0x01 + bne- print_memory_0xb0 + cmpwi r17, 0x00 + bne+ print_memory_0x8 + +print_memory_0xb0 + _log '^n' + mtlr r18 + blr + + + +; print_memory_logical + +; Xrefs: +; panic + +print_memory_logical ; OUTSIDE REFERER + mflr r18 + srwi r17, r17, 4 + +print_memory_logical_0x8 + mr r8, r16 + bl Printw + _log ' ' + li r19, 0x10 + +print_memory_logical_0x24 + mr r27, r16 + bl PagingFunc1 + beq- print_memory_logical_0x5c + blt- print_memory_logical_0x48 + _log '..' + b print_memory_logical_0x6c + +print_memory_logical_0x48 + _log '--' + b print_memory_logical_0x6c + +print_memory_logical_0x5c + bl PagingFunc4 + rlwimi r31, r27, 0, 20, 31 + lbz r8, 0x0000(r31) + bl print_unknown + +print_memory_logical_0x6c + addi r16, r16, 0x01 + addi r19, r19, -0x01 + andi. r8, r19, 0x03 + bne- print_memory_logical_0x84 + li r8, 0x20 + bl Printc + +print_memory_logical_0x84 + cmpwi r19, 0x00 + bgt+ print_memory_logical_0x24 + _log ' *' + li r8, 0x10 + addi r16, r16, -0x10 + mtctr r8 + +print_memory_logical_0xac + mr r27, r16 + bl PagingFunc1 + li r8, 0x20 + bne- print_memory_logical_0xdc + bl PagingFunc4 + rlwimi r31, r27, 0, 20, 31 + lbz r8, 0x0000(r31) + cmpwi r8, 0xff + beq- print_memory_logical_0xd8 + cmpwi r8, 0x20 + bgt- print_memory_logical_0xdc + +print_memory_logical_0xd8 + li r8, 0x20 + +print_memory_logical_0xdc + bl Printc + addi r16, r16, 0x01 + bdnz+ print_memory_logical_0xac + _log '*^n' + addi r17, r17, -0x01 + bl getchar + cmpwi r8, -0x01 + bne- print_memory_logical_0x114 + cmpwi r17, 0x00 + bne+ print_memory_logical_0x8 + +print_memory_logical_0x114 + _log '^n' + mtlr r18 + blr + + + +; cmd_lookup + +; Xrefs: +; panic + +; > r16 = command strings +; > r17 = lut + +; < cr0 = found +; < r17 = ptr to lut entry + +cmd_lookup ; OUTSIDE REFERER + addi r15, r15, -0x01 + addi r16, r16, -0x01 + mr r18, r15 + +cmd_lookup_0xc + lbzu r21, 0x0001(r16) + lbzu r20, 0x0001(r15) + cmpwi r21, 0xff + cmpwi cr1, r21, 0x00 + beq- cmd_lookup_0x44 + beq- cr1, cmd_lookup_0x50 + cmpw r20, r21 + beq+ cmd_lookup_0xc + +cmd_lookup_0x2c + lbzu r21, 0x0001(r16) + cmpwi r21, 0x00 + bne+ cmd_lookup_0x2c + +cmd_lookup_0x38 + addi r17, r17, 0x04 + mr r15, r18 + b cmd_lookup_0xc + +cmd_lookup_0x44 + addi r15, r18, 0x01 + cmpw r15, r18 + blr + +cmd_lookup_0x50 + cmpwi r20, 0x20 + beqlr- + cmpwi r20, 0x00 + beqlr- + b cmd_lookup_0x38 + + + +; next_cmd_word + +; Xrefs: +; panic + +; > r15 = start + +; < r15 = ptr +; < r16 = char + +next_cmd_word ; OUTSIDE REFERER + addi r15, r15, -0x01 + +next_cmd_word_0x4 + lbzu r16, 0x0001(r15) + cmpwi r16, 0x20 + beq+ next_cmd_word_0x4 + blr + + + +; major_0x187b0 + +; Xrefs: +; panic + +major_0x187b0 ; OUTSIDE REFERER + addi r15, r15, -0x01 + li r16, 0x00 + +major_0x187b0_0x8 + lbzu r17, 0x0001(r15) + cmplwi r17, 0x30 + cmplwi cr1, r17, 0x39 + blt- major_0x187b0_0x28 + bgt- cr1, major_0x187b0_0x28 + slwi r16, r16, 4 + rlwimi r16, r17, 0, 28, 31 + b major_0x187b0_0x8 + +major_0x187b0_0x28 + cmplwi r17, 0x61 + cmplwi cr1, r17, 0x66 + blt- major_0x187b0_0x48 + bgt- cr1, major_0x187b0_0x48 + addi r17, r17, -0x57 + slwi r16, r16, 4 + rlwimi r16, r17, 0, 28, 31 + b major_0x187b0_0x8 + +major_0x187b0_0x48 + cmplwi r17, 0x41 + cmplwi cr1, r17, 0x46 + blt- major_0x187b0_0x68 + bgt- cr1, major_0x187b0_0x68 + addi r17, r17, -0x37 + slwi r16, r16, 4 + rlwimi r16, r17, 0, 28, 31 + b major_0x187b0_0x8 + +major_0x187b0_0x68 + cmpwi r17, 0x00 + beqlr- + cmpwi r17, 0x20 + blr + + +prereturn ; OUTSIDE REFERER + lwz r1, EWA.PA_KDP(r1) + + mfmsr r0 + _bset r0, r0, MSR_FPbit + mtmsr r0 + isync + + lfd f31, 0x08fc(r1) + mtfsf 0xff, f31 + lfd f0, 0x0800(r1) + lfd f1, 0x0808(r1) + lfd f2, 0x0810(r1) + lfd f3, 0x0818(r1) + lfd f4, 0x0820(r1) + lfd f5, 0x0828(r1) + lfd f6, 0x0830(r1) + lfd f7, 0x0838(r1) + lfd f8, 0x0840(r1) + lfd f9, 0x0848(r1) + lfd f10, 0x0850(r1) + lfd f11, 0x0858(r1) + lfd f12, 0x0860(r1) + lfd f13, 0x0868(r1) + lfd f14, 0x0870(r1) + lfd f15, 0x0878(r1) + lfd f16, 0x0880(r1) + lfd f17, 0x0888(r1) + lfd f18, 0x0890(r1) + lfd f19, 0x0898(r1) + lfd f20, 0x08a0(r1) + lfd f21, 0x08a8(r1) + lfd f22, 0x08b0(r1) + lfd f23, 0x08b8(r1) + lfd f24, 0x08c0(r1) + lfd f25, 0x08c8(r1) + lfd f26, 0x08d0(r1) + lfd f27, 0x08d8(r1) + lfd f28, 0x08e0(r1) + lfd f29, 0x08e8(r1) + lfd f30, 0x08f0(r1) + lfd f31, 0x08f8(r1) + + lwz r0, 0x07c0(r1) + mtsr 0x00, r0 + lwz r0, 0x07c4(r1) + mtsr 0x01, r0 + lwz r0, 0x07c8(r1) + mtsr 0x02, r0 + lwz r0, 0x07cc(r1) + mtsr 0x03, r0 + lwz r0, 0x07d0(r1) + mtsr 0x04, r0 + lwz r0, 0x07d4(r1) + mtsr 0x05, r0 + lwz r0, 0x07d8(r1) + mtsr 0x06, r0 + lwz r0, 0x07dc(r1) + mtsr 0x07, r0 + lwz r0, 0x07e0(r1) + mtsr 0x08, r0 + lwz r0, 0x07e4(r1) + mtsr 0x09, r0 + lwz r0, 0x07e8(r1) + mtsr 0x0a, r0 + lwz r0, 0x07ec(r1) + mtsr 0x0b, r0 + lwz r0, 0x07f0(r1) + mtsr 0x0c, r0 + lwz r0, 0x07f4(r1) + mtsr 0x0d, r0 + lwz r0, 0x07f8(r1) + mtsr 0x0e, r0 + lwz r0, 0x07fc(r1) + mtsr 0x0f, r0 + + lwz r0, 0x07a8(r1) + mtspr dec, r0 + + lwz r0, 0x07b4(r1) + mtspr srr0, r0 + lwz r0, 0x07b8(r1) + mtspr srr1, r0 + + lwz r0, 0x07bc(r1) + mtmsr r0 + + mfpvr r0 + rlwinm. r0, r0, 0, 0, 14 + + bne- @not_601 + lwz r0, 0x0784(r1) + mtspr mq, r0 +@not_601 + + lwz r0, 0x0788(r1) + mtxer r0 + lwz r0, 0x078c(r1) + mtsprg 2, r0 + lwz r0, 0x0790(r1) + mtctr r0 + + ; Only because this crashes QEMU + + if &TYPE('NKDebugShim') = 'UNDEFINED' + lwz r0, 0x0794(r1) + mtspr pvr, r0 + endif + + lwz r0, 0x0798(r1) + mtspr dsisr, r0 + lwz r0, 0x079c(r1) + mtspr dar, r0 + lwz r0, 0x0780(r1) + mtcr r0 + lwz r0, 0x0700(r1) + lwz r2, 0x0704(r1) + mtsprg 1, r2 + lmw r2, 0x0708(r1) + + + blr + + align 5 diff --git a/NanoKernel/NKTimers.s b/NanoKernel/NKTimers.s new file mode 100644 index 0000000..fa0d7eb --- /dev/null +++ b/NanoKernel/NKTimers.s @@ -0,0 +1,1002 @@ +Local_Panic set * + b panic + + + +; InitTMRQs + +; Xrefs: +; setup + +InitTMRQs ; OUTSIDE REFERER + addi r9, r1, -0xa84 + lis r8, 0x544d + ori r8, r8, 0x5251 + stw r8, 0x0004(r9) + stw r9, 0x0008(r9) + stw r9, 0x000c(r9) + li r8, 0x00 + stb r8, 0x0014(r9) + li r8, 0x01 + stb r8, 0x0016(r9) + stb r8, 0x0017(r9) + lis r8, 0x7fff + ori r8, r8, 0xffff + mtspr dec, r8 + stw r8, 0x0038(r9) + oris r8, r8, 0xffff + stw r8, 0x003c(r9) + mfspr r8, pvr + rlwinm. r8, r8, 0, 0, 14 + beq- InitTMRQs_0x7c + mflr r30 + li r8, 0x40 + +; r1 = kdp +; r8 = size + bl PoolAlloc +; r8 = ptr + + mr. r31, r8 + beq+ Local_Panic + stw r31, -0x0434(r1) + li r9, 0x07 + stb r9, 0x0014(r31) + li r9, 0x01 + stb r9, 0x0016(r31) + mtlr r30 + +InitTMRQs_0x7c + mfspr r8, pvr + rlwinm. r8, r8, 0, 0, 14 + beq- InitTMRQs_0xb4 + mflr r30 + li r8, 0x40 + +; r1 = kdp +; r8 = size + bl PoolAlloc +; r8 = ptr + + mr. r31, r8 + beq+ Local_Panic + stw r31, -0x0364(r1) + li r9, 0x08 + stb r9, 0x0014(r31) + li r9, 0x01 + stb r9, 0x0016(r31) + mtlr r30 + +InitTMRQs_0xb4 + lwz r30, 0x0630(r1) + lhz r31, 0x0378(r30) + cmplwi r31, 0x101 + blt- InitTMRQs_0x140 + lwz r31, 0x0388(r30) + clrlwi. r8, r31, 0x1f + beq- InitTMRQs_0x140 + lwz r8, 0x0edc(r1) + ori r8, r8, 0x02 + stw r8, 0x0edc(r1) + mflr r30 + li r8, 0x40 + +; r1 = kdp +; r8 = size + bl PoolAlloc +; r8 = ptr + + mr. r31, r8 + beq+ Local_Panic + li r9, 0x06 + stb r9, 0x0014(r31) + li r9, 0x01 + stb r9, 0x0016(r31) + bl GetTime + stw r8, 0x0038(r31) + stw r9, 0x003c(r31) + mr r8, r31 + bl called_by_init_tmrqs + _log 'Nanodebugger activated.^n' + mtlr r30 + +InitTMRQs_0x140 + blr + + + +; TimerDispatch + +; Xrefs: +; IntDecrementer +; major_0x130f0 + +TimerTable + + dc.l major_0x130f0 - NKTop + dc.l major_0x13120 - NKTop + dc.l major_0x1318c - NKTop + dc.l major_0x1324c - NKTop + dc.l major_0x132e8 - NKTop + dc.l major_0x13350 - NKTop + dc.l major_0x135b8 - NKTop + dc.l major_0x134bc - NKTop + dc.l major_0x13524 - NKTop + +TimerDispatch ; OUTSIDE REFERER + mflr r19 + mfsprg r18, 0 + stw r19, -0x0258(r18) + +TimerDispatch_0x30 ; OUTSIDE REFERER + mfspr r8, pvr + rlwinm. r8, r8, 0, 0, 14 + beq- TimerDispatch_0x54 + +TimerDispatch_0x3c + mftbu r8 + mftb r9 + mftbu r16 + cmpw r8, r16 + bne- TimerDispatch_0x3c + b TimerDispatch_0x90 + +TimerDispatch_0x54 + mfspr r8, rtcu + mfspr r9, rtcl + mfspr r16, rtcu + cmpw r8, r16 + bne- TimerDispatch_0x54 + lis r16, 0x3b9a + ori r16, r16, 0xca00 + mfspr r17, mq + dc.l 0x7d1040d6 + mfspr r16, mq + mtspr mq, r17 + mfxer r17 + addc r9, r16, r9 + addze r8, r8 + mtxer r17 + +TimerDispatch_0x90 + lbz r19, -0x0309(r18) + addi r30, r18, -0x320 + cmpwi r19, 0x01 + lwz r16, 0x0038(r30) + bne- TimerDispatch_0xcc + lwz r17, 0x003c(r30) + cmpw r16, r8 + cmplw cr1, r17, r9 + bgt- TimerDispatch_0xcc + blt- TimerDispatch_0xbc + bgt- cr1, TimerDispatch_0xcc + +TimerDispatch_0xbc + li r19, 0x00 + stw r30, -0x0254(r18) + stb r19, 0x0017(r30) + b major_0x132e8_0x10 + +TimerDispatch_0xcc + lwz r30, -0x0a7c(r1) + lwz r16, 0x0038(r30) + lwz r17, 0x003c(r30) + cmpw r16, r8 + cmplw cr1, r17, r9 + bgt- TimerDispatch_0x188 + blt- TimerDispatch_0xec + bgt- cr1, TimerDispatch_0x188 + +TimerDispatch_0xec + lwz r19, 0x0008(r30) + lwz r20, 0x000c(r30) + stw r19, 0x0008(r20) + stw r20, 0x000c(r19) + li r19, 0x00 + stw r19, 0x0008(r30) + stw r19, 0x000c(r30) + lwz r19, 0x064c(r1) + lbz r20, 0x0014(r30) + rlwimi r19, r20, 2, 23, 29 + cmplwi r20, 0x09 + llabel r20, TimerTable + li r21, 0x00 + add r20, r20, r19 + bgel+ Local_Panic + stb r21, 0x0017(r30) + lwz r20, 0x0000(r20) + add r20, r20, r19 + mtlr r20 + stw r30, -0x0254(r18) + blr + +TimerDispatch_0x144 + mfsprg r18, 0 + lwz r30, -0x0254(r18) + lbz r19, 0x0016(r30) + cmpwi r19, 0x01 + lwz r8, 0x0000(r30) + beq+ TimerDispatch_0x30 + bl DeleteID + mr r8, r30 + bl PoolFree + lwz r8, 0x001c(r30) + cmpwi r8, 0x00 + beq- TimerDispatch_0x180 + bl PoolFree + li r8, 0x00 + stw r8, 0x001c(r30) + +TimerDispatch_0x180: + mfsprg r18, 0 + b TimerDispatch_0x30 + +TimerDispatch_0x188 + lwz r19, -0x0258(r18) + mtlr r19 + b major_0x13060_0x18 + + + +; StartTimeslicing + +; Xrefs: +; setup + +StartTimeslicing ; OUTSIDE REFERER + mfsprg r19, 0 + + li r8, 1 + stb r8, -0x0309(r19) + + li r8, 0 + stw r8, -0x02e8(r19) + stw r8, -0x02e4(r19) + + mflr r19 + _log 'Starting timeslicing^n' + mtlr r19 + + + +; major_0x13060 + +; Xrefs: +; TimerDispatch +; StartTimeslicing +; called_by_init_tmrqs +; major_0x136c8 +; major_0x148ec + +major_0x13060 ; OUTSIDE REFERER + mflr r19 + bl GetTime + mtlr r19 + +major_0x13060_0xc ; OUTSIDE REFERER + lwz r18, -0x0a7c(r1) + lwz r16, 0x0038(r18) + lwz r17, 0x003c(r18) + +major_0x13060_0x18 ; OUTSIDE REFERER + mfxer r20 + mfsprg r19, 0 + lis r21, 0x7fff + lbz r18, -0x0309(r19) + ori r21, r21, 0xffff + cmpwi r18, 0x01 + bne- major_0x13060_0x58 + lwz r18, -0x02e8(r19) + lwz r19, -0x02e4(r19) + cmpw r16, r18 + cmplw cr1, r17, r19 + blt- major_0x13060_0x58 + bgt- major_0x13060_0x50 + ble- cr1, major_0x13060_0x58 + +major_0x13060_0x50 + mr r17, r19 + mr r16, r18 + +major_0x13060_0x58 + subfc r17, r9, r17 + subfe. r16, r8, r16 + mtxer r20 + blt- major_0x13060_0x84 + bne- major_0x13060_0x7c + cmplw r16, r21 + bgt- major_0x13060_0x7c + mtspr dec, r17 + blr + +major_0x13060_0x7c + mtspr dec, r21 + blr + +major_0x13060_0x84 + mtspr dec, r21 + mtspr dec, r16 + blr + + + +; major_0x130f0 + +; Xrefs: +; TimerDispatch + +major_0x130f0 ; OUTSIDE REFERER + _log 'TimerInformation.kind is zero??^n' + + + +; major_0x13120 + +; Xrefs: +; TimerDispatch +; major_0x130f0 + +major_0x13120 ; OUTSIDE REFERER + bl Local_Panic + lwz r18, 0x0018(r30) + stw r16, 0x0080(r18) + stw r17, 0x0084(r18) + lwz r8, 0x0018(r30) + li r16, 0x00 + lbz r17, 0x0018(r8) + lwz r19, 0x0088(r8) + cmpwi r17, 0x00 + stw r16, 0x011c(r19) + bne- major_0x13120_0x64 + addi r16, r8, 0x08 + lwz r17, 0x0008(r16) + lwz r19, 0x000c(r16) + stw r17, 0x0008(r19) + stw r19, 0x000c(r17) + li r17, 0x00 + stw r17, 0x0008(r16) + stw r17, 0x000c(r16) + li r17, 0x01 + stb r17, 0x0019(r8) + bl TaskReadyAsPrev + bl CalculateTimeslice + bl major_0x14af8 + b TimerDispatch_0x144 + +major_0x13120_0x64 + lwz r16, 0x0064(r8) + rlwinm. r16, r16, 0, 30, 30 + + + +; major_0x1318c + +; Xrefs: +; TimerDispatch +; major_0x13120 + +major_0x1318c ; OUTSIDE REFERER + bne+ TimerDispatch_0x144 + bl Local_Panic + lwz r18, 0x0018(r30) + stw r16, 0x0080(r18) + stw r17, 0x0084(r18) + lwz r8, 0x0018(r30) + li r16, -0x7270 + lbz r17, 0x0018(r8) + lwz r18, 0x0088(r8) + cmpwi r17, 0x00 + bne- major_0x1324c_0x8 + stw r16, 0x011c(r18) + lwz r8, 0x0008(r8) + lwz r8, 0x0000(r8) + +; r8 = id + bl LookupID + cmpwi r9, Queue.kIDClass + + cmpwi cr1, r9, 0x05 + beq- major_0x1318c_0x8c + beq- cr1, major_0x1318c_0x7c + cmpwi r9, 0x09 + cmpwi cr1, r9, 0x06 + beq- major_0x1318c_0x6c + bne+ cr1, Local_Panic + lwz r16, 0x0020(r8) + addi r16, r16, -0x01 + stw r16, 0x0020(r8) + b major_0x1318c_0x98 + +major_0x1318c_0x6c + lwz r16, 0x001c(r8) + addi r16, r16, -0x01 + stw r16, 0x001c(r8) + b major_0x1318c_0x98 + +major_0x1318c_0x7c + lwz r16, 0x001c(r8) + addi r16, r16, -0x01 + stw r16, 0x001c(r8) + b major_0x1318c_0x98 + +major_0x1318c_0x8c + lwz r16, 0x002c(r8) + addi r16, r16, -0x01 + stw r16, 0x002c(r8) + +major_0x1318c_0x98 + lwz r8, 0x0018(r30) + addi r16, r8, 0x08 + lwz r17, 0x0008(r16) + lwz r18, 0x000c(r16) + stw r17, 0x0008(r18) + stw r18, 0x000c(r17) + li r17, 0x00 + stw r17, 0x0008(r16) + stw r17, 0x000c(r16) + bl TaskReadyAsPrev + + + +; major_0x1324c + +; Xrefs: +; TimerDispatch +; major_0x1318c + +major_0x1324c ; OUTSIDE REFERER + bl major_0x14af8 + b TimerDispatch_0x144 + +major_0x1324c_0x8 ; OUTSIDE REFERER + b Local_Panic + + + +; major_0x13258 + +; Dead code -- probably removed from TimerTable + + lwz r8, 0x0018(r30) + +; r8 = id + bl LookupID + cmpwi r9, Queue.kIDClass + + mr r31, r8 + bne- major_0x13258_0x68 + lwz r16, 0x0024(r31) + lwz r8, 0x001c(r30) + cmpwi r16, 0x00 + cmpwi cr1, r8, 0x00 + beq- major_0x13258_0x40 + lwz r17, 0x0028(r31) + mr. r8, r17 + lwz r17, 0x0008(r17) + beq- major_0x13258_0x68 + stw r17, 0x0028(r31) + b major_0x13258_0x4c + +major_0x13258_0x40 + beq- cr1, major_0x13258_0x68 + li r16, 0x00 + stw r16, 0x001c(r30) + +major_0x13258_0x4c + lwz r16, 0x0020(r30) + lwz r17, 0x0024(r30) + lwz r18, 0x0028(r30) + stw r16, 0x0010(r8) + stw r17, 0x0014(r8) + stw r18, 0x0018(r8) + bl major_0x0c8b4 + +major_0x13258_0x68 + lwz r8, 0x0034(r30) + +; r8 = id + bl LookupID + cmpwi r9, Semaphore.kIDClass + + mr r31, r8 + bne- major_0x13258_0x80 + bl major_0x0ccf4 + +major_0x13258_0x80 + lwz r8, 0x002c(r30) + +; r8 = id + bl LookupID + cmpwi r9, EventGroup.kIDClass + + mr r31, r8 + + + +; major_0x132e8 + +; Xrefs: +; TimerDispatch +; major_0x13258 + +major_0x132e8 ; OUTSIDE REFERER + bne- major_0x132e8_0xc + lwz r8, 0x0030(r30) + bl major_0x0d35c + +major_0x132e8_0xc + b TimerDispatch_0x144 + +major_0x132e8_0x10 ; OUTSIDE REFERER + mfsprg r28, 0 + lwz r29, -0x0008(r28) + mr r8, r29 + bl major_0x13e4c + lbz r17, 0x0019(r29) + cmpwi r17, 0x02 + bge- major_0x132e8_0x64 + mr r8, r29 + lwz r16, 0x0038(r30) + lwz r17, 0x003c(r30) + bl clear_cr0_lt + bge- major_0x132e8_0x50 + mr r8, r29 + bl TaskReadyAsPrev + bl CalculateTimeslice + b major_0x13350_0x8 + +major_0x132e8_0x50 + li r18, 0x02 + stb r18, 0x0019(r29) + mr r8, r29 + bl TaskReadyAsPrev + b major_0x13350_0x8 + +major_0x132e8_0x64 + mr r8, r29 + + + +; major_0x13350 + +; Xrefs: +; TimerDispatch +; major_0x132e8 + +major_0x13350 ; OUTSIDE REFERER + bl TaskReadyAsPrev + bl major_0x149d4 + +major_0x13350_0x8 ; OUTSIDE REFERER + bl major_0x14af8 + mfsprg r18, 0 + b TimerDispatch_0x30 + + + +; major_0x13364 + +; Dead code -- probably removed from TimerTable + + _log 'Heartbeat: Ext ' + lwz r16, 0x0e80(r1) + mr r8, r16 + bl printd + _log 'Alerts ' + lwz r16, 0x0ee0(r1) + mr r8, r16 + bl printd + _log 'Blue cpu-' + lwz r17, -0x08f0(r1) + lhz r16, 0x001a(r17) + mr r8, r16 + bl printb + _log 'state-' + lbz r16, 0x0018(r17) + mr r8, r16 + bl printb + _log 'scr-' + lwz r16, 0x0658(r1) + lwz r18, 0x0674(r1) + lwz r16, 0x00dc(r16) + and r16, r16, r18 + mr r8, r16 + bl printw + _log 'mcr-' + lwz r16, -0x0440(r1) + mr r8, r16 + bl printw + _log 'IPL-' + lwz r16, 0x067c(r1) + lhz r16, 0x0000(r16) + mr r8, r16 + bl printh + _log 'eSR-' + lwz r16, 0x0658(r1) + lwz r16, 0x01cc(r16) + andi. r16, r16, 0x07 + mr r8, r16 + bl printb + _log '^n' + mfxer r19 + lwz r16, 0x0038(r30) + lwz r17, 0x003c(r30) + lwz r18, 0x0f2c(r1) + slwi r18, r18, 3 + addc r17, r17, r18 + + + +; major_0x134bc + +; Xrefs: +; TimerDispatch +; major_0x13364 + +major_0x134bc ; OUTSIDE REFERER + addze r16, r16 + stw r16, 0x0038(r30) + stw r17, 0x003c(r30) + mtxer r19 + mr r8, r30 + bl called_by_init_tmrqs + b TimerDispatch_0x144 + + + +; major_0x134d8 + +; Dead code -- probably removed from TimerTable + + lwz r18, -0x0438(r1) + lwz r19, 0x0f88(r1) + subf. r19, r18, r19 + ble- major_0x13524_0x1c + srwi r19, r19, 11 + mfxer r20 + +major_0x134d8_0x18 + mftbu r16 + mftb r17, 0x10c + mftbu r18 + cmpw r16, r18 + li r18, 0x00 + bne- major_0x134d8_0x18 + mttb r18 + addc r17, r17, r19 + addze r16, r16 + mttbu r16 + mttb r17 + lwz r18, -0x0438(r1) + srwi r18, r18, 11 + + + +; major_0x13524 + +; Xrefs: +; TimerDispatch +; major_0x134d8 + +major_0x13524 ; OUTSIDE REFERER + addc r17, r17, r18 + addze r16, r16 + stw r16, 0x0038(r30) + stw r17, 0x003c(r30) + mtxer r20 + mr r8, r30 + bl called_by_init_tmrqs + +major_0x13524_0x1c ; OUTSIDE REFERER + b TimerDispatch_0x144 + + + +; major_0x13544 + +; Dead code -- probably removed from TimerTable + + lwz r19, -0x036c(r1) + mfxer r20 + cmpwi cr1, r19, 0x00 + srawi r8, r19, 31 + beq- cr1, major_0x135b8_0x4 + +major_0x13544_0x14 + mftbu r16 + mftb r17, 0x10c + mftbu r18 + cmpw r16, r18 + li r18, 0x00 + bne- major_0x13544_0x14 + mttb r18 + addc r19, r17, r19 + adde r18, r16, r8 + mttbu r18 + mttb r19 + bgt- cr1, major_0x13544_0x64 + +major_0x13544_0x44 + mftbu r18 + mftb r19, 0x10c + mftbu r8 + cmpw r18, r8 + bne- major_0x13544_0x44 + subfc r19, r17, r19 + subfe. r18, r16, r18 + blt+ major_0x13544_0x44 + +major_0x13544_0x64 + lwz r18, -0x0368(r1) + addc r17, r17, r18 + addze r16, r16 + stw r16, 0x0038(r30) + + + +; major_0x135b8 + +; Xrefs: +; TimerDispatch +; major_0x13544 + +major_0x135b8 ; OUTSIDE REFERER + stw r17, 0x003c(r30) + +major_0x135b8_0x4 ; OUTSIDE REFERER + mtxer r20 + beq+ cr1, TimerDispatch_0x144 + mr r8, r30 + bl called_by_init_tmrqs + b TimerDispatch_0x144 + + + +; major_0x135d0 + +; Dead code -- probably removed from TimerTable + + mfxer r19 + lwz r16, 0x0038(r30) + lwz r17, 0x003c(r30) + lwz r18, 0x0f2c(r1) + srwi r18, r18, 1 + addc r17, r17, r18 + addze r16, r16 + stw r16, 0x0038(r30) + stw r17, 0x003c(r30) + mtxer r19 + mr r8, r30 + bl called_by_init_tmrqs + bl getchar + cmpwi r8, -0x01 + beq+ TimerDispatch_0x144 + bl panic_non_interactive + b TimerDispatch_0x144 + + + +; called_by_init_tmrqs + +; Xrefs: +; MPCall_55 +; NKSetClockStep +; NKSetClockDriftCorrection +; MPCall_18 +; MPCall_23 +; MPCall_27 +; MPCall_52 +; MPCall_31 +; InitTMRQs + +; ARG KernelData *r1, TimerQueueStruct *r8 + +called_by_init_tmrqs ; OUTSIDE REFERER + lwz r16, 0x0038(r8) + lwz r17, 0x003c(r8) + lwz r20, PSA.TimerQueue + TimerQueueStruct.LLL + LLL.Next(r1) + lwz r18, 0x0038(r20) + lwz r19, 0x003c(r20) + cmpw r16, r18 + cmplw cr1, r17, r19 + bgt- called_by_init_tmrqs_0x5c + blt- called_by_init_tmrqs_0x28 + bge- cr1, called_by_init_tmrqs_0x5c + +called_by_init_tmrqs_0x28 + addi r20, r1, -0xa84 + li r18, 0x01 + stb r18, 0x0017(r8) + lwz r19, 0x0000(r8) + lwz r9, 0x0000(r20) + stw r9, 0x0000(r8) + lwz r9, 0x0008(r20) + stw r9, 0x0008(r8) + stw r20, 0x000c(r8) + stw r8, 0x000c(r9) + stw r8, 0x0008(r20) + stw r19, 0x0000(r8) + b major_0x13060 + +called_by_init_tmrqs_0x5c + lwz r20, -0x0a78(r1) + +called_by_init_tmrqs_0x60 + lwz r18, 0x0038(r20) + lwz r19, 0x003c(r20) + cmpw r16, r18 + cmplw cr1, r17, r19 + bgt- called_by_init_tmrqs_0x84 + blt- called_by_init_tmrqs_0x7c + bge- cr1, called_by_init_tmrqs_0x84 + +called_by_init_tmrqs_0x7c + lwz r20, 0x000c(r20) + b called_by_init_tmrqs_0x60 + +called_by_init_tmrqs_0x84 + li r18, 0x01 + stb r18, 0x0017(r8) + lwz r19, 0x0000(r8) + lwz r9, 0x0000(r20) + stw r9, 0x0000(r8) + lwz r9, 0x0008(r20) + stw r9, 0x0008(r8) + stw r20, 0x000c(r8) + stw r8, 0x000c(r9) + stw r8, 0x0008(r20) + stw r19, 0x0000(r8) + blr + + + + + + + +; major_0x136c8 + +; Xrefs: +; NKSetClockStep +; NKSetClockDriftCorrection +; MPCall_16 +; major_0x0c8b4 +; major_0x0ccf4 +; MPCall_21 +; MPCall_28 +; MPCall_26 +; MPCall_50 +; major_0x0d35c +; MPCall_41 +; MPCall_31 +; MPCall_32 +; major_0x0dce8 +; MPCall_9 +; CommonPIHPath + +major_0x136c8 ; OUTSIDE REFERER + lwz r16, 0x0008(r8) + cmpwi r16, 0x00 + lwz r18, -0x0a7c(r1) + beq+ Local_Panic + lwz r16, 0x0008(r8) + lwz r17, 0x000c(r8) + stw r16, 0x0008(r17) + stw r17, 0x000c(r16) + li r16, 0x00 + stw r16, 0x0008(r8) + stw r16, 0x000c(r8) + li r16, 0x00 + cmpw r18, r8 + stb r16, 0x0017(r8) + beq+ major_0x13060 + blr + + + +; TimebaseTicksPerPeriod + +; Xrefs: +; MPCall_18 +; MPCall_23 +; MPCall_27 +; MPCall_52 +; MPCall_31 +; InitRDYQs + +; Get the number of timebase ticks in a specified period + +; ARG long r8 period (positive for ms, negative for us) + +TimebaseTicksPerPeriod + mr. r17, r8 + li r19, 250 + lwz r9, KDP.ProcessorInfo + NKProcessorInfo.DecClockRateHz(r1) + + bgt+ @period_positive + blt+ @period_negative + li r8, 0 + li r9, 0 + blr ; fail +@period_negative + neg r17, r17 + lisori r19, 250000 +@period_positive + + divw r19, r9, r19 + + mullw r9, r19, r17 + mulhw r8, r19, r17 + + srwi r9, r9, 2 + rlwimi r9, r8, 30, 0, 1 + srwi r8, r8, 2 + + blr + + + + +; Xrefs: +; NKSetClockStep +; NKSetClockDriftCorrection +; MPCall_18 +; MPCall_23 +; MPCall_27 +; MPCall_52 +; MPCall_40 +; MPCall_32 +; CreateTask +; InitTMRQs +; major_0x13060 +; major_0x142dc +; major_0x14548 + +; RET long r8 tbu, long r9 tbl +; CLOB r16, r17 + +GetTime + + mfpvr r8 + rlwinm. r8, r8, 0, 0, 14 + beq- @is_601 + +@retry_timebase: + mftbu r8 + mftb r9 + mftbu r16 + cmpw r8, r16 + bne- @retry_timebase + + b @return + +@is_601 + dialect POWER ; disassembled this in POWER mode! + +@retry_rtc + mfrtcu r8 + mfrtcl r9 + mfrtcu r16 + cmp 0, r8, r16 + + dialect PowerPC + bne- @retry_rtc ; POWER chokes on hints? + dialect POWER + + liu r16, 1000000000 >> 16 + oril r16, r16, 1000000000 & 0xffff + + mfmq r17 + mul r8, r16, r8 + mfmq r16 + mtmq r17 + + mfxer r17 + a r9, r16, r9 + aze r8, r8 + mtxer r17 + + dialect POWERPC + +@return + blr diff --git a/NanoKernel/NKTranslation.s b/NanoKernel/NKTranslation.s new file mode 100644 index 0000000..50e7b95 --- /dev/null +++ b/NanoKernel/NKTranslation.s @@ -0,0 +1,4374 @@ +; This file is tricky. Along with the file immediately before it, +; Interrupts.s, it emulates unsupported PowerPC instructions. +; This mechanism is heavily optimized, and the jumping between +; tables (which I have tried to describe as well as I can) is +; very confusing. + +; It is called 'FDP' because of a long-ago confusion about what it did. + +; Some of the mnemonics might look a bit odd, because I used MPW +; to disassemble instead of ppcdisasm.py or gas. + +; The init code puts a pointer to 'FDP' in the part of the KDP that is +; mostly shared with NKv1. Therefore this is probably deep Davidianian +; magic. The tables here contain relative references to other tables +; in Interrupts.s. What a mess. + + + align 11 + + +FDP + + +FDP_panic + bl panic + + +FDP_0004 + b FDP_024C + + +; This stuff is for emulating float storage instructions + +FDP_0008 ; stfs(x) + rlwinm r17, r17, 0, 16, 10 + + +FDP_000c ; stfsu(x) + crclr cr7_SO + b FDP_001C + + +FDP_0014 ; stfd(x), stfiwx + rlwinm r17, r17, 0, 16, 10 + + +FDP_0018 ; stfdu(x) + crset cr7_SO + + +FDP_001c ; called from above + clrrwi r19, r25, 10 + rlwimi r19, r17, 14, 24, 28 + addi r19, r19, FloatSaveJumpTable - FDP + mtlr r19 + rlwimi r14, r11, 0, 18, 18 + mtmsr r14 + isync + blr + + +FDP_003c ; Called by the jump table in the previous file + ori r11, r11, 0x2000 + lwz r20, -0x02E0(r1) + lwz r21, -0x02DC(r1) + bso cr7, FDP_00E8 + extrwi r23, r20, 11, 1 + cmpwi r23, 896 + insrwi r20, r20, 27, 2 + inslwi r20, r21, 3, 29 + mr r21, r20 + bgt FDP_00E8 + cmpwi r23, 874 + clrrwi r21, r20, 31 + blt FDP_00E8 + oris r20, r20, 0x0080 + neg r23, r23 + clrlwi r20, r20, 8 + srw r20, r20, r23 + rlwimi r21, r20, 31, 9, 31 + b FDP_00E8 + + +FDP_0088 ; stwbrx + rlwinm r28, r17, 13, 25, 29 + lwbrx r21, r1, r28 + b FDP_00E4 + + +FDP_0094 ; sthbrx + rlwinm r28, r17, 13, 25, 29 + addi r21, r1, 2 + lhbrx r21, r21, r28 + b FDP_00E4 + + +FDP_00a4 ; sthu(x) + rlwinm r28, r17, 13, 25, 29 + lwzx r21, r1, r28 + b FDP_00E8 + + +FDP_00b0 ; stwcx. + rlwinm r28, r17, 13, 25, 29 + lwzx r21, r1, r28 + + +FDP_00b8 ; lwarx + crset cr5_SO + b FDP_00E4 + + +FDP_00c0 ; lbzu(x), stbu(x), lhau(x), stmw + clrrwi r18, r18, 4 + rlwimi r15, r11, 0, 6, 6 + b FDP_00E4 + + +FDP_00cc ; lwzu(x) + clrrwi r18, r18, 1 + b FDP_00E4 + + +FDP_00d4 ; lbz(x) + clrrwi r18, r18, 2 + b FDP_00E4 + + +FDP_00dc ; ecowx, sth(x) + rlwinm r28, r17, 13, 25, 29 + lwzx r21, r1, r28 + + +FDP_00e4 ; eciwx, lwz(x), lbz(x), lhz(x), lha(x), lfs(x), lfd(x) + rlwinm r17, r17, 0, 16, 10 + + +FDP_00e8 ; lwbrx, lhbrx, lmw, lhzu(x), lhfsu(x), lfdu(x) + extrwi. r22, r17, 5, 26 + add r19, r18, r22 + b FDP_03AC + + +FDP_00f4 + srwi r23, r21, 16 + sth r23, -0x0004(r19) + subi r17, r17, 4 + sth r21, -0x0002(r19) + b FDP_011C + + +FDP_0108 + lhz r23, -0x0004(r19) + subi r17, r17, 4 + insrwi r21, r23, 16, 0 + + +FDP_0114 + lhz r23, -0x0002(r19) + insrwi r21, r23, 16, 16 + + +FDP_011c ; exported, r25 = address of routine in MixedTable + li r0, -3 + sc + bl major_0x03548 + rlwinm. r28, r17, 18, 25, 29 + mtlr r25 + mfsprg r1, 0 + cror cr0_EQ, cr0_EQ, cr3_EQ + mtsprg 3, r24 + beqlr + crset cr3_SO + stwx r18, r1, r28 + blr + + +FDP_014C + extsh r21, r21 + + +FDP_0150 + rlwinm r28, r17, 13, 25, 29 + crset cr3_SO + stwx r21, r1, r28 + + +FDP_015C + b FDP_0dA0 + + +FDP_0160 + slwi r21, r21, 16 + + +FDP_0164 + rlwinm r28, r17, 13, 25, 29 + crset cr3_SO + stwbrx r21, r1, r28 + b FDP_0dA0 + + +FDP_0174 + b FDP_0fA8 + +FDP_0178 + clrrwi r23, r25, 10 + rlwimi r23, r17, 14, 24, 28 + addi r23, r23, FloatLoadJumpTable - FDP + mtlr r23 + stw r20, -0x02E0(r1) + stw r21, -0x02DC(r1) + rlwimi r14, r11, 0, 18, 18 + mtmsr r14 + isync + ori r11, r11, 0x2000 + blr + + +FDP_01a4 + rlwinm. r28, r17, 13, 25, 29 + rlwinm r23, r17, 18, 25, 29 + cmpw cr7, r28, r23 + addis r17, r17, 32 + beq FDP_01BC + beq cr7, FDP_01C0 + + +FDP_01bc + stwx r21, r1, r28 + + +FDP_01c0 + cmpwi r28, 124 + li r22, 9 + insrwi r17, r22, 6, 26 + addi r19, r19, 4 + bne FDP_03AC + b FDP_0dA0 + + +FDP_01d8 + addis r17, r17, 32 + rlwinm. r28, r17, 13, 25, 29 + beq FDP_0dA0 + lwzx r21, r1, r28 + li r22, 8 + insrwi r17, r22, 6, 26 + addi r19, r19, 4 + b FDP_03AC + + +FDP_01f8 ; dcbz + lwz r21, -0x0004(r1) + lhz r21, 0x0F4A(r21) + neg r21, r21 + and r19, r18, r21 + b FDP_0224 + + +FDP_020c + lwz r21, -0x0004(r1) + lhz r21, 0x0F4A(r21) + subi r21, r21, 8 + and. r22, r19, r21 + clrrwi r19, r19, 3 + beq FDP_0dA0 + + +FDP_0224 + li r22, 16 + insrwi. r17, r22, 6, 26 + addi r19, r19, 8 + li r20, 0 + li r21, 0 + b FDP_03AC + + +FDP_023c + rlwinm r16, r16, 0, 28, 25 + subi r10, r10, 4 + stw r16, -0x0010(r1) + b FDP_0dA0 + + +FDP_024c + li r8, 18 + b major_0x02980 + + +FDP_0254 ; stswi + subi r22, r27, 2048 + extrwi r22, r22, 5, 16 + b FDP_0270 + + +FDP_0260 ; stswx + mfxer r22 + andi. r22, r22, 0x007F + subi r22, r22, 1 + beq FDP_0dA0 + + +FDP_0270 + rlwimi r17, r22, 4, 21, 25 + not r22, r22 + insrwi r17, r22, 2, 4 + mr r19, r18 + b FDP_0e60 + + +FDP_0284 + andi. r22, r17, 0x07C0 + addis r28, r17, 32 + rlwimi r17, r28, 0, 6, 10 + subi r17, r17, 64 + bne FDP_0e60 + b FDP_0dA0 + + +FDP_029c ; lswi + subi r22, r27, 2048 + extrwi r22, r22, 5, 16 + addis r28, r27, 992 + rlwimi r17, r28, 22, 16, 20 + b FDP_02C4 + + +FDP_02b0 ; lswx + mfxer r22 + andi. r22, r22, 0x007F + rlwimi r17, r27, 0, 16, 20 + subi r22, r22, 1 + beq FDP_0dA0 + + +FDP_02c4 + andis. r23, r17, 0x001F + rlwimi r17, r22, 4, 21, 25 + not r22, r22 + insrwi r17, r22, 2, 4 + mr r19, r18 + bne FDP_0eC8 + rlwimi r17, r17, 5, 11, 15 + b FDP_0eC8 + + +FDP_02e4 + andi. r22, r17, 0x07C0 + rlwinm r28, r17, 13, 25, 29 + bne FDP_0e9C + rlwinm r22, r17, 9, 27, 28 + slw r21, r21, r22 + b FDP_0e9C + + +FDP_02fc + rlwinm. r22, r17, 28, 25, 29 + rlwinm r28, r17, 13, 25, 29 + bne FDP_0eF4 + rlwinm r23, r17, 9, 27, 28 + slw r21, r21, r23 + b FDP_0eF4 + + +FDP_0314 ; unknown table entries + mfxer r22 + + +FDP_0318 + andi. r22, r22, 0x007F + rlwimi r17, r27, 0, 16, 20 + insrwi r17, r27, 1, 3 + cmpw cr7, r27, r22 + beq FDP_0f80 + subi r22, r22, 1 + andis. r23, r17, 0x001F + rlwimi r17, r22, 4, 21, 25 + not r22, r22 + insrwi r17, r22, 2, 4 + mr r19, r18 + bne FDP_0eC8 + rlwimi r17, r17, 5, 11, 15 + b FDP_0eC8 + + +FDP_0350 ; stw(x) + li r20, 11040 + b FDP_1024 + + +FDP_0358 ; stwu(x) + clrrwi r18, r18, 1 + li r20, 11296 + b FDP_1024 + + +FDP_0364 ; stb(x) + clrrwi r18, r18, 2 + li r20, 11552 + b FDP_1024 + + +FDP_0370 + subi r23, r1, 736 + li r20, 10016 + insrwi r23, r18, 4, 28 + stb r21, 0x0000(r23) + b FDP_1000 + + +FDP_0384 + subi r23, r1, 736 + li r20, 10272 + insrwi r23, r18, 4, 28 + sth r21, 0x0000(r23) + b FDP_1000 + + +FDP_0398 + subi r23, r1, 736 + li r20, 10528 + insrwi r23, r18, 4, 28 + stw r21, 0x0000(r23) + b FDP_1000 + + +FDP_03ac + lwz r1, -0x0004(r1) + clrrwi r25, r25, 10 + insrwi r25, r19, 3, 28 + insrwi r25, r17, 5, 23 + lha r22, 0x0C00(r25) + addi r23, r1, 1248 + add r22, r22, r25 + mfsprg r1, 0 + mtlr r22 + ori r15, r15, 0x4000 + mtsprg 3, r23 + mtmsr r15 + isync + insrwi r25, r26, 8, 22 + bnelr + b FDP_011C + + +FDP_03ec + lbz r23, -0x0008(r19) + subi r17, r17, 2 + insrwi r20, r23, 8, 0 + + +FDP_03f8 + lhz r23, -0x0007(r19) + subi r17, r17, 4 + insrwi r20, r23, 16, 8 + b FDP_0414 + + +FDP_0408 + lbz r23, -0x0006(r19) + subi r17, r17, 2 + insrwi r20, r23, 8, 16 + + +FDP_0414 + lwz r23, -0x0005(r19) + subi r17, r17, 8 + inslwi r20, r23, 8, 24 + insrwi r21, r23, 24, 0 + b FDP_0490 + + +FDP_0428 + lbz r23, -0x0008(r19) + subi r17, r17, 2 + insrwi r20, r23, 8, 0 + +FDP_0434 + lwz r23, -0x0007(r19) + subi r17, r17, 8 + inslwi r20, r23, 24, 8 + insrwi r21, r23, 8, 0 + b FDP_0474 + + +FDP_0448 + lbz r23, -0x0006(r19) + subi r17, r17, 2 + insrwi r20, r23, 8, 16 + + +FDP_0454 + lhz r23, -0x0005(r19) + subi r17, r17, 4 + rlwimi r20, r23, 24, 24, 31 + insrwi r21, r23, 8, 0 + b FDP_0474 + + +FDP_0468 + lbz r23, -0x0004(r19) + subi r17, r17, 2 + insrwi r21, r23, 8, 0 + + +FDP_0474 + lhz r23, -0x0003(r19) + subi r17, r17, 4 + insrwi r21, r23, 16, 8 + b FDP_0490 + + +FDP_0484 + lbz r23, -0x0002(r19) + subi r17, r17, 2 + insrwi r21, r23, 8, 16 + + +FDP_0490 + lbz r23, -0x0001(r19) + insrwi r21, r23, 8, 24 + b FDP_011C + + +FDP_049c + lhz r23, -0x0008(r19) + subi r17, r17, 4 + insrwi r20, r23, 16, 0 + b FDP_04B8 + + +FDP_04ac + lbz r23, -0x0007(r19) + subi r17, r17, 2 + insrwi r20, r23, 8, 8 + + +FDP_04b8 + lwz r23, -0x0006(r19) + subi r17, r17, 8 + inslwi r20, r23, 16, 16 + insrwi r21, r23, 16, 0 + b FDP_0114 + + +FDP_04cc + lbz r23, -0x0005(r19) + subi r17, r17, 2 + insrwi r20, r23, 8, 24 + b FDP_0108 + + +FDP_04dc + lbz r23, -0x0003(r19) + subi r17, r17, 2 + insrwi r21, r23, 8, 8 + b FDP_0114 + + +FDP_04ec + lwz r20, -0x0008(r19) + subi r17, r17, 8 + lwz r21, -0x0004(r19) + b FDP_011C + + +FDP_04fc + lbz r23, -0x0007(r19) + subi r17, r17, 2 + insrwi r20, r23, 8, 8 + + +FDP_0508 + lhz r23, -0x0006(r19) + subi r17, r17, 4 + insrwi r20, r23, 16, 16 + lwz r21, -0x0004(r19) + b FDP_011C + + +FDP_051c + lbz r23, -0x0005(r19) + subi r17, r17, 2 + insrwi r20, r23, 8, 24 + lwz r21, -0x0004(r19) + b FDP_011C + + +FDP_0530 + bso cr5, FDP_053C + lwz r21, -0x0004(r19) + b FDP_011C + + +FDP_053c + li r23, -4 + lwarx r21, r23, r19 + b FDP_011C + + +FDP_0548 + lwz r20, -0x0008(r19) + lwz r21, -0x0004(r19) + b FDP_011C + + +FDP_0554 + clrrwi r23, r25, 10 + rlwimi r23, r17, 14, 24, 28 + addi r23, r23, 9760 + mtlr r23 + mr r23, r18 + oris r11, r11, 0x0200 + blr + + +FDP_0570 + srwi r23, r20, 24 + stb r23, -0x0008(r19) + subi r17, r17, 2 + + +FDP_057c + srwi r23, r20, 8 + sth r23, -0x0007(r19) + subi r17, r17, 4 + b FDP_0598 + + +FDP_058c + srwi r23, r20, 8 + stb r23, -0x0006(r19) + subi r17, r17, 2 + + +FDP_0598 + srwi r23, r21, 8 + insrwi r23, r20, 8, 0 + stw r23, -0x0005(r19) + subi r17, r17, 8 + stb r21, -0x0001(r19) + b FDP_011C + + +FDP_05b0 + srwi r23, r20, 24 + stb r23, -0x0008(r19) + subi r17, r17, 2 + + +FDP_05bc + srwi r23, r21, 24 + insrwi r23, r20, 24, 0 + stw r23, -0x0007(r19) + subi r17, r17, 8 + b FDP_05FC + + +FDP_05d0 + srwi r23, r20, 8 + stb r23, -0x0006(r19) + subi r17, r17, 2 + + +FDP_05dc + srwi r23, r21, 24 + insrwi r23, r20, 8, 16 + sth r23, -0x0005(r19) + subi r17, r17, 4 + b FDP_05FC + + +FDP_05f0 + srwi r23, r21, 24 + stb r23, -0x0004(r19) + subi r17, r17, 2 + + +FDP_05fc + srwi r23, r21, 8 + sth r23, -0x0003(r19) + subi r17, r17, 4 + stb r21, -0x0001(r19) + b FDP_011C + + +FDP_0610 + srwi r23, r21, 8 + stb r23, -0x0002(r19) + subi r17, r17, 2 + + +FDP_061c + stb r21, -0x0001(r19) + b FDP_011C + + +FDP_0624 + srwi r23, r20, 16 + sth r23, -0x0008(r19) + subi r17, r17, 4 + b FDP_0640 + + +FDP_0634 + srwi r23, r20, 16 + stb r23, -0x0007(r19) + subi r17, r17, 2 + + +FDP_0640 + srwi r23, r21, 16 + insrwi r23, r20, 16, 0 + stw r23, -0x0006(r19) + subi r17, r17, 8 + sth r21, -0x0002(r19) + b FDP_011C + + +FDP_0658 + stb r20, -0x0005(r19) + subi r17, r17, 2 + b FDP_00F4 + + +FDP_0664 + srwi r23, r21, 16 + stb r23, -0x0003(r19) + subi r17, r17, 2 + + +FDP_0670 + sth r21, -0x0002(r19) + b FDP_011C + + +FDP_0678 + stw r20, -0x0008(r19) + subi r17, r17, 8 + stw r21, -0x0004(r19) + b FDP_011C + + +FDP_0688 + srwi r23, r20, 16 + stb r23, -0x0007(r19) + subi r17, r17, 2 + + +FDP_0694 + sth r20, -0x0006(r19) + subi r17, r17, 4 + stw r21, -0x0004(r19) + b FDP_011C + + +FDP_06a4 + stb r20, -0x0005(r19) + subi r17, r17, 2 + stw r21, -0x0004(r19) + b FDP_011C + + +FDP_06b4 + bso cr5, FDP_06C0 + stw r21, -0x0004(r19) + b FDP_011C + + +FDP_06c0 + li r23, -4 + stwcx. r21, r23, r19 + isync + mfcr r23 + rlwimi r13, r23, 0, 0, 3 + b FDP_011C + + +FDP_06d8 + stw r20, -0x0008(r19) + stw r21, -0x0004(r19) + b FDP_011C + + +FDP_06e4 + clrrwi r23, r25, 10 + rlwimi r23, r17, 14, 24, 28 + addi r23, r23, 10784 + mtlr r23 + mr r23, r18 + oris r11, r11, 0x0200 + blr + + + + + + +; major_0x05f00 + + ; Which to use? Probably align. + align 9 +; org FDP + 0x800 + + + + macro + MisalignmentOpcodeTableEntry &hihalf, &primaryfunc, &secondaryfunc + + dc.w &hihalf + dc.b (&primaryfunc - FDP) >> 2 + dc.b (&secondaryfunc - FDP) >> 2 + + endm + + + + macro + MisalignmentOpcodeTableMacro &FirstTable + + +; X-form extended opcodes: 0 4 8 12 16 20 24 28 +; lwarx + + MisalignmentOpcodeTableEntry 0x2540, FDP_00b8, FDP_0150 + + +; X-form extended opcodes: 64 68 72 76 80 84 88 92 + + MisalignmentOpcodeTableEntry 0x4550, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 128 132 136 140 144 148 152 156 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 192 196 200 204 208 212 216 220 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 256 260 264 268 272 276 280 284 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 320 324 328 332 336 340 344 348 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 384 388 392 396 400 404 408 412 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 448 452 456 460 464 468 472 476 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 512 516 520 524 528 532 536 540 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 576 580 584 588 592 596 600 604 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 640 644 648 652 656 660 664 668 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 704 708 712 716 720 724 728 732 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 768 772 776 780 784 788 792 796 + + MisalignmentOpcodeTableEntry 0x4430, FDP_00e4, FDP_0150 + + +; X-form extended opcodes: 832 836 840 844 848 852 856 860 + + MisalignmentOpcodeTableEntry 0x2460, FDP_00e4, FDP_0150 + + +; X-form extended opcodes: 896 900 904 908 912 916 920 924 + + MisalignmentOpcodeTableEntry 0x4130, FDP_00dc, FDP_015C + + +; X-form extended opcodes: 960 964 968 972 976 980 984 988 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 32 36 40 44 48 52 56 60 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 96 100 104 108 112 116 120 124 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 160 164 168 172 176 180 184 188 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 224 228 232 236 240 244 248 252 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 288 292 296 300 304 308 312 316 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 352 356 360 364 368 372 376 380 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 416 420 424 428 432 436 440 444 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 480 484 488 492 496 500 504 508 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 544 548 552 556 560 564 568 572 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 608 612 616 620 624 628 632 636 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 672 676 680 684 688 692 696 700 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 736 740 744 748 752 756 760 764 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 800 804 808 812 816 820 824 828 + + MisalignmentOpcodeTableEntry 0x4430, FDP_00e8, FDP_0150 + + +; X-form extended opcodes: 864 868 872 876 880 884 888 892 + + MisalignmentOpcodeTableEntry 0x45b3, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 928 932 936 940 944 948 952 956 + + MisalignmentOpcodeTableEntry 0x4130, FDP_00a4, FDP_015C + + +; X-form extended opcodes: 992 996 1000 1004 1008 1012 1016 1020 + + MisalignmentOpcodeTableEntry 0x41f2, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 1 5 9 13 17 21 25 29 + + MisalignmentOpcodeTableEntry 0x4430, FDP_00e4, FDP_0150 + + +; X-form extended opcodes: 65 69 73 77 81 85 89 93 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 129 133 137 141 145 149 153 157 + + MisalignmentOpcodeTableEntry 0x4130, FDP_00dc, FDP_015C + + +; X-form extended opcodes: 193 197 201 205 209 213 217 221 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 257 261 265 269 273 277 281 285 + + MisalignmentOpcodeTableEntry 0x268b, FDP_0314, FDP_02FC + + +; X-form extended opcodes: 321 325 329 333 337 341 345 349 + + MisalignmentOpcodeTableEntry 0x2460, FDP_00e4, FDP_0150 + + +; X-form extended opcodes: 385 389 393 397 401 405 409 413 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 449 453 457 461 465 469 473 477 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; lswx +; X-form extended opcodes: 513 517 521 525 529 533 537 541 + + MisalignmentOpcodeTableEntry 0x260b, FDP_02b0, FDP_02E4 + + +; lswi +; X-form extended opcodes: 577 581 585 589 593 597 601 605 + + MisalignmentOpcodeTableEntry 0x260f, FDP_029c, FDP_02E4 + + +; stswx +; X-form extended opcodes: 641 645 649 653 657 661 665 669 + + MisalignmentOpcodeTableEntry 0x2242, FDP_0260, FDP_0284 + + +; stswi +; X-form extended opcodes: 705 709 713 717 721 725 729 733 + + MisalignmentOpcodeTableEntry 0x224e, FDP_0254, FDP_0284 + + +; X-form extended opcodes: 769 773 777 781 785 789 793 797 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 833 837 841 845 849 853 857 861 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 897 901 905 909 913 917 921 925 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 961 965 969 973 977 981 985 989 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 33 37 41 45 49 53 57 61 + + MisalignmentOpcodeTableEntry 0x4430, FDP_00e8, FDP_0150 + + +; X-form extended opcodes: 97 101 105 109 113 117 121 125 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 161 165 169 173 177 181 185 189 + + MisalignmentOpcodeTableEntry 0x4130, FDP_00a4, FDP_015C + + +; X-form extended opcodes: 225 229 233 237 241 245 249 253 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 289 293 297 301 305 309 313 317 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 353 357 361 365 369 373 377 381 + + MisalignmentOpcodeTableEntry 0x2460, FDP_00e8, FDP_015C + + +; X-form extended opcodes: 417 421 425 429 433 437 441 445 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 481 485 489 493 497 501 505 509 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 545 549 553 557 561 565 569 573 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 609 613 617 621 625 629 633 637 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 673 677 681 685 689 693 697 701 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 737 741 745 749 753 757 761 765 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 801 805 809 813 817 821 825 829 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 865 869 873 877 881 885 889 893 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 929 933 937 941 945 949 953 957 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 993 997 1001 1005 1009 1013 1017 1021 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 2 6 10 14 18 22 26 30 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 66 70 74 78 82 86 90 94 + + MisalignmentOpcodeTableEntry 0x0fe2, FDP_00e8, FDP_023C + + +; X-form extended opcodes: 130 134 138 142 146 150 154 158 +; stwcx. + + MisalignmentOpcodeTableEntry 0x2160, FDP_00b0, FDP_015C + + +; X-form extended opcodes: 194 198 202 206 210 214 218 222 + + MisalignmentOpcodeTableEntry 0x4170, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 258 262 266 270 274 278 282 286 + + MisalignmentOpcodeTableEntry 0x0fe2, FDP_00e8, FDP_023C + + +; X-form extended opcodes: 322 326 330 334 338 342 346 350 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 386 390 394 398 402 406 410 414 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 450 454 458 462 466 470 474 478 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; lwbrx +; X-form extended opcodes: 514 518 522 526 530 534 538 542 + + MisalignmentOpcodeTableEntry 0x24a2, FDP_00e8, FDP_0164 + + +; X-form extended opcodes: 578 582 586 590 594 598 602 606 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; stwbrx +; X-form extended opcodes: 642 646 650 654 658 662 666 670 + + MisalignmentOpcodeTableEntry 0x2120, FDP_0088, FDP_015C + + +; X-form extended opcodes: 706 710 714 718 722 726 730 734 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; lhbrx +; X-form extended opcodes: 770 774 778 782 786 790 794 798 + + MisalignmentOpcodeTableEntry 0x1492, FDP_00e8, FDP_0160 + + +; X-form extended opcodes: 834 838 842 846 850 854 858 862 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; sthbrx +; X-form extended opcodes: 898 902 906 910 914 918 922 926 + + MisalignmentOpcodeTableEntry 0x1110, FDP_0094, FDP_015C + + +; X-form extended opcodes: 962 966 970 974 978 982 986 990 + + MisalignmentOpcodeTableEntry 0x0fe2, FDP_00e8, FDP_023C + + +; X-form extended opcodes: 34 38 42 46 50 54 58 62 + + if &FirstTable + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + else + MisalignmentOpcodeTableEntry 0x0fe2, FDP_00e8, FDP_023C + endif + + +; X-form extended opcodes: 98 102 106 110 114 118 122 126 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 162 166 170 174 178 182 186 190 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 226 230 234 238 242 246 250 254 + + MisalignmentOpcodeTableEntry 0x0fe2, FDP_00e8, FDP_023C + + +; eciwx +; X-form extended opcodes: 290 294 298 302 306 310 314 318 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_00e4, FDP_024C + + +; X-form extended opcodes: 354 358 362 366 370 374 378 382 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; ecowx +; X-form extended opcodes: 418 422 426 430 434 438 442 446 + + MisalignmentOpcodeTableEntry 0x03f0, FDP_00dc, FDP_024C + + +; X-form extended opcodes: 482 486 490 494 498 502 506 510 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 546 550 554 558 562 566 570 574 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 610 614 618 622 626 630 634 638 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 674 678 682 686 690 694 698 702 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 738 742 746 750 754 758 762 766 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 802 806 810 814 818 822 826 830 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 866 870 874 878 882 886 890 894 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 930 934 938 942 946 950 954 958 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; dcbz +; X-form extended opcodes: 994 998 1002 1006 1010 1014 1018 1022 + + MisalignmentOpcodeTableEntry 0x4302, FDP_01f8, FDP_020C + + +; lwzx +; X-form extended opcodes: 3 7 11 15 19 23 27 31 +; D-form opcodes: 0 32 +; lwz + + if &FirstTable + MisalignmentOpcodeTableEntry 0x0f50, FDP_00e4, FDP_0370 + else + MisalignmentOpcodeTableEntry 0x2420, FDP_00e4, FDP_0150 + endif + + +; lbzx +; X-form extended opcodes: 67 71 75 79 83 87 91 95 +; D-form opcodes: 2 34 +; lbz + + if &FirstTable + MisalignmentOpcodeTableEntry 0x2770, FDP_00d4, FDP_0398 + else + MisalignmentOpcodeTableEntry 0x0c00, FDP_00e4, FDP_0150 + endif + + +; stwx +; X-form extended opcodes: 131 135 139 143 147 151 155 159 +; D-form opcodes: 4 36 +; stw + + if &FirstTable + MisalignmentOpcodeTableEntry 0x0b90, FDP_0350, FDP_015C + else + MisalignmentOpcodeTableEntry 0x2120, FDP_00dc, FDP_015C + endif + + +; stbx +; X-form extended opcodes: 195 199 203 207 211 215 219 223 +; D-form opcodes: 6 38 +; stb + + if &FirstTable + MisalignmentOpcodeTableEntry 0x23b0, FDP_0364, FDP_015C + else + MisalignmentOpcodeTableEntry 0x0900, FDP_00dc, FDP_015C + endif + + +; lhzx +; X-form extended opcodes: 259 263 267 271 275 279 283 287 +; D-form opcodes: 8 40 +; lhz + + MisalignmentOpcodeTableEntry 0x1410, FDP_00e4, FDP_0150 + +; lhax +; X-form extended opcodes: 323 327 331 335 339 343 347 351 +; D-form opcodes: 10 42 +; lha + + MisalignmentOpcodeTableEntry 0x1450, FDP_00e4, FDP_014C + + +; sthx +; X-form extended opcodes: 387 391 395 399 403 407 411 415 +; D-form opcodes: 12 44 +; sth + + MisalignmentOpcodeTableEntry 0x1110, FDP_00dc, FDP_015C + + +; X-form extended opcodes: 451 455 459 463 467 471 475 479 +; D-form opcodes: 14 46 +; lmw + + MisalignmentOpcodeTableEntry 0x25a3, FDP_00e8, FDP_01A4 + + +; lfsx +; X-form extended opcodes: 515 519 523 527 531 535 539 543 +; D-form opcodes: 16 48 +; lfs + + MisalignmentOpcodeTableEntry 0x24e0, FDP_00e4, FDP_0174 + + +; lfdx +; X-form extended opcodes: 579 583 587 591 595 599 603 607 +; D-form opcodes: 18 50 +; lfd + + MisalignmentOpcodeTableEntry 0x44f0, FDP_00e4, FDP_0178 + + +; stfsx +; X-form extended opcodes: 643 647 651 655 659 663 667 671 +; D-form opcodes: 20 52 +; stfs + + MisalignmentOpcodeTableEntry 0x2120, FDP_0008, FDP_015C + + +; stfdx +; X-form extended opcodes: 707 711 715 719 723 727 731 735 +; D-form opcodes: 22 54 +; stfd + + MisalignmentOpcodeTableEntry 0x4130, FDP_0014, FDP_015C + + +; X-form extended opcodes: 771 775 779 783 787 791 795 799 +; D-form opcodes: 24 56 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 835 839 843 847 851 855 859 863 +; D-form opcodes: 26 58 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 899 903 907 911 915 919 923 927 +; D-form opcodes: 28 60 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; stfiwx +; X-form extended opcodes: 963 967 971 975 979 983 987 991 +; D-form opcodes: 30 62 + + MisalignmentOpcodeTableEntry 0x2120, FDP_0014, FDP_015C + + +; lwzux +; X-form extended opcodes: 35 39 43 47 51 55 59 63 +; D-form opcodes: 1 33 +; lwzu + + if &FirstTable + MisalignmentOpcodeTableEntry 0x1760, FDP_00cc, FDP_0384 + else + MisalignmentOpcodeTableEntry 0x2420, FDP_00e8, FDP_0150 + endif + + +; lbzux +; X-form extended opcodes: 99 103 107 111 115 119 123 127 +; D-form opcodes: 3 35 +; lbzu + + if &FirstTable + MisalignmentOpcodeTableEntry 0x8740, FDP_00c0, FDP_015C + else + MisalignmentOpcodeTableEntry 0x0c00, FDP_00e8, FDP_0150 + endif + + +; stwux +; X-form extended opcodes: 163 167 171 175 179 183 187 191 +; D-form opcodes: 5 37 +; stwu + + if &FirstTable + MisalignmentOpcodeTableEntry 0x23a0, FDP_0358, FDP_015C + else + MisalignmentOpcodeTableEntry 0x2120, FDP_00a4, FDP_015C + endif + + +; stbux +; X-form extended opcodes: 227 231 235 239 243 247 251 255 +; D-form opcodes: 7 39 +; stbu + + if &FirstTable + MisalignmentOpcodeTableEntry 0x8380, FDP_00c0, FDP_015C + else + MisalignmentOpcodeTableEntry 0x0900, FDP_00a4, FDP_015C + endif + + +; lhzux +; X-form extended opcodes: 291 295 299 303 307 311 315 319 +; D-form opcodes: 9 41 +; lhzu + + MisalignmentOpcodeTableEntry 0x1410, FDP_00e8, FDP_0150 + + +; lhaux +; X-form extended opcodes: 355 359 363 367 371 375 379 383 +; D-form opcodes: 11 43 +; lhau + + if &FirstTable + MisalignmentOpcodeTableEntry 0x8740, FDP_00c0, FDP_015C + else + MisalignmentOpcodeTableEntry 0x1450, FDP_00e8, FDP_014C + endif + + +; sthux +; X-form extended opcodes: 419 423 427 431 435 439 443 447 +; D-form opcodes: 13 45 +; sthu + + MisalignmentOpcodeTableEntry 0x1110, FDP_00a4, FDP_015C + + +; X-form extended opcodes: 483 487 491 495 499 503 507 511 +; D-form opcodes: 15 47 +; stmw + + if &FirstTable + MisalignmentOpcodeTableEntry 0x8380, FDP_00c0, FDP_015C + else + MisalignmentOpcodeTableEntry 0x21e2, FDP_00a4, FDP_01D8 + endif + + +; lfsux +; X-form extended opcodes: 547 551 555 559 563 567 571 575 +; D-form opcodes: 17 49 +; lfsu + + MisalignmentOpcodeTableEntry 0x24e0, FDP_00e8, FDP_0174 + + +; lfdux +; X-form extended opcodes: 611 615 619 623 627 631 635 639 +; D-form opcodes: 19 51 +; lfdu + + MisalignmentOpcodeTableEntry 0x44f0, FDP_00e8, FDP_0178 + + +; stfsux +; X-form extended opcodes: 675 679 683 687 691 695 699 703 +; D-form opcodes: 21 53 +; stfsu + + MisalignmentOpcodeTableEntry 0x2120, FDP_000c, FDP_015C + + +; stfdux +; X-form extended opcodes: 739 743 747 751 755 759 763 767 +; D-form opcodes: 23 55 +; stfdu + + MisalignmentOpcodeTableEntry 0x4130, FDP_0018, FDP_015C + + +; X-form extended opcodes: 803 807 811 815 819 823 827 831 +; D-form opcodes: 25 57 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 867 871 875 879 883 887 891 895 +; D-form opcodes: 27 59 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 931 935 939 943 947 951 955 959 +; D-form opcodes: 29 61 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 995 999 1003 1007 1011 1015 1019 1023 +; D-form opcodes: 31 63 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + endm + + + + MisalignmentOpcodeTableMacro 1 + MisalignmentOpcodeTableMacro 0 + + + + + + + + macro + HalfWordTableEntry &n, &target + +@flashback + org HalfWordTable + 2*&n + dc.w &target - FDP - 2*&n + org @flashback + + endm + +HalfWordTable ; FDP + 0xc00 + dcb.w 144, 0xcafe;(FDP_panic - FDP) - (* - HalfWordTable) + + + HalfWordTableEntry 0, FDP_06e4 + HalfWordTableEntry 1, FDP_06e4 + HalfWordTableEntry 2, FDP_06e4 + HalfWordTableEntry 3, FDP_06e4 + HalfWordTableEntry 4, FDP_06e4 + HalfWordTableEntry 5, FDP_06e4 + HalfWordTableEntry 6, FDP_06e4 + HalfWordTableEntry 7, FDP_06e4 + + HalfWordTableEntry 8, FDP_0554 + HalfWordTableEntry 9, FDP_0554 + HalfWordTableEntry 10, FDP_0554 + HalfWordTableEntry 11, FDP_0554 + HalfWordTableEntry 12, FDP_0554 + HalfWordTableEntry 13, FDP_0554 + HalfWordTableEntry 14, FDP_0554 + HalfWordTableEntry 15, FDP_0554 + + HalfWordTableEntry 16, FDP_061c + HalfWordTableEntry 17, FDP_061c + HalfWordTableEntry 18, FDP_061c + HalfWordTableEntry 19, FDP_061c + HalfWordTableEntry 20, FDP_061c + HalfWordTableEntry 21, FDP_061c + HalfWordTableEntry 22, FDP_061c + HalfWordTableEntry 23, FDP_061c + + HalfWordTableEntry 24, FDP_0490 + HalfWordTableEntry 25, FDP_0490 + HalfWordTableEntry 26, FDP_0490 + HalfWordTableEntry 27, FDP_0490 + HalfWordTableEntry 28, FDP_0490 + HalfWordTableEntry 29, FDP_0490 + HalfWordTableEntry 30, FDP_0490 + HalfWordTableEntry 31, FDP_0490 + + HalfWordTableEntry 32, FDP_0670 + HalfWordTableEntry 33, FDP_0610 + HalfWordTableEntry 34, FDP_0670 + HalfWordTableEntry 35, FDP_0610 + HalfWordTableEntry 36, FDP_0670 + HalfWordTableEntry 37, FDP_0610 + HalfWordTableEntry 38, FDP_0670 + HalfWordTableEntry 39, FDP_0610 + + HalfWordTableEntry 40, FDP_0114 + HalfWordTableEntry 41, FDP_0484 + HalfWordTableEntry 42, FDP_0114 + HalfWordTableEntry 43, FDP_0484 + HalfWordTableEntry 44, FDP_0114 + HalfWordTableEntry 45, FDP_0484 + HalfWordTableEntry 46, FDP_0114 + HalfWordTableEntry 47, FDP_0484 + + HalfWordTableEntry 48, FDP_0664 + HalfWordTableEntry 49, FDP_05fc + HalfWordTableEntry 50, FDP_0664 + HalfWordTableEntry 51, FDP_05fc + HalfWordTableEntry 52, FDP_0664 + HalfWordTableEntry 53, FDP_05fc + HalfWordTableEntry 54, FDP_0664 + HalfWordTableEntry 55, FDP_05fc + + HalfWordTableEntry 56, FDP_04dc + HalfWordTableEntry 57, FDP_0474 + HalfWordTableEntry 58, FDP_04dc + HalfWordTableEntry 59, FDP_0474 + HalfWordTableEntry 60, FDP_04dc + HalfWordTableEntry 61, FDP_0474 + HalfWordTableEntry 62, FDP_04dc + HalfWordTableEntry 63, FDP_0474 + + HalfWordTableEntry 64, FDP_06b4 + HalfWordTableEntry 65, FDP_05f0 + HalfWordTableEntry 66, FDP_00f4 + HalfWordTableEntry 67, FDP_05f0 + HalfWordTableEntry 68, FDP_06b4 + HalfWordTableEntry 69, FDP_05f0 + HalfWordTableEntry 70, FDP_00f4 + HalfWordTableEntry 71, FDP_05f0 + + HalfWordTableEntry 72, FDP_0530 + HalfWordTableEntry 73, FDP_0468 + HalfWordTableEntry 74, FDP_0108 + HalfWordTableEntry 75, FDP_0468 + HalfWordTableEntry 76, FDP_0530 + HalfWordTableEntry 77, FDP_0468 + HalfWordTableEntry 78, FDP_0108 + HalfWordTableEntry 79, FDP_0468 + + HalfWordTableEntry 80, FDP_06a4 + HalfWordTableEntry 81, FDP_0598 + HalfWordTableEntry 82, FDP_0658 + HalfWordTableEntry 83, FDP_05dc + HalfWordTableEntry 84, FDP_06a4 + HalfWordTableEntry 85, FDP_0598 + HalfWordTableEntry 86, FDP_0658 + HalfWordTableEntry 87, FDP_05dc + + HalfWordTableEntry 88, FDP_051c + HalfWordTableEntry 89, FDP_0414 + HalfWordTableEntry 90, FDP_04cc + HalfWordTableEntry 91, FDP_0454 + HalfWordTableEntry 92, FDP_051c + HalfWordTableEntry 93, FDP_0414 + HalfWordTableEntry 94, FDP_04cc + HalfWordTableEntry 95, FDP_0454 + + HalfWordTableEntry 96, FDP_0694 + HalfWordTableEntry 97, FDP_058c + HalfWordTableEntry 98, FDP_0640 + HalfWordTableEntry 99, FDP_05d0 + HalfWordTableEntry 100, FDP_0694 + HalfWordTableEntry 101, FDP_058c + HalfWordTableEntry 102, FDP_0640 + HalfWordTableEntry 103, FDP_05d0 + + HalfWordTableEntry 104, FDP_0508 + HalfWordTableEntry 105, FDP_0408 + HalfWordTableEntry 106, FDP_04b8 + HalfWordTableEntry 107, FDP_0448 + HalfWordTableEntry 108, FDP_0508 + HalfWordTableEntry 109, FDP_0408 + HalfWordTableEntry 110, FDP_04b8 + HalfWordTableEntry 111, FDP_0448 + + HalfWordTableEntry 112, FDP_0688 + HalfWordTableEntry 113, FDP_057c + HalfWordTableEntry 114, FDP_0634 + HalfWordTableEntry 115, FDP_05bc + HalfWordTableEntry 116, FDP_0688 + HalfWordTableEntry 117, FDP_057c + HalfWordTableEntry 118, FDP_0634 + HalfWordTableEntry 119, FDP_05bc + + HalfWordTableEntry 120, FDP_04fc + HalfWordTableEntry 121, FDP_03f8 + HalfWordTableEntry 122, FDP_04ac + HalfWordTableEntry 123, FDP_0434 + HalfWordTableEntry 124, FDP_04fc + HalfWordTableEntry 125, FDP_03f8 + HalfWordTableEntry 126, FDP_04ac + HalfWordTableEntry 127, FDP_0434 + + HalfWordTableEntry 128, FDP_06d8 + HalfWordTableEntry 129, FDP_0570 + HalfWordTableEntry 130, FDP_0624 + HalfWordTableEntry 131, FDP_05b0 + HalfWordTableEntry 132, FDP_0678 + HalfWordTableEntry 133, FDP_0570 + HalfWordTableEntry 134, FDP_0624 + HalfWordTableEntry 135, FDP_05b0 + + HalfWordTableEntry 136, FDP_0548 + HalfWordTableEntry 137, FDP_03ec + HalfWordTableEntry 138, FDP_049c + HalfWordTableEntry 139, FDP_0428 + HalfWordTableEntry 140, FDP_04ec + HalfWordTableEntry 141, FDP_03ec + HalfWordTableEntry 142, FDP_049c + HalfWordTableEntry 143, FDP_0428 + + + + + macro + MixedTableEntry &flags, &target + + dc.b &flags + dc.b (&target - FDP) >> 2 + + endm + +; this is the d20 table +MixedTable + MixedTableEntry %01, FDP_0150 + MixedTableEntry %01, FDP_0150 + MixedTableEntry %01, FDP_0150 + MixedTableEntry %01, FDP_0150 + MixedTableEntry %01, FDP_0004 + MixedTableEntry %01, FDP_014C + MixedTableEntry %01, FDP_0150 + MixedTableEntry %01, FDP_0004 + MixedTableEntry %01, FDP_0004 + MixedTableEntry %11, FDP_0160 + MixedTableEntry %11, FDP_0164 + MixedTableEntry %01, FDP_0004 + MixedTableEntry %01, FDP_0004 + MixedTableEntry %01, FDP_0004 + MixedTableEntry %01, FDP_0174 + MixedTableEntry %01, FDP_0178 + MixedTableEntry %01, FDP_015C + MixedTableEntry %01, FDP_015C + MixedTableEntry %01, FDP_015C + MixedTableEntry %01, FDP_015C + MixedTableEntry %01, FDP_0150 + MixedTableEntry %01, FDP_0004 + MixedTableEntry %01, FDP_015C + MixedTableEntry %01, FDP_0004 + MixedTableEntry %01, FDP_0004 + MixedTableEntry %01, FDP_0004 + MixedTableEntry %11, FDP_01A4 + MixedTableEntry %11, FDP_0004 + MixedTableEntry %01, FDP_0004 + MixedTableEntry %01, FDP_0004 + MixedTableEntry %11, FDP_01D8 + MixedTableEntry %11, FDP_0004 + MixedTableEntry %11, FDP_02E4 + MixedTableEntry %11, FDP_02E4 + MixedTableEntry %11, FDP_02E4 + MixedTableEntry %11, FDP_02E4 + MixedTableEntry %11, FDP_0284 + MixedTableEntry %11, FDP_0284 + MixedTableEntry %11, FDP_0284 + MixedTableEntry %11, FDP_0284 + MixedTableEntry %11, FDP_02FC + MixedTableEntry %11, FDP_02FC + MixedTableEntry %11, FDP_02FC + MixedTableEntry %11, FDP_02FC + MixedTableEntry %11, FDP_02FC + MixedTableEntry %11, FDP_02FC + MixedTableEntry %11, FDP_02FC + MixedTableEntry %11, FDP_02FC + MixedTableEntry %11, FDP_020C + MixedTableEntry %01, FDP_0004 + MixedTableEntry %01, FDP_0004 + MixedTableEntry %01, FDP_0004 + MixedTableEntry %01, FDP_015C + MixedTableEntry %01, FDP_0370 + MixedTableEntry %01, FDP_0384 + MixedTableEntry %01, FDP_0398 + MixedTableEntry %01, FDP_015C + MixedTableEntry %01, FDP_015C + MixedTableEntry %01, FDP_015C + MixedTableEntry %01, FDP_015C + MixedTableEntry %01, FDP_0004 + MixedTableEntry %01, FDP_0004 + MixedTableEntry %11, FDP_023C + MixedTableEntry %01, FDP_024C + + + +FDP_0DA0 + li r0, -3 + sc + andi. r23, r16, 0x0020 + addi r10, r10, 4 + mfsprg SP, 0 + mtsrr0 r10 + mtsrr1 r11 + bne FDP_0E30 + mtlr r12 + bns cr3, FDP_0DFC + + +FDP_0DC8 + mtcrf 255, r13 + lmw r2, 0x0008(SP) + lwz r0, 0x0000(SP) + lwz SP, 0x0004(SP) + rfi + dcb.b 32, 0 + + +FDP_0DFC + mtcrf 255, r13 + lmw r10, 0x0028(SP) + lwz r0, 0x0000(SP) + lwz SP, 0x0004(SP) + rfi + dcb.b 32, 0 + + +FDP_0E30 + mfsprg r24, 3 + mtsprg 2, r12 + rlwinm r16, r16, 0, 27, 25 + lwz r12, 0x0034(r24) + stw r16, -0x0010(SP) + mtcrf 255, r13 + mtlr r12 + lmw r2, 0x0008(SP) + lwz r0, 0x0000(SP) + lwz SP, 0x0004(SP) + mtsprg 1, SP + blrl + + +FDP_0E60 + andi. r23, r17, 0x07C0 + rlwinm r28, r17, 13, 25, 29 + lwzx r21, SP, r28 + li r22, 8 + insrwi r17, r22, 6, 26 + addi r19, r19, 4 + bne FDP_03AC + rlwinm r22, r17, 9, 27, 28 + srw r21, r21, r22 + extrwi r22, r17, 2, 4 + neg r22, r22 + add r19, r19, r22 + addi r22, r22, 4 + insrwi. r17, r22, 5, 26 + b FDP_03AC + + +FDP_0E9C + rlwinm r23, r17, 18, 25, 29 + cmpw cr7, r28, r23 + rlwinm r23, r17, 23, 25, 29 + cmpw cr6, r28, r23 + beq cr7, FDP_0EB8 + beq cr6, FDP_0EB8 + stwx r21, SP, r28 + + +FDP_0EB8 + addis r28, r17, 32 + rlwimi r17, r28, 0, 6, 10 + subi r17, r17, 64 + beq FDP_0DA0 + + +FDP_0EC8 + andi. r23, r17, 0x07C0 + li r22, 9 + insrwi r17, r22, 6, 26 + addi r19, r19, 4 + bne FDP_03AC + extrwi r22, r17, 2, 4 + neg r22, r22 + add r19, r19, r22 + addi r22, r22, 4 + insrwi. r17, r22, 5, 26 + b FDP_03AC + + +FDP_0EF4 + rlwinm r23, r17, 18, 25, 29 + cmpw cr7, r28, r23 + rlwinm r23, r17, 23, 25, 29 + cmpw cr6, r28, r23 + beq cr7, FDP_0F10 + beq cr6, FDP_0F10 + stwx r21, SP, r28 + + +FDP_0F10 + addis r28, r17, 32 + rlwimi r17, r28, 0, 6, 10 + subi r17, r17, 64 + not r22, r22 + rlwimi r22, r17, 6, 30, 31 + li r28, 1 + mfxer r23 + extrwi r23, r23, 8, 16 + srwi r20, r21, 24 + cmpw cr7, r20, r23 + add. r22, r22, r28 + beq cr7, FDP_0F80 + beq FDP_0F80 + extrwi r20, r21, 8, 8 + cmpw cr7, r20, r23 + add. r22, r22, r28 + beq cr7, FDP_0F80 + beq FDP_0F80 + extrwi r20, r21, 8, 16 + cmpw cr7, r20, r23 + add. r22, r22, r28 + beq cr7, FDP_0F80 + beq FDP_0F80 + clrlwi r20, r21, 24 + cmpw cr7, r20, r23 + add. r22, r22, r28 + beq cr7, FDP_0F80 + bne FDP_0EC8 + + +FDP_0F80 + rlwinm. r28, r17, 0, 3, 3 + mfxer r23 + add r22, r22, r23 + insrwi r23, r22, 7, 25 + mtxer r23 + beq FDP_0DA0 + mfcr r23 + clrlwi r23, r23, 30 + insrwi r13, r23, 4, 0 + b FDP_0DA0 + + +FDP_0FA8 + clrrwi r20, r21, 31 + xor. r21, r20, r21 + beq FDP_0178 + rlwinm. r23, r21, 16, 17, 24 + addi r23, r23, 128 + rlwimi r20, r21, 29, 5, 31 + extsh r23, r23 + rlwimi r20, r21, 0, 1, 1 + slwi r21, r21, 29 + subi r23, r23, 16512 + rlwimi r20, r23, 0, 2, 4 + bne FDP_0178 + srwi r21, r21, 20 + insrwi r21, r20, 20, 0 + cntlzw r23, r21 + slw r21, r21, r23 + neg r23, r23 + rlwimi r20, r21, 21, 12, 31 + addi r23, r23, 896 + slwi r21, r21, 21 + insrwi r20, r23, 11, 1 + b FDP_0178 + + +FDP_1000 + clrrwi r21, r25, 10 + rlwimi r21, r17, 14, 24, 28 + rlwimi r14, r11, 0, 6, 6 + add r21, r21, r20 + mtmsr r14 + mtlr r21 + isync + oris r11, r11, 0x0200 + blr + + +FDP_1024 + clrrwi r19, r25, 10 + rlwimi r19, r17, 14, 24, 28 + add r19, r19, r20 + mtlr r19 + rlwimi r14, r11, 0, 6, 6 + subi r23, SP, 736 + mtmsr r14 + insrwi r23, r18, 4, 28 + isync + blr + + +FDP_104c + oris r11, r11, 0x0200 + lbz r21, 0x0000(r23) + b FDP_00E4 + + +FDP_1058 + oris r11, r11, 0x0200 + lhz r21, 0x0000(r23) + b FDP_00E4 + + +FDP_1064 + oris r11, r11, 0x0200 + lwz r21, 0x0000(r23) + b FDP_00E4 + + + + + + + + + +; Called by setup. QEMU naturally complains. + +; SPRs: +;MMCR0 equ 952 ; monitor control register 0 +MMCR1 equ 956 ; monitor control register 1 +MMCR2 equ 944 ; monitor control register 2 +;PMC1 equ 953 ; performance counter 1 +;PMC2 equ 954 ; performance counter 2 +PMC3 equ 957 ; performance counter 3 +PMC4 equ 958 ; performance counter 4 +BAMR equ 951 ; breakpoint address mask register 1 +;SIA equ 955 ; sampled instruction address 1 +;SDA equ 959 ; sampled data address (604 only?) + + + macro + TestSPR &dest, &goodgpr, &badgpr, &spr + + mtspr &spr, &goodgpr + not &badgpr, &goodgpr + mfspr &badgpr, &spr + xor&dot &dest, &goodgpr, &badgpr + + endm + + + +ProbePerfMonitor ; OUTSIDE REFERER + + ; We will populate r23 with bit fields describing perf monitor capabilities + li r23, 0 + + + ; Temporarily disable program interrupts (leave old handler in r20) + lwz r21, KDP.PA_NanoKernelCode(r1) + lwz r20, KDP.YellowVecBase + VecTable.ProgramIntVector(r1) + llabel r18, IgnoreSoftwareInt + add r21, r18, r21 + stw r21, KDP.YellowVecBase + VecTable.ProgramIntVector(r1) + + + + ; SET BIT 31 if all the 604 perf monitor registers work + + li r18, 0 + + TestSPR r17, r18, r19, MMCR0 + TestSPR r19, r18, r19, PMC1 + or r17, r17, r19 + TestSPR r19, r18, r19, PMC2 + or r17, r17, r19 + TestSPR r19, r18, r19, SIA + or. r17, r17, r19 + + bne- @dont_set_bit_31 + _bset r23, r23, 31 +@dont_set_bit_31 + + ; ONLY test for bits 28-30 if bit 31 was just set... + + mr. r23, r23 + beq- @stop_testing_perf_monitor + + ; SET BIT 30 if all the 750 perf monitor registers work + + TestSPR r17, r18, r19, MMCR1 + TestSPR r19, r18, r19, PMC3 + or r17, r17, r19 + TestSPR r19, r18, r19, PMC4 + or. r17, r17, r19 + + bne- @dont_set_bit_30 + _bset r23, r23, 30 +@dont_set_bit_30 + + ; SET BIT 29 if SDA (604 but not 750) works + + li r18, 0xaaa0 + TestSPR. r17, r18, r19, SDA + + beq- @dont_set_bit_29 + _bset r23, r23, 29 +@dont_set_bit_29 + + ; SET BIT 28 if EVEN MORE perf monitor registers work + + li r18, 0x00 + TestSPR r17, r18, r19, MMCR2 + + li r18, 0x00 + TestSPR r19, r18, r19, BAMR + + or. r17, r17, r19 + + bne- @dont_set_bit_28 + _bset r23, r23, 28 +@dont_set_bit_28 + +@stop_testing_perf_monitor + + + ; Restore program interrupts + stw r20, KDP.YellowVecBase + VecTable.ProgramIntVector(r1) + + + ; Test r23 and save + mr. r23, r23 + stw r23, KDP.PerfMonitorBits(r1) + + + ; Set HiLevelPerfMonitorBits + li r23, 0 + _bset r23, r23, 14 + _bset r23, r23, 15 + + + ; SET BIT 18 if any perf monitor features present + beq- * + 8 + _bset r23, r23, 18 + + + ; And save + stw r23, KDP.HiLevelPerfMonitorBits(r1) + + + ; Now do some insane arithmetic with the decrementer clock. TBE. + + lisori r20, 0x80587ff3 + lisori r21, 0xd62611e3 + + ; Left-justify the decrementer clock rate + lwz r19, KDP.ProcessorInfo + NKProcessorInfo.DecClockRateHz(r1) + cntlzw r23, r19 + slw r19, r19, r23 + + cmpw cr1, r20, r19 + addi r23, r23, 0x02 + xor. r24, r24, r24 + bge- cr1, ProbePerfMonitor_0x180 + addi r23, r23, -0x01 + +ProbePerfMonitor_0x160 + cmpwi cr1, r20, 0x00 + slwi r20, r20, 1 + rlwimi r20, r21, 1, 31, 31 + cmplw cr2, r20, r19 + rlwinm. r24, r24, 1, 0, 30 + slwi r21, r21, 1 + blt- cr1, ProbePerfMonitor_0x180 + blt- cr2, ProbePerfMonitor_0x188 + +ProbePerfMonitor_0x180 + subf r20, r19, r20 + ori r24, r24, 0x01 + +ProbePerfMonitor_0x188 + bge+ ProbePerfMonitor_0x160 + stw r24, 0x05bc(r1) + stb r23, 0x05b8(r1) + li r21, 0x20 + subf r21, r23, r21 + stb r21, 0x05bb(r1) + blr + + + +; FDP_1214 + +; Xrefs: +; IntProgram + +FDP_1214 ; OUTSIDE REFERER + mfsprg r1, 0 + lwz r8, 0x0104(r6) + stw r8, 0x0000(r1) + stw r2, 0x0008(r1) + stw r3, 0x000c(r1) + stw r4, 0x0010(r1) + stw r5, 0x0014(r1) + stmw r14, 0x0038(r1) + mr r16, r7 + lwz r7, 0x013c(r6) + stw r7, 0x001c(r1) + lwz r8, 0x0144(r6) + stw r8, 0x0020(r1) + lwz r9, 0x014c(r6) + stw r9, 0x0024(r1) + lwz r23, 0x0154(r6) + stw r23, 0x0028(r1) + lwz r23, 0x015c(r6) + stw r23, 0x002c(r1) + lwz r23, 0x0164(r6) + stw r23, 0x0030(r1) + lwz r23, 0x016c(r6) + stw r23, 0x0034(r1) + lwz r1, -0x0004(r1) + addi r22, r6, 0xc4 + lwz r23, 0x0ea0(r1) + lwz r25, 0x0650(r1) + addi r23, r23, 0x01 + stw r23, 0x0ea0(r1) + mfsprg r24, 3 + addi r23, r1, 0x4e0 + mfmsr r14 + ori r15, r14, 0x10 + mtsprg 3, r23 + mtmsr r15 + isync + lwz r27, 0x0000(r10) + mtmsr r14 + isync + mtsprg 3, r24 + srwi r23, r27, 26 + cmpwi cr6, r23, 0x09 + cmpwi r23, 0x16 + cmpwi cr1, r23, 0x1f + lwz r20, 0x05b8(r1) + rlwinm r21, r16, 15, 14, 14 + neg r21, r21 + rlwimi r21, r16, 14, 16, 16 + or r21, r21, r20 + rlwimi r21, r27, 0, 21, 31 + rlwimi r16, r16, 27, 26, 26 + mfsprg r1, 0 + rlwinm r17, r27, 13, 25, 29 + rlwinm r18, r27, 18, 25, 29 + beq- cr6, FDP_1214_0x2b4 + mtcrf 0x3f, r21 + rlwinm r19, r27, 23, 25, 29 + beq- FDP_1bd0 + bne- cr1, FDP_1324 + rlwinm r21, r27, 2, 24, 28 + add r21, r21, r25 + lwz r20, 0x1374(r21) + rlwinm r23, r27, 26, 27, 31 + lwz r21, 0x1378(r21) + rotlw. r20, r20, r23 + add r21, r21, r25 + mtlr r21 + bltlr- + +FDP_1324 + ble- cr1, FDP_1338 + lis r20, 0x5556 + ori r20, r20, 0x5500 + rotlw. r20, r20, r23 + blt- FDP_1c18 + +FDP_1338 + mtcrf 0x70, r11 + li r8, 0x04 + ble- cr3, FDP_1354 + + +FDP_1344 + mtcrf 0x0f, r11 + li r8, 0x04 + ble- cr4, FDP_1354 + li r8, 0x05 + +FDP_1354 + lwz r6, -0x0004(r1) + lwz r9, 0x0ea0(r6) + lmw r14, 0x0038(r1) + addi r9, r9, -0x01 + stw r9, 0x0ea0(r6) + lwz r6, -0x0014(r1) + lwz r7, -0x0010(r1) + b major_0x02980_0x134 + + + +; What the hell is this? +ProgramIntTable + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00910091, FDP_148c - FDP + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x10301030, 0x0000151c + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00328000, 0x000016d0 + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x0080a000, 0x00001c18 + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x55545502, 0x00001c20 + dc.l 0x0f000f0c, 0x00001ad0 + dc.l 0x0a008a08, 0x00001aa8 + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x80008000, 0x00001b8c + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00000000, FDP_1338 - FDP + +FDP_1474 + stw r20, 0(r22) + + +FDP_1478 + bns cr7, FDP_1484 + mfcr r23 + rlwimi r13, r23, 0, 0, 3 + +FDP_1484 + stwx r21, r1, r17 + b FDP_0da0 + +FDP_148c + bns cr2, FDP_1338 + lwzx r18, SP, r18 + bge cr6, FDP_14EC + bgt cr5, FDP_14B0 + mr. r21, r18 + crxor cr5_SO, cr5_SO, cr0_LT + bns cr5, FDP_1478 + neg. r21, r18 + b FDP_1478 + +FDP_14b0 + li r21, 0 + addo. r21, r18, r21 + crxor cr5_SO, cr5_SO, cr0_LT + bns cr5, FDP_1478 + nego. r21, r18 + b FDP_1478 + +FDP_1214_0x2b4 + mtcrf 0x3f, r21 + bns+ cr2, FDP_1338 + lwzx r18, r1, r18 + extsh r19, r27 + cmpw cr1, r19, r18 + subf r21, r21, r21 + blt+ cr1, FDP_1484 + subf r21, r18, r19 + b FDP_1484 + +FDP_14ec + lwzx r19, SP, r19 + bgt cr5, FDP_1508 + cmpw cr1, r19, r18 + sub. r21, r21, r21 + blt cr1, FDP_1478 + sub. r21, r19, r18 + b FDP_1478 + + +FDP_1508 + cmpw cr1, r19, r18 + subo. r21, r21, r21 + blt cr1, FDP_1478 + subo. r21, r19, r18 + b FDP_1478 + bge cr2, FDP_1338 + lwzx r19, SP, r19 + lwzx r18, SP, r18 + bne cr5, FDP_16B8 + cmpwi cr1, r19, 0 + bgt cr6, FDP_1548 + lwz r24, 0(r22) + srwi r21, r24, 31 + add. r21, r21, r18 + bne FDP_1590 + mr r18, r24 + + +FDP_1548 + cmpwi r19, -1 + bgt cr5, FDP_1574 + beq FDP_1568 + beq cr1, FDP_1580 + divw r21, r18, r19 + + +FDP_155c + mullw r20, r21, r19 + sub. r20, r18, r20 + b FDP_1474 + + +FDP_1568 + neg r21, r18 + sub. r20, r18, r18 + b FDP_1474 + + +FDP_1574 + divwo r21, r18, r19 + beq FDP_1568 + bne cr1, FDP_155C + + +FDP_1580 + rlwinm r23, r18, 2, 30, 30 + subi r21, r23, 1 + mr. r20, r18 + b FDP_1474 + + +FDP_1590 + mfxer r26 ; XER = 1 + beq cr1, FDP_1698 + cmpwi r19, 0 + cmpwi cr1, r18, 0 + crxor cr1_SO, cr0_LT, cr1_LT + bge FDP_15AC + neg r19, r19 + + +FDP_15ac + bge cr1, FDP_15B8 + subfic r24, r24, 0 + subfze r18, r18 + + +FDP_15b8 + cmplw r18, r19 + bge FDP_1698 + cntlzw r21, r19 + xor r18, r18, r24 + slw r19, r19, r21 + rotlw r18, r18, r21 + slw r24, r24, r21 + xor r18, r18, r24 + srwi r23, r19, 16 + divwu r20, r18, r23 + mullw r23, r20, r23 + sub r18, r18, r23 + slwi r18, r18, 16 + inslwi r18, r24, 16, 16 + slwi r24, r24, 16 + clrlwi r23, r19, 16 + mullw r23, r20, r23 + subc r18, r18, r23 + subfe. r23, r23, r23 + add r24, r24, r20 + bge FDP_161C + + +FDP_160c + addc r18, r18, r19 + addze. r23, r23 + subi r24, r24, 1 + blt FDP_160C + + +FDP_161c + srwi r23, r19, 16 + divwu r20, r18, r23 + mullw r23, r20, r23 + sub r18, r18, r23 + slwi r18, r18, 16 + inslwi r18, r24, 16, 16 + slwi r24, r24, 16 + clrlwi r23, r19, 16 + mullw r23, r20, r23 + subc r18, r18, r23 + subfe. r23, r23, r23 + add r24, r24, r20 + bge FDP_1660 + + +FDP_1650 + addc r18, r18, r19 + addze. r23, r23 + subi r24, r24, 1 + blt FDP_1650 + + +FDP_1660 + srw r20, r18, r21 + mr. r21, r24 + bge cr1, FDP_1670 + neg r20, r20 + + +FDP_1670 + bns cr1, FDP_1678 + neg. r21, r21 + + +FDP_1678 + ble cr5, FDP_168C + crxor cr0_LT, cr0_LT, cr1_SO + rlwinm r26, r26, 0, 2, 0 + bge FDP_168C + oris r26, r26, 0xC000 + + +FDP_168c + mtxer r26 ; XER = 1 + mr. r20, r20 + b FDP_1474 + + +FDP_1698 + ble cr5, FDP_16A0 + oris r26, r26, 0xC000 + + +FDP_16a0 + mtxer r26 ; XER = 1 + not r21, r18 + srwi r23, r18, 31 + mr. r20, r24 + add r21, r23, r21 + b FDP_1474 + + +FDP_16b8 + mulhw r21, r18, r19 + bgt cr5, FDP_16C8 + mullw. r20, r18, r19 + b FDP_1474 + + +FDP_16c8 + mullwo. r20, r18, r19 + b FDP_1474 + bgt cr6, FDP_18D8 + bgt cr5, FDP_1A64 + cmpwi r18, 64 + cmpwi cr1, r18, 0 + cmpwi cr6, r18, 4 + bso cr5, FDP_1938 + bge FDP_17F8 + crclr cr0_LT + beq cr1, FDP_1734 + beq cr6, FDP_1740 + cmpwi cr1, r18, 20 + cmpwi cr6, r18, 24 + beq cr1, FDP_1750 + beq cr6, FDP_17C8 + cmpwi cr1, r18, 32 + cmpwi cr6, r18, 36 + beq cr1, FDP_17D4 + beq cr6, FDP_17E8 + cmpwi cr6, r18, 16 + lwzx r18, SP, r18 + lwzx r19, SP, r19 + add. r21, r18, r19 + beq cr6, FDP_1750 + bne cr3, FDP_1338 + b FDP_1B54 + + +FDP_1734 + bge cr2, FDP_1338 + lwz r21, 0(r22) + b FDP_1478 + + +FDP_1740 + bne cr3, FDP_1338 + mtcrf %10000000, r13 + dc.l 0x7EA102A7 ; mfxer r21 | bit 31 + b FDP_1478 + + +FDP_1750 + ble cr2, FDP_1338 + lwz r22, -0x0004(SP) + + +FDP_1758 + mftbu r20 + mftb r21 + mftbu r23 + cmplw cr1, r23, r20 + bne- cr1, FDP_1758 + lwz r23, 0x05BC(r22) + lbz r18, 0x05B8(r22) + lbz r19, 0x05BB(r22) + mullw r22, r20, r23 + mulhwu r24, r21, r23 + add r22, r22, r24 + bne cr6, FDP_17A8 + cmplw cr1, r22, r24 + srw r22, r22, r19 + mulhwu r21, r20, r23 + bge+ cr1, FDP_179C + addi r21, r21, 1 + + +FDP_179c + slw r21, r21, r18 + add r21, r21, r22 + b FDP_1478 + + +FDP_17a8 + mullw r21, r21, r23 + srw r21, r21, r19 + slw r22, r22, r18 + add r21, r21, r22 + lis r23, 15258 + ori r23, r23, 0xCA00 + mulhwu r21, r21, r23 + b FDP_1478 + + +FDP_17c8 + bne cr2, FDP_1338 + mfdec r21 ; DEC = 22 + b FDP_1478 + + +FDP_17d4 + bne cr3, FDP_1338 + mtcrf %10000000, r13 + mtlr r12 ; LR = 8 + dc.l 0x7EA802A7 ; mflr r21 | bit 31 + b FDP_1478 + + +FDP_17e8 + bne cr3, FDP_1338 + mtcrf %10000000, r13 + dc.l 0x7EA902A7 ; mfctr r21 | bit 31 + b FDP_1478 + + +FDP_17f8 + lwz r23, -0x0004(SP) + mtcrf %10000000, r13 + lwz r23, 0x05C0(r23) + extrwi r19, r27, 10, 11 + cmplwi cr1, r19, 0x03E8 + beq cr1, FDP_187C + clrlslwi r23, r23, 28, 20 + bne cr4, FDP_1344 + mtcrf 32, r23 + cmplwi cr1, r19, 0x031D + beq cr1, FDP_1898 + cmplwi cr1, r19, 0x033D + beq cr1, FDP_18A0 + cmplwi cr1, r19, 0x035D + beq cr1, FDP_18A8 + cmplwi cr1, r19, 0x037D + beq cr1, FDP_18B0 + bgt cr2, FDP_1848 + cmplwi cr1, r19, 0x03FD + beq cr1, FDP_18D0 + + +FDP_1848 + bne cr2, FDP_1344 + cmplwi cr1, r19, 0x039D + beq cr1, FDP_18B8 + cmplwi cr1, r19, 0x03BD + beq cr1, FDP_18C0 + cmplwi cr1, r19, 0x03DD + beq cr1, FDP_18C8 + bge cr2, FDP_1344 + cmplwi cr1, r19, 0x021D + beq cr1, FDP_1888 + cmplwi cr1, r19, 0x02FD + beq cr1, FDP_1890 + b FDP_1344 + + +FDP_187c + ble cr4, FDP_1344 + dc.l 0x7EBF42A7 ; mfpvr r21 | bit 31 + b FDP_1478 + + +FDP_1888 + dc.l 0x7EB0EAA7 ; mfspr r21, MMCR2 | bit 31 + b FDP_1478 + + +FDP_1890 + dc.l 0x7EB7EAA7 ; mfspr r21, BAMR | bit 31 + b FDP_1478 + + +FDP_1898 + dc.l 0x7EB8EAA7 ; mfspr r21, MMCR0 | bit 31 + b FDP_1478 + + +FDP_18a0 + dc.l 0x7EB9EAA7 ; mfspr r21, PMC1 | bit 31 + b FDP_1478 + + +FDP_18a8 + dc.l 0x7EBAEAA7 ; mfspr r21, PMC2 | bit 31 + b FDP_1478 + + +FDP_18b0 + dc.l 0x7EBBEAA7 ; mfspr r21, SIA | bit 31 + b FDP_1478 + + +FDP_18b8 + dc.l 0x7EBCEAA7 ; mfspr r21, MMCR1 | bit 31 + b FDP_1478 + + +FDP_18c0 + dc.l 0x7EBDEAA7 ; mfspr r21, PMC3 | bit 31 + b FDP_1478 + + +FDP_18c8 + dc.l 0x7EBEEAA7 ; mfspr r21, PMC4 | bit 31 + b FDP_1478 + + +FDP_18d0 + dc.l 0x7EBFEAA7 ; mfspr r21, SDA | bit 31 + b FDP_1478 + + +FDP_18d8 + extrwi r23, r27, 10, 11 + cmplwi cr1, r23, 0x0188 + cmplwi cr6, r23, 0x01A8 + cror cr0_EQ, cr1_EQ, cr6_EQ + bne FDP_1338 + + +FDP_18ec + DIALECT POWER + mfrtcu r20 ; RTCU = 4 + mfrtcl r21 ; RTCL = 5 + mfrtcu r23 ; RTCU = 4 + DIALECT PowerPC + + xor. r23, r23, r20 + lis r23, 15258 + ori r23, r23, 0xCA00 + bne- FDP_18EC + mfspr r24, MQ ; 0 + crset cr3_SO + mullw r19, r20, r23 + mtspr MQ, r24 ; 0 + add r21, r21, r19 + beq cr1, FDP_1484 + cmplw r21, r19 + mulhwu r21, r20, r23 + mtspr MQ, r24 ; 0 + bge FDP_1484 + addi r21, r21, 1 + b FDP_1484 + + +FDP_1938 + lwzx r17, SP, r17 + bge FDP_1998 + mr. r17, r17 + beq cr1, FDP_1964 + bne cr3, FDP_1338 + beq cr6, FDP_1970 + cmpwi cr1, r18, 32 + cmpwi cr6, r18, 36 + beq cr1, FDP_197C + beq cr6, FDP_198C + b FDP_1B54 + + +FDP_1964 + bge cr2, FDP_1338 + stw r17, 0(r22) + b FDP_1B54 + + +FDP_1970 + mtcrf %10000000, r13 + dc.l 0x7E2103A7 ; mtxer r17 | bit 31 + b FDP_1B54 + + +FDP_197c + mtcrf %10000000, r13 + mr r12, r17 + dc.l 0x7E2803A7 ; mtlr r17 | bit 31 + b FDP_1B54 + + +FDP_198c + mtcrf %10000000, r13 + dc.l 0x7E2903A7 ; mtctr r17 | bit 31 + b FDP_1B54 + + +FDP_1998 + lwz r23, -0x0004(SP) + bne cr4, FDP_1344 + lwz r23, 0x05C0(r23) + mtcrf %10000000, r13 + clrlslwi r23, r23, 28, 20 + extrwi r19, r27, 10, 11 + mtcrf 32, r23 + cmplwi cr1, r19, 0x031D + beq cr1, FDP_1A24 + cmplwi cr1, r19, 0x033D + beq cr1, FDP_1A2C + cmplwi cr1, r19, 0x035D + beq cr1, FDP_1A34 + cmplwi cr1, r19, 0x037D + beq cr1, FDP_1A3C + bgt cr2, FDP_19E0 + cmplwi cr1, r19, 0x03FD + beq cr1, FDP_1A5C + + +FDP_19e0 + bne cr2, FDP_1344 + cmplwi cr1, r19, 0x039D + beq cr1, FDP_1A44 + cmplwi cr1, r19, 0x03BD + beq cr1, FDP_1A4C + cmplwi cr1, r19, 0x03DD + beq cr1, FDP_1A54 + bge cr2, FDP_1344 + cmplwi cr1, r19, 0x021D + beq cr1, FDP_1A14 + cmplwi cr1, r19, 0x02FD + beq cr1, FDP_1A1C + b FDP_1344 + + +FDP_1a14 + dc.l 0x7E30EBA7 ; mtspr r17, MMCR2 | bit 31 + b FDP_1B54 + + +FDP_1a1c + dc.l 0x7E37EBA7 ; mtspr r17, BAMR | bit 31 + b FDP_1B54 + + +FDP_1a24 + dc.l 0x7E38EBA7 ; mtspr r17, MMCR0 | bit 31 + b FDP_1B54 + + +FDP_1a2c + dc.l 0x7E39EBA7 ; mtspr r17, PMC1 | bit 31 + b FDP_1B54 + + +FDP_1a34 + dc.l 0x7E3AEBA7 ; mtspr r17, PMC2 | bit 31 + b FDP_1B54 + + +FDP_1a3c + dc.l 0x7E3BEBA7 ; mtspr r17, SIA | bit 31 + b FDP_1B54 + + +FDP_1a44 + dc.l 0x7E3CEBA7 ; mtspr r17, MMCR1 | bit 31 + b FDP_1B54 + + +FDP_1a4c + dc.l 0x7E3DEBA7 ; mtspr r17, PMC3 | bit 31 + b FDP_1B54 + + +FDP_1a54 + dc.l 0x7E3EEBA7 ; mtspr r17, PMC4 | bit 31 + b FDP_1B54 + + +FDP_1a5c + dc.l 0x7E3FEBA7 ; mtspr r17, SDA | bit 31 + b FDP_1B54 + + +FDP_1a64 + lwz r23, -0x0004(SP) + bge cr3, FDP_1338 + extrwi. r18, r27, 4, 12 + rlwinm r21, r27, 16, 28, 30 + cmpwi cr1, r21, 10 + addi r18, r18, 6808 + lbzx r18, r25, r18 + addi r21, r23, 3872 + beq cr1, FDP_1A90 + lhzx r21, r21, r18 + b FDP_1478 + + +FDP_1a90 + lwzx r21, r21, r18 + b FDP_1478 + + DIALECT POWER + dozi SP, r4, 9252 + dozi r17, r8, 10784 + dc.l 0x2c2e1814 ; cmpdi r14, 6164 + DIALECT PowerPC + + subfic r17, r4, 9252 + lwzx r19, SP, r19 + clrlwi r19, r19, 27 + bso cr5, FDP_1B1C + bns cr2, FDP_1338 + lwzx r17, SP, r17 + lis r23, -32768 + lwzx r21, SP, r18 + srw r23, r23, r19 + srw r17, r17, r19 + b FDP_1C08 + bgt cr6, FDP_1B18 + lwzx r19, SP, r19 + clrlwi r19, r19, 26 + bge cr6, FDP_1B1C + cmpwi r19, 31 + crnot cr5_SO, cr5_SO + ble FDP_1B1C + bge cr2, FDP_1338 + lwz r20, 0(r22) + li r23, -1 + clrlwi r19, r19, 27 + bgt cr5, FDP_1B0C + slw r23, r23, r19 + and. r21, r20, r23 + b FDP_1B50 + + +FDP_1b0c + srw r23, r23, r19 + and. r21, r20, r23 + b FDP_1B50 + + +FDP_1b18 + extrwi r19, r27, 5, 16 + + +FDP_1b1c + bge cr2, FDP_1338 + lwzx r17, SP, r17 + bgt cr5, FDP_1B64 + slw. r21, r17, r19 + rotlw r20, r17, r19 + bge cr6, FDP_1B4C + li r23, -1 + slw r23, r23, r19 + + +FDP_1b3c + lwz r19, 0(r22) + andc r23, r19, r23 + or. r21, r21, r23 + bns cr5, FDP_1B50 + + +FDP_1b4c + stw r20, 0(r22) + + +FDP_1b50 + stwx r21, r1, r18 + + +FDP_1b54 + bns+ cr7, FDP_0da0 + mfcr r23 + rlwimi r13, r23, 0, 0, 3 + b FDP_0da0 + + +FDP_1b64 + neg r20, r19 + rotlw r20, r17, r20 + beq cr5, FDP_1B84 + srw. r21, r17, r19 + bge cr6, FDP_1B4C + li r23, -1 + srw r23, r23, r19 + b FDP_1B3C + + +FDP_1b84 + sraw. r21, r17, r19 + b FDP_1B4C + bns cr2, FDP_1338 + lwzx r19, SP, r19 + lwzx r17, SP, r17 + bgt cr5, FDP_1BBC + li r21, -1 + sub r19, r19, r17 + not r19, r19 + clrlwi r19, r19, 27 + neg r17, r17 + slw r21, r21, r19 + rotlw. r21, r21, r17 + b FDP_1B50 + + +FDP_1bbc + lwzx r21, SP, r18 + and r17, r17, r19 + andc r21, r21, r19 + or. r21, r21, r17 + b FDP_1B50 + + +FDP_1bd0 + bns+ cr2, FDP_1338 + lwzx r17, r1, r17 + rlwinm r20, r27, 26, 27, 31 + lwzx r19, r1, r19 + rlwinm r21, r27, 31, 27, 31 + li r23, -0x01 + subf r21, r20, r21 + not r21, r21 + clrlwi r21, r21, 0x1b + neg r20, r20 + slw r23, r23, r21 + lwzx r21, r1, r18 + rotlw r23, r23, r20 + rotlw r17, r17, r19 + + +FDP_1c08 + and r17, r17, r23 + andc r21, r21, r23 + or. r21, r21, r17 + b FDP_1b50 + + +FDP_1c18 + ble+ cr3, FDP_1338 + b major_0x03324 + bgt cr6, FDP_1C18 + bge cr4, FDP_1338 + b major_0x03324 + + + +; FDP_1c40 + +; Xrefs: +; "vec" +; major_0x07ac0 + + align 5 + +FDP_1c40 ; OUTSIDE REFERER +; r6 = saved at *(ewa + 0x18) +; sprg1 = saved at *(ewa + 4) +; rN (0,7,8,9,10,11,12,13, not r1) = saved at *(*(ewa - 0x14) + 0x104 + 8*N) + bl int_prepare +; r0 = 0 +; r1 = *(ewa - 4) +; r6 = kdp +; r7 = *(ewa - 0x10) # flags? +; r8 = ewa +; r10 = srr0 +; r11 = srr1 +; r12 = sprg2 +; r13 = cr + + mfsprg r1, 0 + lwz r8, 0x0104(r6) + stw r8, 0x0000(r1) + stw r2, 0x0008(r1) + stw r3, 0x000c(r1) + stw r4, 0x0010(r1) + stw r5, 0x0014(r1) + stmw r14, 0x0038(r1) + mr r16, r7 + lwz r7, 0x013c(r6) + stw r7, 0x001c(r1) + lwz r8, 0x0144(r6) + stw r8, 0x0020(r1) + lwz r9, 0x014c(r6) + stw r9, 0x0024(r1) + lwz r23, 0x0154(r6) + stw r23, 0x0028(r1) + lwz r23, 0x015c(r6) + stw r23, 0x002c(r1) + lwz r23, 0x0164(r6) + stw r23, 0x0030(r1) + lwz r23, 0x016c(r6) + stw r23, 0x0034(r1) + lwz r1, -0x0004(r1) + addi r22, r6, 0xc4 + mfsprg r24, 3 + addi r23, r1, 0x4e0 + mfmsr r14 + oris r14, r14, 0x200 + ori r15, r14, 0x10 + mtsprg 3, r23 + mtmsr r15 + isync + lwz r27, 0x0000(r10) + mtmsr r14 + isync + mtsprg 3, r24 + lwz r24, 0x00d8(r6) + addi r24, r24, 0x00 + li r8, 0x00 + stvx v0, r24, r8 + li r9, 0x10 + stvx v1, r24, r9 + li r8, 0x20 + stvx v2, r24, r8 + li r9, 0x30 + stvx v3, r24, r9 + li r8, 0x40 + stvx v4, r24, r8 + li r9, 0x50 + stvx v5, r24, r9 + li r8, 0x60 + stvx v6, r24, r8 + li r9, 0x70 + stvx v7, r24, r9 + li r8, 0x80 + stvx v8, r24, r8 + li r9, 0x90 + stvx v9, r24, r9 + li r8, 160 + stvx v10, r24, r8 + li r9, 0xb0 + stvx v11, r24, r9 + li r8, 0xc0 + stvx v12, r24, r8 + li r9, 0xd0 + stvx v13, r24, r9 + li r8, 0xe0 + stvx v14, r24, r8 + li r9, 240 + stvx v15, r24, r9 + li r8, 0x100 + stvx v16, r24, r8 + li r9, 0x110 + stvx v17, r24, r9 + li r8, 0x120 + stvx v18, r24, r8 + li r9, 0x130 + stvx v19, r24, r9 + li r8, 320 + stvx v20, r24, r8 + li r9, 0x150 + stvx v21, r24, r9 + li r8, 0x160 + stvx v22, r24, r8 + li r9, 0x170 + stvx v23, r24, r9 + li r8, 0x180 + stvx v24, r24, r8 + li r9, 400 + stvx v25, r24, r9 + li r8, 0x1a0 + stvx v26, r24, r8 + li r9, 0x1b0 + stvx v27, r24, r9 + li r8, 0x1c0 + stvx v28, r24, r8 + li r9, 0x1d0 + stvx v29, r24, r9 + li r8, 480 + stvx v30, r24, r8 + li r9, 0x1f0 + stvx v31, r24, r9 + lwz r23, 0x0ed8(r1) + lwz r25, 0x0650(r1) + addi r23, r23, 0x01 + stw r23, 0x0ed8(r1) + rlwinm. r8, r27, 26, 0, 0 + rlwinm r9, r27, 24, 30, 31 + cmpwi cr1, r9, 0x03 + cmpwi cr2, r9, 0x00 + rlwinm r17, r27, 15, 23, 27 + rlwinm r18, r27, 20, 23, 27 + rlwinm r19, r27, 25, 23, 27 + blt- FDP_1c40_0x398 + beq- cr2, FDP_1c40_0x43c + bgt- cr1, FDP_1c40_0x278 + lvx v3, r24, r19 + vspltisw v31, 0x00 + vspltisw v29, 0x01 + vcfux v29, v29, 0x00 + vspltisw v30, -0x01 + vspltisw v22, 0x09 + vsrw v28, v30, v22 + vslw v27, v30, v30 + vnor v26, v28, v27 + vsraw v24, v3, v30 + vand v23, v3, v28 + vcmpequw v23, v23, v31 + vand v22, v3, v26 + vcmpequw v22, v22, v31 + vandc v25, v22, v23 + lwz r9, 0x064c(r1) + llabel r8, blergh + add r9, r9, r8 + rlwinm r8, r27, 28, 26, 29 + add r9, r9, r8 + mtlr r9 + blr + +blergh + b panic + b panic + b panic + b panic + b major_0x07ac0_0x14c + b major_0x07ac0_0x100 + b major_0x07ac0_0x24c + b major_0x07ac0_0x220 + b FDP_1c40_0x4d0 + b FDP_1c40_0x4e0 + b FDP_1c40_0x4f0 + b FDP_1c40_0x500 + b panic + b panic + b FDP_1c40_0x514 + b major_0x07980_0x100 + +FDP_1c40_0x274 ; OUTSIDE REFERER + stvx v1, r24, r17 + +FDP_1c40_0x278 + li r8, 0x00 + lvx v0, r24, r8 + li r8, 0x10 + lvx v1, r24, r8 + li r8, 0x20 + lvx v2, r24, r8 + li r8, 0x30 + lvx v3, r24, r8 + li r8, 0x40 + lvx v4, r24, r8 + li r8, 0x50 + lvx v5, r24, r8 + li r8, 0x60 + lvx v6, r24, r8 + li r8, 0x70 + lvx v7, r24, r8 + li r8, 0x80 + lvx v8, r24, r8 + li r8, 0x90 + lvx v9, r24, r8 + li r8, 160 + lvx v10, r24, r8 + li r8, 0xb0 + lvx v11, r24, r8 + li r8, 0xc0 + lvx v12, r24, r8 + li r8, 0xd0 + lvx v13, r24, r8 + li r8, 0xe0 + lvx v14, r24, r8 + li r8, 240 + lvx v15, r24, r8 + li r8, 0x100 + lvx v16, r24, r8 + li r8, 0x110 + lvx v17, r24, r8 + li r8, 0x120 + lvx v18, r24, r8 + li r8, 0x130 + lvx v19, r24, r8 + li r8, 320 + lvx v20, r24, r8 + li r8, 0x150 + lvx v21, r24, r8 + li r8, 0x160 + lvx v22, r24, r8 + li r8, 0x170 + lvx v23, r24, r8 + li r8, 0x180 + lvx v24, r24, r8 + li r8, 400 + lvx v25, r24, r8 + li r8, 0x1a0 + lvx v26, r24, r8 + li r8, 0x1b0 + lvx v27, r24, r8 + li r8, 0x1c0 + lvx v28, r24, r8 + li r8, 0x1d0 + lvx v29, r24, r8 + li r8, 480 + lvx v30, r24, r8 + li r8, 0x1f0 + lvx v31, r24, r8 + andi. r23, r16, 0x20 + addi r10, r10, 0x04 + mfsprg r1, 0 + mtspr srr0, r10 + mtspr srr1, r11 + bne+ FDP_0E30 + mtlr r12 + b FDP_0DC8 + +FDP_1c40_0x398 + rlwinm r22, r27, 30, 23, 27 + mfmsr r14 + ori r15, r14, 0x2000 + mtmsr r15 + isync + rlwinm. r8, r11, 0, 18, 18 + beq- FDP_1c40_0x3cc + stfd f0, 0x0200(r6) + mffs f0 + stfd f1, 0x0208(r6) + stfd f2, 0x0210(r6) + stfd f3, 0x0218(r6) + stfd f0, 0x00e0(r6) + +FDP_1c40_0x3cc + dc.l 0xff80010c + crmove 30, 2 + rlwinm. r9, r27, 31, 0, 0 + li r8, 0x03 + crmove 26, 0 + +FDP_1c40_0x3e0 + lfsx f0, r24, r18 + addic. r8, r8, -0x01 + lfsx f1, r24, r19 + lfsx f2, r24, r22 + bne- cr6, FDP_1c40_0x408 + fnmsubs f3, f0, f2, f1 + stfsx f3, r24, r17 + addi r24, r24, 0x04 + bge+ FDP_1c40_0x3e0 + b FDP_1c40_0x418 + +FDP_1c40_0x408 + fmadds f3, f0, f2, f1 + stfsx f3, r24, r17 + addi r24, r24, 0x04 + bge+ FDP_1c40_0x3e0 + +FDP_1c40_0x418 + addi r24, r24, -0x10 + beq+ cr7, FDP_1c40_0x278 + lfd f0, 0x00e0(r6) + mtfsf 0xff, f0 + lfd f0, 0x0200(r6) + lfd f1, 0x0208(r6) + lfd f2, 0x0210(r6) + lfd f3, 0x0218(r6) + b FDP_1c40_0x278 + +FDP_1c40_0x43c + mfmsr r14 + ori r15, r14, 0x2000 + mtmsr r15 + isync + rlwinm. r8, r11, 0, 18, 18 + beq- FDP_1c40_0x468 + stfd f0, 0x0200(r6) + mffs f0 + stfd f1, 0x0208(r6) + stfd f3, 0x0218(r6) + stfd f0, 0x00e0(r6) + +FDP_1c40_0x468 + dc.l 0xff80010c + crmove 30, 2 + rlwinm. r9, r27, 25, 0, 0 + li r8, 0x03 + crmove 26, 0 + +FDP_1c40_0x47c + lfsx f0, r24, r18 + addic. r8, r8, -0x01 + lfsx f1, r24, r19 + bne- cr6, FDP_1c40_0x4a0 + fsubs f3, f0, f1 + stfsx f3, r24, r17 + addi r24, r24, 0x04 + bge+ FDP_1c40_0x47c + b FDP_1c40_0x4b0 + +FDP_1c40_0x4a0 + fadds f3, f0, f1 + stfsx f3, r24, r17 + addi r24, r24, 0x04 + bge+ FDP_1c40_0x47c + +FDP_1c40_0x4b0 + addi r24, r24, -0x10 + beq+ cr7, FDP_1c40_0x278 + lfd f0, 0x00e0(r6) + mtfsf 0xff, f0 + lfd f0, 0x0200(r6) + lfd f1, 0x0208(r6) + lfd f3, 0x0218(r6) + b FDP_1c40_0x278 + +FDP_1c40_0x4d0 + vsel v22, v31, v27, v24 + vsel v23, v3, v22, v25 + vrfin v1, v23 + b FDP_1c40_0x274 + +FDP_1c40_0x4e0 + vsel v22, v31, v27, v24 + vsel v23, v3, v22, v25 + vrfiz v1, v23 + b FDP_1c40_0x274 + +FDP_1c40_0x4f0 + vsel v22, v29, v27, v24 + vsel v23, v3, v22, v25 + vrfip v1, v23 + b FDP_1c40_0x274 + +FDP_1c40_0x500 + vor v29, v29, v27 + vsel v22, v31, v29, v24 + vsel v23, v3, v22, v25 + vrfim v1, v23 + b FDP_1c40_0x274 + +FDP_1c40_0x514 + vsel v23, v3, v31, v25 + lwz r9, 0x064c(r1) + llabel r8, FDP_2180 + add r8, r8, r9 + srwi r9, r18, 1 + add r8, r8, r9 + mtlr r8 + blr + + + + align 6 + +FDP_2180 + dc.l 0x1020BB8A + b FDP_1c40_0x274 + dc.l 0x1021BB8A + b FDP_1c40_0x274 + dc.l 0x1022BB8A + b FDP_1c40_0x274 + dc.l 0x1023BB8A + b FDP_1c40_0x274 + dc.l 0x1024BB8A + b FDP_1c40_0x274 + dc.l 0x1025BB8A + b FDP_1c40_0x274 + dc.l 0x1026BB8A + b FDP_1c40_0x274 + dc.l 0x1027BB8A + b FDP_1c40_0x274 + dc.l 0x1028BB8A + b FDP_1c40_0x274 + dc.l 0x1029BB8A + b FDP_1c40_0x274 + dc.l 0x102ABB8A + b FDP_1c40_0x274 + dc.l 0x102BBB8A + b FDP_1c40_0x274 + dc.l 0x102CBB8A + b FDP_1c40_0x274 + dc.l 0x102DBB8A + b FDP_1c40_0x274 + dc.l 0x102EBB8A + b FDP_1c40_0x274 + dc.l 0x102FBB8A + b FDP_1c40_0x274 + dc.l 0x1030BB8A + b FDP_1c40_0x274 + dc.l 0x1031BB8A + b FDP_1c40_0x274 + dc.l 0x1032BB8A + b FDP_1c40_0x274 + dc.l 0x1033BB8A + b FDP_1c40_0x274 + dc.l 0x1034BB8A + b FDP_1c40_0x274 + dc.l 0x1035BB8A + b FDP_1c40_0x274 + dc.l 0x1036BB8A + b FDP_1c40_0x274 + dc.l 0x1037BB8A + b FDP_1c40_0x274 + dc.l 0x1038BB8A + b FDP_1c40_0x274 + dc.l 0x1039BB8A + b FDP_1c40_0x274 + dc.l 0x103ABB8A + b FDP_1c40_0x274 + dc.l 0x103BBB8A + b FDP_1c40_0x274 + dc.l 0x103CBB8A + b FDP_1c40_0x274 + dc.l 0x103DBB8A + b FDP_1c40_0x274 + dc.l 0x103EBB8A + b FDP_1c40_0x274 + dc.l 0x103FBB8A + b FDP_1c40_0x274 + +major_0x07980_0x100 ; OUTSIDE REFERER + vsel v23, v3, v31, v25 + lwz r9, 0x064c(r1) + llabel r8, FDP_22c0 + add r8, r8, r9 + srwi r9, r18, 1 + add r8, r8, r9 + mtlr r8 + blr + + + +; major_0x07ac0 + +; Xrefs: +; FDP_1c40 + + align 6 + +FDP_22c0 + dc.l 0x1020BBCA + b FDP_1c40_0x274 + dc.l 0x1021BBCA + b FDP_1c40_0x274 + dc.l 0x1022BBCA + b FDP_1c40_0x274 + dc.l 0x1023BBCA + b FDP_1c40_0x274 + dc.l 0x1024BBCA + b FDP_1c40_0x274 + dc.l 0x1025BBCA + b FDP_1c40_0x274 + dc.l 0x1026BBCA + b FDP_1c40_0x274 + dc.l 0x1027BBCA + b FDP_1c40_0x274 + dc.l 0x1028BBCA + b FDP_1c40_0x274 + dc.l 0x1029BBCA + b FDP_1c40_0x274 + dc.l 0x102ABBCA + b FDP_1c40_0x274 + dc.l 0x102BBBCA + b FDP_1c40_0x274 + dc.l 0x102CBBCA + b FDP_1c40_0x274 + dc.l 0x102DBBCA + b FDP_1c40_0x274 + dc.l 0x102EBBCA + b FDP_1c40_0x274 + dc.l 0x102FBBCA + b FDP_1c40_0x274 + dc.l 0x1030BBCA + b FDP_1c40_0x274 + dc.l 0x1031BBCA + b FDP_1c40_0x274 + dc.l 0x1032BBCA + b FDP_1c40_0x274 + dc.l 0x1033BBCA + b FDP_1c40_0x274 + dc.l 0x1034BBCA + b FDP_1c40_0x274 + dc.l 0x1035BBCA + b FDP_1c40_0x274 + dc.l 0x1036BBCA + b FDP_1c40_0x274 + dc.l 0x1037BBCA + b FDP_1c40_0x274 + dc.l 0x1038BBCA + b FDP_1c40_0x274 + dc.l 0x1039BBCA + b FDP_1c40_0x274 + dc.l 0x103ABBCA + b FDP_1c40_0x274 + dc.l 0x103BBBCA + b FDP_1c40_0x274 + dc.l 0x103CBBCA + b FDP_1c40_0x274 + dc.l 0x103DBBCA + b FDP_1c40_0x274 + dc.l 0x103EBBCA + b FDP_1c40_0x274 + dc.l 0x103FBBCA + b FDP_1c40_0x274 + +major_0x07ac0_0x100 ; OUTSIDE REFERER + bl major_0x07d80_0x20 + vspltisw v19, 0x01 + vadduwm v22, v22, v19 + vspltisw v23, -0x07 + vsrw v21, v23, v23 + vsubuwm v23, v21, v22 + vspltisw v21, -0x09 + vslw v23, v23, v21 + vrsqrtefp v19, v23 + vslw v20, v3, v22 + vor v23, v29, v27 + vsel v23, v31, v23, v24 + vsel v21, v3, v23, v25 + vandc v25, v25, v24 + vrsqrtefp v20, v20 + vrsqrtefp v21, v21 + vmaddfp v1, v20, v19, v27 + vsel v1, v21, v1, v25 + b FDP_1c40_0x274 + +major_0x07ac0_0x14c ; OUTSIDE REFERER + bl major_0x07d80_0x20 + vspltisw v19, 0x01 + vadduwm v22, v22, v19 + vslw v20, v3, v22 + vsel v20, v31, v20, v25 + vrefp v20, v20 + vspltisw v21, -0x09 + vandc v23, v20, v27 + vsrw v23, v23, v21 + mfvscr v29 + vsrw v19, v30, v19 + vsrw v19, v19, v21 + vaddubs v23, v22, v23 + mtvscr v29 + vcmpequw v22, v23, v19 + vslw v23, v23, v21 + vsel v23, v20, v23, v26 + vand v22, v22, v28 + vsel v23, v23, v31, v22 + vsel v20, v31, v27, v24 + vsel v1, v23, v30, v20 + vspltisw v19, 0x01 + vslw v22, v3, v19 + vspltisw v23, -0x04 + vsraw v22, v22, v21 + vsraw v22, v22, v19 + vcmpgtuw v23, v22, v23 + vcmpequw v19, v22, v30 + vandc v23, v23, v19 + vspltisw v19, 0x02 + vsubuwm v22, v22, v19 + vslw v22, v22, v21 + vsel v22, v3, v22, v26 + vsel v22, v31, v22, v23 + vrefp v22, v22 + vspltisw v19, 0x01 + vandc v22, v22, v27 + vslw v29, v19, v21 + vor v28, v28, v29 + vcmpgtuw v28, v22, v28 + vsrw v29, v29, v19 + vsel v22, v22, v31, v26 + vsrw v22, v22, v19 + vor v22, v22, v29 + vsel v19, v19, v31, v28 + vsrw v22, v22, v19 + vor v22, v22, v20 + vsel v1, v1, v22, v23 + vor v25, v25, v23 + vsel v23, v3, v31, v25 + vrefp v23, v23 + vsel v1, v23, v1, v25 + b FDP_1c40_0x274 + +major_0x07ac0_0x220 ; OUTSIDE REFERER + bl major_0x07d80_0x20 + vspltisw v19, 0x01 + vadduwm v22, v22, v19 + vslw v20, v3, v22 + vsel v23, v3, v20, v25 + vlogefp v23, v23 + vsubsws v22, v31, v22 + vcfsx v22, v22, 0x00 + vaddfp v1, v22, v23 + vsel v1, v23, v1, v25 + b FDP_1c40_0x274 + +major_0x07ac0_0x24c ; OUTSIDE REFERER + lwz r9, 0x064c(r1) + llabel r8, FDP_2590 + add r8, r8, r9 + lvx v23, 0, r8 + vspltw v21, v23, 0x03 + vspltw v20, v23, 0x00 + vcmpgefp v21, v3, v21 + vcmpgtfp v20, v3, v20 + vspltw v19, v23, 0x02 + vandc v22, v21, v20 + vsel v29, v31, v3, v22 + vaddfp v29, v29, v19 + vsel v19, v3, v29, v22 + vexptefp v1, v19 + vspltisw v25, -0x09 + vspltw v23, v23, 0x01 + vsrw v19, v1, v25 + vspltisw v29, 0x01 + vsubuwm v19, v23, v19 + vslw v26, v29, v25 + vsel v28, v31, v1, v28 + vor v28, v28, v26 + vsrw v28, v28, v19 + vsel v1, v1, v28, v22 + b FDP_1c40_0x274 + + + +; major_0x07d80 + +; Xrefs: +; major_0x07ac0 + + align 5 + +FDP_2580 + dc.l 0x17030202 + dc.l 0x01010101 + dc.l 0x00000000 + dc.l 0x00000000 + +FDP_2590 + dc.l 0xc2fc0004 + dc.l 0x00000041 + dc.l 0x42800000 + dc.l 0xc3150001 + +major_0x07d80_0x20 ; OUTSIDE REFERER + vspltisw v23, 9 + vslw v19, v3, v23 + lwz r9, 0x064c(r1) + llabel r8, FDP_2580 + add r8, r8, r9 + lvx v23, 0, r8 + vperm v22, v23, v23, v19 + vspltisw v21, 4 + vsrw v21, v19, v21 + vperm v21, v23, v23, v21 + li r8, 0 + lvsl v20, r8, r8 + vspltisw v23, 3 + vslw v20, v20, v23 + vspltisb v23, 4 + vaddubm v19, v20, v23 + vspltw v20, v20, 0 + vspltw v19, v19, 0 + vaddubm v21, v21, v20 + vaddubm v22, v22, v19 + vminub v22, v22, v21 + vsldoi v21, v22, v22, 2 + vminub v22, v22, v21 + vsldoi v21, v22, v22,1 + vminub v22, v22, v21 + vspltisw v21, -8 + vsrw v22, v22, v21 + blr + + + +; No clue what this does + + align 5 + +FDP_2620 + dc.l 0x7C00B8CE + b FDP_011C + dc.l 0x7C20B8CE + b FDP_011C + dc.l 0x7C40B8CE + b FDP_011C + dc.l 0x7C60B8CE + b FDP_011C + dc.l 0x7C80B8CE + b FDP_011C + dc.l 0x7CA0B8CE + b FDP_011C + dc.l 0x7CC0B8CE + b FDP_011C + dc.l 0x7CE0B8CE + b FDP_011C + dc.l 0x7D00B8CE + b FDP_011C + dc.l 0x7D20B8CE + b FDP_011C + dc.l 0x7D40B8CE + b FDP_011C + dc.l 0x7D60B8CE + b FDP_011C + dc.l 0x7D80B8CE + b FDP_011C + dc.l 0x7DA0B8CE + b FDP_011C + dc.l 0x7DC0B8CE + b FDP_011C + dc.l 0x7DE0B8CE + b FDP_011C + dc.l 0x7E00B8CE + b FDP_011C + dc.l 0x7E20B8CE + b FDP_011C + dc.l 0x7E40B8CE + b FDP_011C + dc.l 0x7E60B8CE + b FDP_011C + dc.l 0x7E80B8CE + b FDP_011C + dc.l 0x7EA0B8CE + b FDP_011C + dc.l 0x7EC0B8CE + b FDP_011C + dc.l 0x7EE0B8CE + b FDP_011C + dc.l 0x7F00B8CE + b FDP_011C + dc.l 0x7F20B8CE + b FDP_011C + dc.l 0x7F40B8CE + b FDP_011C + dc.l 0x7F60B8CE + b FDP_011C + dc.l 0x7F80B8CE + b FDP_011C + dc.l 0x7FA0B8CE + b FDP_011C + dc.l 0x7FC0B8CE + b FDP_011C + dc.l 0x7FE0B8CE + b FDP_011C + dc.l 0x7C00B80E + b FDP_0DA0 + dc.l 0x7C20B80E + b FDP_0DA0 + dc.l 0x7C40B80E + b FDP_0DA0 + dc.l 0x7C60B80E + b FDP_0DA0 + dc.l 0x7C80B80E + b FDP_0DA0 + dc.l 0x7CA0B80E + b FDP_0DA0 + dc.l 0x7CC0B80E + b FDP_0DA0 + dc.l 0x7CE0B80E + b FDP_0DA0 + dc.l 0x7D00B80E + b FDP_0DA0 + dc.l 0x7D20B80E + b FDP_0DA0 + dc.l 0x7D40B80E + b FDP_0DA0 + dc.l 0x7D60B80E + b FDP_0DA0 + dc.l 0x7D80B80E + b FDP_0DA0 + dc.l 0x7DA0B80E + b FDP_0DA0 + dc.l 0x7DC0B80E + b FDP_0DA0 + dc.l 0x7DE0B80E + b FDP_0DA0 + dc.l 0x7E00B80E + b FDP_0DA0 + dc.l 0x7E20B80E + b FDP_0DA0 + dc.l 0x7E40B80E + b FDP_0DA0 + dc.l 0x7E60B80E + b FDP_0DA0 + dc.l 0x7E80B80E + b FDP_0DA0 + dc.l 0x7EA0B80E + b FDP_0DA0 + dc.l 0x7EC0B80E + b FDP_0DA0 + dc.l 0x7EE0B80E + b FDP_0DA0 + dc.l 0x7F00B80E + b FDP_0DA0 + dc.l 0x7F20B80E + b FDP_0DA0 + dc.l 0x7F40B80E + b FDP_0DA0 + dc.l 0x7F60B80E + b FDP_0DA0 + dc.l 0x7F80B80E + b FDP_0DA0 + dc.l 0x7FA0B80E + b FDP_0DA0 + dc.l 0x7FC0B80E + b FDP_0DA0 + dc.l 0x7FE0B80E + b FDP_0DA0 + dc.l 0x7C00B84E + b FDP_0DA0 + dc.l 0x7C20B84E + b FDP_0DA0 + dc.l 0x7C40B84E + b FDP_0DA0 + dc.l 0x7C60B84E + b FDP_0DA0 + dc.l 0x7C80B84E + b FDP_0DA0 + dc.l 0x7CA0B84E + b FDP_0DA0 + dc.l 0x7CC0B84E + b FDP_0DA0 + dc.l 0x7CE0B84E + b FDP_0DA0 + dc.l 0x7D00B84E + b FDP_0DA0 + dc.l 0x7D20B84E + b FDP_0DA0 + dc.l 0x7D40B84E + b FDP_0DA0 + dc.l 0x7D60B84E + b FDP_0DA0 + dc.l 0x7D80B84E + b FDP_0DA0 + dc.l 0x7DA0B84E + b FDP_0DA0 + dc.l 0x7DC0B84E + b FDP_0DA0 + dc.l 0x7DE0B84E + b FDP_0DA0 + dc.l 0x7E00B84E + b FDP_0DA0 + dc.l 0x7E20B84E + b FDP_0DA0 + dc.l 0x7E40B84E + b FDP_0DA0 + dc.l 0x7E60B84E + b FDP_0DA0 + dc.l 0x7E80B84E + b FDP_0DA0 + dc.l 0x7EA0B84E + b FDP_0DA0 + dc.l 0x7EC0B84E + b FDP_0DA0 + dc.l 0x7EE0B84E + b FDP_0DA0 + dc.l 0x7F00B84E + b FDP_0DA0 + dc.l 0x7F20B84E + b FDP_0DA0 + dc.l 0x7F40B84E + b FDP_0DA0 + dc.l 0x7F60B84E + b FDP_0DA0 + dc.l 0x7F80B84E + b FDP_0DA0 + dc.l 0x7FA0B84E + b FDP_0DA0 + dc.l 0x7FC0B84E + b FDP_0DA0 + dc.l 0x7FE0B84E + b FDP_0DA0 + dc.l 0x7C00B88E + b FDP_0DA0 + dc.l 0x7C20B88E + b FDP_0DA0 + dc.l 0x7C40B88E + b FDP_0DA0 + dc.l 0x7C60B88E + b FDP_0DA0 + dc.l 0x7C80B88E + b FDP_0DA0 + dc.l 0x7CA0B88E + b FDP_0DA0 + dc.l 0x7CC0B88E + b FDP_0DA0 + dc.l 0x7CE0B88E + b FDP_0DA0 + dc.l 0x7D00B88E + b FDP_0DA0 + dc.l 0x7D20B88E + b FDP_0DA0 + dc.l 0x7D40B88E + b FDP_0DA0 + dc.l 0x7D60B88E + b FDP_0DA0 + dc.l 0x7D80B88E + b FDP_0DA0 + dc.l 0x7DA0B88E + b FDP_0DA0 + dc.l 0x7DC0B88E + b FDP_0DA0 + dc.l 0x7DE0B88E + b FDP_0DA0 + dc.l 0x7E00B88E + b FDP_0DA0 + dc.l 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0x7E20B98E + b FDP_1064 + dc.l 0x7E40B98E + b FDP_1064 + dc.l 0x7E60B98E + b FDP_1064 + dc.l 0x7E80B98E + b FDP_1064 + dc.l 0x7EA0B98E + b FDP_1064 + dc.l 0x7EC0B98E + b FDP_1064 + dc.l 0x7EE0B98E + b FDP_1064 + dc.l 0x7F00B98E + b FDP_1064 + dc.l 0x7F20B98E + b FDP_1064 + dc.l 0x7F40B98E + b FDP_1064 + dc.l 0x7F60B98E + b FDP_1064 + dc.l 0x7F80B98E + b FDP_1064 + dc.l 0x7FA0B98E + b FDP_1064 + dc.l 0x7FC0B98E + b FDP_1064 + dc.l 0x7FE0B98E + b FDP_1064 diff --git a/NanoKernel/NKVMCalls.s b/NanoKernel/NKVMCalls.s new file mode 100644 index 0000000..31cf116 --- /dev/null +++ b/NanoKernel/NKVMCalls.s @@ -0,0 +1,1988 @@ +Local_Panic set * + b panic + + + + align 5 + + + +MaxVMCallCount equ 26 + + + + MACRO + DeclareVMCall &n, &code + +@h + org VMDispatchMainTable + &n * 4 + dc.l &code - NKTop - &n * 4 + + org VMDispatchAltTable + &n * 4 + dc.l &code - NKTop - &n * 4 + + org @h + + ENDM + + + MACRO + DeclareVMCallWithAlt &n, &code, &alt + +@h + org VMDispatchMainTable + &n * 4 + dc.l &code - NKTop - &n * 4 + + org VMDispatchAltTable + &n * 4 + dc.l &alt - NKTop - &n * 4 + + org @h + + ENDM + + + +; Accessed ONLY via Sup table + +kcVMDispatch ; OUTSIDE REFERER + + _Lock PSA.HTABLock, scratch1=r8, scratch2=r9 + + mfsprg r8, 0 + stw r7, -0x0010(r8) + lwz r6, EWA.r6(r8) + stw r14, EWA.r14(r8) + stw r15, EWA.r15(r8) + stw r16, EWA.r16(r8) + +; Whoa... where did cr0 get set? +; And why do we set cr2? + mfpvr r9 + srwi r9, r9, 16 + cmpwi cr2, r9, 0x0009 + beq- @other_pvr_test + cmpwi cr2, r9, 0x000a +@other_pvr_test + + lwz r7, KDP.NanoKernelInfo + NKNanoKernelInfo.VMDispatchCountTblPtr(r1) + rlwinm r8, r3, 2, 20, 29 + cmplwi r7, 0 + beq- @no_count + lwzx r9, r7, r8 + addi r9, r9, 1 + stwx r9, r7, r8 +@no_count + + lwz r7, KDP.PA_NanoKernelCode(r1) + b VMDispatchTableEnd + +VMDispatchMainTable + dcb.l MaxVMCallCount, 0;Local_Panic - (* - VMDispatchMainTable) +VMDispatchAltTable + dcb.l MaxVMCallCount, 0;Local_Panic - (* - VMDispatchAltTable) +VMDispatchTableEnd + + lwz r9, KDP.VMMaxVirtualPages(r1) + cmplwi r3, MaxVMCallCount + cmpwi cr1, r9, 0 + rlwimi r7, r3, 2, 23, 29 + llabel r8, VMDispatchMainTable + + bne- cr1, @noalt + llabel r8, VMDispatchAltTable +@noalt + + lwzx r8, r8, r7 + lwz r9, KDP.UsablePhysicalPages(r1) + add r8, r8, r7 + mtlr r8 + bltlr- + + + + +; UNIMPLEMENTED kcVMDispatch selectors: + +; VMUnInit: 'un-init the MMU virtual space' + + DeclareVMCall 1, VMReturn + + +; VMGetPhysicalAddress: 'return phys address given log page (can be different from above!)' +; ('above' means VMGetPhysicalPage) + + DeclareVMCallWithAlt 11, VMReturnMinus1, VMReturnNotReady + + +; VMReload: 'reload the ATC with specified page' + + DeclareVMCall 13, VMReturn + + +; VMFlushAddressTranslationCache: 'just do it' + + DeclareVMCall 14, VMReturn + + +; VMFlushDataCache: 'wack the data cache' + + DeclareVMCall 15, VMReturn + + +; VMFlushCodeCache: 'wack the code cache' + + DeclareVMCall 16, VMReturn + + + + +; VMReturn + +; VMGetPhysicalAddress_one + +; Xrefs: +; kcVMDispatch +; VMFinalInit +; VMInit +; VMExchangePages +; VMGetPhysicalPage +; getPTEntryGivenPage +; major_0x08d88 +; VMIsInited +; VMIsResident +; VMIsUnmodified +; VMLRU +; VMMakePageCacheable +; VMMakePageWriteThrough +; PageSetCommon +; VMMakePageNonCacheable +; VMMarkBacking +; VMMarkCleanUnused +; VMMarkUndefined +; VMMarkResident +; VMPTest +; setPTEntryGivenPage +; VMShouldClean +; VMAllocateMemory +; VeryPopularFunction +; major_0x09c9c + +VMReturnMinus1 ; OUTSIDE REFERER + li r3, -0x01 + b VMReturn + +VMReturnNotReady ; OUTSIDE REFERER + b VMReturnMinus1 + +VMReturn0 ; OUTSIDE REFERER + li r3, 0x00 + b VMReturn + +VMReturn1 ; OUTSIDE REFERER + li r3, 0x01 + +VMReturn ; OUTSIDE REFERER + mfsprg r8, 0 + lwz r14, 0x0038(r8) + lwz r15, 0x003c(r8) + lwz r16, 0x0040(r8) + lwz r7, -0x0010(r8) + lwz r6, -0x0014(r8) + sync + lwz r8, -0x0b90(r1) + cmpwi cr1, r8, 0x00 + li r8, 0x00 + bne+ cr1, VMReturn_0x4c + mflr r8 + bl panic + +VMReturn_0x4c + stw r8, -0x0b90(r1) + b skeleton_key + + + +; 'last chance to init after new memory dispatch is installed' +; +; Does protecting the kernel mean *wiring* the kernel? + + DeclareVMCall 2, VMFinalInit + +VMFinalInit ; OUTSIDE REFERER + mfsprg r8, 0 + stmw r29, EWA.r29(r8) + + lwz r29, KDP.TopOfFreePages(r1) + lwz r30, KDP.PA_NanoKernelCode(r1) + lwz r31, KDP.OtherFreeThing(r1) + + subf r30, r30, r29 + cmpwi r31, 0 + add r30, r30, r31 ; r30 = TopOfFreePages - PA_NanoKernelCode + OtherFreeThing + + beq- @skip + + li r8, 0 + stw r8, KDP.OtherFreeThing(r1) + + _log 'Protecting the nanokernel: ' + + mr r8, r31 + bl printw + + mr r8, r30 + bl printw + + _log '^n' + + addi r29, r1, 4096 + +@loop + srwi r4, r31, 12 + lwz r9, KDP.UsablePhysicalPages(r1) + bl VeryPopularFunction + bge- cr4, @skip + bltl- cr5, VMDoSomethingWithTLB + bgel- cr5, VMSecondLastExportedFunc + ori r16, r16, 0x400 + rlwimi r9, r29, 0, 0, 19 + bl major_0x09b40 + addi r31, r31, 0x1000 + cmplw r31, r30 + ble+ @loop + +@skip + mfsprg r8, 0 + lmw r29, EWA.r29(r8) + b VMReturn1 + + + +; 'init the MMU virtual space' + + DeclareVMCallWithAlt 0, VMInit, VMReturn1 + +VMInit ; OUTSIDE REFERER + _log 'Legacy VMInit ' + mr r8, r4 + bl printw + mr r8, r5 + bl printw + _log '^n' + lwz r7, KDP.FlatPageListPtr(r1) + lwz r8, 0x06c0(r1) + cmpw r7, r8 + bne+ VMReturn1 + stw r4, 0x06a8(r1) + stw r5, KDP.FlatPageListPtr(r1) + lwz r6, 0x05e8(r1) + li r5, 0x00 + li r4, 0x00 + +VMInit_0x60 + lwz r8, 0x0000(r6) + addi r6, r6, 0x08 + lhz r3, 0x0000(r8) + lhz r7, 0x0002(r8) + lwz r8, 0x0004(r8) + addi r7, r7, 0x01 + cmpwi cr1, r3, 0x00 + andi. r3, r8, 0xc00 + cmpwi r3, 0xc00 + bne- VMInit_0x110 + bnel+ cr1, Local_Panic + rlwinm r15, r8, 22, 0, 29 + addi r3, r1, 0x6c0 + rlwimi r3, r5, 2, 28, 29 + stw r15, 0x0000(r3) + slwi r3, r5, 16 + cmpw r3, r4 + bnel+ Local_Panic + +VMInit_0xa8 + lwz r16, 0x0000(r15) + addi r7, r7, -0x01 + andi. r3, r16, 0x01 + beql+ Local_Panic + andi. r3, r16, 0x800 + beq- VMInit_0x100 + lwz r14, 0x06a4(r1) + rlwinm r3, r16, 23, 9, 28 + lwzux r8, r14, r3 + lwz r9, 0x0004(r14) + andis. r3, r8, 0x8000 + beql+ Local_Panic + andi. r3, r9, 0x03 + cmpwi r3, 0x00 + beql+ Local_Panic + rlwinm r3, r16, 17, 22, 31 + rlwimi r3, r8, 10, 16, 21 + rlwimi r3, r8, 21, 12, 15 + cmpw r3, r4 + bnel+ Local_Panic + bl VMDoSomethingWithTLB + bl major_0x09b40 + +VMInit_0x100 + cmpwi r7, 0x00 + addi r15, r15, 0x04 + addi r4, r4, 0x01 + bne+ VMInit_0xa8 + +VMInit_0x110 + lwz r7, 0x06b4(r1) + addi r5, r5, 0x01 + addi r7, r7, -0x01 + srwi r7, r7, 16 + cmpw r5, r7 + ble+ VMInit_0x60 + lwz r7, 0x06ac(r1) + cmpw r4, r7 + bnel+ Local_Panic + lwz r5, KDP.FlatPageListPtr(r1) + lwz r4, 0x06a8(r1) + andi. r7, r5, 0xfff + li r3, 0x02 + bne- VMInit_0x374 + lwz r7, 0x06b4(r1) + cmplw r7, r4 + li r3, 0x03 + blt- VMInit_0x374 + addi r7, r4, 0x3ff + srwi r6, r7, 10 + srwi r8, r5, 12 + add r8, r8, r6 + lwz r9, 0x06ac(r1) + cmplw r8, r9 + li r3, 0x04 + bgt- VMInit_0x374 + cmplw r4, r9 + li r3, 0x05 + blt- VMInit_0x374 + srwi r7, r5, 12 + bl major_0x09c9c + stw r9, KDP.FlatPageListPtr(r1) + mr r15, r9 + srwi r7, r5, 12 + add r7, r7, r6 + addi r7, r7, -0x01 + bl major_0x09c9c + subf r9, r15, r9 + srwi r9, r9, 12 + addi r9, r9, 0x01 + cmpw r9, r6 + li r3, 0x06 + bne- VMInit_0x374 + stw r4, 0x06a8(r1) + lwz r8, -0x0020(r1) + slwi r7, r4, 12 + stw r7, 0x0dc8(r8) + slwi r7, r4, 2 + li r8, 0x00 + +VMInit_0x1d4 + subi r7, r7, 4 + cmpwi r7, 0x00 + stwx r8, r15, r7 + bne+ VMInit_0x1d4 + lwz r7, 0x06ac(r1) + slwi r6, r7, 2 + +VMInit_0x1ec + subi r6, r6, 4 + srwi r7, r6, 2 + bl major_0x09c9c + cmpwi r6, 0x00 + ori r16, r9, 0x21 + stwx r16, r15, r6 + bne+ VMInit_0x1ec + lwz r15, KDP.FlatPageListPtr(r1) + srwi r7, r5, 10 + add r15, r15, r7 + lwz r5, 0x06a8(r1) + +VMInit_0x218 + lwz r16, 0x0000(r15) + andi. r7, r16, 0x01 + beql+ Local_Panic + ori r16, r16, 0x404 + stw r16, 0x0000(r15) + addi r5, r5, -0x400 + cmpwi r5, 0x00 + addi r15, r15, 0x04 + bgt+ VMInit_0x218 + lwz r9, 0x06b4(r1) + lwz r6, 0x05e8(r1) + addi r9, r9, -0x01 + li r8, 0xa00 + ori r7, r8, 0xffff + +VMInit_0x250 + cmplwi r9, 0xffff + lwz r3, 0x0000(r6) + addi r6, r6, 0x08 + stw r7, 0x0000(r3) + stw r8, 0x0004(r3) + stw r7, 0x0008(r3) + stw r8, 0x000c(r3) + addis r9, r9, -0x01 + bgt+ VMInit_0x250 + sth r9, 0x0002(r3) + sth r9, 0x000a(r3) + lwz r6, 0x05e8(r1) + lwz r9, 0x06a8(r1) + lwz r15, KDP.FlatPageListPtr(r1) + +VMInit_0x288 + lwz r8, 0x0000(r6) + lis r7, 0x01 + rlwinm. r3, r9, 16, 16, 31 + bne- VMInit_0x29c + mr r7, r9 + +VMInit_0x29c + subf. r9, r7, r9 + addi r7, r7, -0x01 + stw r7, 0x0000(r8) + rlwinm r7, r15, 10, 22, 19 + ori r7, r7, 0xc00 + stw r7, 0x0004(r8) + addis r15, r15, 0x04 + addi r6, r6, 0x08 + bne+ VMInit_0x288 + mfsprg r9, 0 + lwz r6, -0x0014(r9) + +; r6 = ewa + bl Save_r14_r31 +; r8 = sprg0 (not used by me) + + lwz r8, -0x001c(r9) + li r9, 0x00 + bl FindAreaAbove + lwz r16, 0x0024(r8) + cmpwi r16, 0x00 + bne+ Local_Panic + li r16, 0x00 + stw r16, 0x003c(r8) + lwz r16, KDP.FlatPageListPtr(r1) + stw r16, 0x0040(r8) + lwz r16, 0x06a8(r1) + slwi r16, r16, 12 + stw r16, 0x002c(r8) + addi r16, r16, -0x01 + stw r16, 0x0028(r8) + mr r17, r8 + _log 'Adjusting area ' + lwz r8, 0x0000(r17) + mr r8, r8 + bl printw + _log 'to size ' + lwz r8, 0x002c(r17) + mr r8, r8 + bl printw + _log '^n' + +; r6 = ewa + bl Restore_r14_r31 + b VMReturn0 + +VMInit_0x374 + lwz r7, 0x06ac(r1) + lwz r8, 0x06c0(r1) + stw r7, 0x06a8(r1) + stw r8, KDP.FlatPageListPtr(r1) + b VMReturn + + + +; 'exchange physical page contents' + + DeclareVMCallWithAlt 12, VMExchangePages, VMReturnNotReady + +VMExchangePages ; OUTSIDE REFERER + bl VeryPopularFunction + bge+ cr4, VMReturnMinus1 + bgt+ cr5, VMReturnMinus1 + bns+ cr7, VMReturnMinus1 + bgt+ cr6, VMReturnMinus1 + bne+ cr6, VMReturnMinus1 + bltl- cr5, VMDoSomethingWithTLB + bltl- cr5, major_0x09b40 + mr r6, r15 + mr r4, r5 + mr r5, r16 + lwz r9, 0x06a8(r1) + bl VeryPopularFunction + bge+ cr4, VMReturnMinus1 + bgt+ cr5, VMReturnMinus1 + bns+ cr7, VMReturnMinus1 + bgt+ cr6, VMReturnMinus1 + bne+ cr6, VMReturnMinus1 + bltl- cr5, VMDoSomethingWithTLB + bltl- cr5, major_0x09b40 + stw r5, 0x0000(r15) + stw r16, 0x0000(r6) + rlwinm r4, r5, 0, 0, 19 + rlwinm r5, r16, 0, 0, 19 + li r9, 0x1000 + li r6, 0x04 + +VMExchangePages_0x68 + subf. r9, r6, r9 + lwzx r7, r4, r9 + lwzx r8, r5, r9 + stwx r7, r5, r9 + stwx r8, r4, r9 + bne+ VMExchangePages_0x68 + b VMReturn + + + +; 'return phys page given log page' + + DeclareVMCall 10, VMGetPhysicalPage + +VMGetPhysicalPage ; OUTSIDE REFERER + bne- cr1, VMGetPhysicalPage_0x30 + mfsprg r9, 0 + lwz r6, -0x0014(r9) + +; r6 = ewa + bl Save_r14_r31 +; r8 = sprg0 (not used by me) + + slwi r29, r4, 12 + bl major_0x08d88 + blt- VMGetPhysicalPage_0x28 + bns- cr7, major_0x08d88_0xa8 + srwi r3, r17, 12 + b major_0x08d88_0xb0 + +VMGetPhysicalPage_0x28 +; r6 = ewa + bl Restore_r14_r31 + lwz r9, 0x06a8(r1) + +VMGetPhysicalPage_0x30 + bl VeryPopularFunction + bns+ cr7, VMReturnMinus1 + srwi r3, r9, 12 + b VMReturn + + + +; 'given a page, get its 68K PTE' + + DeclareVMCall 19, getPTEntryGivenPage + +getPTEntryGivenPage ; OUTSIDE REFERER + bne- cr1, getPTEntryGivenPage_0x50 + mfsprg r9, 0 + lwz r6, -0x0014(r9) + +; r6 = ewa + bl Save_r14_r31 +; r8 = sprg0 (not used by me) + + slwi r29, r4, 12 + bl major_0x08d88 + blt- getPTEntryGivenPage_0x48 + lwz r3, 0x0000(r30) + beq- getPTEntryGivenPage_0x3c + bns- cr7, getPTEntryGivenPage_0x3c + bge- cr5, getPTEntryGivenPage_0x3c + bl MPCall_95_0x2e0 + bl MPCall_95_0x334 + lwz r3, 0x0000(r30) + rlwimi r3, r17, 0, 0, 19 + +getPTEntryGivenPage_0x3c + li r16, 0x882 + andc r3, r3, r16 + b major_0x08d88_0xb0 + +getPTEntryGivenPage_0x48 +; r6 = ewa + bl Restore_r14_r31 + lwz r9, 0x06a8(r1) + +getPTEntryGivenPage_0x50 + bl VeryPopularFunction + mr r3, r16 + bns- cr7, getPTEntryGivenPage_0x74 + rlwimi r3, r9, 0, 0, 19 + bge- cr5, getPTEntryGivenPage_0x74 + bl VMDoSomethingWithTLB + bl VMDoSomeIO_0x4 + mr r3, r16 + rlwimi r3, r9, 0, 0, 19 + +getPTEntryGivenPage_0x74 + li r8, 0x882 + andc r3, r3, r8 + b VMReturn + + + +; major_0x08d88 + +; Xrefs: +; VMGetPhysicalPage +; getPTEntryGivenPage +; VMIsResident +; VMMarkBacking +; VMMarkResident +; setPTEntryGivenPage + +major_0x08d88 ; OUTSIDE REFERER + mfsprg r28, 0 + mflr r27 + mr r9, r29 + lwz r8, -0x001c(r28) + bl FindAreaAbove + mr r31, r8 + lwz r16, 0x0024(r31) + lwz r17, 0x0028(r31) + lwz r18, 0x0020(r31) + cmplw r29, r16 + cmplw cr1, r29, r17 + blt- major_0x08d88_0x74 + bgt- cr1, major_0x08d88_0x74 + rlwinm. r8, r18, 0, 16, 16 + lwz r19, 0x0070(r31) + beq- major_0x08d88_0x8c + lwz r17, 0x0038(r31) + rlwinm r19, r19, 0, 0, 19 + cmpwi r17, 0x00 + subf r18, r16, r29 + beq- major_0x08d88_0x74 + mtlr r27 + crclr cr0_lt + crset cr0_eq + add r17, r18, r19 + addi r30, r31, 0x74 + crset cr7_so + rlwimi r18, r17, 0, 0, 19 + blr + +major_0x08d88_0x74 + mtlr r27 + srwi r8, r29, 28 + cmpwi r8, 0x07 + beq- major_0x08d88_0xa8 + crset cr0_lt + blr + +major_0x08d88_0x8c + mr r8, r29 + bl MPCall_95_0x1e4 + bl MPCall_95_0x2b0 + mtlr r27 + crclr cr0_lt + crclr cr0_eq + blr + +major_0x08d88_0xa8 ; OUTSIDE REFERER +; r6 = ewa + bl Restore_r14_r31 + b VMReturnMinus1 + +major_0x08d88_0xb0 ; OUTSIDE REFERER +; r6 = ewa + bl Restore_r14_r31 + b VMReturn + + + +; 'ask about page status' (typo?) + + DeclareVMCallWithAlt 5, VMIsInited, VMReturnNotReady + +VMIsInited ; OUTSIDE REFERER + bl VeryPopularFunction + bso+ cr7, VMReturn1 + rlwinm r3, r16, 16, 31, 31 + b VMReturn + + + +; 'ask about page status' (typo?) + + DeclareVMCall 3, VMIsResident + +VMIsResident ; OUTSIDE REFERER + bne- cr1, VMIsResident_0x30 + mfsprg r9, 0 + lwz r6, -0x0014(r9) + +; r6 = ewa + bl Save_r14_r31 +; r8 = sprg0 (not used by me) + + slwi r29, r4, 12 + bl major_0x08d88 + blt- VMIsResident_0x28 + lwz r16, 0x0000(r30) + srwi r3, r16, 31 + b major_0x08d88_0xb0 + +VMIsResident_0x28 +; r6 = ewa + bl Restore_r14_r31 + lwz r9, 0x06a8(r1) + +VMIsResident_0x30 + bl VeryPopularFunction + clrlwi r3, r16, 0x1f + b VMReturn + + + +; 'ask about page status' (typo?) + + DeclareVMCallWithAlt 4, VMIsUnmodified, VMReturnNotReady + +VMIsUnmodified ; OUTSIDE REFERER + bl VeryPopularFunction + rlwinm r3, r16, 28, 31, 31 + xori r3, r3, 0x01 + bge+ cr5, VMReturn + bl VMDoSomethingWithTLB + bl VMDoSomeIO_0x4 + rlwinm r3, r16, 28, 31, 31 + xori r3, r3, 0x01 + b VMReturn + + + +; Cube-E has no comment + + DeclareVMCallWithAlt 22, VMLRU, VMReturnNotReady + +VMLRU ; OUTSIDE REFERER + rlwinm. r9, r9, 2, 0, 29 + lwz r15, KDP.FlatPageListPtr(r1) + lwz r14, 0x06a4(r1) + add r15, r15, r9 + srwi r4, r9, 2 + li r5, 0x100 + li r6, 0x08 + +VMLRU_0x1c + lwzu r16, -0x0004(r15) + addi r4, r4, -0x01 + mtcrf 0x07, r16 + cmpwi r4, 0x00 + rlwinm r7, r16, 23, 9, 28 + bns- cr7, VMLRU_0x5c + bge- cr5, VMLRU_0x50 + add r14, r14, r7 + lwz r8, 0x0000(r14) + bl VMDoSomethingWithTLB + andc r9, r9, r5 + bl major_0x09b40 + subf r14, r7, r14 + +VMLRU_0x50 + rlwimi r16, r16, 6, 22, 22 + andc r16, r16, r6 + stw r16, 0x0000(r15) + +VMLRU_0x5c + bne+ VMLRU_0x1c + b VMReturn + + + +; major_0x08f14 + +; Xrefs: +; VMMakePageCacheable +; VMMakePageWriteThrough +; VMMakePageNonCacheable + +major_0x08f14 ; OUTSIDE REFERER + mflr r28 + mr r29, r8 + mr r30, r9 + mfsprg r18, 0 + slwi r9, r4, 12 + lwz r8, -0x001c(r18) + bl FindAreaAbove + lwz r17, 0x0020(r8) + lwz r16, 0x0024(r8) + rlwinm. r18, r17, 0, 16, 16 + cmplw cr1, r16, r9 + beq+ Local_Panic + bgt+ cr1, Local_Panic + li r16, -0x01 + mtlr r28 + stw r16, 0x0038(r8) + mr r8, r29 + mr r9, r30 + blr + + + +; 'make it so' + + DeclareVMCall 17, VMMakePageCacheable + +VMMakePageCacheable ; OUTSIDE REFERER + bne- cr1, VMMakePageCacheable_0x4 + +VMMakePageCacheable_0x4 + bl VeryPopularFunction + rlwinm r7, r16, 0, 25, 26 + cmpwi r7, 0x20 + bns+ cr7, VMReturnMinus1 + beq+ VMReturn + bge- cr4, VMMakePageCacheable_0x40 + bltl- cr5, VMDoSomethingWithTLB + bgel- cr5, VMSecondLastExportedFunc + rlwinm r16, r16, 0, 27, 24 + rlwinm r9, r9, 0, 27, 24 + lwz r7, 0x0688(r1) + rlwimi r9, r7, 0, 27, 28 + ori r16, r16, 0x20 + bl VMDoSomeIO + b VMReturn + +VMMakePageCacheable_0x40 + rlwinm r7, r4, 16, 28, 31 + cmpwi r7, 0x08 + blt+ VMReturnMinus1 + ble+ cr6, VMReturnMinus1 + _log 'VMMakePageCacheable for I/O ' + mr r8, r4 + bl printw + _log '^n' + mfsprg r6, 0 + lwz r6, -0x0014(r6) + +; r6 = ewa + bl Save_r14_r31 +; r8 = sprg0 (not used by me) + + bl major_0x08f14 + +; r6 = ewa + bl Restore_r14_r31 + lwz r5, 0x000c(r15) + andi. r6, r5, 0xe01 + cmpwi r6, 0xa01 + beq- VMMakePageCacheable_0xec + addi r15, r15, -0x08 + lwz r5, 0x0004(r15) + lhz r6, 0x0000(r15) + andi. r5, r5, 0xc00 + lhz r5, 0x0002(r15) + bne+ VMReturnMinus1 + addi r5, r5, 0x01 + add r6, r6, r5 + xor r6, r6, r4 + andi. r6, r6, 0xffff + bne+ VMReturnMinus1 + sth r5, 0x0002(r15) + b PageSetCommon + +VMMakePageCacheable_0xec + lwz r5, 0x0000(r15) + lwz r6, 0x0004(r15) + stw r5, 0x0008(r15) + stw r6, 0x000c(r15) + slwi r5, r4, 16 + stw r5, 0x0000(r15) + slwi r5, r4, 12 + ori r5, r5, 0x12 + stw r5, 0x0004(r15) + b PageSetCommon + + + +; Cube-E has no comment + + DeclareVMCall 24, VMMakePageWriteThrough + +VMMakePageWriteThrough ; OUTSIDE REFERER + bne- cr1, VMMakePageWriteThrough_0x4 + +VMMakePageWriteThrough_0x4 + bl VeryPopularFunction + rlwinm. r7, r16, 0, 25, 26 + bns+ cr7, VMReturnMinus1 + beq+ VMReturn + bge- cr4, VMMakePageWriteThrough_0x3c + bltl- cr5, VMDoSomethingWithTLB + bgel- cr5, VMSecondLastExportedFunc + rlwinm r16, r16, 0, 27, 24 + rlwinm r9, r9, 0, 27, 24 + lwz r7, 0x0688(r1) + rlwimi r9, r7, 0, 27, 28 + ori r9, r9, 0x40 + bl VMDoSomeIO + b VMMakePageNonCacheable_0x3c + +VMMakePageWriteThrough_0x3c + rlwinm r7, r4, 16, 28, 31 + cmpwi r7, 0x08 + blt+ VMReturnMinus1 + ble+ cr6, VMReturnMinus1 + _log 'VMMakePageWriteThrough for I/O ' + mr r8, r4 + bl printw + _log '^n' + mfsprg r6, 0 + lwz r6, -0x0014(r6) + +; r6 = ewa + bl Save_r14_r31 +; r8 = sprg0 (not used by me) + + bl major_0x08f14 + +; r6 = ewa + bl Restore_r14_r31 + lwz r5, 0x000c(r15) + andi. r6, r5, 0xe01 + cmpwi r6, 0xa01 + beq- VMMakePageWriteThrough_0xec + addi r15, r15, -0x08 + lwz r5, 0x0004(r15) + lhz r6, 0x0000(r15) + andi. r5, r5, 0xc00 + lhz r5, 0x0002(r15) + bne+ VMReturnMinus1 + addi r5, r5, 0x01 + add r6, r6, r5 + xor r6, r6, r4 + andi. r6, r6, 0xffff + bne+ VMReturnMinus1 + sth r5, 0x0002(r15) + b PageSetCommon + +VMMakePageWriteThrough_0xec + lwz r5, 0x0000(r15) + lwz r6, 0x0004(r15) + stw r5, 0x0008(r15) + stw r6, 0x000c(r15) + slwi r5, r4, 16 + stw r5, 0x0000(r15) + slwi r5, r4, 12 + ori r5, r5, 0x52 + stw r5, 0x0004(r15) + + + +; PageSetCommon + +; Xrefs: +; VMMakePageCacheable +; VMMakePageWriteThrough +; VMMakePageNonCacheable + +PageSetCommon ; OUTSIDE REFERER + lwz r15, 0x06a0(r1) + lwz r14, 0x06a4(r1) + slwi r6, r4, 12 + mfsrin r6, r6 + rlwinm r8, r6, 7, 0, 20 + xor r6, r6, r4 + slwi r7, r6, 6 + and r15, r15, r7 + rlwimi r8, r4, 22, 26, 31 + crset cr0_eq + oris r8, r8, 0x8000 + +PageSetCommon_0x2c + lwzux r7, r14, r15 + lwz r15, 0x0008(r14) + lwz r6, 0x0010(r14) + lwz r5, 0x0018(r14) + cmplw cr1, r7, r8 + cmplw cr2, r15, r8 + cmplw cr3, r6, r8 + cmplw cr4, r5, r8 + beq- cr1, PageSetCommon_0xc8 + beq- cr2, PageSetCommon_0xc4 + beq- cr3, PageSetCommon_0xc0 + beq- cr4, PageSetCommon_0xbc + lwzu r7, 0x0020(r14) + lwz r15, 0x0008(r14) + lwz r6, 0x0010(r14) + lwz r5, 0x0018(r14) + cmplw cr1, r7, r8 + cmplw cr2, r15, r8 + cmplw cr3, r6, r8 + cmplw cr4, r5, r8 + beq- cr1, PageSetCommon_0xc8 + beq- cr2, PageSetCommon_0xc4 + beq- cr3, PageSetCommon_0xc0 + beq- cr4, PageSetCommon_0xbc + crnot 2, 2 + lwz r15, 0x06a0(r1) + lwz r14, 0x06a4(r1) + slwi r6, r4, 12 + mfsrin r6, r6 + xor r6, r6, r4 + not r6, r6 + slwi r7, r6, 6 + and r15, r15, r7 + xori r8, r8, 0x40 + bne+ PageSetCommon_0x2c + b VMReturn + +PageSetCommon_0xbc + addi r14, r14, 0x08 + +PageSetCommon_0xc0 + addi r14, r14, 0x08 + +PageSetCommon_0xc4 + addi r14, r14, 0x08 + +PageSetCommon_0xc8 + bl VMDoSomethingWithTLB + li r8, 0x00 + li r9, 0x00 + bl VMDoSomeIO_0x4 + b VMReturn + + + +; 'make it so' + + DeclareVMCall 18, VMMakePageNonCacheable + +VMMakePageNonCacheable ; OUTSIDE REFERER + bne- cr1, VMMakePageNonCacheable_0x4 + +VMMakePageNonCacheable_0x4 + bl VeryPopularFunction + rlwinm r7, r16, 0, 25, 26 + cmpwi r7, 0x60 + bns+ cr7, VMReturnMinus1 + beq+ VMReturn + bge- cr4, VMMakePageNonCacheable_0x78 + bltl- cr5, VMDoSomethingWithTLB + bgel- cr5, VMSecondLastExportedFunc + rlwinm r9, r9, 0, 27, 24 + lwz r7, 0x0688(r1) + rlwimi r9, r7, 0, 27, 28 + ori r16, r16, 0x60 + ori r9, r9, 0x20 + bl VMDoSomeIO + +VMMakePageNonCacheable_0x3c ; OUTSIDE REFERER + rlwinm r4, r9, 0, 0, 19 + lhz r8, 0x0f4a(r1) + add r5, r4, r8 + li r7, 0x1000 + slwi r8, r8, 1 + +VMMakePageNonCacheable_0x50 + subf. r7, r8, r7 + dcbf r7, r4 + dcbf r7, r5 + sync + icbi r7, r4 + icbi r7, r5 + bne+ VMMakePageNonCacheable_0x50 + sync + isync + b VMReturn + +VMMakePageNonCacheable_0x78 + rlwinm r7, r4, 16, 28, 31 + cmpwi r7, 0x08 + blt+ VMReturnMinus1 + bgt+ cr6, VMReturnMinus1 + _log 'VMMakePageNonCacheable for I/O ' + mr r8, r4 + bl printw + _log '^n' + mfsprg r6, 0 + lwz r6, -0x0014(r6) + +; r6 = ewa + bl Save_r14_r31 +; r8 = sprg0 (not used by me) + + bl major_0x08f14 + +; r6 = ewa + bl Restore_r14_r31 + lwz r5, 0x0004(r15) + srwi r6, r5, 12 + cmpw r6, r4 + bne+ VMReturnMinus1 + lis r7, 0x00 + lis r8, 0x00 + lis r9, 0x00 + srwi r6, r5, 12 + lhz r8, 0x0002(r15) + lhz r7, 0x0000(r15) + addi r6, r6, 0x01 + cmpwi r8, 0x00 + beq- VMMakePageNonCacheable_0x134 + addi r7, r7, 0x01 + addi r8, r8, -0x01 + rlwimi r5, r6, 12, 0, 19 + sth r7, 0x0000(r15) + sth r8, 0x0002(r15) + stw r5, 0x0004(r15) + b PageSetCommon + +VMMakePageNonCacheable_0x134 + lis r6, 0x00 + lwz r7, 0x0008(r15) + lwz r8, 0x000c(r15) + lis r5, 0x00 + ori r6, r6, 0xa01 + stw r7, 0x0000(r15) + stw r8, 0x0004(r15) + stw r5, 0x0008(r15) + stw r6, 0x000c(r15) + dcbf 0, r15 + b PageSetCommon + + + +; 'set page status' + + DeclareVMCall 8, VMMarkBacking + +VMMarkBacking ; OUTSIDE REFERER + bne- cr1, VMMarkBacking_0x58 + mfsprg r9, 0 + lwz r6, -0x0014(r9) + +; r6 = ewa + bl Save_r14_r31 +; r8 = sprg0 (not used by me) + + slwi r29, r4, 12 + bl major_0x08d88 + blt- VMMarkBacking_0x50 + beq+ major_0x08d88_0xa8 + bns- cr7, VMMarkBacking_0x30 + bge- cr5, VMMarkBacking_0x30 + bl MPCall_95_0x2e0 + bl MPCall_95_0x348 + +VMMarkBacking_0x30 + lwz r18, 0x0000(r30) + rlwinm r18, r18, 0, 0, 30 + stw r18, 0x0000(r30) + lwz r18, 0x0068(r31) + lwz r17, 0x0038(r31) + subf r17, r18, r17 + stw r17, 0x0038(r31) + b major_0x08d88_0xb0 + +VMMarkBacking_0x50 +; r6 = ewa + bl Restore_r14_r31 + lwz r9, 0x06a8(r1) + +VMMarkBacking_0x58 + bl VeryPopularFunction + bge+ cr4, VMReturnMinus1 + bgt+ cr5, VMReturnMinus1 + bltl- cr5, VMDoSomethingWithTLB + bltl- cr5, major_0x09b40 + rlwimi r16, r5, 16, 15, 15 + li r7, 0x01 + andc r16, r16, r7 + stw r16, 0x0000(r15) + b VMReturn + + + +; 'ask about page status' (typo?) + + DeclareVMCallWithAlt 9, VMMarkCleanUnused, VMReturnNotReady + +VMMarkCleanUnused ; OUTSIDE REFERER + bl VeryPopularFunction + bge+ cr4, VMReturnMinus1 + bns+ cr7, VMReturnMinus1 + bltl- cr5, VMDoSomethingWithTLB + beq- cr2, VMMarkCleanUnused_0x2c + bgel- cr5, VMSecondLastExportedFunc + li r7, 0x180 + andc r9, r9, r7 + ori r16, r16, 0x100 + bl VMDoSomeIO + b VMReturn + +VMMarkCleanUnused_0x2c + bgel- cr5, VMSecondLastExportedFunc + ori r16, r16, 0x100 + li r7, 0x18 + andc r16, r16, r7 + bl major_0x09b40 + b VMReturn + + + +; Cube-E has no comment + + DeclareVMCallWithAlt 23, VMMarkUndefined, VMReturnNotReady + +VMMarkUndefined ; OUTSIDE REFERER + cmplw r4, r9 + cmplw cr1, r5, r9 + add r7, r4, r5 + cmplw cr2, r7, r9 + bge+ VMReturnMinus1 + bgt+ cr1, VMReturnMinus1 + bgt+ cr2, VMReturnMinus1 + lwz r15, KDP.FlatPageListPtr(r1) + slwi r8, r7, 2 + li r7, 0x01 + +VMMarkUndefined_0x28 + subi r8, r8, 4 + subf. r5, r7, r5 + lwzx r16, r15, r8 + blt+ VMReturn + rlwimi r16, r6, 7, 24, 24 + stwx r16, r15, r8 + b VMMarkUndefined_0x28 + + + +; 'set page status' + + DeclareVMCall 7, VMMarkResident + +VMMarkResident ; OUTSIDE REFERER + bne- cr1, VMMarkResident_0x58 + mfsprg r9, 0 + lwz r6, -0x0014(r9) + +; r6 = ewa + bl Save_r14_r31 +; r8 = sprg0 (not used by me) + + slwi r29, r4, 12 + slwi r26, r5, 12 + bl major_0x08d88 + blt- VMMarkResident_0x50 + beq+ major_0x08d88_0xa8 + bso+ cr7, major_0x08d88_0xa8 + bltl+ cr5, Local_Panic + lwz r16, 0x0000(r30) + rlwimi r16, r5, 12, 0, 19 + ori r16, r16, 0x01 + stw r16, 0x0000(r30) + lwz r18, 0x0068(r31) + lwz r17, 0x0038(r31) + add r17, r17, r18 + stw r17, 0x0038(r31) + b major_0x08d88_0xb0 + +VMMarkResident_0x50 +; r6 = ewa + bl Restore_r14_r31 + lwz r9, 0x06a8(r1) + +VMMarkResident_0x58 + bl VeryPopularFunction + bge+ cr4, VMReturnMinus1 + bso+ cr7, VMReturnMinus1 + bltl+ cr5, Local_Panic + rlwimi r16, r5, 12, 0, 19 + ori r16, r16, 0x01 + stw r16, 0x0000(r15) + bl VMSecondLastExportedFunc + bl VMDoSomeIO + b VMReturn + + + +; 'ask why we got this page fault' + + DeclareVMCallWithAlt 21, VMPTest, VMReturnNotReady + +VMPTest ; OUTSIDE REFERER + srwi r4, r4, 12 + cmplw r4, r9 + li r3, 0x4000 + bge+ VMReturn + bl VeryPopularFunction + li r3, 0x400 + bns+ cr7, VMReturn + li r3, 0x00 + ori r3, r3, 0x8000 + ble+ cr7, VMReturn + cmpwi r6, 0x00 + beq+ VMReturn + li r3, 0x800 + b VMReturn + + + +; 'given a page & 68K pte, set the real PTE' + + DeclareVMCall 20, setPTEntryGivenPage + +setPTEntryGivenPage ; OUTSIDE REFERER + bne- cr1, setPTEntryGivenPage_0x64 + mfsprg r9, 0 + lwz r6, -0x0014(r9) + +; r6 = ewa + bl Save_r14_r31 +; r8 = sprg0 (not used by me) + + mr r26, r4 + slwi r29, r5, 12 + bl major_0x08d88 + blt- setPTEntryGivenPage_0x5c + beq+ major_0x08d88_0xa8 + bns- cr7, setPTEntryGivenPage_0x34 + bge- cr5, setPTEntryGivenPage_0x34 + bl MPCall_95_0x2e0 + bl MPCall_95_0x348 + +setPTEntryGivenPage_0x34 + lwz r18, 0x0000(r30) + xor r8, r18, r26 + li r3, 0x461 + rlwimi r3, r18, 24, 29, 29 + and. r3, r3, r8 + bne+ major_0x08d88_0xa8 + andi. r8, r8, 0x11c + xor r18, r18, r8 + stw r18, 0x0000(r30) + b major_0x08d88_0xb0 + +setPTEntryGivenPage_0x5c +; r6 = ewa + bl Restore_r14_r31 + lwz r9, 0x06a8(r1) + +setPTEntryGivenPage_0x64 + mr r6, r4 + mr r4, r5 + bl VeryPopularFunction + bge+ cr4, VMReturnMinus1 + xor r7, r16, r6 + li r3, 0x461 + rlwimi r3, r16, 24, 29, 29 + and. r3, r3, r7 + bne+ VMReturnMinus1 + andi. r7, r7, 0x11c + xor r16, r16, r7 + stw r16, 0x0000(r15) + bge+ cr5, VMReturn + bl VMDoSomethingWithTLB + lwz r16, 0x0000(r15) + bne- cr2, setPTEntryGivenPage_0xb4 + andi. r7, r16, 0x08 + bne- setPTEntryGivenPage_0xb4 + bl major_0x09b40 + b VMReturn + +setPTEntryGivenPage_0xb4 + rlwimi r9, r16, 5, 23, 23 + rlwimi r9, r16, 3, 24, 24 + rlwimi r9, r16, 30, 31, 31 + bl VMDoSomeIO_0x4 + b VMReturn + + + +; 'ask about page status' (typo?) + + DeclareVMCallWithAlt 6, VMShouldClean, VMReturnNotReady + +VMShouldClean ; OUTSIDE REFERER + bl VeryPopularFunction + bns+ cr7, VMReturn0 + bge+ cr4, VMReturnMinus1 + bltl- cr5, VMDoSomethingWithTLB + blt- cr7, VMShouldClean_0x34 + bns- cr6, VMShouldClean_0x34 + xori r16, r16, 0x10 + ori r16, r16, 0x100 + stw r16, 0x0000(r15) + bge+ cr5, VMReturn1 + xori r9, r9, 0x80 + bl VMDoSomeIO_0x4 + b VMReturn1 + +VMShouldClean_0x34 + bltl- cr5, VMDoSomeIO_0x4 + b VMReturn0 + + + +; Cube-E has no comment + + DeclareVMCallWithAlt 25, VMAllocateMemory, VMReturnNotReady + +VMAllocateMemory ; OUTSIDE REFERER + lwz r7, KDP.FlatPageListPtr(r1) + lwz r8, 0x06c0(r1) + cmpwi cr6, r5, 0x00 + cmpw cr7, r7, r8 + or r7, r4, r6 + rlwinm. r7, r7, 0, 0, 11 + ble+ cr6, VMReturnMinus1 + lwz r9, 0x06a8(r1) + bne+ cr7, VMReturnMinus1 + mr r7, r4 + bne+ VMReturnMinus1 + mr r4, r9 + slwi r6, r6, 12 + lwz r9, -0x0408(r1) + crclr cr3_eq + cmpwi cr6, r6, 0x00 + cmplw cr7, r9, r5 + bne- cr6, VMAllocateMemory_0x6c + blt- cr7, VMAllocateMemory_0x6c + lwz r9, -0x040c(r1) + subf r4, r5, r9 + slwi r4, r4, 2 + lwz r15, KDP.FlatPageListPtr(r1) + add r15, r15, r4 + srwi r4, r4, 2 + crset cr3_eq + b VMAllocateMemory_0xc0 + +VMAllocateMemory_0x6c + lwz r9, 0x06a8(r1) + addi r5, r5, -0x01 + +VMAllocateMemory_0x74 + addi r4, r4, -0x01 + bl VeryPopularFunction + bltl- cr5, VMDoSomethingWithTLB + bltl- cr5, major_0x09b40 + lwz r9, 0x06a8(r1) + subf r8, r4, r9 + cmplw cr7, r5, r8 + and. r8, r16, r6 + bge+ cr7, VMAllocateMemory_0x74 + bne+ VMAllocateMemory_0x74 + cmpwi cr6, r6, 0x00 + beq- cr6, VMAllocateMemory_0xc0 + slwi r8, r5, 2 + lwzx r8, r15, r8 + slwi r14, r5, 12 + add r14, r14, r16 + xor r8, r8, r14 + rlwinm. r8, r8, 0, 0, 19 + bne+ VMAllocateMemory_0x74 + +VMAllocateMemory_0xc0 + slwi r4, r7, 12 + lwz r9, 0x06b4(r1) + cmplw cr7, r7, r9 + rlwinm. r9, r7, 0, 0, 11 + blt+ cr7, VMReturnMinus1 + bne+ VMReturnMinus1 + lwz r14, 0x05e8(r1) + rlwinm r9, r7, 19, 25, 28 + lwzx r14, r14, r9 + clrlwi r9, r7, 0x10 + lhz r8, 0x0000(r14) + b VMAllocateMemory_0xf4 + +VMAllocateMemory_0xf0 + lhzu r8, 0x0008(r14) + +VMAllocateMemory_0xf4 + lhz r16, 0x0002(r14) + subf r8, r8, r9 + cmplw cr7, r8, r16 + bgt+ cr7, VMAllocateMemory_0xf0 + add r8, r8, r5 + cmplw cr7, r8, r16 + bgt+ cr7, VMReturnMinus1 + lwz r16, 0x0004(r14) + slwi r8, r7, 16 + andi. r16, r16, 0xe01 + cmpwi r16, 0xa01 + or r8, r8, r5 + addi r5, r5, 0x01 + bne+ VMReturnMinus1 + stw r8, 0x0000(r14) + bnel- cr6, VMAllocateMemory_0x2e8 + mr r7, r15 + rotlwi r15, r15, 0x0a + ori r15, r15, 0xc00 + stw r15, 0x0004(r14) + bne- cr3, VMAllocateMemory_0x164 + lwz r8, -0x0408(r1) + subf r8, r5, r8 + stw r8, -0x0408(r1) + lwz r8, -0x040c(r1) + subf r8, r5, r8 + stw r8, -0x040c(r1) + b VMAllocateMemory_0x1a4 + +VMAllocateMemory_0x164 + lwz r7, 0x06ac(r1) + subf r7, r5, r7 + stw r7, 0x06ac(r1) + stw r7, 0x06a8(r1) + lwz r5, -0x0020(r1) + slwi r8, r7, 12 + stw r8, 0x0dc4(r5) + stw r8, 0x0dc8(r5) + mr r5, r14 + lwz r7, 0x06b4(r1) + li r8, 0xa00 + bl VMAllocateMemory_0x33c + lwz r7, 0x06ac(r1) + li r8, 0xc00 + bl VMAllocateMemory_0x33c + mr r14, r5 + +VMAllocateMemory_0x1a4 + mfsprg r6, 0 + lwz r6, -0x0014(r6) + +; r6 = ewa + bl Save_r14_r31 +; r8 = sprg0 (not used by me) + + mr r30, r14 + _log ' VMAllocateMemory - creating area' + li r8, 160 + +; r1 = kdp +; r8 = size + bl PoolAlloc +; r8 = ptr + + mr. r31, r8 + beq+ Local_Panic + lwz r17, 0x0004(r30) + lhz r16, 0x0002(r30) + lis r8, 0x6172 + ori r8, r8, 0x6561 + stw r8, 0x0004(r31) + addi r16, r16, 0x01 + mr r15, r4 + slwi r16, r16, 12 + lwz r8, -0x041c(r1) + lwz r8, 0x0014(r8) + stw r8, 0x006c(r31) + stw r15, 0x0024(r31) + stw r16, 0x002c(r31) + stw r16, 0x0038(r31) + li r8, 0x00 + stw r8, 0x0030(r31) + _log ' at 0x' + mr r8, r15 + bl printw + mr r8, r16 + bl printw + _log '^n' + li r8, 0x07 + stw r8, 0x001c(r31) + lis r8, 0x00 + ori r8, r8, 0x600c + stw r8, 0x0020(r31) + rlwinm r8, r17, 22, 0, 29 + stw r8, 0x0040(r31) + lwz r8, 0x0008(r31) + ori r8, r8, 0xc0 + stw r8, 0x0008(r31) + mr r8, r31 + bl createarea + cmpwi r9, 0x00 + bne+ Local_Panic + mr r31, r8 + mfsprg r9, 0 + lwz r8, -0x001c(r9) + li r9, 0x00 + bl FindAreaAbove + lwz r16, 0x0024(r8) + cmpwi r16, 0x00 + bne+ Local_Panic + lwz r16, 0x06a8(r1) + lwz r17, 0x002c(r8) + slwi r16, r16, 12 + cmpw r17, r16 + beq- VMAllocateMemory_0x2e0 + stw r16, 0x002c(r8) + addi r16, r16, -0x01 + stw r16, 0x0028(r8) + +VMAllocateMemory_0x2e0 +; r6 = ewa + bl Restore_r14_r31 + b VMReturn1 + +VMAllocateMemory_0x2e8 + lwz r16, 0x0000(r15) + lwz r7, 0x06ac(r1) + lwz r8, KDP.FlatPageListPtr(r1) + slwi r7, r7, 2 + add r7, r7, r8 + slwi r8, r5, 2 + subf r7, r8, r7 + cmplw r15, r7 + beqlr- + subi r7, r7, 4 + +VMAllocateMemory_0x310 + lwzx r9, r15, r8 + cmplw r15, r7 + stw r9, 0x0000(r15) + addi r15, r15, 0x04 + blt+ VMAllocateMemory_0x310 + +VMAllocateMemory_0x324 + cmpwi r8, 0x04 + subi r8, r8, 4 + stwu r16, 0x0004(r7) + addi r16, r16, 0x1000 + bgt+ VMAllocateMemory_0x324 + blr + +VMAllocateMemory_0x33c + addi r14, r1, 120 + lwz r15, KDP.FlatPageListPtr(r1) + addi r7, r7, -0x01 + cmpwi cr7, r8, 0xc00 + +VMAllocateMemory_0x34c + cmplwi r7, 0xffff + lwzu r16, 0x0008(r14) + bne- cr7, VMAllocateMemory_0x360 + rotlwi r8, r15, 0x0a + ori r8, r8, 0xc00 + +VMAllocateMemory_0x360 + stw r8, 0x0004(r16) + addis r15, r15, 0x04 + addis r7, r7, -0x01 + bgt+ VMAllocateMemory_0x34c + sth r7, 0x0002(r16) + blr + + + +; VeryPopularFunction + +; Xrefs: +; VMFinalInit +; VMExchangePages +; VMGetPhysicalPage +; getPTEntryGivenPage +; VMIsInited +; VMIsResident +; VMIsUnmodified +; VMMakePageCacheable +; VMMakePageWriteThrough +; VMMakePageNonCacheable +; VMMarkBacking +; VMMarkCleanUnused +; VMMarkResident +; VMPTest +; setPTEntryGivenPage +; VMShouldClean +; VMAllocateMemory +; VMLastExportedFunc +; major_0x0b144 + +VeryPopularFunction ; OUTSIDE REFERER + cmplw cr4, r4, r9 + lwz r15, KDP.FlatPageListPtr(r1) + slwi r8, r4, 2 + bge- cr4, VeryPopularFunction_0x40 + +VeryPopularFunction_0x10 + lwzux r16, r15, r8 + lwz r14, 0x06a4(r1) + mtcrf 0x07, r16 + rlwinm r8, r16, 23, 9, 28 + rlwinm r9, r16, 0, 0, 19 + bgelr- cr5 + lwzux r8, r14, r8 + lwz r9, 0x0004(r14) + mtcrf 0x80, r8 + bns+ cr7, Local_Panic + bltlr- + bl Local_Panic + +VeryPopularFunction_0x40 + lwz r9, 0x06b4(r1) + cmplw cr4, r4, r9 + rlwinm. r9, r4, 0, 0, 11 + blt+ cr4, VMReturnMinus1 + bne+ VMReturnMinus1 + lwz r15, 0x05e8(r1) + rlwinm r9, r4, 19, 25, 28 + lwzx r15, r15, r9 + clrlwi r9, r4, 0x10 + lhz r8, 0x0000(r15) + b VeryPopularFunction_0x70 + +VeryPopularFunction_0x6c + lhzu r8, 0x0008(r15) + +VeryPopularFunction_0x70 + lhz r16, 0x0002(r15) + subf r8, r8, r9 + cmplw cr4, r8, r16 + bgt+ cr4, VeryPopularFunction_0x6c + lwz r9, 0x0004(r15) + andi. r16, r9, 0xc00 + cmpwi cr6, r16, 0x400 + cmpwi cr7, r16, 0xc00 + beq- VeryPopularFunction_0xac + beq- cr6, VeryPopularFunction_0xb4 + bne+ cr7, VMReturnMinus1 + slwi r8, r8, 2 + rlwinm r15, r9, 22, 0, 29 + crset cr4_lt + b VeryPopularFunction_0x10 + +VeryPopularFunction_0xac + slwi r8, r8, 12 + add r9, r9, r8 + +VeryPopularFunction_0xb4 + rlwinm r16, r9, 0, 0, 19 + crclr cr4_lt + rlwinm r9, r9, 0, 22, 19 + rlwimi r16, r9, 1, 25, 25 + rlwimi r16, r9, 31, 26, 26 + xori r16, r16, 0x20 + rlwimi r16, r9, 29, 27, 27 + rlwimi r16, r9, 27, 28, 28 + rlwimi r16, r9, 2, 29, 29 + ori r16, r16, 0x01 + mtcrf 0x07, r16 + blr + + + +; VMDoSomethingWithTLB + +; Xrefs: +; VMFinalInit +; VMInit +; VMExchangePages +; getPTEntryGivenPage +; VMIsUnmodified +; VMLRU +; VMMakePageCacheable +; VMMakePageWriteThrough +; PageSetCommon +; VMMakePageNonCacheable +; VMMarkBacking +; VMMarkCleanUnused +; setPTEntryGivenPage +; VMShouldClean +; VMAllocateMemory +; VMLastExportedFunc +; major_0x0b144 + +VMDoSomethingWithTLB ; OUTSIDE REFERER + mfpvr r9 + clrlwi r8, r8, 0x01 + rlwinm. r9, r9, 0, 0, 14 + stw r8, 0x0000(r14) + slwi r9, r4, 12 + sync + tlbie r9 + beq- VMDoSomethingWithTLB_0x28 + sync + tlbsync + +VMDoSomethingWithTLB_0x28 + sync + isync + lwz r9, 0x0004(r14) + oris r8, r8, 0x8000 + rlwimi r16, r9, 29, 27, 27 + rlwimi r16, r9, 27, 28, 28 + mtcrf 0x07, r16 + blr + + + +; VMDoSomeIO + +; Xrefs: +; getPTEntryGivenPage +; VMIsUnmodified +; VMMakePageCacheable +; VMMakePageWriteThrough +; PageSetCommon +; VMMakePageNonCacheable +; VMMarkCleanUnused +; VMMarkResident +; setPTEntryGivenPage +; VMShouldClean +; major_0x09b40 +; major_0x0b144 + +VMDoSomeIO ; OUTSIDE REFERER + stw r16, 0x0000(r15) + +VMDoSomeIO_0x4 ; OUTSIDE REFERER + stw r9, 0x0004(r14) + eieio + stw r8, 0x0000(r14) + sync + blr + + + +; major_0x09b40 + +; Xrefs: +; VMFinalInit +; VMInit +; VMExchangePages +; VMLRU +; VMMakePageCacheable +; VMMakePageWriteThrough +; VMMakePageNonCacheable +; VMMarkBacking +; VMMarkCleanUnused +; VMMarkResident +; setPTEntryGivenPage +; VMAllocateMemory +; major_0x0b144 + +major_0x09b40 ; OUTSIDE REFERER + lwz r8, 0x0e98(r1) + rlwinm r16, r16, 0, 21, 19 + addi r8, r8, 0x01 + stw r8, 0x0e98(r1) + rlwimi r16, r9, 0, 0, 19 + li r8, -0x01 + stw r8, 0x0340(r1) + stw r8, 0x0348(r1) + stw r8, 0x0350(r1) + stw r8, 0x0358(r1) + li r8, 0x00 + li r9, 0x00 + b VMDoSomeIO + +VMSecondLastExportedFunc ; OUTSIDE REFERER + lwz r8, 0x06a0(r1) + + + +; VMLastExportedFunc + +; Xrefs: +; major_0x09b40 + + +VMLastExportedFunc + lwz r14, 0x06a4(r1) + slwi r9, r4, 12 + mfsrin r6, r9 + xor r9, r6, r4 + slwi r7, r9, 6 + and r8, r8, r7 + lwzux r7, r14, r8 + lwz r8, 0x0008(r14) + lwz r9, 0x0010(r14) + lwz r5, 0x0018(r14) + cmpwi r7, 0x00 + cmpwi cr1, r8, 0x00 + cmpwi cr2, r9, 0x00 + cmpwi cr3, r5, 0x00 + bge- VMLastExportedFunc_0x87 + bge- cr1, VMLastExportedFunc_0x83 + bge- cr2, VMLastExportedFunc_0x7f + bge- cr3, VMLastExportedFunc_0x7b + lwzu r7, 0x0020(r14) + lwz r8, 0x0008(r14) + lwz r9, 0x0010(r14) + lwz r5, 0x0018(r14) + cmpwi r7, 0x00 + cmpwi cr1, r8, 0x00 + cmpwi cr2, r9, 0x00 + cmpwi cr3, r5, 0x00 + bge- VMLastExportedFunc_0x87 + bge- cr1, VMLastExportedFunc_0x83 + bge- cr2, VMLastExportedFunc_0x7f + blt- cr3, VMLastExportedFunc_0xd7 + +VMLastExportedFunc_0x7b + addi r14, r14, 0x08 + +VMLastExportedFunc_0x7f + addi r14, r14, 0x08 + +VMLastExportedFunc_0x83 + addi r14, r14, 0x08 + +VMLastExportedFunc_0x87 + lwz r9, 0x0e94(r1) + rlwinm r8, r6, 7, 1, 24 + addi r9, r9, 0x01 + stw r9, 0x0e94(r1) + rlwimi r8, r4, 22, 26, 31 + lwz r9, 0x0688(r1) + oris r8, r8, 0x8000 + rlwimi r9, r16, 0, 0, 19 + ori r9, r9, 0x100 + ori r16, r16, 0x08 + rlwimi r9, r16, 3, 24, 24 + rlwimi r9, r16, 31, 26, 26 + rlwimi r9, r16, 1, 25, 25 + xori r9, r9, 0x40 + rlwimi r9, r16, 30, 31, 31 + lwz r7, 0x06a4(r1) + ori r16, r16, 0x801 + subf r7, r7, r14 + rlwimi r16, r7, 9, 0, 19 + blr + +VMLastExportedFunc_0xd7 + mr r7, r27 + mr r8, r29 + mr r9, r30 + mr r5, r31 + mr r16, r28 + mr r14, r26 + mflr r6 + slwi r27, r4, 12 + bl PagingFunc1 + bnel+ Local_Panic + mr r27, r7 + mr r29, r8 + mr r30, r9 + mr r31, r5 + mr r28, r16 + mr r26, r14 + lwz r9, 0x06a8(r1) + bl VeryPopularFunction + mtlr r6 + b VMDoSomethingWithTLB + + + +; major_0x09c9c + +; Xrefs: +; VMInit + +major_0x09c9c ; OUTSIDE REFERER + addi r8, r1, 0x6c0 + lwz r9, 0x06ac(r1) + rlwimi r8, r7, 18, 26, 29 + cmplw r7, r9 + lwz r8, 0x0000(r8) + rlwinm r7, r7, 2, 14, 29 + bge+ VMReturnMinus1 + lwzx r9, r8, r7 + rlwinm r9, r9, 0, 0, 19 + blr diff --git a/NanoKernel/NanoKernel.s b/NanoKernel/NanoKernel.s new file mode 100644 index 0000000..0c0b4e5 --- /dev/null +++ b/NanoKernel/NanoKernel.s @@ -0,0 +1,59 @@ + include 'MacErrors.a' + + include 'InfoRecords.a' + include 'EmulatorPublic.a' + include 'NKPublic.a' + include 'NKOpaque.a' + + include 'NKEquates.s' + include 'NKMacros.s' + +NKTop + include 'NKInit.s' + align 5 + include 'NKInterrupts.s' + align 5 + include 'NKPaging.s' + align 5 + include 'NKTranslation.s' + align 5 + include 'NKVMCalls.s' + align 5 + include 'NKPowerCalls.s' + align 5 + include 'NKRTASCalls.s' + align 5 + include 'NKCacheCalls.s' + + ; Mostly MP calls: + align 5 + include 'NKMPCalls.s' + align 5 + include 'NKQueues.s' + align 5 + include 'NKTasks.s' + align 5 + include 'NKAddressSpaceMPCalls.s' + + align 5 + include 'NKPoolAllocator.s' + align 5 + include 'NKTimers.s' + align 5 + include 'NKScheduler.s' + align 5 + include 'NKIndex.s' + align 5 + include 'NKPrimaryIntHandlers.s' + align 5 + include 'NKConsoleLog.s' + align 5 + include 'NKSleep.s' + align 5 + include 'NKThud.s' + align 5 + include 'NKScreenConsole.s' + align 5 + include 'NKAdditions.s' + align 5 +NKBtm diff --git a/PPCExceptionTable.s b/PPCExceptionTable.s new file mode 100644 index 0000000..5ebf776 --- /dev/null +++ b/PPCExceptionTable.s @@ -0,0 +1,483 @@ +HASH1 equ 978 +HASH2 equ 979 +ICMP equ 981 +DCMP equ 977 +IMISS equ 980 +DMISS equ 976 +RPA equ 982 + + + + macro + Vanilla &idx + +@start + b @jump1 + b @jump2 + +@jump1 + ; r1 -> SPRG1 + ; LR -> SPRG2 + ; targ -> r1 + ; optr -> LR + mtsprg 1, r1 + mflr r1 + mtsprg 2, r1 + mfsprg r1, 3 + lwz r1, &idx(r1) + mtlr r1 + blrl + dc.l @start - TableStart + mflr r1 + +@jump2 + mtsprg 1, r1 + mfsprg r1, 3 + mtsprg 2, r1 + mtlr r1 + lwz r1, &idx(r1) + dc.l @start - TableStart + blrl + + endm + + + +TableStart + + + +; 0000-00ff: For software use only + + org 0x0000 + mtsprg 1, r1 + mfsprg r1, 3 + lwz r1, 0x00BC(r1) + mtlr r1 + blrl + + + org 0x0080 + dc.l 0x0000D000 ; '....' (invalid instruction) + + + +; 0100-0fff: Architecture-defined exceptions + + org 0x0100 + b $+0x0008 ; 0x00000108 + b $+0x0050 ; 0x00000154 + mtsprg 1, r1 + mfcr r1 + mtsprg 2, r1 + mfsrr1 r1 + mtcrf 255, r1 + bne cr7, RTASFairyDust + mfspr r1, HID0 + mtcrf 255, r1 + bns cr3, RTASFairyDust + mfsprg r1, 2 + mtcrf 255, r1 + mflr r1 + mtsprg 2, r1 + mfsprg r1, 3 + lwz r1, 0x0004(r1) + mtlr r1 + blrl + dc.l 0x00000100 ; '....' (invalid instruction) + + + org 0x180 +PerfMon + mtsprg 2, r1 + mfsprg r1, 3 + stw r2, 0x0000(r1) + mfsprg r2, 2 + rlwinm r2, r2, 26, 24, 29 + lwzx r1, r2, r1 + mflr r2 + mtlr r1 + mfsprg r1, 2 + mtsprg 2, r2 + mfsprg r2, 3 + lwz r2, 0x0000(r2) + blr + + + org 0x0200 ; Machine Check + Vanilla 0x0008 + + + org 0x0300 ; Data Storage + Vanilla 0x000C + + + org 0x0400 ; Instruction Storage + Vanilla 0x0010 + + + org 0x0500 ; External + Vanilla 0x0014 + + + org 0x0600 ; Alignment + Vanilla 0x0018 + + + org 0x0700 ; Program + Vanilla 0x001C + + + org 0x0800 ; FP Unavailable + Vanilla 0x0020 + + + org 0x0900 ; Decrementer + Vanilla 0x0024 + + + org 0x0A00 + Vanilla 0x0028 + + + org 0x0B00 + Vanilla 0x002C + + + org 0x0C00 ; System Call + Vanilla 0x0030 + + + org 0x0D00 ; Trace + Vanilla 0x0034 + + + org 0x0E00 + Vanilla 0x0038 + + + ; Performance monitor??? + + org 0x0F00 + mtsprg 1, r1 + li r1, 0xF00 + b PerfMon + + org 0x0F20 + mtsprg 1, r1 + li r1, 0xF20 + b PerfMon + + + + +; 1000-2fff: Implementation-specific exceptions + + org 0x1000 + mfspr r2, HASH1 + lwz r1, 0x0000(r2) + mfctr r0 + mfspr r3, ICMP + cmpw r1, r3 + beq $+0x001C ; 0x00001030 + li r1, 7 + mtctr r1 + lwzu r1, 0x0008(r2) + cmpw r1, r3 + bdnzf cr0_EQ, $-0x0008 ; 0x00001020 + bne $+0x0038 ; 0x00001064 + lwz r1, 0x0004(r2) + mtctr r0 + andi. r3, r1, 0x0008 + bne $+0x006C ; 0x000010A8 + mfspr r0, IMISS + mfsrr1 r3 + mtcrf 128, r3 + mtspr RPA, r1 + ori r1, r1, 0x0100 + srwi r1, r1, 8 + dc.l 0x7C0007E4 ; '|...' (invalid instruction) + stb r1, 0x0006(r2) + rfi + andi. r1, r3, 0x0040 + bne $+0x0014 ; 0x0000107C + mfspr r2, HASH2 + lwz r1, 0x0000(r2) + ori r3, r3, 0x0040 + b $-0x0068 ; 0x00001010 + mfsrr1 r3 + clrlwi r2, r3, 16 + oris r2, r2, 0x4000 + mtctr r0 + mtsrr1 r2 + mfmsr r0 + xoris r0, r0, 0x0002 + mtcrf 128, r3 + mtmsr r0 + isync + b $-0x0CA4 ; 0x00000400 + mfsrr1 r3 + clrlwi r2, r3, 16 + oris r2, r2, 0x1000 + b $-0x0028 ; 0x0000108C + + + org 0x1100 + mfspr r2, HASH1 + lwz r1, 0x0000(r2) + mfctr r0 + mfspr r3, DCMP + cmpw r1, r3 + beq $+0x001C ; 0x00001130 + li r1, 7 + mtctr r1 + lwzu r1, 0x0008(r2) + cmpw r1, r3 + bdnzf cr0_EQ, $-0x0008 ; 0x00001120 + bne $+0x0034 ; 0x00001160 + lwz r1, 0x0004(r2) + mtctr r0 + mfspr r0, DMISS + mfsrr1 r3 + mtcrf 128, r3 + mtspr RPA, r1 + ori r1, r1, 0x0100 + srwi r1, r1, 8 + dc.l 0x7C0007A4 ; '|...' (invalid instruction) + stb r1, 0x0006(r2) + rfi + nop + andi. r1, r3, 0x0040 + bne $+0x013C ; 0x000012A0 + mfspr r2, HASH2 + lwz r1, 0x0000(r2) + ori r3, r3, 0x0040 + b $-0x0064 ; 0x00001110 + + + org 0x1200 + mfspr r2, HASH1 + lwz r1, 0x0000(r2) + mfctr r0 + mfspr r3, DCMP + cmpw r1, r3 + beq $+0x001C ; 0x00001230 + li r1, 7 + mtctr r1 + lwzu r1, 0x0008(r2) + cmpw r1, r3 + bdnzf cr0_EQ, $-0x0008 ; 0x00001220 + bne $+0x003C ; 0x00001268 + lwz r1, 0x0004(r2) + mtctr r0 + slwi. r3, r1, 30 + bge $+0x0044 ; 0x00001280 + andi. r3, r1, 0x0001 + bne $+0x0054 ; 0x00001298 + mfspr r0, DMISS + mfsrr1 r3 + mtcrf 128, r3 + ori r1, r1, 0x0180 + mtspr RPA, r1 + dc.l 0x7C0007A4 ; '|...' (invalid instruction) + sth r1, 0x0006(r2) + rfi + andi. r1, r3, 0x0040 + bne $+0x0034 ; 0x000012A0 + mfspr r2, HASH2 + lwz r1, 0x0000(r2) + ori r3, r3, 0x0040 + b $-0x006C ; 0x00001210 + mfsrr1 r0 + extrwi r0, r0, 1, 17 + mfspr r3, DMISS + mfsrin r3, r3 + rlwnm. r3, r3, r0, 1, 1 + beq $-0x004C ; 0x00001248 + lis r1, 2048 + b $+0x000C ; 0x000012A8 + lis r1, 16384 + mtctr r0 + mfsrr1 r3 + rlwimi r1, r3, 9, 6, 6 + clrlwi r2, r3, 16 + mtsrr1 r2 + mtdsisr r1 + mfspr r1, DMISS + andi. r2, r2, 0x0001 + beq+ $+0x0008 ; 0x000012CC + xori r1, r1, 0x0007 + mtdar r1 + mfmsr r0 + xoris r0, r0, 0x0002 + mtcrf 128, r3 + mtmsr r0 + isync + b $-0x0FE4 ; 0x00000300 + + + org 0x1300 + Vanilla 0x004C + + + org 0x1400 + Vanilla 0x0050 + + + org 0x1500 + Vanilla 0x0054 + + + org 0x1600 + Vanilla 0x0058 + + + org 0x1700 + Vanilla 0x005C + + + org 0x1800 + Vanilla 0x0060 + + + org 0x1900 + Vanilla 0x0064 + + + org 0x1A00 + Vanilla 0x0068 + + + org 0x1B00 + Vanilla 0x006C + + + org 0x1C00 + Vanilla 0x0070 + + + org 0x1D00 + Vanilla 0x0074 + + + org 0x1E00 + Vanilla 0x0078 + + + org 0x1F00 + Vanilla 0x007C + + + org 0x2000 + Vanilla 0x0080 + + + org 0x2100 + Vanilla 0x0084 + + + org 0x2200 + Vanilla 0x0088 + + + org 0x2300 + Vanilla 0x008C + + + org 0x2400 + Vanilla 0x0090 + + + org 0x2500 + Vanilla 0x0094 + + + org 0x2600 + Vanilla 0x0098 + + + org 0x2700 + Vanilla 0x009C + + + org 0x2800 + Vanilla 0x00A0 + + + org 0x2900 + Vanilla 0x00A4 + + + org 0x2A00 + Vanilla 0x00A8 + + + org 0x2B00 + Vanilla 0x00AC + + + org 0x2C00 + Vanilla 0x00B0 + + + org 0x2D00 + Vanilla 0x00B4 + + + org 0x2E00 + Vanilla 0x00B8 + + + org 0x2F00 + Vanilla 0x00BC + + + +; Outside the exception table, but called by it: + + org 0x3000 +RTASFairyDust + mr r21,r3 + + li r0,0 + + lwz r5, 0(r21) + lwz r4, 4(r21) + + lwz r9, 12(r21) + lwz r3, 12(r9) + + lwz r6, 8(r21) + lwz r8, 16(r21) + lwz r22,24(r21) + lwz r23,28(r21) + + bl @clrbats + + lis r7, 'RT' + ori r7,r7,'AS' + + ; Soo, we jump to *(arg + 24) the ugly way + mtlr r22 + blr + +@clrbats + mtdbatl 0,r0 + mtdbatu 0,r0 + mtdbatl 1,r0 + mtdbatu 1,r0 + mtdbatl 2,r0 + mtdbatu 2,r0 + mtdbatl 3,r0 + mtdbatu 3,r0 + mtibatl 0,r0 + mtibatu 0,r0 + mtibatl 1,r0 + mtibatu 1,r0 + mtibatl 2,r0 + mtibatu 2,r0 + mtibatl 3,r0 + mtibatu 3,r0 + isync + + blr diff --git a/README.md b/README.md new file mode 100644 index 0000000..fdf71ae --- /dev/null +++ b/README.md @@ -0,0 +1,59 @@ +The PowerPC ROM for NewWorld Macs +================================= +This repo is part of the *CDG5* project. It builds a 4 MB PowerPC Mac ROM by appending PowerPC code to a 68k Mac ROM (either the included dump, [or one that you built yourself](https://github.com/elliotnunn/mac-rom)). The build result is a byte-perfect copy of the ROM inside the final "Mac OS ROM" release. + +Fixing line endings +------------------- + +MPW requires old-style Mac line endings (CR), while Git works better with Unix line endings (LF). Git filters can be used to convert between the two. Files committed to the repo are "cleaned" (LF-ed), and then "smudged" (CR-ed) when they hit the working tree. After cloning, append these snippets to your Git config. + +Append this to `.git/config`: + + [filter "maclines"] + clean = LC_CTYPE=C tr \\\\r \\\\n + smudge = LC_CTYPE=C tr \\\\n \\\\r + +Append this to `.git/info/attributes`: + + * filter=maclines + *.* -filter + *.s filter=maclines + *.a filter=maclines + *.c filter=maclines + *.h filter=maclines + +Finally, do a once-off "re-smudge": + + rm -rf ../powermac-rom/* + git checkout . + +Setting type and creator codes +------------------------------ + +Some MPW Tools require their input files to have the correct Mac OS file type, but Git does not save Mac OS type and creator codes. This shell script will give enough files a "TEXT" type to keep MPW happy. + + sh SetFileTypes.sh + +Building +-------- +This code is built with the [Macintosh Programmer's Workshop](https://en.wikipedia.org/wiki/Macintosh_Programmer%27s_Workshop) (MPW), which runs on the Classic Mac OS. To satisfy the memory requirements of the build process, the MPW Shell should get a memory partition of at least 16 MB. Once you have MPW set up, the build process is not particularly fussy. + +Not many computers run the Classic Mac OS any more. Here are a few workarounds: + +* Just find a Mac running Mac OS 7.5-9.2. (Not much fun if it's also your test machine.) +* Use the Classic environment on a PowerPC Mac running Mac OS X 10.4 or earlier. (A small PowerBook or iBook is perfect.) +* Use [EMPW](https://github.com/elliotnunn/empw) ("Emulated MPW"), a package of command-line tools, emulators and OS images that lets you run MPW commands straight from your macOS Terminal. This is my preferred solution. + +Once MPW is set up, the build command is: + + EasyBuild + +Using EMPW, that's: + + empw -b EasyBuild + +The 4 MB image will be at `BuildResults/PowerROM`. + +What's next? +------------ +On NewWorld Macs, this image is extracted into RAM from a "Mac OS ROM" file at boot. Use https://github.com/elliotnunn/newworld-rom to build such a file. diff --git a/RomMondo.bin b/RomMondo.bin new file mode 100644 index 0000000..8b3cabe Binary files /dev/null and b/RomMondo.bin differ diff --git a/SetFileTypes.sh b/SetFileTypes.sh new file mode 100755 index 0000000..9608d28 --- /dev/null +++ b/SetFileTypes.sh @@ -0,0 +1,3 @@ +#!/bin/sh + +cd "`dirname "$0"`" && find . -type f -not -path '*/.*' -not -ipath './BuildResults/*' \( -not -name '*.*' -o -iname '*.s' -o -iname '*.a' -o -iname '*.c' -o -iname '*.h' \) -exec SetFile -t 'TEXT' -c 'MPS ' {} \;