mirror of
https://github.com/elliotnunn/powermac-rom.git
synced 2024-07-29 19:28:57 +00:00
1142 lines
29 KiB
ArmAsm
1142 lines
29 KiB
ArmAsm
; AUTO-GENERATED SYMBOL LIST
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; IMPORTS:
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; NKConsoleLog
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; printw
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; NKExceptions
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; Exception
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; IntReturn
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; IntReturnToOtherBlueContext
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; NKIndex
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; LookupID
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; NKInit
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; ResetBuiltinKernel
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; NKIntHandlers
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; LoadInterruptRegisters
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; MaskedInterruptTaken
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; save_all_registers
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; NKMPCalls
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; kcMPDispatch
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; NKPaging
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; PagingL2PWithBATs
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; NKScheduler
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; Restore_v0_v31
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; SchExitInterrupt
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; SchRestoreStartingAtR14
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; SchSaveStartingAtR14
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; SchSwitchSpace
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; NKSync
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; CauseNotification
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; NKTranslation
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; FDPEmulateInstruction
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; EXPORTS:
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; HandlePerfMonitorInt (=> NKInit)
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; IgnoreSoftwareInt (=> NKInit, NKTranslation)
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; IntExternalAlternate (=> NKInit)
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; IntExternalSystem (=> NKInit)
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; IntPerfMonitor (=> NKInit)
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; IntProgram (=> NKInit)
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; IntReturnFromSIGP (=> NKExceptions, NKIntHandlers)
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; IntSyscall (=> NKInit)
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; IntThermalEvent (=> NKInit)
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; IntTrace (=> NKInit)
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; SIGP (=> NKMPCalls, NKScheduler, NKSleep)
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; kcPrioritizeInterrupts (=> NKInit)
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; kcResetSystem (=> NKInit)
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; kcRunAlternateContext (=> NKInit)
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; kcThud (=> NKInit)
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; major_0x046d0 (=> NKInit)
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; major_0x04a20 (=> NKInit)
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; wordfill (=> NKInit, NKPowerCalls)
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major_0x04180 ; OUTSIDE REFERER
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stw r6, -0x0290(r1)
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stw r10, -0x028c(r1)
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stw r11, -0x0288(r1)
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lwz r6, -0x0014(r1)
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lwz r10, 0x00d8(r6)
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mfspr r11, srr1
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cmpwi r10, 0x00
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beql major_0x04180_0x9c
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oris r11, r11, 0x200
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stw r9, -0x027c(r1)
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mtspr srr1, r11
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mfmsr r11
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oris r11, r11, 0x200
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mtmsr r11
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isync
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bl Restore_v0_v31
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lwz r8, -0x0004(r1)
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lwz r11, 0x0ed4(r8)
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addi r11, r11, 0x01
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stw r11, 0x0ed4(r8)
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mtcr r13
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lwz r6, -0x0290(r1)
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lwz r10, -0x028c(r1)
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lwz r11, -0x0288(r1)
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lwz r13, -0x0284(r1)
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lwz r8, -0x0280(r1)
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lwz r9, -0x027c(r1)
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mfsprg r1, 2
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mtlr r1
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mfsprg r1, 1
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rfi
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dcb.b 32, 0
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major_0x04180_0x9c
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mtcr r13
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lwz r6, -0x0290(r1)
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lwz r10, -0x028c(r1)
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lwz r11, -0x0288(r1)
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lwz r13, -0x0284(r1)
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bl LoadInterruptRegisters
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li r8, ecInvalidInstr
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b Exception
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### ###### # #
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# # # ##### # # ###### ##### ###### ## ## #### # # # ##### #### #####
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# ## # # # # # # # # # # # # # # ## # # # # # # #
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# # # # # ###### ##### # # ##### # # # # # # # # # # # # # #
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# # # # # # # ##### # # # # # # # # # # # # #####
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# # ## # # # # # # # # # # # ## # # # # # #
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### # # # # ###### # # # # # #### # # # # #### # #
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align kIntAlign
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IntPerfMonitor ; OUTSIDE REFERER
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mtlr r1
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mfsprg r1, 0
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stw r8, -0x0280(r1)
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stw r13, -0x0284(r1)
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mflr r8
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mfcr r13
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cmpwi r8, 0xf20
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beq major_0x04180
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mtcr r13
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lwz r13, -0x0284(r1)
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lwz r8, -0x0280(r1)
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bl save_all_registers
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mr r28, r8
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rlwinm. r9, r11, 0, 16, 16
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beq MaskedInterruptTaken
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_Lock PSA.SchLock, scratch1=r8, scratch2=r9
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lwz r8, PSA.PMFHandlerID(r1)
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; r8 = id
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bl LookupID
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cmpwi r9, Notification.kIDClass
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mr r30, r8
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bne IntPerfMonitor_0x88
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lwz r16, -0x0340(r28)
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lwz r17, -0x0008(r28)
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stw r16, 0x0010(r30)
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lwz r16, 0x0000(r17)
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stw r16, 0x0014(r30)
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mfspr r16, 955
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stw r16, 0x0018(r30)
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bl CauseNotification
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IntPerfMonitor_0x88
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_AssertAndRelease PSA.SchLock, scratch=r8
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; r6 = ewa
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bl SchRestoreStartingAtR14
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b IntReturn
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; Notify the Thermal Handler
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align kIntAlign
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IntThermalEvent ; OUTSIDE REFERER
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bl save_all_registers
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mr r28, r8
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rlwinm. r9, r11, 0, 16, 16
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beq MaskedInterruptTaken
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_log 'Thermal event^n'
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_Lock PSA.SchLock, scratch1=r8, scratch2=r9
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lwz r8, PSA.ThermalHandlerID(r1)
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bl LookupID
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cmpwi r9, Notification.kIDClass
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mr r30, r8
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bne @no_thermal_handler
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lwz r16, EWA.CPUBase + CPU.ID(r28)
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stw r16, Notification.MsgWord1(r30)
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bl CauseNotification
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@no_thermal_handler
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_AssertAndRelease PSA.SchLock, scratch=r8
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bl SchRestoreStartingAtR14
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b IntReturn
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###### # #####
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# # #### # # # # # # # # # ##### ###### ##### # # ## ##### ###### # # #### # # ##### ###### # # #####
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# # # # # # # # ## # # # # # # # # ## # # # # # # # # ## # # # # # #
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#### # ###### # # # # # # # # # ##### # # # # # # # # ##### # # # # # # # ##### ## #
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# # # # # # # # # # ####### # # # ##### # # # ###### # # # # # # # # # # ## #
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# # # # # # # # # ## # # # # # # # # ## # # # # # # # # # ## # # # # #
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# # #### # # #### # # # # ###### # ###### # # # # # # # ###### ##### #### # # # ###### # # #
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; We can assume that this is being called from the emulator
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; We accept a logical NCB ptr but the kernel needs a physical one.
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; So we keep a four-entry cache in KDP, mapping logical NCB ptrs
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; to physical ones. But when are there multiple alt contexts?
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; ARG flags? r3, mask r4
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align kIntAlign
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kcRunAlternateContext
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mtcrf 0x3f, r7
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bcl BO_IF_NOT, EWA.kFlagBlue, IntReturn
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and. r8, r4, r13
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lwz r9, KDP.NCBCacheLA0(r1)
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rlwinm r8, r3, 0, 0, 25
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cmpw cr1, r8, r9
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bne IntReturn
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lwz r9, KDP.NCBCachePA0(r1)
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bne cr1, @search_cache
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@found_physical_in_cache ; can come here from below after a more thorough search
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addi r8, r1, KDP.VecBaseAlternate ; the only use of this vector table?
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mtsprg 3, r8
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lwz r8, KDP.LA_EmulatorKernelTrapTable(r1)
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mtcrf 0x3f, r7
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mfsprg r1, 0
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clrlwi r7, r7, 8
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stw r8, ContextBlock.LA_EmulatorKernelTrapTable(r9)
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stw r9, EWA.PA_ContextBlock(r1)
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b IntReturnToOtherBlueContext
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@search_cache
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lwz r9, KDP.NCBCacheLA1(r1)
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cmpw cr1, r8, r9
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beq cr1, @found_in_slot_1
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lwz r9, KDP.NCBCacheLA2(r1)
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cmpw cr1, r8, r9
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beq cr1, @found_in_slot_2
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lwz r9, KDP.NCBCacheLA3(r1)
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cmpw cr1, r8, r9
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beq cr1, @found_in_slot_3
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; No luck with the cache
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mfsprg r1, 0
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stmw r14, EWA.r14(r1)
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lwz r1, EWA.PA_KDP(r1)
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cmpw cr1, r8, r6
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beq cr1, @fail
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mr r27, r8
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addi r29, r1, KDP.BATs + 0xa0
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bl PagingL2PWithBATs
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clrlwi r23, r8, 20
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beq @fail
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cmplwi r23, 0x0d00
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mr r9, r8
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mr r8, r31
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ble @not_straddling_pages
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addi r27, r27, 0x1000
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addi r29, r1, KDP.BATs + 0xa0
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bl PagingL2PWithBATs
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beq @fail
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subi r31, r31, 0x1000
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xor r23, r8, r31
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rlwinm. r23, r23, 0, 25, 22
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bne @fail ; because physical pages are discontiguous
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@not_straddling_pages
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clrlwi r23, r31, 30
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cmpwi r23, 3
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rlwimi r8, r9, 0, 20, 31
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beq @fail
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; Found a non-cached physical address for this NCB!
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lwz r23, KDP.NanoKernelInfo + NKNanoKernelInfo.NCBPtrCacheMissCount(r1)
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addi r23, r23, 1
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stw r23, KDP.NanoKernelInfo + NKNanoKernelInfo.NCBPtrCacheMissCount(r1)
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; Stick it in cache slot 3
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mfsprg r1, 0
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lmw r14, EWA.r14(r1)
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lwz r1, EWA.PA_KDP(r1)
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stw r8, KDP.NCBCachePA3(r1)
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@found_in_slot_3 ; so promote to slot 2
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lwz r8, KDP.NCBCacheLA2(r1)
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stw r9, KDP.NCBCacheLA2(r1)
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stw r8, KDP.NCBCacheLA3(r1)
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lwz r9, KDP.NCBCachePA3(r1)
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lwz r8, KDP.NCBCachePA2(r1)
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stw r9, KDP.NCBCachePA2(r1)
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stw r8, KDP.NCBCachePA3(r1)
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lwz r9, KDP.NCBCacheLA2(r1)
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@found_in_slot_2 ; so promote to slot 1
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lwz r8, KDP.NCBCacheLA1(r1)
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stw r9, KDP.NCBCacheLA1(r1)
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stw r8, KDP.NCBCacheLA2(r1)
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lwz r9, KDP.NCBCachePA2(r1)
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lwz r8, KDP.NCBCachePA1(r1)
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stw r9, KDP.NCBCachePA1(r1)
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stw r8, KDP.NCBCachePA2(r1)
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lwz r9, KDP.NCBCacheLA1(r1)
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@found_in_slot_1 ; so promote to slot 0, save elsewhere, and push on
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lwz r8, KDP.NCBCacheLA0(r1)
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stw r9, KDP.NCBCacheLA0(r1)
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stw r9, KDP.LA_NCB(r1)
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stw r8, KDP.NCBCacheLA1(r1)
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lwz r9, KDP.NCBCachePA1(r1)
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lwz r8, KDP.NCBCachePA0(r1)
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stw r9, KDP.NCBCachePA0(r1)
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stw r8, KDP.NCBCachePA1(r1)
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b @found_physical_in_cache
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@fail
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mfsprg r1, 0
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lmw r14, EWA.r14(r1)
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lwz r1, EWA.PA_KDP(r1)
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li r8, ecTrapInstr
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b Exception
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; > r8 = dest
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; > r22 = len in bytes
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; > r23 = fillword
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wordfill ; OUTSIDE REFERER
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subic. r22, r22, 4
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stwx r23, r8, r22
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bne wordfill
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blr
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###### #####
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# # #### # # ###### #### ###### ##### # # # # #### ##### ###### # #
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# # # # # # # # # # # # # # # # ## ##
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#### # ###### ##### #### ##### # ##### # #### # ##### # ## #
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# # # # # # # # # # # # # # # #
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# # # # # # # # # # # # # # # # # # # #
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# # #### # # ###### #### ###### # ##### # #### # ###### # #
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; Handle a 68k reset trap.
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; If A0(r3)/A1(r4) == 'Gary'/$05051955, load the register list in A3? Or is this now disabled?
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; New SRR0 = SRR0 & ~r5(D0) | r7(D2)
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align kIntAlign
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kcResetSystem ; OUTSIDE REFERER
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; r6 = ewa
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bl SchSaveStartingAtR14
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; r8 = sprg0 (not used by me)
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; Check for 601 (rtc vs timebase)
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mfpvr r9
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rlwinm. r9, r9, 0, 0, 14
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; This xoris/cmplwi technique is very cool
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xoris r8, r3, 'Ga'
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beq @is_601
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mftb r9
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b @endif_601
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@is_601
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dialect POWER
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mfrtcl r9
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dialect PowerPC
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@endif_601
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; Not sure why this would need to hit cr0?
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andis. r9, r9, 0xffff
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cmplwi r8, 'ry'
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bne NonGaryReset
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; r4 (i.e. A1) == 5 May 1956?
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xoris r8, r4, 0x0505
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cmplwi r8, 0x1956
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bne NonGaryReset
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andc r11, r11, r5
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lwz r8, ContextBlock.r7(r6)
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or r11, r11, r8
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_log 'Skeleton key inserted at'
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mr r8, r11
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bl Printw
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mr r8, r10
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bl Printw
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_log '^n'
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b IntReturn
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; NonGaryReset
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; A 68k reset trap without Gary Davidian's magic numbers.
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NonGaryReset
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_log 'ResetSystem trap entered^n'
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lwz r8, KDP.OldKDP(r1)
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cmpwi r8, 0
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beq ResetBuiltinKernel
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_log 'Unplugging the replacement nanokernel^n'
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lwz r8, KDP.OldKDP(r1)
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mfsprg r1, 0
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addi r9, r8, KDP.VecBaseSystem
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mtsprg 0, r8 ; old NK has only one EWA!
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mtsprg 3, r9
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lwz r9, EWA.r1(r1)
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stw r9, EWA.r1(r8)
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lwz r9, EWA.r6(r1)
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stw r9, EWA.r6(r8)
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stw r6, 0x065c(r8)
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stw r7, 0x0660(r8) ; ??????????
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lwz r9, EWA.Enables(r1)
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stw r9, 0x0664(r8)
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; r6 = ewa
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bl SchRestoreStartingAtR14
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subi r10, r10, 4
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lwz r1, -0x0004(r1)
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; sprg0 = for r1 and r6
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; r1 = kdp
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; r6 = register restore area
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; r7 = flag to insert into XER
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; r10 = new srr0 (return location)
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; r11 = new srr1
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; r12 = lr restore
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; r13 = cr restore
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b SchExitInterrupt
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###### ###
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# # #### # # ##### # #### ##### # ##### # ###### ###### # # # ##### ###### ##### ##### # # ##### ##### ####
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# # # # # # # # # # # # # # # # # # # ## # # # # # # # # # # # # #
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#### # ###### # # # # # # # # # # # ##### # # # # # ##### # # # # # # # # # ####
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# # # # ##### # # # ##### # # # # # # # # # # # ##### ##### # # ##### # #
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# # # # # # # # # # # # # # # # # # # ## # # # # # # # # # # # #
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# # #### # # # # #### # # # # # ###### ###### ### # # # ###### # # # # #### # # ####
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; > r1 = kdp
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kcPrioritizeInterrupts ; OUTSIDE REFERER
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lwz r9, KDP.PA_InterruptHandler(r1)
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mtlr r9
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blr
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; Move registers from CB to EWA, and Thud.
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align kIntAlign
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kcThud
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stw r2, EWA.r2(r1)
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stw r3, EWA.r3(r1)
|
|
stw r4, EWA.r4(r1)
|
|
stw r5, EWA.r5(r1)
|
|
|
|
lwz r8, ContextBlock.r7(r6)
|
|
lwz r9, ContextBlock.r8(r6)
|
|
stw r8, EWA.r7(r1)
|
|
stw r9, EWA.r8(r1)
|
|
|
|
lwz r8, ContextBlock.r9(r6)
|
|
lwz r9, ContextBlock.r10(r6)
|
|
stw r8, EWA.r9(r1)
|
|
stw r9, EWA.r10(r1)
|
|
|
|
lwz r8, ContextBlock.r11(r6)
|
|
lwz r9, ContextBlock.r12(r6)
|
|
stw r8, EWA.r11(r1)
|
|
stw r9, EWA.r12(r1)
|
|
|
|
lwz r8, ContextBlock.r13(r6)
|
|
stw r8, EWA.r13(r1)
|
|
|
|
stmw r14, EWA.r14(r1)
|
|
|
|
bl IntPanicIsland
|
|
|
|
|
|
|
|
major_0x046d0 ; OUTSIDE REFERER
|
|
|
|
bl LoadInterruptRegisters
|
|
|
|
li r8, ecTrapInstr
|
|
b Exception
|
|
|
|
|
|
|
|
### ####### #
|
|
# # # ##### # # # ##### ###### ##### # # ## # # # # ##### ###### ##### # # ## ##### ######
|
|
# ## # # # # # # # # # ## # # # # # # # # # # # ## # # # # #
|
|
# # # # # ##### ## # ##### # # # # # # # # # # # # ##### # # # # # # # # #####
|
|
# # # # # # ## # # ##### # # # ###### # ####### # # # ##### # # # ###### # #
|
|
# # ## # # # # # # # # # ## # # # # # # # # # # # ## # # # #
|
|
### # # # ####### # # # ###### # # # # # # ###### # # ###### # ###### # # # # # # # ######
|
|
|
|
; For when the alternate context is running?
|
|
|
|
align kIntAlign
|
|
|
|
IntExternalAlternate
|
|
|
|
bl LoadInterruptRegisters
|
|
mtcrf 0x3f, r7
|
|
bcl BO_IF_NOT, EWA.kFlagBlue, IntPanicIsland
|
|
li r8, ecNoException
|
|
b Exception
|
|
|
|
|
|
|
|
### ######
|
|
# # # ##### # # ##### #### #### ##### ## # #
|
|
# ## # # # # # # # # # # # # # # ## ##
|
|
# # # # # ###### # # # # # # # # # # ## #
|
|
# # # # # # ##### # # # ### ##### ###### # #
|
|
# # ## # # # # # # # # # # # # # #
|
|
### # # # # # # #### #### # # # # # #
|
|
|
|
align kIntAlign
|
|
|
|
IntProgram
|
|
|
|
bl LoadInterruptRegisters
|
|
|
|
lwz r8, KDP.LA_EmulatorKernelTrapTable(r1)
|
|
mtcr r11 ; UNUSUAL to have SRR1 in condition register
|
|
xor r8, r10, r8
|
|
bc BO_IF_NOT, 14, @not_trap
|
|
|
|
|
|
; Program interrupt caused by a trap instruction
|
|
|
|
|
|
; From the table of twis in the emulator code image? Then return will be to LR.
|
|
|
|
cmplwi cr0, r8, NanoKernelCallTable.ReturnFromException
|
|
cmplwi cr1, r8, NanoKernelCallTable.MPDispatch
|
|
beq cr0, @emutrap_0_return_from_exception
|
|
beq cr1, @emutrap_8_mpdispatch
|
|
cmplwi cr0, r8, NanoKernelCallTable.VMDispatch
|
|
cmplwi cr1, r8, NanoKernelCallTable.Size
|
|
beq cr0, @emutrap_3_vmdispatch
|
|
blt cr1, @emutrap_other
|
|
|
|
|
|
; Not from the emulator image? Return will be to next instruction,
|
|
; and we will read the trap instruction from memory
|
|
|
|
; If !MSR[IR], turn on MSR[DR] for just a moment
|
|
bc BO_IF_NOT, 26, @_IntProgram_0x58
|
|
stw r14, ContextBlock.r14(r6)
|
|
mfsprg r14, 3
|
|
addi r8, r1, PSA.VecBasePIH
|
|
mfmsr r9
|
|
mtsprg 3, r8
|
|
_bset r8, r9, 27 ; turn on data paging (MSR[DR]) for just a sec
|
|
mtmsr r8
|
|
isync
|
|
@_IntProgram_0x58
|
|
|
|
; Get the offending instruction!
|
|
lwz r8, 0(r10)
|
|
|
|
; If !MSR[IR], restore MSR
|
|
bc BO_IF_NOT, 26, @_IntProgram_0x74
|
|
isync
|
|
mtmsr r9
|
|
isync
|
|
mtsprg 3, r14
|
|
lwz r14, ContextBlock.r14(r6)
|
|
@_IntProgram_0x74
|
|
|
|
|
|
; Switch from SRR1-in-CR to Flags-in-CR
|
|
|
|
mtcr r7
|
|
|
|
|
|
; Read the bottom half of the non-emu-image trap instruction, getting trapnum*8 in r8
|
|
xoris r8, r8, 0xfff
|
|
cmplwi cr0, r8, NanoKernelCallTable.Size / 4
|
|
cmplwi cr1, r8, NanoKernelCallTable.ReturnFromException / 4
|
|
bge cr0, @trap_too_high
|
|
cmplwi cr7, r8, NanoKernelCallTable.MPDispatch / 4
|
|
cmplwi cr0, r8, NanoKernelCallTable.VMDispatch / 4
|
|
slwi r8, r8, 2
|
|
beq cr1, @nonemu_return_from_exception
|
|
beq cr7, @nonemu_mpdispatch
|
|
beq cr0, @nonemu_vmdispatch
|
|
|
|
; Fall through to some hard truths
|
|
bc BO_IF, 16, @_IntProgram_0x150
|
|
bc BO_IF, 8, @_IntProgram_0xac
|
|
bc BO_IF_NOT, 9, @_IntProgram_0x150
|
|
|
|
@nonemu_return_from_exception
|
|
@nonemu_vmdispatch
|
|
@_IntProgram_0xac
|
|
add r8, r8, r1
|
|
lwz r9, KDP.NanoKernelInfo + NKNanoKernelInfo.NanoKernelCallCounts(r8)
|
|
addi r9, r9, 1
|
|
stw r9, KDP.NanoKernelInfo + NKNanoKernelInfo.NanoKernelCallCounts(r8)
|
|
|
|
@nonemu_go
|
|
lwz r8, KDP.NanoKernelCallTable(r8)
|
|
mtlr r8
|
|
addi r10, r10, 4
|
|
rlwimi r7, r7, 27, 26, 26 ; copy EWA.kFlagBE into EWA.kFlag26
|
|
blr
|
|
|
|
@nonemu_mpdispatch
|
|
lwz r9, ContextBlock.r0(r6)
|
|
add r8, r8, r1
|
|
cmpwi r9, -1
|
|
lwz r9, KDP.NanoKernelInfo + NKNanoKernelInfo.NanoKernelCallCounts(r8)
|
|
addi r9, r9, 1
|
|
stw r9, KDP.NanoKernelInfo + NKNanoKernelInfo.NanoKernelCallCounts(r8)
|
|
bne @nonemu_go
|
|
|
|
; Non-emu MPDispatch trap with r0 == -1: muck around a bit?
|
|
addi r10, r10, 4
|
|
rlwimi r7, r7, 27, 26, 26 ; copy EWA.kFlagBE into EWA.kFlag26
|
|
mfsprg r8, 0
|
|
rlwimi r13, r7, 8, 2, 2
|
|
lwz r9, EWA.PA_CurTask(r8)
|
|
xoris r13, r13, 0x2000
|
|
lwz r8, Task.SomeLabelField(r9)
|
|
stw r8, ContextBlock.r0(r6)
|
|
b IntReturn
|
|
|
|
|
|
@emutrap_other
|
|
@_IntProgram_0x110
|
|
mtcr r7
|
|
bc BO_IF, 16, @_IntProgram_0x150
|
|
bc BO_IF, 8, @_IntProgram_0x120
|
|
bc BO_IF_NOT, 9, @_IntProgram_0x150
|
|
|
|
@emutrap_0_return_from_exception
|
|
@emutrap_8_mpdispatch
|
|
@emutrap_3_vmdispatch
|
|
@_IntProgram_0x120
|
|
add r8, r8, r1
|
|
lwz r9, KDP.NanoKernelInfo + NKNanoKernelInfo.NanoKernelCallCounts(r8)
|
|
lwz r10, KDP.NanoKernelCallTable(r8)
|
|
addi r9, r9, 1
|
|
stw r9, KDP.NanoKernelInfo + NKNanoKernelInfo.NanoKernelCallCounts(r8)
|
|
mtlr r10
|
|
mr r10, r12 ; return to whatever the emulator left in the PPC link register
|
|
rlwimi r7, r7, 27, 26, 26
|
|
blr
|
|
|
|
|
|
; Program interrupt not caused by a trap instruction: consult SRR1 bits 11-13
|
|
|
|
@not_trap
|
|
bc BO_IF+1, 12, FDPEmulateInstruction ; illegal instruction exception
|
|
bc BO_IF, 13, FDPEmulateInstruction ; privileged instruction exception
|
|
bc BO_IF, 11, @floating_point_exception ; floating point exception
|
|
|
|
@trap_too_high
|
|
@_IntProgram_0x150
|
|
rlwinm r8, r11, 17, 28, 29 ; whoa
|
|
addi r8, r8, 0x4b3
|
|
rlwnm r8, r8, r8, 28, 31
|
|
b Exception
|
|
|
|
@floating_point_exception
|
|
li r8, ecFloatException
|
|
|
|
bc BO_IF, 15, Exception ; if SRR0 points to subsequent instr
|
|
addi r10, r10, 4 ; if SRR0 points to offending instr
|
|
rlwimi r7, r7, 27, 26, 26 ; copy EWA.kFlagBE into EWA.kFlag26
|
|
b Exception
|
|
|
|
|
|
|
|
align kIntAlign
|
|
|
|
IntExternalSystem
|
|
|
|
bl LoadInterruptRegisters
|
|
|
|
|
|
; Sanity check
|
|
|
|
rlwinm. r9, r11, 0, MSR_EEbit, MSR_EEbit
|
|
beq MaskedInterruptTaken
|
|
|
|
|
|
; How many CPUs?
|
|
|
|
lwz r9, EWA.CPUBase + CPU.LLL + LLL.Freeform(r8)
|
|
lwz r9, CoherenceGroup.CpuCount(r9)
|
|
cmpwi r9, 2
|
|
|
|
|
|
; Uniprocessor machine: go straight to PIH
|
|
|
|
blt kcPrioritizeInterrupts
|
|
|
|
|
|
; Check with the CPU plugin whether this is an interprocessor interrupt
|
|
; (i.e. an alert to flag a scheduler evaluation)
|
|
|
|
bl SchSaveStartingAtR14
|
|
|
|
li r9, kSIGP9
|
|
stw r9, EWA.SIGPSelector(r8)
|
|
li r8, 1 ; args are in EWA
|
|
bl SIGP
|
|
bl SchRestoreStartingAtR14
|
|
|
|
cmpwi cr0, r8, -29278 ; real external interrupt
|
|
cmpwi cr1, r8, -29277 ; ignore
|
|
cmpwi cr2, r8, -29279 ; interprocessor interrupt!
|
|
; else: real external interrupt
|
|
|
|
beq cr0, kcPrioritizeInterrupts
|
|
beq cr1, IntReturn
|
|
bne cr2, kcPrioritizeInterrupts
|
|
|
|
mfsprg r9, 0 ; "alert" => run scheduler evaluation
|
|
li r8, 1
|
|
stb r8, EWA.SchEvalFlag(r9)
|
|
b IntReturn ; goes to SchReturn
|
|
|
|
|
|
|
|
##### ### ##### ######
|
|
# # # # # # #
|
|
# # # # #
|
|
##### # # #### ######
|
|
# # # # #
|
|
# # # # # #
|
|
##### ### ##### #
|
|
|
|
; "SIGnal Plugin": Call the CPU plugin PEF bundle synchronously.
|
|
; (blue address space but in supervisor mode without interrupts)
|
|
|
|
; ARG:
|
|
|
|
; if r8 == 0, i.e. userspace MPCpuPlugin call:
|
|
; r3 => routine selector
|
|
; executing CPU index => r3
|
|
; r4-10 => r4-10
|
|
|
|
; if r8 != 0, i.e. internal NanoKernel call:
|
|
; EWA.SIGPSelector => routine selector
|
|
; executing CPU index => r3
|
|
; PlugCallR4-10 => r4-10
|
|
|
|
; For most NK SIGPs, r4 contains the index of the CPU being operated on
|
|
|
|
align 5
|
|
|
|
SIGP
|
|
|
|
mfsprg r23, 0
|
|
mtcr r7
|
|
|
|
; r20 = offset into CPU plugin dispatch table = routine number * 4
|
|
;
|
|
lwz r16, EWA.PA_CurAddressSpace(r23)
|
|
slwi r20, r3, 2
|
|
stw r16, EWA.SIGPSpacOnResume(r23)
|
|
bc BO_IF, EWA.kFlagSIGP, IntReturnFromSIGP ; not sure about this
|
|
cmpwi cr2, r8, 0
|
|
lwz r18, EWA.SIGPSelector(r23)
|
|
beq cr2, @args_in_registers
|
|
slwi r20, r18, 2
|
|
@args_in_registers
|
|
|
|
; Check that a CPU plugin is installed and that the
|
|
; plugin dispatch table includes this command number.
|
|
lwz r22, EWA.CPUBase + CPU.LLL + LLL.Freeform(r23)
|
|
li r8, -0x7266
|
|
lwz r17, CoherenceGroup.PA_CpuPluginDesc(r22)
|
|
lwz r16, CoherenceGroup.CpuPluginSelectorCount(r22)
|
|
mr. r17, r17
|
|
beqlr
|
|
slwi r16, r16, 2
|
|
li r8, -0x7267
|
|
cmplw r20, r16
|
|
bgelr
|
|
|
|
; Save some registers in advance of this unusual "upcall".
|
|
stw r10, EWA.SIGPSavedR10(r23)
|
|
stw r11, EWA.SIGPSavedR11(r23)
|
|
stw r12, EWA.SIGPSavedR12(r23)
|
|
stw r13, EWA.SIGPSavedR13(r23)
|
|
mfxer r16
|
|
mfctr r17
|
|
stw r16, EWA.SIGPSavedXER(r23)
|
|
mflr r16
|
|
stw r17, EWA.SIGPSavedCTR(r23)
|
|
stw r16, EWA.SIGPSavedLR(r23) ; obviously this is getting revisited somewhere
|
|
stw r6, EWA.SIGPSavedR6(r23)
|
|
stw r7, EWA.SIGPSavedR7(r23)
|
|
|
|
; Change to the CPU plugin's preferred address space.
|
|
lwz r9, EWA.PA_CurAddressSpace(r23)
|
|
lwz r8, CoherenceGroup.CpuPluginSpacePtr(r22)
|
|
cmpw r9, r8
|
|
beq @noNeedToSwitchSpace
|
|
bl SchSwitchSpace
|
|
@noNeedToSwitchSpace
|
|
|
|
; Save user registers to ContextBlock (odd way to do this).
|
|
lwz r16, EWA.r1(r23)
|
|
lwz r17, EWA.r6(r23)
|
|
stw r16, ContextBlock.r1(r6)
|
|
stw r2, ContextBlock.r2(r6)
|
|
stw r3, ContextBlock.r3(r6)
|
|
stw r4, ContextBlock.r4(r6)
|
|
stw r5, ContextBlock.r5(r6)
|
|
stw r17, ContextBlock.r6(r6)
|
|
|
|
; Return address for CPU plugin code (=> twi 31, r31, 0 => kcReturnFromException)
|
|
lwz r17, KDP.LA_EmulatorKernelTrapTable + NanoKernelCallTable.ReturnFromException(r1)
|
|
|
|
; Need CPU index to look up the CPU plugin stack pointer in a table
|
|
lhz r16, EWA.CPUIndex(r23)
|
|
|
|
; MSR for CPU plugin with EE (external ints) and PR (problem state) switched off
|
|
lwz r19, PSA.UserModeMSR(r1)
|
|
slwi r16, r16, 2
|
|
rlwinm r19, r19, 0, 18, 15
|
|
|
|
; SRR0 (=> program counter) = TOC[routine_idx][first long]
|
|
; r1 (stack ptr) = stackPtrs[cpu_idx]
|
|
; r2 (RTOC) = TOC[routine_idx][second long]
|
|
lwz r8, CoherenceGroup.PA_CpuPluginTOC(r22)
|
|
lwz r9, CoherenceGroup.PA_CpuPluginStackPtrs(r22)
|
|
lwzx r20, r8, r20
|
|
lwz r18, 0(r20)
|
|
mtlr r17
|
|
mtspr srr0, r18
|
|
mtspr srr1, r19
|
|
lwzx r1, r9, r16
|
|
lwz r2, 4(r20)
|
|
|
|
; r3 (first arg) = CPU index
|
|
srwi r3, r16, 2
|
|
|
|
; Flags |= 0x8000
|
|
_bset r7, r7, EWA.kFlagSIGP
|
|
mr r16, r6
|
|
stw r7, EWA.Flags(r23)
|
|
|
|
; Not sure where this ContextBlock comes from?
|
|
addi r6, r23, -0x318
|
|
stw r6, EWA.PA_ContextBlock(r23)
|
|
|
|
beq cr2, @args_in_registers_2
|
|
|
|
;args not in registers
|
|
lwz r4, EWA.SIGPCallR4(r23)
|
|
lwz r5, EWA.SIGPCallR5(r23)
|
|
lwz r6, EWA.SIGPCallR6(r23)
|
|
lwz r7, EWA.SIGPCallR7(r23)
|
|
lwz r8, EWA.SIGPCallR8(r23)
|
|
lwz r9, EWA.SIGPCallR9(r23)
|
|
lwz r10, EWA.SIGPCallR10(r23)
|
|
|
|
; Go.
|
|
rfi
|
|
|
|
@args_in_registers_2
|
|
lwz r6, ContextBlock.r6(r16)
|
|
lwz r7, ContextBlock.r7(r16)
|
|
lwz r8, ContextBlock.r8(r16)
|
|
lwz r9, ContextBlock.r9(r16)
|
|
lwz r10, ContextBlock.r10(r16)
|
|
|
|
; Go.
|
|
rfi
|
|
|
|
|
|
|
|
major_0x04a20
|
|
|
|
mfsprg r23, 0
|
|
lwz r6, -0x0014(r23)
|
|
lwz r7, -0x0010(r23)
|
|
lwz r1, -0x0004(r23)
|
|
mfspr r10, srr0
|
|
mfspr r11, srr1
|
|
|
|
|
|
|
|
IntReturnFromSIGP
|
|
|
|
mfsprg r23, 0
|
|
lwz r7, EWA.SIGPSavedR7(r23)
|
|
andis. r8, r11, 0x0002 ; MSR bit 14??
|
|
stw r7, -0x0010(r23)
|
|
bne @msr_14_set
|
|
li r3, -29285
|
|
@msr_14_set
|
|
|
|
; Restore address space
|
|
lwz r8, EWA.SIGPSpacOnResume(r23)
|
|
lwz r9, EWA.PA_CurAddressSpace(r23)
|
|
cmpw r9, r8
|
|
beq @no_switch_space
|
|
bl SchSwitchSpace
|
|
@no_switch_space
|
|
|
|
lwz r10, EWA.SIGPSavedR10(r23)
|
|
lwz r11, EWA.SIGPSavedR11(r23)
|
|
lwz r12, EWA.SIGPSavedR12(r23)
|
|
lwz r13, EWA.SIGPSavedR13(r23)
|
|
lwz r8, EWA.SIGPSavedXER(r23)
|
|
lwz r9, EWA.SIGPSavedCTR(r23)
|
|
mtxer r8
|
|
lwz r8, EWA.SIGPSavedLR(r23)
|
|
lwz r6, EWA.SIGPSavedR6(r23)
|
|
mtctr r9
|
|
stw r6, EWA.PA_ContextBlock(r23)
|
|
mtlr r8
|
|
mr r8, r3
|
|
mr r9, r4
|
|
lwz r16, ContextBlock.r1(r6)
|
|
lwz r2, ContextBlock.r2(r6)
|
|
lwz r3, ContextBlock.r3(r6)
|
|
lwz r4, ContextBlock.r4(r6)
|
|
lwz r5, ContextBlock.r5(r6)
|
|
lwz r17, ContextBlock.r6(r6)
|
|
stw r16, EWA.r1(r23)
|
|
stw r17, EWA.r6(r23)
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blr
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### #####
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# # # ##### # # # # #### #### ## # #
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# ## # # # # # # # # # # # #
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# # # # # ##### # #### # # # # #
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# # # # # # # # # ###### # #
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# # ## # # # # # # # # # # # #
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### # # # ##### # #### #### # # ###### ######
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; IntSyscall
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; Not fully sure about this one
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IntSyscall ; OUTSIDE REFERER
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; Only r1 and LR have been saved, so these compares clobber cr0
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cmpwi r0, -3
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bne @not_minus_3
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; sc -3: used by FDP to go back to supervisor mode after instruction emulation.
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; For security reasons, FDP goes into user mode when it emulates loads and stores.
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; This is how it goes back into supervisor mode afterwards. During instruction emulation
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; it has data paging on, but keeps instruction paging off. User Mode code never has instruction
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; paging disabled, so this is not a privilege escalation.
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; unset MSR_PR bit
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mfspr r1, srr1
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rlwinm. r0, r1, 26, 26, 27 ;move MSR_IR bit to sign bit (and a few others that don't matter)
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_bclr r1, r1, 17
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blt @not_in_FDP ; only do if MSR_IR = 0 (MSR_IR is sign bit, so it is < 0 if it is true)
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mtspr srr1, r1
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@not_in_FDP
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; restore LR from SPRG2, r1 from SPRG1
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mfsprg r1, 2
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mtlr r1
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mfsprg r1, 1
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rfi
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@not_minus_3
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cmpwi r0, -1
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mfsprg r1, 0
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bne @not_minus_1
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; sc -1: quick-test whether "this task" is blue (cr0.eq if not blue)
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lwz r0, EWA.Flags(r1)
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mfsprg r1, 2
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rlwinm. r0, r0, 0, EWA.kFlagBlue, EWA.kFlagBlue
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mtlr r1
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mfsprg r1, 1
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rfi
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@not_minus_1
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cmpwi r0, -2
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bne @not_any_special
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; sc -2: more flag nonsense?
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lwz r0, EWA.Flags(r1)
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lwz r1, -0x0008(r1)
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rlwinm. r0, r0, 0, 10, 10
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lwz r0, 0x00ec(r1)
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mfsprg r1, 2
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mtlr r1
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mfsprg r1, 1
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rfi
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@not_any_special
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; Positive numbered syscalls are a fast path to MPDispatch (twi 31, r31, 8)
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bl LoadInterruptRegisters ; Save the usual suspects and get comfy
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lwz r9, KDP.NanoKernelInfo + NKNanoKernelInfo.NanoKernelCallCounts + 32(r1)
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addi r9, r9, 1
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stw r9, KDP.NanoKernelInfo + NKNanoKernelInfo.NanoKernelCallCounts + 8*4(r1)
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; Not sure what to make of these
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_bset r11, r11, 14
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rlwimi r7, r7, 27, 26, 26
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b kcMPDispatch
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### #######
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# # # ##### # ##### ## #### ######
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# ## # # # # # # # # # #
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# # # # # # # # # # # #####
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# # # # # # ##### ###### # #
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# # ## # # # # # # # # #
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### # # # # # # # # #### ######
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align kIntAlign
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IntTrace ; OUTSIDE REFERER
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bl LoadInterruptRegisters
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li r8, ecInstTrace
|
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b Exception
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### ##### ###
|
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# #### # # #### ##### ###### # # #### ###### ##### # # ## ##### ###### # # # #####
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|
# # # ## # # # # # # # # # # # # # # # # # # # ## # #
|
|
# # # # # # # # # ##### ##### # # ##### # # # # # # # ##### # # # # #
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|
# # ### # # # # # ##### # # # # # # # ## # ###### ##### # # # # # #
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|
# # # # ## # # # # # # # # # # # ## ## # # # # # # # ## #
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### #### # # #### # # ###### ##### #### # # # # # # # # ###### ### # # #
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|
align kIntAlign
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|
|
IgnoreSoftwareInt ; OUTSIDE REFERER
|
|
mfspr r1, srr0
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|
addi r1, r1, 0x04
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|
mtspr srr0, r1
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|
mfsprg r1, 2
|
|
mtlr r1
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|
mfsprg r1, 1
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|
rfi
|
|
dcb.b 32, 0
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# # ###### # # ###
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# # ## # # ##### # ###### # # ###### ##### ###### ## ## #### # # # ##### #### ##### # # # #####
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# # # # ## # # # # # # # # # # # # # # # # # ## # # # # # # # # ## # #
|
|
####### # # # # # # # # ##### ###### ##### # # ##### # # # # # # # # # # # # # # # # # # #
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# # ###### # # # # # # # # # ##### # # # # # # # # # # # # ##### # # # # #
|
|
# # # # # ## # # # # # # # # # # # # # # ## # # # # # # # # ## #
|
|
# # # # # # ##### ###### ###### # ###### # # # # # #### # # # # #### # # ### # # #
|
|
|
|
align kIntAlign
|
|
|
|
HandlePerfMonitorInt ; OUTSIDE REFERER
|
|
mfspr r1, srr1
|
|
oris r1, r1, 0x200
|
|
mtspr srr1, r1
|
|
mfsprg r1, 2
|
|
mtlr r1
|
|
mfsprg r1, 1
|
|
rfi
|
|
dcb.b 32, 0
|