mirror of
https://github.com/elliotnunn/powermac-rom.git
synced 2024-06-09 07:29:36 +00:00
441 lines
21 KiB
ArmAsm
441 lines
21 KiB
ArmAsm
;_______________________________________________________________________
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; Configuration Info Record
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; Used to pass Configuration information from the Boot Program to the
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; NanoKernel for data structure and address mapping initialization.
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;_______________________________________________________________________
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NKConfigurationInfo record 0,increment
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ROMByteCheckSums ds.l 8 ; 000 ; ROM Checksums - one word for each of 8 byte lanes
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ROMCheckSum64 ds.l 2 ; 020 ; ROM Checksum - 64 bit sum of doublewords
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ROMImageBaseOffset ds.l 1 ; 028 ; Offset of Base of total ROM image
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ROMImageSize ds.l 1 ; 02c ; Number of bytes in ROM image
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ROMImageVersion ds.l 1 ; 030 ; ROM Version number for entire ROM
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Mac68KROMOffset ds.l 1 ; 034 ; Offset of base of Macintosh 68K ROM
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Mac68KROMSize ds.l 1 ; 038 ; Number of bytes in Macintosh 68K ROM
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ExceptionTableOffset ds.l 1 ; 03c ; Offset of base of PowerPC Exception Table Code
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ExceptionTableSize ds.l 1 ; 040 ; Number of bytes in PowerPC Exception Table Code
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HWInitCodeOffset ds.l 1 ; 044 ; Offset of base of Hardware Init Code (field moved!)
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HWInitCodeSize ds.l 1 ; 048 ; Number of bytes in Hardware Init Code
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KernelCodeOffset ds.l 1 ; 04c ; Offset of base of NanoKernel Code
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KernelCodeSize ds.l 1 ; 050 ; Number of bytes in NanoKernel Code
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EmulatorCodeOffset ds.l 1 ; 054 ; Offset of base of Emulator Code
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EmulatorCodeSize ds.l 1 ; 058 ; Number of bytes in Emulator Code
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OpcodeTableOffset ds.l 1 ; 05c ; Offset of base of Opcode Table
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OpcodeTableSize ds.l 1 ; 060 ; Number of bytes in Opcode Table
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BootstrapVersion ds.b 16 ; 064 ; Bootstrap loader version info
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BootVersionOffset ds.l 1 ; 074 ; offset within EmulatorData of BootstrapVersion
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ECBOffset ds.l 1 ; 078 ; offset within EmulatorData of ECB
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IplValueOffset ds.l 1 ; 07c ; offset within EmulatorData of IplValue
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EmulatorEntryOffset ds.l 1 ; 080 ; offset within Emulator Code of entry point
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KernelTrapTableOffset ds.l 1 ; 084 ; offset within Emulator Code of KernelTrapTable
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TestIntMaskInit ds.l 1 ; 088 ; initial value for test interrupt mask
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ClearIntMaskInit ds.l 1 ; 08c ; initial value for clear interrupt mask
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PostIntMaskInit ds.l 1 ; 090 ; initial value for post interrupt mask
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LA_InterruptCtl ds.l 1 ; 094 ; logical address of Interrupt Control I/O page
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InterruptHandlerKind ds.b 1 ; 098 ; kind of handler to use
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ds.b 3 ; 099 ; filler
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LA_InfoRecord ds.l 1 ; 09c ; logical address of InfoRecord page
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LA_KernelData ds.l 1 ; 0a0 ; logical address of KernelData page
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LA_EmulatorData ds.l 1 ; 0a4 ; logical address of EmulatorData page
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LA_DispatchTable ds.l 1 ; 0a8 ; logical address of Dispatch Table
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LA_EmulatorCode ds.l 1 ; 0ac ; logical address of Emulator Code
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MacLowMemInitOffset ds.l 1 ; 0b0 ; offset to list of LowMem addr/data values
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PageAttributeInit ds.l 1 ; 0b4 ; default WIMG/PP settings for PTE creation
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PageMapInitSize ds.l 1 ; 0b8 ; size of page mapping info
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PageMapInitOffset ds.l 1 ; 0bc ; offset to page mapping info (from base of ConfigInfo)
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PageMapIRPOffset ds.l 1 ; 0c0 ; offset of InfoRecord map info (from base of PageMap)
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PageMapKDPOffset ds.l 1 ; 0c4 ; offset of KernelData map info (from base of PageMap)
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PageMapEDPOffset ds.l 1 ; 0c8 ; offset of EmulatorData map info (from base of PageMap)
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SegMaps
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SegMap32SupInit ds.l 32 ; 0cc ; 32 bit mode Segment Map Supervisor space
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SegMap32UsrInit ds.l 32 ; 14c ; 32 bit mode Segment Map User space
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SegMap32CPUInit ds.l 32 ; 1cc ; 32 bit mode Segment Map CPU space
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SegMap32OvlInit ds.l 32 ; 24c ; 32 bit mode Segment Map Overlay mode
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BATRangeInit ds.l 32 ; 2cc ; BAT mapping ranges
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BatMap32SupInit ds.l 1 ; 34c ; 32 bit mode BAT Map Supervisor space
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BatMap32UsrInit ds.l 1 ; 350 ; 32 bit mode BAT Map User space
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BatMap32CPUInit ds.l 1 ; 354 ; 32 bit mode BAT Map CPU space
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BatMap32OvlInit ds.l 1 ; 358 ; 32 bit mode BAT Map Overlay mode
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SharedMemoryAddr ds.l 1 ; 35c ; physical address of Mac/Smurf shared message mem
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PA_RelocatedLowMemInit ds.l 1 ; 360 ; physical address of RelocatedLowMem
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OpenFWBundleOffset ds.l 1 ; 364 ; Offset of base of OpenFirmware PEF Bundle
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OpenFWBundleSize ds.l 1 ; 368 ; Number of bytes in OpenFirmware PEF Bundle
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LA_OpenFirmware ds.l 1 ; 36c ; logical address of Open Firmware
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PA_OpenFirmware ds.l 1 ; 370 ; physical address of Open Firmware
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LA_HardwarePriv ds.l 1 ; 374 ; logical address of HardwarePriv callback
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align 5 ; pad to nice cache block alignment
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endr
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;_______________________________________________________________________
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; System Info Record
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;
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; Used to pass System information from the NanoKernel to user mode
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; software.
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;_______________________________________________________________________
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NKSystemInfoPtr equ $5FFFEFF0 ; logical address of NKSystemInfo record
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NKSystemInfoVer equ $5FFFEFF4 ; version number of NKSystemInfo record
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NKSystemInfoLen equ $5FFFEFF6 ; length of NKSystemInfo record
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NKSystemInfo record 0,increment
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PhysicalMemorySize ds.l 1 ; 000 ; Number of bytes in Physical RAM
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UsableMemorySize ds.l 1 ; 004 ; Number of bytes in Usable RAM
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LogicalMemorySize ds.l 1 ; 008 ; Number of bytes in Logical RAM
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HashTableSize ds.l 1 ; 00c ; Number of bytes in Memory Hash Table
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L2DataCacheTotalSize ds.l 1 ; 010 ; number of bytes in the L2 Data Cache
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L2InstCacheTotalSize ds.l 1 ; 014 ; number of bytes in the L2 Instruction Cache
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L2CombinedCaches ds.w 1 ; 018 ; 1 <- combined or no cache, 0 <- split cache
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L2InstCacheBlockSize ds.w 1 ; 01a ; number of bytes in a Block of the L2 Instruction Cache
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L2DataCacheBlockSize ds.w 1 ; 01c ; number of bytes in a Block of the L2 Data Cache
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L2InstCacheAssociativity ds.w 1 ; 01e ; Associativity of the L2 Instruction Cache
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L2DataCacheAssociativity ds.w 1 ; 020 ; Associativity of the L2 Data Cache
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ds.b 2 ; 022 ; unused
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ds.b 2 ; 024 ; unused
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FlashManufacturerCode ds.b 1 ; 026 ; Flash ROM Manufacturer code
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FlashDeviceCode ds.b 1 ; 027 ; Flash ROM Device code
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FlashStart ds.l 1 ; 028 ; Starting address of Flash ROM
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FlashSize ds.l 1 ; 02c ; Number of bytes in Flash ROM
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Bank0Start ds.l 1 ; 030 ; Starting address of RAM bank 0
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Bank0Size ds.l 1 ; 034 ; Number of bytes in RAM bank 0
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Bank1Start ds.l 1 ; 038 ; Starting address of RAM bank 1
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Bank1Size ds.l 1 ; 03c ; Number of bytes in RAM bank 1
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Bank2Start ds.l 1 ; 040 ; Starting address of RAM bank 2
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Bank2Size ds.l 1 ; 044 ; Number of bytes in RAM bank 2
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Bank3Start ds.l 1 ; 048 ; Starting address of RAM bank 3
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Bank3Size ds.l 1 ; 04c ; Number of bytes in RAM bank 3
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Bank4Start ds.l 1 ; 050 ; Starting address of RAM bank 4
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Bank4Size ds.l 1 ; 054 ; Number of bytes in RAM bank 4
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Bank5Start ds.l 1 ; 058 ; Starting address of RAM bank 5
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Bank5Size ds.l 1 ; 05c ; Number of bytes in RAM bank 5
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Bank6Start ds.l 1 ; 060 ; Starting address of RAM bank 6
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Bank6Size ds.l 1 ; 064 ; Number of bytes in RAM bank 6
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Bank7Start ds.l 1 ; 068 ; Starting address of RAM bank 7
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Bank7Size ds.l 1 ; 06c ; Number of bytes in RAM bank 7
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Bank8Start ds.l 1 ; 070 ; Starting address of RAM bank 8
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Bank8Size ds.l 1 ; 074 ; Number of bytes in RAM bank 8
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Bank9Start ds.l 1 ; 078 ; Starting address of RAM bank 9
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Bank9Size ds.l 1 ; 07c ; Number of bytes in RAM bank 9
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Bank10Start ds.l 1 ; 080 ; Starting address of RAM bank 10
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Bank10Size ds.l 1 ; 084 ; Number of bytes in RAM bank 10
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Bank11Start ds.l 1 ; 088 ; Starting address of RAM bank 11
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Bank11Size ds.l 1 ; 08c ; Number of bytes in RAM bank 11
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Bank12Start ds.l 1 ; 090 ; Starting address of RAM bank 12
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Bank12Size ds.l 1 ; 094 ; Number of bytes in RAM bank 12
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Bank13Start ds.l 1 ; 098 ; Starting address of RAM bank 13
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Bank13Size ds.l 1 ; 09c ; Number of bytes in RAM bank 13
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Bank14Start ds.l 1 ; 0a0 ; Starting address of RAM bank 14
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Bank14Size ds.l 1 ; 0a4 ; Number of bytes in RAM bank 14
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Bank15Start ds.l 1 ; 0a8 ; Starting address of RAM bank 15
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Bank15Size ds.l 1 ; 0ac ; Number of bytes in RAM bank 15
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align 32 ; pad to nice cache block alignment
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MaxBanks equ 16 ; 16 banks, 0...15
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Size equ *
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endr
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;_______________________________________________________________________
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; Diagnostic Info Record
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;
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; Used to pass Diagnostic information from the power on Diagnostics to
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; the NanoKernel, and from the NanoKernel to user mode software.
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;_______________________________________________________________________
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NKDiagInfoPtr equ $5FFFEFE8 ; logical address of DiagnosticInfo record
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NKDiagInfoVer equ $5FFFEFEC ; version number of DiagnosticInfo record
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NKDiagInfoLen equ $5FFFEFEE ; length of DiagnosticInfo record
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NKDiagInfo record 0,increment
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BankMBFailOffset ds.l 1 ; 000 ; Mother Board RAM failure code
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BankAFailOffset ds.l 1 ; 004 ; Bank A RAM failure code
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BankBFailOffset ds.l 1 ; 008 ; Bank B RAM failure code
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BankCFailOffset ds.l 1 ; 00c ; Bank C RAM failure code
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BankDFailOffset ds.l 1 ; 010 ; Bank D RAM failure code
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BankEFailOffset ds.l 1 ; 014 ; Bank E RAM failure code
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BankFFailOffset ds.l 1 ; 018 ; Bank F RAM failure code
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BankGFailOffset ds.l 1 ; 01c ; Bank G RAM failure code
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BankHFailOffset ds.l 1 ; 020 ; Bank H RAM failure code
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CacheFailOffset ds.l 1 ; 024 ; cache failure code
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LongBootParamOffset ds.l 1 ; 028 ; on longBoot this is where the params will be
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POSTTraceOffset ds.l 1 ; 02c ; this tells us what route the POST took
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POSTOldWarmOffset ds.l 1 ; 030 ; logged address of old warmstart flag
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POSTOldLongOffset ds.l 1 ; 034 ; logged address of old long boot flag
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POSTOldGlobbOffset ds.l 1 ; 038 ; logged address of old Diagnostic Info Record
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POSTOldParamOffset ds.l 1 ; 03c ; the params from the old diag globb
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POSTStartRTCUOffset ds.l 1 ; 040 ; PPC Real Time Clock Upper at start of POST
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POSTStartRTCLOffset ds.l 1 ; 044 ; PPC Real Time Clock Lower at start of POST
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POSTEndRTCUOffset ds.l 1 ; 048 ; PPC Real Time Clock Upper at end of POST
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POSTEndRTCLOffset ds.l 1 ; 04c ; PPC Real Time Clock Lower at end of POST
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POSTTestTypeOffset ds.l 1 ; 050 ; when long RAM tests fail test type which failed is put here
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POSTError2Offset ds.l 1 ; 054 ; result codes from tests
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POSTError3Offset ds.l 1 ; 058 ; result codes from tests
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POSTError4Offset ds.l 1 ; 05c ; result codes from tests
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RegistersStore ds.b 140 ; 060 ; store all 60x registers here, still fit into 256 bytes size.
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; Everything BEFORE here is new (hence the funny-sized register store)
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DiagPOSTResult2 ds.l 1 ; 0ec ; POST results
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DiagPOSTResult1 ds.l 1 ; 0f0 ; POST results
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DiagLongBootSig ds.l 1 ; 0f4 ; Burn in restart flag
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DiagWarmStartHigh ds.l 1 ; 0f8 ; First long of native warm start (WLSC) <SM44>
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DiagWarmStartLow ds.l 1 ; 0fc ; Second long of native warm start (SamB) <SM44>
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align 5 ; pad to nice cache block alignment
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Size equ *
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endr
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;_______________________________________________________________________
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; NanoKernel Info Record
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;
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; Used to pass NanoKernel statistics from the NanoKernel to user mode
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; software.
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;_______________________________________________________________________
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NKNanoKernelInfoPtr equ $5FFFEFE0 ; logical address of NanoKernelInfo record
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NKNanoKernelInfoVer equ $5FFFEFE4 ; version number of NanoKernelInfo record
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NKNanoKernelInfoLen equ $5FFFEFE6 ; length of NanoKernelInfo record
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NKNanoKernelInfo record 0,increment
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ExceptionCauseCounts ds.l 32 ; 000 ; counters per exception cause
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NanoKernelCallCounts ds.l 16 ; 080 ; counters per NanoKernel call
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ExternalIntCount ds.l 1 ; 0c0 ; count of External Interrupts
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MisalignmentCount ds.l 1 ; 0c4 ; count of Misalignment Interrupts
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FPUReloadCount ds.l 1 ; 0c8 ; count of FPU reloads on demand
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DecrementerIntCount ds.l 1 ; 0cc ; count of Decrementer Interrupts
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QuietWriteCount ds.l 1 ; 0d0 ; count of Writes to Quiet Read-Only memory
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HashTableCreateCount ds.l 1 ; 0d4 ; count of Hash Table Entry creations
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HashTableDeleteCount ds.l 1 ; 0d8 ; count of Hash Table Entry deletions
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HashTableOverflowCount ds.l 1 ; 0dc ; count of Hash Table Entry overflows
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EmulatedUnimpInstCount ds.l 1 ; 0e0 ; count of Emulated unimplemented instructions
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NCBPtrCacheMissCount ds.l 1 ; 0e4 ; count of NCB Pointer cache misses
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ExceptionPropagateCount ds.l 1 ; 0e8 ; count of Exceptions propagated to system
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ExceptionForcedCount ds.l 1 ; 0ec ; count of Exceptions forced to system
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SysContextCpuTime ds.l 2 ; 0f0 ; CPU Time used by System Context
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AltContextCpuTime ds.l 2 ; 0f8 ; CPU Time used by Alternate Context
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Size equ *
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endr
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;_______________________________________________________________________
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; Processor Info Record
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;
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; Used to pass Processor information from the NanoKernel to user mode
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; software.
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;_______________________________________________________________________
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NKProcessorInfoPtr equ $5FFFEFD8 ; logical address of ProcessorInfo record
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NKProcessorInfoVer equ $5FFFEFDC ; version number of ProcessorInfo record
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NKProcessorInfoLen equ $5FFFEFDE ; length of ProcessorInfo record
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NKProcessorInfo record 0,increment
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ProcessorVersionReg ds.l 1 ; 000 ; contents of the PVR special purpose register
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CpuClockRateHz ds.l 1 ; 004 ; CPU Clock frequency
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BusClockRateHz ds.l 1 ; 008 ; Bus Clock frequency
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DecClockRateHz ds.l 1 ; 00c ; Decrementer Clock frequency
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PageSize ds.l 1 ; 010 ; number of bytes in a memory page
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DataCacheTotalSize ds.l 1 ; 014 ; number of bytes in the Data Cache
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InstCacheTotalSize ds.l 1 ; 018 ; number of bytes in the Instruction Cache
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CoherencyBlockSize ds.w 1 ; 01c ; number of bytes in a Coherency Block
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ReservationGranuleSize ds.w 1 ; 01e ; number of bytes in a Reservation Granule
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CombinedCaches ds.w 1 ; 020 ; 1 <- combined or no cache, 0 <- split cache
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InstCacheLineSize ds.w 1 ; 022 ; number of bytes in a Line of the Instruction Cache
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DataCacheLineSize ds.w 1 ; 024 ; number of bytes in a Line of the Data Cache
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DataCacheBlockSizeTouch ds.w 1 ; 026 ; number of bytes in a Block for DCBT DCBTST
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InstCacheBlockSize ds.w 1 ; 028 ; number of bytes in a Block of the Instruction Cache
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DataCacheBlockSize ds.w 1 ; 02a ; number of bytes in a Block of the Data Cache
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InstCacheAssociativity ds.w 1 ; 02c ; Associativity of the Instruction Cache
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DataCacheAssociativity ds.w 1 ; 02e ; Associativity of the Data Cache
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TransCacheTotalSize ds.w 1 ; 030 ; number of entries in the Translation Cache
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TransCacheAssociativity ds.w 1 ; 032 ; Associativity of the Translation Cache
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align 5 ; pad to nice cache block alignment
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Size equ *
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endr
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;_______________________________________________________________________
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; Hardware Info Record
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;
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; Used to pass hardware information from the NanoKernel to user mode
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; software.
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;_______________________________________________________________________
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NKHWInfoPtr equ $5FFFEFD0 ; logical address of HWInfo record
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NKHWInfoVer equ $5FFFEFD4 ; version number of HWInfo record
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NKHWInfoLen equ $5FFFEFD6 ; length of HWInfo record
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NKHWInfo record 0,increment
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MacROM_Base ds.l 1 ; 000 ; base address (physical) of Mac ROM
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DeviceTreeBase ds.l 1 ; 004 ; base address of the copied device tree properties
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UniversalInfoTableBase ds.l 1 ; 008 ; base address of the Universal Info Table
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ConfigInfoTableBase ds.l 1 ; 00c ; base address of the Config Info Table
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VectorLookupTable ds.l 1 ; 010 ; base address of the interrupt vector lookup table (short *)
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VectorMaskTable ds.l 1 ; 014 ; base address of the interrupt vector mask table (long *)
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OpenPICBaseAddr ds.l 1 ; 018 ; OpenPIC base address
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ISAMaster8259 ds.l 1 ; 01c ; ISA Master 8259 ports (char *)
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ISASlave8259 ds.l 1 ; 020 ; ISA Slave 8259 ports (char *)
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InterruptAck8259 ds.l 1 ; 024 ; address to read to ack 8259 interrupt (long *)
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; interrupt pending bits (actively changing)
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PendingInts ds.l 2 ; 028 ; 64 bits of pending interrupts
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; some Mac I/O device base addresses
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ADB_Base ds.l 1 ; 030 ; base address of ADB
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SCSI_DMA_Base ds.l 1 ; 034 ; base address of SCSI DMA registers
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; RTAS related stuff
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RTAS_PrivDataArea ds.l 1 ; 038 ; RTAS private data area
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MacOS_NVRAM_Offset ds.l 1 ; 03c ; offset into nvram to MacOS data
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RTAS_NVRAM_Fetch ds.l 1 ; 040 ; token for RTAS NVRAM fetch
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RTAS_NVRAM_Store ds.l 1 ; 044 ; token for RTAS NVRAM store
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RTAS_Get_Clock ds.l 1 ; 048 ; token for RTAS clock get
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RTAS_Set_Clock ds.l 1 ; 04c ; token for RTAS clock set
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RTAS_Restart ds.l 1 ; 050 ; token for RTAS Restart
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RTAS_Shutdown ds.l 1 ; 054 ; token for RTAS Shutdown
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RTAS_Restart_At ds.l 1 ; 058 ; token for RTAS system startup at specified time
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RTAS_EventScan ds.l 1 ; 05c ; token for RTAS event scan
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RTAS_Check_Exception ds.l 1 ; 060 ; token for RTAS check exception
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RTAS_Read_PCI_Config ds.l 1 ; 064 ; token for RTAS read PCI config
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RTAS_Write_PCI_Config ds.l 1 ; 068 ; token for RTAS write PCI config
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; SIO interrupt source numbers for the MPIC
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SIOIntVect ds.w 1 ; 06c ; SIO (8259 cascade vector) vector number
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SIOIntBit ds.w 1 ; 06e ; SIO (8259 cascade vector) bit number
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Signature ds.l 1 ; 070 ; signature for this record ('Hnfo')
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; more interrupt source numbers
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SpuriousIntVect ds.w 1 ; 074 ; spurious vector number
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CPU_ID ds.w 1 ; 076 ; the ID of this CPU (universal-tables-related)
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SCCAIntVect ds.w 1 ; 078 ; SCC A (non-DMA) vector number
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SCCBIntVect ds.w 1 ; 07a ; SCC B (non-DMA) vector number
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SCSIIntVect ds.w 1 ; 07c ; SCSI vector number
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SCSIDMAIntVect ds.w 1 ; 07e ; SCSI DMA vector number
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VIAIntVect ds.w 1 ; 080 ; VIA vector number
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VIAIntBit ds.w 1 ; 082 ; VIA bit number
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ADBIntVect ds.w 1 ; 084 ; vector number
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NMIIntVect ds.w 1 ; 086 ; NMI vector number
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NMIIntBit ds.w 1 ; 088 ; NMI bit number
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; current (actively changing) interrupt handling variables
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ISAPendingInt ds.w 1 ; 08a ; currently pending ISA/8259 interrupt
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CompletedInts ds.b 8 ; 08c ; completed interrupts
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nkHWInfoFlagSlowMESH equ 1 ; set if fast MESH doesn't work on this box
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nkHWInfoFlagAsynchMESH equ 2 ; set if Synchronous MESH doesn't work on this box
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nkHWInfoFlagNoCopySWTLB equ 4 ; set if the software TLB walk code for 603 should NOT be copied
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HardwareInfoFlags ds.l 1 ; 094 ; 32 bits of flags (see enum above)
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RTAS_Get_PowerOn_Time ds.l 1 ; 098 ; token for RTAS getting time for system startup
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align 5 ; pad to nice cache block alignment
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Size equ *
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endr
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;_______________________________________________________________________
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; Processor State Record
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;
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; Used to save the state of the processor across sleep.
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;_______________________________________________________________________
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NKProcessorStatePtr equ $5FFFEFC8 ; logical address of ProcessorState record
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NKProcessorStateVer equ $5FFFEFCC ; version number of ProcessorState record
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NKProcessorStateLen equ $5FFFEFCE ; length of ProcessorState record
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NKProcessorState record 0,increment
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saveDBAT0u ds.l 1 ; 000 ; place to store DBAT0U
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saveDBAT0l ds.l 1 ; 004 ; place to store DBAT0L
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saveDBAT1u ds.l 1 ; 008 ; place to store DBAT1U
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saveDBAT1l ds.l 1 ; 00c ; place to store DBAT1L
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saveDBAT2u ds.l 1 ; 010 ; place to store DBAT2U
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saveDBAT2l ds.l 1 ; 014 ; place to store DBAT2L
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saveDBAT3u ds.l 1 ; 018 ; place to store DBAT3U
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saveDBAT3l ds.l 1 ; 01c ; place to store DBAT3L
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saveIBAT0u ds.l 1 ; 020 ; place to store IBAT0U
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saveIBAT0l ds.l 1 ; 024 ; place to store IBAT0L
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saveIBAT1u ds.l 1 ; 028 ; place to store IBAT1U
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saveIBAT1l ds.l 1 ; 02c ; place to store IBAT1L
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saveIBAT2u ds.l 1 ; 030 ; place to store IBAT2U
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saveIBAT2l ds.l 1 ; 034 ; place to store IBAT2L
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saveIBAT3u ds.l 1 ; 038 ; place to store IBAT3U
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saveIBAT3l ds.l 1 ; 03c ; place to store IBAT3L
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saveSPRG0 ds.l 1 ; 040 ; place to store SPRG0
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saveSPRG1 ds.l 1 ; 044 ; place to store SPRG1
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saveSPRG2 ds.l 1 ; 048 ; place to store SPRG2
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saveSPRG3 ds.l 1 ; 04c ; place to store SPRG3
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saveL2CR ds.l 1 ; 050 ; place to store Arthur's L2CR
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saveSRR0 ds.l 1 ; 054 ; place to store SRR0
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saveSRR1 ds.l 1 ; 058 ; place to store SRR1
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saveTBU ds.l 1 ; 05c ; place to store TBU
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saveTBL ds.l 1 ; 060 ; place to store TBL
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saveHID0 ds.l 1 ; 064 ; place to store HID0
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saveDEC ds.l 1 ; 068 ; place to store DEC
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saveMSR ds.l 1 ; 06c ; place to store MSR
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saveSDR1 ds.l 1 ; 070 ; place to store SDR1
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; saveKernelDataPtr needs to always be right after saveReturnAddr
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; because of how the code works. DO NOT CHANGE THIS ORDERING!
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saveReturnAddr ds.l 1 ; 074 ; place to store the addr to jump to.
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saveKernelDataPtr ds.l 1 ; 078 ; place to store the KernelDataPtr
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saveContextPtr ds.l 1 ; 07c ; place to store the ContextPtr
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Size equ *
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endr
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