mirror of
https://github.com/elliotnunn/supermario.git
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275 lines
9.6 KiB
Plaintext
275 lines
9.6 KiB
Plaintext
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;
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; File: PSCEqu.a
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;
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; Contains: Equates for accessing the Peripheral Subsystem Controller (PSC)
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;
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; Written by: Mark A. Law
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;
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; Copyright: © 1992-1993 by Apple Computer, Inc. All rights reserved.
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;
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; Change History (most recent first):
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;
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; <SM7> 6/14/93 kc Roll in Ludwig.
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; <LW5> 4/13/93 chp Cleaned up, reorganized, and generally munged to a greater
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; degree than necessary. Unused fields of PSC_INT_TBL have been
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; removed since the changes in <P5> were only to support the
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; (defunct) DMA Manager.
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; <LW4> 3/16/93 chp Remove the definition of the PSCIntTbl lomem which has been
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; superseded by an equivalent field in ExpandMem.
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; <LW3> 2/24/93 chp Updated UTSC offsets to reflect the correct values for the final
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; PSC silicon and added a generic equate to the beginning of the
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; 64-bit register.
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; <LW2> 1/23/93 mal Added DSP Level 2 interrupt handler & parm placeholders to PSC
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; interrupt table.
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; <SM6> 11/19/92 mal Changed some MACE Enet DMA channel equs.
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; <SM5> 8/13/92 chp Added equates for SCCATX DMA channel number 6 (PSC2).
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; <SM4> 6/21/92 ejb Adding equate L5 ("Level 5") for the RTDrvr.
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; <SM3> 6/21/92 ejb Add equate DSPTOHOST as an alias for the equate DSP (PSC Lvl5
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; irq 0). The latter's name conflicts with RTDrvr equates.
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; <SM2> 5/24/92 RB Changed the DMA flush bit name to avoid a conflict with the
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; Sound Manager equates. From FLUSH to DMAFLUSH.
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; <P7> 4/2/92 mal Added ifdef to ensure we only included once per asm.
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; <P6> 4/2/92 mal Updated PSCIntTbl to real lowmem location.
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; <P5> 2/28/92 chp Modified structure of PSCIntTbl and changed “IRE” references to
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; “IER” (interrupt enable register) for consistency with
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; documentation and other parts of the source.
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; <P4> 2/21/92 mal Removed sound equates.
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; <P3> 2/14/92 mal Removed use of PSCBase, all registers defined as offsets.
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; <P2> 1/24/92 mal Added temporary PSCIntTbl lowmem global.
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;
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IF &TYPE('__IncludingPSCEqu__') = 'UNDEFINED' THEN
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__IncludingPSCEqu__ SET 1
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; PSC Interrupt Register and Interrupt Enable Register offsets
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; level 2 registers - see HardwarePrivateEqu.a
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; level 3 register offsets
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L3IR EQU $130 ; Level 3 Interrupt Register
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L3IER EQU $134 ; Level 3 Interrupt Enable Register
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; level 3 bit offsets, both irq's and enable's
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MACE EQU 0
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L3B7 EQU 7 ; "or" of all irq's, "sense" bit for enables
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; level 4 register offsets
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L4IR EQU $140 ; Level 4 Interrupt Register
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L4IER EQU $144 ; Level 4 Interrupt Enable Register
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; level 4 bit offsets, both irq's and enable's
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SNDSTAT EQU 0
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L4SCCA EQU 1
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L4SCCB EQU 2
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DMA EQU 3
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L4B7 EQU 7 ; "or" of all irq's, "sense" bit for enables
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; level 5 register offsets
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L5 EQU 5 ; Level 5 interrupt
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L5IR EQU $150 ; Level 5 Interrupt Register
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L5IER EQU $154 ; Level 5 Interrupt Enable Register
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; level 5 bit offsets, both irq's and enable's
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DSP EQU 0
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DSPTOHOST EQU 0
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FRMOVRN EQU 1
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L5B7 EQU 7 ; "or" of all irq's, "sense" bit for enables
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; level 6 register offsets
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L6IR EQU $160 ; Level 6 Interrupt Register
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L6IER EQU $164 ; Level 6 Interrupt Enable Register
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; level 6 bit offsets, both irq's and enable's
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L660HZ EQU 0
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L6SCCA EQU 1
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L6SCCB EQU 2
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L6B7 EQU 7 ; "or" of all irq's, "sense" bit for enables
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; Universal Time Stamp Counter Register offsets
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UTSC EQU $300
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LSUTSC EQU $300 ; least significant lword
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MSUTSC EQU $304 ; most significant lword
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PSCTEST EQU $400
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PSC_BERRIE EQU $800 ; Bus Error Interrupt Enable (byte)
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BERRIE EQU 0 ; Bus Error Interrupt Enable bit offset
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PSC_ISR EQU $804 ; Interrupt Status Register (long)
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; PSC DMA Control Register offsets
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SCSI_CNTL EQU $C00 ; Channel 0 control register (word)
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PSC_MACE_RECV_CNTL EQU $C10 ; Channel 1 control register
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PSC_MACE_XMIT_CNTL EQU $C20 ; Channel 2 control register
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FDC_CNTL EQU $C30 ; Channel 3 control register
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SCCA_CNTL EQU $C40 ; Channel 4 control register
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SCCB_CNTL EQU $C50 ; Channel 5 control register
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SCCATX_CNTL EQU $C60 ; Channel 6 control register
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; PSC DMA Set Register offsets
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PSC_DMA_CHNL RECORD 0 ; PSC DMA Channel record for use
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Addr
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Addr0 DS.L 1 ; with Channel base equ's below,
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Cnt
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Cnt0 DS.L 1 ; SCSI_CHNL, MACE_RECV_CHNL, etc.
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CmdStat
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CmdStat0 DS.W 1
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ORG *+6
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Addr1 DS.L 1 ; 32 bits
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Cnt1 DS.L 1 ; 32 bits
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CmdStat1 DS.W 1 ; 16 bits
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ORG *+6
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ENDR
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SCSI EQU $1000 ; Channel 0 base
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SCSI_ADDR0 EQU $1000 ; Register Set 0 address register
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SCSI_CNT0 EQU $1004 ; Register Set 0 count register
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SCSI_CMDSTAT0 EQU $1008 ; Register Set 0 command/status register
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SCSI_ADDR1 EQU $1010 ; Register Set 1 address register
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SCSI_CNT1 EQU $1014 ; Register Set 1 count register
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SCSI_CMDSTAT1 EQU $1018 ; Register Set 1 command/status register
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PSC_MACE_RECV EQU $1020 ; Channel 1 base
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MACE_RECV_ADDR0 EQU $1020 ; Register Set 0 address register
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MACE_RECV_CNT0 EQU $1024 ; Register Set 0 count register
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MACE_RECV_CMDSTAT0 EQU $1028 ; Register Set 0 command/status register
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MACE_RECV_ADDR1 EQU $1030 ; Register Set 1 address register
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MACE_RECV_CNT1 EQU $1034 ; Register Set 1 count register
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MACE_RECV_CMDSTAT1 EQU $1038 ; Register Set 1 command/status register
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PSC_MACE_XMIT EQU $1040 ; Channel 2 base
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MACE_XMIT_ADDR0 EQU $1040 ; Register Set 0 address register
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MACE_XMIT_CNT0 EQU $1044 ; Register Set 0 count register
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MACE_XMIT_CMDSTAT0 EQU $1048 ; Register Set 0 command/status register
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MACE_XMIT_ADDR1 EQU $1050 ; Register Set 1 address register
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MACE_XMIT_CNT1 EQU $1054 ; Register Set 1 count register
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MACE_XMIT_CMDSTAT1 EQU $1058 ; Register Set 1 command/status register
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FDC EQU $1060 ; Channel 3 base
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FDC_ADDR0 EQU $1060 ; Register Set 0 address register
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FDC_CNT0 EQU $1064 ; Register Set 0 count register
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FDC_CMDSTAT0 EQU $1068 ; Register Set 0 command/status register
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FDC_ADDR1 EQU $1070 ; Register Set 1 address register
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FDC_CNT1 EQU $1074 ; Register Set 1 count register
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FDC_CMDSTAT1 EQU $1078 ; Register Set 1 command/status register
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SCCA EQU $1080 ; Channel 4 base
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SCCA_ADDR0 EQU $1080 ; Register Set 0 address register
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SCCA_CNT0 EQU $1084 ; Register Set 0 count register
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SCCA_CMDSTAT0 EQU $1088 ; Register Set 0 command/status register
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SCCA_ADDR1 EQU $1090 ; Register Set 1 address register
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SCCA_CNT1 EQU $1094 ; Register Set 1 count register
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SCCA_CMDSTAT1 EQU $1098 ; Register Set 1 command/status register
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SCCB EQU $10A0 ; Channel 5 base
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SCCB_ADDR0 EQU $10A0 ; Register Set 0 address register
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SCCB_CNT0 EQU $10A4 ; Register Set 0 count register
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SCCB_CMDSTAT0 EQU $10A8 ; Register Set 0 command/status register
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SCCB_ADDR1 EQU $10B0 ; Register Set 1 address register
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SCCB_CNT1 EQU $10B4 ; Register Set 1 count register
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SCCB_CMDSTAT1 EQU $10B8 ; Register Set 1 command/status register
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SCCATX EQU $10C0 ; Channel 6 base
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SCCATX_ADDR0 EQU $10C0 ; Register Set 0 address register
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SCCATX_CNT0 EQU $10C4 ; Register Set 0 count register
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SCCATX_CMDSTAT0 EQU $10C8 ; Register Set 0 command/status register
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SCCATX_ADDR1 EQU $10D0 ; Register Set 1 address register
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SCCATX_CNT1 EQU $10D4 ; Register Set 1 count register
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SCCATX_CMDSTAT1 EQU $10D8 ; Register Set 1 command/status register
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; PSC DMA Channel Register Bits
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; DMA Channel Command/Status Register bit offsets
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IF EQU 8
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DIR EQU 9
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TERMCNT EQU 10
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ENABLED EQU 11
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IE EQU 12
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; DMA Channel Control Register bit offsets
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CIRQ EQU 8
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DMAFLUSH EQU 9
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PAUSE EQU 10
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SWRESET EQU 11
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CIE EQU 12
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BERR EQU 13
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FROZEN EQU 14
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SENSE EQU 15
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; PSC Interrupt Handler Table Template (see InterruptHandlers.a)
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;
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; This table contains address, parm entries for the real handlers for
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; interrupt levels 3, 4, 5, and 6. Individual drivers are responsible
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; for installing themselves and an optional parameter into the table.
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;
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; An interrupt handler is dispatched with its parameter in A1.
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;
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; During Cyclone development, the PSCIntTbl lomem ($1FC0) pointed to this table.
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; Now the pointer is in ExpandMem (emDMADispGlobs).
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PSC_INT_TBL record 0,increment
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; device interrupt handlers - levels 3-6
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;
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MACEhndlr ds.l 1 ; MACE int. handler
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MACEparm ds.l 1
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SNDSTAThndlr ds.l 1 ; Level 4 SNDSTAT int. handler
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SNDSTATparm ds.l 1
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L4SCCAhndlr ds.l 1 ; Level 4 SCCA int. handler
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L4SCCAparm ds.l 1
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L4SCCBhndlr ds.l 1 ; Level 4 SCCB int. handler
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L4SCCBparm ds.l 1
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DSPhndlr ds.l 1 ; Level 5 DSP int. handler
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DSPparm ds.l 1
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FRMOVRNhndlr ds.l 1 ; Level 5 FRMOVRN int. handler
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FRMOVRNparm ds.l 1
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L660HZhndlr ds.l 1 ; Level 6 60 Hz int. handler
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L660HZparm ds.l 1
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L6SCCAhndlr ds.l 1 ; Level 6 SCCA int. handler
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L6SCCAparm ds.l 1 ; (On Mac OS, SCC ints at Level 4)
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L6SCCBhndlr ds.l 1 ; Level 6 SCCB int. handler
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L6SCCBparm ds.l 1 ; (On Mac OS, SCC ints at Level 4)
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; DMA interrupt handlers - level 4
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;
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DMA_hndlrs EQU *
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SCSIhndlr ds.l 1 ; SCSI DMA int. handler
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SCSIparm ds.l 1
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MACE_RECVhndlr ds.l 1 ; Mace Receive DMA int. handler
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MACE_RECVparm ds.l 1
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MACE_XMIThndlr ds.l 1 ; Mace Transmit Done DMA int. handler
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MACE_XMITparm ds.l 1
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FDChndlr ds.l 1 ; FDC DMA int. handler
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FDCparm ds.l 1
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SCCAhndlr ds.l 1 ; SCCA DMA int. handler
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SCCAparm ds.l 1
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SCCBhndlr ds.l 1 ; SCCB DMA int. handler
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SCCBparm ds.l 1
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SCCATXhndlr ds.l 1 ; SCCATX DMA int. handler
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SCCATXparm ds.l 1
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; For Sound compatibility with older systems, the Level 5 DSP Interrupt handler
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; installs a “deferred” handler/parm here. PSCServiceInt will run this handler
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; if one exists and it’s about to RTE to level 0 or 1.
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;
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DSPL2hndlr ds.l 1 ; ptr to head of queue
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DSPL2parm ds.l 1 ; ptr to tail of queue
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PSC_INT_TBL_SZ equ *
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endr
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ENDIF ; including __IncludingPSCEqu__
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