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390 lines
12 KiB
C
390 lines
12 KiB
C
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*
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* File: FPSP.h
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*
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* Contains: General include file for symbols/definitions needed by the FP Emulation Package
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*
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* Originally Written by: Motorola Inc.
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* Adapted to Apple/MPW: Jon Okada
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*
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* Copyright: © 1990, 1991 by Apple Computer, Inc., all rights reserved.
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*
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* This file is used in these builds: Mac32
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*
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* Change History (most recent first):
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*
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* <2> 3/30/91 BG Rolled in latest changes from Jon Okada.
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* <1> 12/14/90 BG First checked into TERROR/BBS.
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*
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; fpsp.h
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; Based upon Motorola file 'fpsp.h'.
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; CHANGE LOG:
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; 01/03/91 JPO Added addresses for vectors to user exception handlers
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; for BSUN, UNDERFLOW, OPERR, OVERFLOW, and SNAN
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; floating-point exceptions and address for vector to
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; system FLINE exception handler.
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; 03/04/91 JPO Added offset "CMDREG2B" to equates.
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;
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*
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* fpsp.h 3.1 3.1
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*
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* Copyright (C) Motorola, Inc. 1990
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* All Rights Reserved
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*
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* THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
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* The copyright notice above does not evidence any
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* actual or intended publication of such source code.
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* fpsp.h --- stack frame offsets during FPSP exception handling
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*
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* These equates are used to access the exception frame, the fsave
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* frame and any local variables needed by the FPSP package.
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*
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* All FPSP handlers begin by executing:
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*
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* link a6,#-LOCAL_SIZE
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* fsave -(a7)
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* movem.l d0-d1/a0-a1,USER_DA(a6)
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* fmovem.x fp0-fp3,USER_FP0(a6)
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* fmove.l fpsr/fpcr/fpiar,USER_FPSR(a6)
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*
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* After initialization, the stack looks like this:
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*
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* A7 ---> +-------------------------------+
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* | |
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* | FPU fsave area |
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* | |
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* +-------------------------------+
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* | |
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* | FPSP Local Variables |
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* | including |
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* | saved registers |
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* | |
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* +-------------------------------+
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* A6 ---> | Saved A6 |
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* +-------------------------------+
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* | |
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* | Exception Frame |
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* | |
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* | |
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*
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* Positive offsets from A6 refer to the exception frame. Negative
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* offsets refer to the Local Variable area and the fsave area.
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* The fsave frame is also accessible 'from the top' via A7.
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*
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* On exit, the handlers execute:
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*
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* movem.l USER_DA(a6),d0-d1/a0-a1
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* fmovem.x USER_FP0(a6),fp0-fp3
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* fmove.l USER_FPSR(a6),fpsr/fpcr/fpiar
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* frestore (a7)+
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* unlk a6
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*
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* and then either 'bra fpsp_done' if the exception was completely
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* handled by the package, or 'bra real_xxxx' which is an external
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* label to a routine that will process a real exception of the
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* type that was generated. Some handlers may omit the 'frestore'
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* if the FPU state after the exception is idle.
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*
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* Sometimes the exception handler will transform the fsave area
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* because it needs to report an exception back to the user. This
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* can happen if the package is entered for an unimplemented float
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* instruction that generates (say) an underflow. Alternatively,
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* a second fsave frame can be pushed onto the stack and the
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* handler exit code will reload the new frame and discard the old.
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*
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* The registers d0, d1, a0, a1 and fp0-fp3 are always saved and
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* restored from the 'local variable' area and can be used as
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* temporaries. If a routine needs to change any
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* of these registers, it should modify the saved copy and let
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* the handler exit code restore the value.
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*
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*----------------------------------------------------------------------
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*
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* Local Variables on the stack
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*
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LOCAL_SIZE equ 192 ;bytes needed for local variables
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LV equ -LOCAL_SIZE ;convenient base value
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*
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USER_DA equ LV+0 ;save space for D0-D1,A0-A1
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USER_D0 equ LV+0 ;saved user D0
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USER_D1 equ LV+4 ;saved user D1
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USER_A0 equ LV+8 ;saved user A0
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USER_A1 equ LV+12 ;saved user A1
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USER_FP0 equ LV+16 ;saved user FP0
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USER_FP1 equ LV+28 ;saved user FP1
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USER_FP2 equ LV+40 ;saved user FP2
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USER_FP3 equ LV+52 ;saved user FP3
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USER_FPCR equ LV+64 ;saved user FPCR
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FPCR_ENABLE equ USER_FPCR+2 ; FPCR exception enable
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FPCR_MODE equ USER_FPCR+3 ; FPCR rounding mode control
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USER_FPSR equ LV+68 ;saved user FPSR
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FPSR_CC equ USER_FPSR+0 ; FPSR condition code
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FPSR_QBYTE equ USER_FPSR+1 ; FPSR quotient
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FPSR_EXCEPT equ USER_FPSR+2 ; FPSR exception
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FPSR_AEXCEPT equ USER_FPSR+3 ; FPSR accrued exception
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USER_FPIAR equ LV+72 ;saved user FPIAR
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FP_SCR1 equ LV+76 ;room for a temporary float value
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FP_SCR2 equ LV+92 ;room for a temporary float value
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L_SCR1 equ LV+108 ;room for a temporary long value
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L_SCR2 equ LV+112 ;room for a temporary long value
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STORE_FLG equ LV+116
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BINDEC_FLG equ LV+117 ;used in bindec
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DNRM_FLG equ LV+118 ;used in res_func
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RES_FLG equ LV+119 ;used in res_func
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DY_MO_FLG equ LV+120 ;dyadic/monadic flag
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UFLG_TMP equ LV+121 ;temporary for uflag errata
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CU_ONLY equ LV+122 ;cu-only flag
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VER_TMP equ LV+123 ;temp holding for version number
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L_SCR3 equ LV+124 ;room for a temporary long value
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FP_SCR3 equ LV+128 ;room for a temporary float value
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FP_SCR4 equ LV+144 ;room for a temporary float value
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FP_SCR5 equ LV+160 ;room for a temporary float value
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FP_SCR6 equ LV+176
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*
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*NEXT equ LV+192 ;need to increase LOCAL_SIZE
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*
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*--------------------------------------------------------------------------
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*
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* fsave offsets and bit definitions
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*
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* Offsets are defined from the end of an fsave because the last 10
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* words of a busy frame are the same as the unimplemented frame.
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*
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CU_SAVEPC equ LV-92 ;micro-pc for CU (1 byte)
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FPR_DIRTY_BITS equ LV-91 ;fpr dirty bits
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*
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WBTEMP equ LV-76 ;write back temp (12 bytes)
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WBTEMP_EX equ WBTEMP ;wbtemp sign and exponent (2 bytes)
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WBTEMP_HI equ WBTEMP+4 ;wbtemp mantissa [63:32] (4 bytes)
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WBTEMP_LO equ WBTEMP+8 ;wbtemp mantissa [31:00] (4 bytes)
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*
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WBTEMP_SGN equ WBTEMP+2 ;used to store sign
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*
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FPSR_SHADOW equ LV-64 ;fpsr shadow reg
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*
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FPIARCU equ LV-60 ;Instr. addr. reg. for CU (4 bytes)
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*
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CMDREG2B equ LV-52 ;cmd reg for machine 2 <3/4/91, JPO>
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*
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CMDREG3B equ LV-48 ;cmd reg for E3 exceptions (2 bytes)
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*
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NMNEXC equ LV-44 ;NMNEXC (unsup,snan bits only)
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nmn_unsup_bit equ 1
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nmn_snan_bit equ 0
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*
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NMCEXC equ LV-43 ;NMNEXC & NMCEXC
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nmn_operr_bit equ 7
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nmn_ovfl_bit equ 6
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nmn_unfl_bit equ 5
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nmc_unsup_bit equ 4
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nmc_snan_bit equ 3
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nmc_operr_bit equ 2
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nmc_ovfl_bit equ 1
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nmc_unfl_bit equ 0
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*
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STAG equ LV-40 ;source tag (1 byte)
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WBTEMP_GRS equ LV-40 ;alias wbtemp guard, round, sticky
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stag_mask equ $E0 ;upper 3 bits are source tag type
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denorm_bit equ 7 ;bit determins if denorm or unnorm
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etemp15_bit equ 4 ;etemp exponent bit #15
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wbtemp66_bit equ 2 ;wbtemp mantissa bit #66
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wbtemp1_bit equ 1 ;wbtemp mantissa bit #1
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wbtemp0_bit equ 0 ;wbtemp mantissa bit #0
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*
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STICKY equ LV-39 ;holds sticky bit
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sticky_bit equ 7
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*
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CMDREG1B equ LV-36 ;cmd reg for E1 exceptions (2 bytes)
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kfact_bit equ 12 ;distinguishes static/dynamic k-factor
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* ;on packed move out's. NOTE: this
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* ;equate only works when CMDREG1B is in
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* ;a register.
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*
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CMDWORD equ LV-35 ;command word in cmd1b
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direction_bit equ 5 ;bit 0 in opclass
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size_bit2 equ 12 ;bit 2 in size field
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*
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DTAG equ LV-32 ;dest tag (1 byte)
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dtag_mask equ $E0 ;upper 3 bits are dest type tag
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fptemp15_bit equ 4 ;fptemp exponent bit #15
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*
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WB_BYTE equ LV-31 ;holds WBTE15 bit (1 byte)
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wbtemp15_bit equ 4 ;wbtemp exponent bit #15
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*
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E_BYTE equ LV-28 ;holds E1 and E3 bits (1 byte)
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E1 equ 2 ;which bit is E1 flag
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E3 equ 1 ;which bit is E3 flag
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SFLAG equ 0 ;which bit is S flag
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*
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T_BYTE equ LV-27 ;holds T and U bits (1 byte)
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XFLAG equ 7 ;which bit is X flag
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UFLAG equ 5 ;which bit is U flag
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TFLAG equ 4 ;which bit is T flag
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*
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FPTEMP equ LV-24 ;fptemp (12 bytes)
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FPTEMP_EX equ FPTEMP ;fptemp sign and exponent (2 bytes)
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FPTEMP_HI equ FPTEMP+4 ;fptemp mantissa [63:32] (4 bytes)
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FPTEMP_LO equ FPTEMP+8 ;fptemp mantissa [31:00] (4 bytes)
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*
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FPTEMP_SGN equ FPTEMP+2 ;used to store sign
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*
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ETEMP equ LV-12 ;etemp (12 bytes)
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ETEMP_EX equ ETEMP ;etemp sign and exponent (2 bytes)
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ETEMP_HI equ ETEMP+4 ;etemp mantissa [63:32] (4 bytes)
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ETEMP_LO equ ETEMP+8 ;etemp mantissa [31:00] (4 bytes)
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*
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ETEMP_SGN equ ETEMP+2 ;used to store sign
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*
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EXC_SR equ 4 ;exception frame status register
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EXC_PC equ 6 ;exception frame program counter
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EXC_VEC equ 10 ;exception frame vector (format+vector#)
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EXC_EA equ 12 ;exception frame effective address
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*
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*--------------------------------------------------------------------------
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*
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* FPSR/FPCR bits
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*
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neg_bit equ 3 ; negative result
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z_bit equ 2 ; zero result
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inf_bit equ 1 ; infinity result
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nan_bit equ 0 ; not-a-number result
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*
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q_sn_bit equ 7 ; sign bit of quotient byte
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*
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bsun_bit equ 7 ; branch on unordered
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snan_bit equ 6 ; signalling nan
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operr_bit equ 5 ; operand error
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ovfl_bit equ 4 ; overflow
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unfl_bit equ 3 ; underflow
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dz_bit equ 2 ; divide by zero
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inex2_bit equ 1 ; inexact result 2
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inex1_bit equ 0 ; inexact result 1
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*
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aiop_bit equ 7 ; accrued illegal operation
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aovfl_bit equ 6 ; accrued overflow
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aunfl_bit equ 5 ; accrued underflow
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adz_bit equ 4 ; accrued divide by zero
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ainex_bit equ 3 ; accrued inexact
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*
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* FPSR individual bit masks
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*
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neg_mask equ $08000000
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z_mask equ $04000000
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inf_mask equ $02000000
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nan_mask equ $01000000
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*
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bsun_mask equ $00008000
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snan_mask equ $00004000
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operr_mask equ $00002000
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ovfl_mask equ $00001000
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unfl_mask equ $00000800
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dz_mask equ $00000400
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inex2_mask equ $00000200
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inex1_mask equ $00000100
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*
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aiop_mask equ $00000080 ; accrued illegal operation
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aovfl_mask equ $00000040 ; accrued overflow
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aunfl_mask equ $00000020 ; accrued underflow
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adz_mask equ $00000010 ; accrued divide by zero
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ainex_mask equ $00000008 ; accrued inexact
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*
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* FPSR combinations used in the FPSP
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*
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dzinf_mask equ inf_mask+dz_mask+adz_mask
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opnan_mask equ nan_mask+operr_mask+aiop_mask
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nzi_mask equ $01ffffff ; clears N, Z, and I
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unfinx_mask equ unfl_mask+inex2_mask+aunfl_mask+ainex_mask
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unf2inx_mask equ unfl_mask+inex2_mask+ainex_mask
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ovfinx_mask equ ovfl_mask+inex2_mask+aovfl_mask+ainex_mask
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inx1a_mask equ inex1_mask+ainex_mask
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inx2a_mask equ inex2_mask+ainex_mask
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snaniop_mask equ nan_mask+snan_mask+aiop_mask
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naniop_mask equ nan_mask+aiop_mask
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neginf_mask equ neg_mask+inf_mask
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infaiop_mask equ inf_mask+aiop_mask
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negz_mask equ neg_mask+z_mask
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opaop_mask equ operr_mask+aiop_mask
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unfl_inx_mask equ unfl_mask+aunfl_mask+ainex_mask
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ovfl_inx_mask equ ovfl_mask+aovfl_mask+ainex_mask
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*
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*--------------------------------------------------------------------------
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*
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* FPCR rounding modes
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*
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x_mode equ $00 ; round to extended
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s_mode equ $40 ; round to single
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d_mode equ $80 ; round to double
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*
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rn_mode equ $00 ; round to nearest
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rz_mode equ $10 ; round to zero
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rm_mode equ $20 ; round to minus infinity
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rp_mode equ $30 ; round to plus infinity
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*
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*--------------------------------------------------------------------------
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*
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* Miscellaneous equates
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*
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signan_bit equ 6 ; signaling nan bit in mantissa
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sign_bit equ 7
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*
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rnd_stky_bit equ 29 ; round/sticky bit of mantissa
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* ; this can only be used if in a data register
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sx_mask equ $01800000 ; set s and x bits in word $48
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*
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LOCAL_EX equ 0
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LOCAL_SGN equ 2
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LOCAL_HI equ 4
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LOCAL_LO equ 8
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LOCAL_GRS equ 12 ; valid ONLY for FP_SCR1, FP_SCR2
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*
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*
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norm_tag equ $00 ; tag bits in {7:5} position
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zero_tag equ $20
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inf_tag equ $40
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nan_tag equ $60
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dnrm_tag equ $80
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*
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* fsave sizes and formats
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*
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VER_4 equ $40 ; fpsp compatible version numbers
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* ; are in the $40s {$40-$4f}
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VER_40 equ $40 ; original version number
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VER_41 equ $41 ; revision version number
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*
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BUSY_SIZE equ 100 ; size of busy frame
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BUSY_FRAME equ LV-BUSY_SIZE ; start of busy frame
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*
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UNIMP_40_SIZE equ 44 ; size of orig unimp frame
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UNIMP_41_SIZE equ 52 ; size of rev unimp frame
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*
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IDLE_SIZE equ 4 ; size of idle frame
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IDLE_FRAME equ LV-IDLE_SIZE ; start of idle frame
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*
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* exception vectors
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*
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TRACE_VEC equ $2024 ; trace trap
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FLINE_VEC equ $002C ; 'real' F-line
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UNIMP_VEC equ $202C ; unimplemented
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INEX_VEC equ $00C4
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*
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dbl_thresh equ $3C01
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sgl_thresh equ $3F81
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*
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; User exception vectors <1/03/91, JPO>
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FPBSUN_VEC040 equ $1FCC
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FPUNFL_VEC040 equ $1FD0
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FPOPERR_VEC040 equ $1FD4
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FPOVFL_VEC040 equ $1FD8
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FPSNAN_VEC040 equ $1FDC
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; FLINE exception vector for system <1/03/91, JPO>
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FLINE_VEC040 equ $1FC8
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