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775 lines
20 KiB
Plaintext
775 lines
20 KiB
Plaintext
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; OpenRISC family. -*- Scheme -*-
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; Copyright 2000, 2001, 2011 Free Software Foundation, Inc.
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; Contributed by Johan Rydberg, jrydberg@opencores.org
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;
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; This program is free software; you can redistribute it and/or modify
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; it under the terms of the GNU General Public License as published by
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; the Free Software Foundation; either version 2 of the License, or
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; (at your option) any later version.
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;
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; This program is distributed in the hope that it will be useful,
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; but WITHOUT ANY WARRANTY; without even the implied warranty of
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; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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; GNU General Public License for more details.
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;
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; You should have received a copy of the GNU General Public License
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; along with this program; if not, write to the Free Software
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; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
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(include "simplify.inc")
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; OpenRISC 1000 is an architecture of a family of open source,
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; synthesizeable RISC microprocessor cores. It is a 32-bit load
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; and store RISC architecture designed with emphasis on speed,
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; compact instruction set and scalability. OpenRISC 1000 targets
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; wide range of embedded environments.
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(define-arch
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(name openrisc)
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(comment "OpenRISC 1000")
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(insn-lsb0? #t)
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(machs openrisc or1300)
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(isas or32)
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)
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; Attributes
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; An attribute to describe if a model has insn and/or data caches.
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(define-attr
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(for model)
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(type enum)
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(name HAS-CACHE)
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(comment "if this model has caches")
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(values DATA-CACHE INSN-CACHE)
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)
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; An attribute to describe if an insn can be in the delay slot or not.
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(define-attr
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(for insn)
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(type boolean)
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(name NOT-IN-DELAY-SLOT)
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(comment "insn can't go in delay slot")
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)
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; IDOC attribute for instruction documentation.
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(define-attr
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(for insn)
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(type enum)
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(name IDOC)
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(comment "insn kind for documentation")
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(attrs META)
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(values
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(MEM - () "Memory")
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(ALU - () "ALU")
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(FPU - () "FPU")
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(BR - () "Branch")
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(PRIV - () "Priviledged")
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(MISC - () "Miscellaneous")
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)
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)
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; Enum for exception vectors.
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(define-enum
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(name e-exception)
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(comment "exception vectors")
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(attrs)
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(prefix E_)
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(values (("RESET") ("BUSERR" -) ("DPF" -) ("IPF" -) ("EXTINT" -) ("ALIGN" -)
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("ILLEGAL" -) ("PEINT" -) ("DTLBMISS" -) ("ITLBMISS" -) ("RRANGE" -)
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("SYSCALL" -) ("BREAK" -) ("RESERVED" -)))
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)
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; Instruction set parameters.
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(define-isa
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; Name of the ISA.
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(name or32)
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; Base insturction length. The insns is always 32 bits wide.
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(base-insn-bitsize 32)
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; Address of insn in delay slot
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(setup-semantics (set-quiet (reg h-delay-insn) (add pc 4)))
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)
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; CPU family definitions.
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(define-cpu
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; CPU names must be distinct from the architecture name and machine names.
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; The "b" suffix stands for "base" and is the convention.
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; The "f" suffix stands for "family" and is the convention.
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(name openriscbf)
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(comment "OpenRISC base family")
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(endian big)
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(word-bitsize 32)
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)
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; Generic machine
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(define-mach
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(name openrisc)
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(comment "Generic OpenRISC cpu")
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(cpu openriscbf)
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(bfd-name "openrisc")
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)
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; OpenRISC 1300 machine
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(define-mach
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(name or1300)
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(comment "OpenRISC 1300")
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(cpu openriscbf)
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(bfd-name "openrisc:1300")
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)
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; Model descriptions
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; Generic OpenRISC model
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(define-model
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(name openrisc-1) (comment "OpenRISC generic model") (attrs)
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(mach openrisc)
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; Nothing special about this.
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(unit u-exec "Execution Unit" () 1 1 () () () ())
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)
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; OpenRISC 1320
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(define-model
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(name or1320-1) (comment "OpenRISC 1320 model")
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; This model has both instruction and data cache
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(attrs (HAS-CACHE INSN-CACHE,DATA-CACHE))
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(mach or1300)
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; Nothing special about this.
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(unit u-exec "Execution Unit" () 1 1 () () () ())
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)
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; Instruction fields.
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; Attributes:
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; . PCREL-ADDR pc relative value (for reloc and disassembly purposes)
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; . ABS-ADDR absolute address (for reloc and disassembly purposes?)
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; . RESERVED bits are not used to decode insn, must be all 0
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; Instruction classes.
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(dnf f-class "insn class" () 31 2)
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(dnf f-sub "sub class" () 29 4)
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; Register fields.
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(dnf f-r1 "r1" () 25 5)
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(dnf f-r2 "r2" () 20 5)
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(dnf f-r3 "r3" () 15 5)
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; Immediates.
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(df f-simm16 "signed imm (16)" () 15 16 INT #f #f)
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(dnf f-uimm16 "unsigned imm (16)" () 15 16)
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(dnf f-uimm5 "unsigned imm (5)" () 4 5)
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(df f-hi16 "high 16" () 15 16 INT #f #f)
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(df f-lo16 "low 16" () 15 16 INT #f #f)
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; Sub fields
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(dnf f-op1 "op1" () 31 2)
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(dnf f-op2 "op2" () 29 4)
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(dnf f-op3 "op3" () 25 2)
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(dnf f-op4 "op4" () 23 3)
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(dnf f-op5 "op3" () 25 5)
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(dnf f-op6 "op4" () 7 3)
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(dnf f-op7 "op5" () 3 4)
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(dnf f-i16-1 "uimm16-1" () 10 11)
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(dnf f-i16-2 "uimm16-2" () 25 5)
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; PC relative, 26-bit (2 shifted to right)
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(df f-disp26 "disp26" (PCREL-ADDR) 25 26 INT
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((value pc) (sra WI (sub WI value pc) (const 2)))
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((value pc) (add WI (sll WI value (const 2)) pc)))
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; absolute, 26-bit (2 shifted to right)
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(df f-abs26 "abs26" (ABS-ADDR) 25 26 INT
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((value pc) (sra WI pc (const 2)))
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((value pc) (sll WI value (const 2))))
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(define-multi-ifield
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(name f-i16nc)
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(comment "16 bit signed")
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(attrs SIGN-OPT)
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(mode HI)
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(subfields f-i16-1 f-i16-2)
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(insert (sequence ()
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(set (ifield f-i16-2) (and (sra (ifield f-i16nc)
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(const 11))
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(const #x1f)))
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(set (ifield f-i16-1) (and (ifield f-i16nc)
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(const #x7ff)))))
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(extract (sequence ()
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(set (ifield f-i16nc) (c-raw-call SI "@arch@_sign_extend_16bit"
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(or (sll (ifield f-i16-2)
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(const 11))
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(ifield f-i16-1))))))
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)
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; Enums.
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; insn-class: bits 31-30
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(define-normal-insn-enum insn-class "FIXME" () OP1_ f-class
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(.map .str (.iota 4))
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)
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(define-normal-insn-enum insn-sub "FIXME" () OP2_ f-sub
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(.map .str (.iota 16))
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)
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(define-normal-insn-enum insn-op3 "FIXME" () OP3_ f-op3
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(.map .str (.iota 4))
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)
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(define-normal-insn-enum insn-op4 "FIXME" () OP4_ f-op4
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(.map .str (.iota 8))
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)
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(define-normal-insn-enum insn-op5 "FIXME" () OP5_ f-op5
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(.map .str (.iota 32))
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)
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(define-normal-insn-enum insn-op6 "FIXME" () OP6_ f-op6
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(.map .str (.iota 8))
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)
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(define-normal-insn-enum insn-op7 "FIXME" () OP7_ f-op7
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(.map .str (.iota 16))
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)
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; Hardware pieces.
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; These entries list the elements of the raw hardware.
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; They're also used to provide tables and other elements of the assembly
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; language.
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(dnh h-pc "program counter" (PC PROFILE) (pc) () () ())
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(define-hardware
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(name h-gr) (comment "general registers") (attrs PROFILE)
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(type register WI (32))
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(indices keyword ""
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((r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7)
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(r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14)
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(r15 15) (r16 16) (r17 17) (r18 18) (r19 19) (r20 20)
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(r21 21) (r22 22) (r23 23) (r24 24) (r25 25) (r26 26)
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(r27 27) (r28 28) (r29 29) (r30 30) (r31 31) (lr 11)
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(sp 1) (fp 2)))
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)
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(define-hardware
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(name h-sr) (comment "special registers")
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(type register WI (#x20000))
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(get (index) (c-call SI "@arch@_h_sr_get_handler" index))
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(set (index newval) (c-call VOID "@arch@_h_sr_set_handler" index newval))
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)
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(dnh h-hi16 "high 16 bits" () (immediate (INT 16)) () () ())
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(dnh h-lo16 "low 16 bits" () (immediate (INT 16)) () () ())
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(dsh h-cbit "condition bit" () (register BI))
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(dsh h-delay-insn "delay insn addr" () (register SI))
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; Instruction operands.
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(dnop sr "special register" (SEM-ONLY) h-sr f-nil)
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(dnop cbit "condition bit" (SEM-ONLY) h-cbit f-nil)
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(dnop simm-16 "16 bit signed immediate" () h-sint f-simm16)
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(dnop uimm-16 "16 bit unsigned immediate" () h-uint f-uimm16)
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(dnop disp-26 "pc-rel 26 bit" () h-iaddr f-disp26)
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(dnop abs-26 "abs 26 bit" () h-iaddr f-abs26)
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(dnop uimm-5 "imm5" () h-uint f-uimm5)
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(dnop rD "destination register" () h-gr f-r1)
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(dnop rA "source register A" () h-gr f-r2)
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(dnop rB "source register B" () h-gr f-r3)
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(dnop op-f-23 "f-op23" () h-uint f-op4)
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(dnop op-f-3 "f-op3" () h-uint f-op5)
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; For hi(foo).
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(define-operand
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(name hi16) (comment "high 16 bit immediate, sign optional")
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(attrs SIGN-OPT)
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(type h-hi16)
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(index f-simm16)
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(handlers (parse "hi16"))
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)
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; For lo(foo)
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(define-operand
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(name lo16) (comment "low 16 bit immediate, sign optional")
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(attrs SIGN-OPT)
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(type h-lo16)
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(index f-lo16)
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(handlers (parse "lo16"))
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)
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(define-operand
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(name ui16nc)
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(comment "16 bit immediate, sign optional")
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(attrs)
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(type h-lo16)
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(index f-i16nc)
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(handlers (parse "lo16"))
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)
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; Instructions.
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; Branch releated instructions
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(dni l-j "jump (absolute iaddr)"
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; This function may not be in delay slot
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(NOT-IN-DELAY-SLOT)
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"l.j ${abs-26}"
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(+ OP1_0 OP2_0 abs-26)
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; We execute the delay slot before doin' the real branch
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(delay 1 (set pc abs-26))
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()
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)
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(dni l-jal "jump and link (absolute iaddr)"
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; This function may not be in delay slot
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(NOT-IN-DELAY-SLOT)
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"l.jal ${abs-26}"
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(+ OP1_0 OP2_1 abs-26)
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; We execute the delay slot before doin' the real branch
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; Set LR to (delay insn addr + 4)
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(sequence ()
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(set (reg h-gr 11) (add (reg h-delay-insn) 4))
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(delay 1 (set pc abs-26)))
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()
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)
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(dni l-jr "jump register (absolute iaddr)"
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; This function may not be in delay slot
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(NOT-IN-DELAY-SLOT)
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"l.jr $rA"
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(+ OP1_0 OP2_5 OP3_0 OP4_0 rA uimm-16)
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; We execute the delay slot before doin' the real branch
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(delay 1 (set pc rA))
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()
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)
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(dni l-jalr "jump register and link (absolute iaddr)"
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; This function may not be in delay slot
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(NOT-IN-DELAY-SLOT)
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"l.jalr $rA"
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(+ OP1_0 OP2_5 OP3_0 OP4_1 rA uimm-16)
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; We save the value of rA in a temporary slot before setting
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; the link register. This because "l.jalr r11" would cause
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; a forever-and-ever loop otherwise.
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;
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; We execute the delay slot before doin' the real branch
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(sequence ((WI tmp-slot))
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(set tmp-slot rA)
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(set (reg h-gr 11) (add (reg h-delay-insn) 4))
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(delay 1 (set pc tmp-slot)))
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()
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)
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(dni l-bal "branch and link (pc relative iaddr)"
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; This function may not be in delay slot
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(NOT-IN-DELAY-SLOT)
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"l.bal ${disp-26}"
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(+ OP1_0 OP2_2 disp-26)
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; We execute the delay slot before doin' the real branch
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; Set LR to (delay insn addr + 4)
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(sequence ()
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(set (reg h-gr 11) (add (reg h-delay-insn) 4))
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(delay 1 (set pc disp-26)))
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()
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|
)
|
|||
|
|
|||
|
(dni l-bnf "branch if condition bit not set (pc relative iaddr)"
|
|||
|
; This function may not be in delay slot
|
|||
|
(NOT-IN-DELAY-SLOT)
|
|||
|
|
|||
|
"l.bnf ${disp-26}"
|
|||
|
(+ OP1_0 OP2_3 disp-26)
|
|||
|
|
|||
|
; We execute the delay slot before doin' the real branch
|
|||
|
(if (eq cbit 0)
|
|||
|
(sequence ()
|
|||
|
(delay 1 (set pc disp-26))))
|
|||
|
()
|
|||
|
)
|
|||
|
|
|||
|
(dni l-bf "branch if condition bit is set (pc relative iaddr)"
|
|||
|
; This function may not be in delay slot
|
|||
|
(NOT-IN-DELAY-SLOT)
|
|||
|
|
|||
|
"l.bf ${disp-26}"
|
|||
|
(+ OP1_0 OP2_4 disp-26)
|
|||
|
|
|||
|
; We execute the delay slot before doin' the real branch
|
|||
|
(if (eq cbit 1)
|
|||
|
(sequence ()
|
|||
|
(delay 1 (set pc disp-26))))
|
|||
|
()
|
|||
|
)
|
|||
|
|
|||
|
(dni l-brk "break (exception)"
|
|||
|
; This function may not be in delay slot
|
|||
|
(NOT-IN-DELAY-SLOT)
|
|||
|
|
|||
|
"l.brk ${uimm-16}"
|
|||
|
(+ OP1_0 OP2_5 OP3_3 OP4_0 rA uimm-16)
|
|||
|
|
|||
|
; FIXME should we do it like this ??
|
|||
|
(c-call VOID "@cpu@_cpu_brk" uimm-16)
|
|||
|
()
|
|||
|
)
|
|||
|
|
|||
|
(dni l-rfe "return from exception"
|
|||
|
; This function may not be in delay slot
|
|||
|
(NOT-IN-DELAY-SLOT)
|
|||
|
|
|||
|
"l.rfe $rA"
|
|||
|
(+ OP1_0 OP2_5 OP3_0 OP4_2 rA uimm-16)
|
|||
|
(sequence ()
|
|||
|
(delay 1 (set pc (c-call SI "@cpu@_cpu_rfe" rA))))
|
|||
|
()
|
|||
|
)
|
|||
|
|
|||
|
(dni l-sys "syscall (exception)"
|
|||
|
; This function may not be in delay slot
|
|||
|
(NOT-IN-DELAY-SLOT)
|
|||
|
|
|||
|
"l.sys ${uimm-16}"
|
|||
|
(+ OP1_0 OP2_5 OP3_2 OP4_0 rA uimm-16)
|
|||
|
(sequence()
|
|||
|
(delay 1 (set pc (c-call SI "@cpu@_except" pc
|
|||
|
#xc00 uimm-16))))
|
|||
|
()
|
|||
|
)
|
|||
|
|
|||
|
|
|||
|
; Misc instructions
|
|||
|
|
|||
|
(dni l-nop "nop"
|
|||
|
()
|
|||
|
"l.nop"
|
|||
|
(+ OP1_0 OP2_5 OP3_1 OP4_0 rA uimm-16)
|
|||
|
(nop)
|
|||
|
()
|
|||
|
)
|
|||
|
|
|||
|
(dnmi l-ret "ret" ()
|
|||
|
"l.ret"
|
|||
|
(emit l-jr (rA 11) (uimm-16 0))
|
|||
|
)
|
|||
|
|
|||
|
(dni l-movhi "movhi"
|
|||
|
(DELAY-SLOT)
|
|||
|
"l.movhi $rD,$hi16"
|
|||
|
(+ OP1_0 OP2_6 hi16 rD rA)
|
|||
|
(set rD (sll WI hi16 (const 16)))
|
|||
|
()
|
|||
|
)
|
|||
|
|
|||
|
|
|||
|
; System releated instructions
|
|||
|
|
|||
|
(dni l-mfsr "mfsr"
|
|||
|
(DELAY-SLOT)
|
|||
|
"l.mfsr $rD,$rA"
|
|||
|
(+ OP1_0 OP2_7 rD rA uimm-16)
|
|||
|
(set rD (c-call SI "@cpu@_cpu_mfsr" rA))
|
|||
|
()
|
|||
|
)
|
|||
|
|
|||
|
(dni l-mtsr "mtsr"
|
|||
|
(DELAY-SLOT)
|
|||
|
"l.mtsr $rA,$rB"
|
|||
|
(+ OP1_1 OP2_0 rA rB rD (f-i16-1 0))
|
|||
|
(c-call VOID "@cpu@_cpu_mtsr" rA rB)
|
|||
|
()
|
|||
|
)
|
|||
|
|
|||
|
|
|||
|
|
|||
|
; Load instructions
|
|||
|
|
|||
|
(dni l-lw "load word"
|
|||
|
(DELAY-SLOT)
|
|||
|
"l.lw $rD,${simm-16}($rA)"
|
|||
|
(+ OP1_2 OP2_0 rD rA simm-16)
|
|||
|
(set rD (mem SI (add rA simm-16)))
|
|||
|
()
|
|||
|
)
|
|||
|
|
|||
|
(dni l-lbz "load byte (zero extend)"
|
|||
|
(DELAY-SLOT)
|
|||
|
"l.lbz $rD,${simm-16}($rA)"
|
|||
|
(+ OP1_2 OP2_1 rD rA simm-16)
|
|||
|
(set rD (zext SI (mem QI (add rA simm-16))))
|
|||
|
()
|
|||
|
)
|
|||
|
|
|||
|
(dni l-lbs "load byte (sign extend)"
|
|||
|
(DELAY-SLOT)
|
|||
|
"l.lbs $rD,${simm-16}($rA)"
|
|||
|
(+ OP1_2 OP2_2 rD rA simm-16)
|
|||
|
(set rD (ext SI (mem QI (add rA simm-16))))
|
|||
|
()
|
|||
|
)
|
|||
|
|
|||
|
(dni l-lhz "load halfword (zero extend)"
|
|||
|
(DELAY-SLOT)
|
|||
|
"l.lhz $rD,${simm-16}($rA)"
|
|||
|
(+ OP1_2 OP2_3 rD simm-16 rA)
|
|||
|
(set rD (zext SI (mem HI (add rA simm-16))))
|
|||
|
()
|
|||
|
)
|
|||
|
|
|||
|
(dni l-lhs "load halfword (sign extend)"
|
|||
|
(DELAY-SLOT)
|
|||
|
"l.lhs $rD,${simm-16}($rA)"
|
|||
|
(+ OP1_2 OP2_4 rD rA simm-16)
|
|||
|
(set rD (ext SI (mem HI (add rA simm-16))))
|
|||
|
()
|
|||
|
)
|
|||
|
|
|||
|
|
|||
|
; Store instructions
|
|||
|
;
|
|||
|
; We have to use a multi field since the integer is splited over 2 fields
|
|||
|
|
|||
|
(define-pmacro (store-insn mnemonic op2-op mode-op)
|
|||
|
(begin
|
|||
|
(dni (.sym l- mnemonic)
|
|||
|
(.str "l." mnemonic " imm(reg)/reg")
|
|||
|
(DELAY-SLOT)
|
|||
|
(.str "l." mnemonic " ${ui16nc}($rA),$rB")
|
|||
|
(+ OP1_3 op2-op rB rD ui16nc)
|
|||
|
(set (mem mode-op (add rA ui16nc)) rB)
|
|||
|
()
|
|||
|
)
|
|||
|
)
|
|||
|
)
|
|||
|
|
|||
|
(store-insn sw OP2_5 SI)
|
|||
|
(store-insn sb OP2_6 QI)
|
|||
|
(store-insn sh OP2_7 HI)
|
|||
|
|
|||
|
|
|||
|
|
|||
|
; Shift and rotate instructions
|
|||
|
|
|||
|
; Reserved fields.
|
|||
|
(dnf f-f-15-8 "nop" (RESERVED) 15 8)
|
|||
|
(dnf f-f-10-3 "nop" (RESERVED) 10 3)
|
|||
|
(dnf f-f-4-1 "nop" (RESERVED) 4 1)
|
|||
|
(dnf f-f-7-3 "nop" (RESERVED) 7 3)
|
|||
|
|
|||
|
(define-pmacro (shift-insn mnemonic op4-op)
|
|||
|
(begin
|
|||
|
(dni (.sym l- mnemonic)
|
|||
|
(.str "l." mnemonic " reg/reg/reg")
|
|||
|
()
|
|||
|
(.str "l." mnemonic " $rD,$rA,$rB")
|
|||
|
(+ OP1_3 OP2_8 rD rA rB (f-f-10-3 0) op4-op (f-f-4-1 0) OP7_8)
|
|||
|
(set rD (mnemonic rA rB))
|
|||
|
()
|
|||
|
)
|
|||
|
(dni (.sym l- mnemonic "i")
|
|||
|
(.str "l." mnemonic " reg/reg/imm")
|
|||
|
()
|
|||
|
(.str "l." mnemonic "i $rD,$rA,${uimm-5}")
|
|||
|
(+ OP1_2 OP2_13 rD rA (f-f-15-8 0) op4-op uimm-5)
|
|||
|
(set rD (mnemonic rA uimm-5))
|
|||
|
()
|
|||
|
)
|
|||
|
)
|
|||
|
)
|
|||
|
|
|||
|
(shift-insn sll OP6_0)
|
|||
|
(shift-insn srl OP6_1)
|
|||
|
(shift-insn sra OP6_2)
|
|||
|
(shift-insn ror OP6_4)
|
|||
|
|
|||
|
|
|||
|
; Arethmetic insns
|
|||
|
|
|||
|
; Reserved fields.
|
|||
|
(dnf f-f-10-7 "nop" (RESERVED) 10 7)
|
|||
|
|
|||
|
(define-pmacro (ar-insn-u mnemonic op2-op op5-op)
|
|||
|
(begin
|
|||
|
(dni (.sym l- mnemonic)
|
|||
|
(.str "l." mnemonic " reg/reg/reg")
|
|||
|
()
|
|||
|
(.str "l." mnemonic " $rD,$rA,$rB")
|
|||
|
(+ OP1_3 OP2_8 rD rA rB (f-f-10-7 0) op5-op)
|
|||
|
(set rD (mnemonic rA rB))
|
|||
|
()
|
|||
|
)
|
|||
|
(dni (.sym l- mnemonic "i")
|
|||
|
(.str "l." mnemonic " reg/reg/lo16")
|
|||
|
()
|
|||
|
(.str "l." mnemonic "i $rD,$rA,$lo16")
|
|||
|
(+ OP1_2 op2-op rD rA lo16)
|
|||
|
(set rD (mnemonic rA (and lo16 #xffff)))
|
|||
|
()
|
|||
|
)
|
|||
|
)
|
|||
|
)
|
|||
|
|
|||
|
(define-pmacro (ar-insn-s mnemonic op2-op op5-op)
|
|||
|
(begin
|
|||
|
(dni (.sym l- mnemonic)
|
|||
|
(.str "l." mnemonic " reg/reg/reg")
|
|||
|
()
|
|||
|
(.str "l." mnemonic " $rD,$rA,$rB")
|
|||
|
(+ OP1_3 OP2_8 rD rA rB (f-f-10-7 0) op5-op)
|
|||
|
(set rD (mnemonic rA rB))
|
|||
|
()
|
|||
|
)
|
|||
|
(dni (.sym l- mnemonic "i")
|
|||
|
(.str "l." mnemonic " reg/reg/lo16")
|
|||
|
()
|
|||
|
(.str "l." mnemonic "i $rD,$rA,$lo16")
|
|||
|
(+ OP1_2 op2-op rD rA lo16)
|
|||
|
(set rD (mnemonic rA lo16))
|
|||
|
()
|
|||
|
)
|
|||
|
)
|
|||
|
)
|
|||
|
|
|||
|
(ar-insn-s add OP2_5 OP7_0)
|
|||
|
;;(ar-op-s addc OP2_5 OP7_0)
|
|||
|
(ar-insn-s sub OP2_7 OP7_2)
|
|||
|
(ar-insn-u and OP2_8 OP7_3)
|
|||
|
(ar-insn-u or OP2_9 OP7_4)
|
|||
|
(ar-insn-u xor OP2_10 OP7_5)
|
|||
|
(ar-insn-u mul OP2_11 OP7_6)
|
|||
|
;;(ar-op-u mac OP2_12 OP7_7)
|
|||
|
|
|||
|
|
|||
|
(dni l-div "divide (signed)"
|
|||
|
(DELAY-SLOT)
|
|||
|
"l.div $rD,$rA,$rB"
|
|||
|
(+ OP1_3 OP2_8 rD rA rB (f-f-10-7 0) OP7_9)
|
|||
|
(if VOID (eq rB (const 0))
|
|||
|
(c-call VOID "@arch@_cpu_trap" pc (enum SI E_ILLEGAL))
|
|||
|
(set rD (div rA rB)))
|
|||
|
()
|
|||
|
)
|
|||
|
|
|||
|
(dni l-divu "divide (unsigned)"
|
|||
|
(DELAY-SLOT)
|
|||
|
"l.divu $rD,$rA,$rB"
|
|||
|
(+ OP1_3 OP2_8 rD rA rB (f-f-10-7 0) OP7_10)
|
|||
|
(if VOID (eq rB (const 0))
|
|||
|
(c-call VOID "@arch@_cpu_trap" pc (enum SI E_ILLEGAL))
|
|||
|
(set rD (udiv rA rB)))
|
|||
|
()
|
|||
|
)
|
|||
|
|
|||
|
|
|||
|
; Compare instructions
|
|||
|
|
|||
|
; Reserved fields.
|
|||
|
(dnf f-f-10-11 "nop" (RESERVED) 10 11)
|
|||
|
|
|||
|
; Register compare (both signed and unsigned)
|
|||
|
(define-pmacro (sf-insn-r op1-op op2-op op3-op op3-op-2 sem-op)
|
|||
|
(begin
|
|||
|
(dni (.sym l- "sf" (.sym sem-op "s"))
|
|||
|
(.str "l." mnemonic " reg/reg")
|
|||
|
(DELAY-SLOT)
|
|||
|
(.str "l.sf" (.str sem-op) "s $rA,$rB")
|
|||
|
(+ op1-op op2-op op3-op-2 rA rB (f-f-10-11 0))
|
|||
|
(set cbit (sem-op rA rB))
|
|||
|
()
|
|||
|
)
|
|||
|
(dni (.sym l- "sf" (.sym sem-op "u"))
|
|||
|
(.str "l." mnemonic " reg/reg")
|
|||
|
(DELAY-SLOT)
|
|||
|
(.str "l.sf" (.str sem-op) "u $rA,$rB")
|
|||
|
(+ op1-op op2-op op3-op rA rB (f-f-10-11 0))
|
|||
|
(set cbit (sem-op rA rB))
|
|||
|
()
|
|||
|
)
|
|||
|
)
|
|||
|
)
|
|||
|
|
|||
|
; Immediate compare (both signed and unsigned)
|
|||
|
(define-pmacro (sf-insn-i op1-op op2-op op3-op op3-op-2 sem-op)
|
|||
|
(begin
|
|||
|
(dni (.sym l- "sf" (.sym sem-op "si"))
|
|||
|
(.str "l." mnemonic "si reg/imm")
|
|||
|
(DELAY-SLOT)
|
|||
|
(.str "l.sf" (.str sem-op) "si $rA,${simm-16}")
|
|||
|
(+ op1-op op2-op op3-op-2 rA simm-16)
|
|||
|
(set cbit (sem-op rA simm-16))
|
|||
|
()
|
|||
|
)
|
|||
|
(dni (.sym l- "sf" (.sym sem-op "ui"))
|
|||
|
(.str "l." mnemonic "ui reg/imm")
|
|||
|
(DELAY-SLOT)
|
|||
|
(.str "l.sf" (.str sem-op) "ui $rA,${uimm-16}")
|
|||
|
(+ op1-op op2-op op3-op rA uimm-16)
|
|||
|
(set cbit (sem-op rA uimm-16))
|
|||
|
()
|
|||
|
)
|
|||
|
)
|
|||
|
)
|
|||
|
|
|||
|
(define-pmacro (sf-insn op5-op sem-op)
|
|||
|
(begin
|
|||
|
(dni (.sym l- "sf" sem-op)
|
|||
|
(.str "l." mnemonic " reg/reg")
|
|||
|
(DELAY-SLOT)
|
|||
|
(.str "l.sf" (.str sem-op) " $rA,$rB")
|
|||
|
(+ OP1_3 OP2_9 op5-op rA rB (f-f-10-11 0))
|
|||
|
(set cbit (sem-op rA rB))
|
|||
|
()
|
|||
|
)
|
|||
|
(dni (.sym l- "sf" (.sym sem-op "i"))
|
|||
|
(.str "l." mnemonic "i reg/imm")
|
|||
|
(DELAY-SLOT)
|
|||
|
(.str "l.sf" (.str sem-op) "i $rA,${simm-16}")
|
|||
|
(+ OP1_2 OP2_14 op5-op rA simm-16)
|
|||
|
(set cbit (sem-op rA simm-16))
|
|||
|
()
|
|||
|
)
|
|||
|
)
|
|||
|
)
|
|||
|
|
|||
|
|
|||
|
(sf-insn-r OP1_3 OP2_9 OP5_2 OP5_6 gt)
|
|||
|
(sf-insn-r OP1_3 OP2_9 OP5_3 OP5_7 ge)
|
|||
|
(sf-insn-r OP1_3 OP2_9 OP5_4 OP5_8 lt)
|
|||
|
(sf-insn-r OP1_3 OP2_9 OP5_5 OP5_9 le)
|
|||
|
|
|||
|
(sf-insn-i OP1_2 OP2_14 OP5_2 OP5_6 gt)
|
|||
|
(sf-insn-i OP1_2 OP2_14 OP5_3 OP5_7 ge)
|
|||
|
(sf-insn-i OP1_2 OP2_14 OP5_4 OP5_8 lt)
|
|||
|
(sf-insn-i OP1_2 OP2_14 OP5_5 OP5_9 le)
|
|||
|
|
|||
|
(sf-insn OP5_0 eq)
|
|||
|
(sf-insn OP5_1 ne)
|