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281 lines
11 KiB
C
281 lines
11 KiB
C
/* asm.h -- CR16 architecture intrinsic functions
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*
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* Copyright (c) 2012 National Semiconductor Corporation
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*
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* The authors hereby grant permission to use, copy, modify, distribute,
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* and license this software and its documentation for any purpose, provided
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* that existing copyright notices are retained in all copies and that this
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* notice is included verbatim in any distributions. No written agreement,
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* license, or royalty fee is required for any of the authorized uses.
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* Modifications to this software may be copyrighted by their authors
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* and need not follow the licensing terms described here, provided that
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* the new terms are clearly indicated on the first page of each file where
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* they apply.
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*/
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#ifndef _ASM
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#define _ASM
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/* Note that immediate input values are not checked for validity. It is
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the user's responsibility to use the intrinsic functions with appropriate
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immediate values. */
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/* Addition Instructions */
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#define _addb_(src, dest) __asm__("addb %1, %0" : "=r" (dest) : \
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"ri" ((unsigned char)src), "0" (dest) : "cc")
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#define _addub_(src, dest) __asm__("addub %1, %0" : "=r" (dest) : \
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"ri" ((unsigned char)src), "0" (dest) : "cc")
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#define _addw_(src, dest) __asm__("addw %1, %0" : "=r" (dest) : \
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"ri" ((unsigned short)src), "0" (dest) : "cc")
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#define _adduw_(src, dest) __asm__("adduw %1, %0" : "=r" (dest) : \
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"ri" ((unsigned short)src), "0" (dest) : "cc")
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#define _addd_(src, dest) __asm__("addd %1, %0" : "=r" (dest) : \
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"ri" ((unsigned long)src), "0" (dest) : "cc")
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/* Add with Carry */
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#define _addcb_(src, dest) __asm__("addcb %1, %0" : "=r" (dest) : \
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"ri" ((unsigned char)src), "0" (dest) : "cc")
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#define _addcw_(src, dest) __asm__("addcw %1, %0" : "=r" (dest) : \
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"ri" ((unsigned short)src), "0" (dest) : "cc")
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/* Bitwise Logical AND */
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#define _andb_(src, dest) __asm__("andb %1,%0" : "=r" (dest) : \
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"ri" ((unsigned char)src) , "0" (dest))
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#define _andw_(src, dest) __asm__("andw %1,%0" : "=r" (dest) : \
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"ri" ((unsigned short)src) , "0" (dest))
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#define _andd_(src, dest) __asm__("andd %1,%0" : "=r" (dest) : \
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"ri" ((unsigned long)src) , "0" (dest))
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/* Arithmetic shift Instructions */
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#define _ashub_(count, dest) __asm__("ashub %1,%0" : "=r" (dest) : \
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"ri" ((char)count) , "0" (dest) )
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#define _ashuw_(count, dest) __asm__("ashuw %1,%0" : "=r" (dest) : \
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"ri" ((char)count) , "0" (dest) )
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#define _ashud_(count, dest) __asm__("ashud %1,%0" : "=r" (dest) : \
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"ri" ((char)count) , "0" (dest) )
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/* cbit (clear bit) Instructions */
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#define _cbitb_(pos, dest) __asm__("cbitb %1,%0" : "=mr" (dest) : \
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"i" ((unsigned char)pos) , "0" (dest) : "cc")
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#define _cbitw_(pos, dest) __asm__("cbitw %1,%0" : "=mr" (dest) : \
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"i" ((unsigned char)pos) , "0" (dest) : "cc")
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/* Compare Instructions */
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#define _cmpb_(src1, src2) __asm__("cmpb %0,%1" : /* no output */ : \
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"ri" ((unsigned char)src1) , "r" (src2) : "cc")
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#define _cmpw_(src1, src2) __asm__("cmpw %0,%1" : /* no output */ : \
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"ri" ((unsigned short)src1) , "r" (src2) : "cc")
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#define _cmpd_(src1, src2) __asm__("cmpd %0,%1" : /* no output */ : \
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"ri" ((unsigned long)src1) , "r" (src2) : "cc")
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/* Disable Inerrupts instructions */
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#define _di_() __asm__ volatile ("di\n" : : : "cc")
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#define _disable_() __asm__ volatile ("di\n" : : : "cc")
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#define _disable_interrupt_() _di_
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/* Enable Inerrupts instructions */
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#define _ei_() __asm__ volatile ("ei\n" : : : "cc")
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#define _enable_() __asm__ volatile ("ei\n" : : : "cc")
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#define _enable_interrupt_() _ei_
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/* Enable Inerrupts instructions and Wait */
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#define _eiwait_() __asm__ volatile ("eiwait" : : : "cc")
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/* excp Instructions */
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#define _excp_(vector) __asm__ volatile ("excp " # vector)
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/* lpr and lprd Instructions */
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#define _lpr_(procreg, src) __asm__("lpr\t%0," procreg : \
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/* no output */ : "r" (src) : "cc")
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#define _lprd_(procregd, src) __asm__("lprd\t%0," procregd : \
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/* no output */ : "r" (src) : "cc")
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/* Left Shift Instructions */
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#define _lshb_(count, dest) __asm__("lshb %1,%0" : "=r" (dest) : \
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"ri" ((char)count) , "0" (dest) )
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#define _lshw_(count, dest) __asm__("lshw %1,%0" : "=r" (dest) : \
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"ri" ((char)count) , "0" (dest) )
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#define _lshd_(count, dest) __asm__("lshd %1,%0" : "=r" (dest) : \
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"ri" ((char)count) , "0" (dest) )
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/* Load Instructions */
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#define _loadb_(base, dest) __asm__("loadb %1,%0" : "=r" (dest) : \
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"m" (base) , "0" (dest))
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#define _loadw_(base, dest) __asm__("loadw %1,%0" : "=r" (dest) : \
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"m" (base) , "0" (dest))
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#define _loadd_(base, dest) __asm__("loadd %1,%0" : "=r" (dest) : \
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"m" (base) , "0" (dest))
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/* Load Multiple Instructions */
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#define _loadm_(src, mask) __asm__("loadm %0,%1" : /* No output */ : \
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"r" ((unsigned int)src) , "i" (mask))
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#define _loadmp_(src, mask) __asm__("loadmp %0,%1" : /* No output */ : \
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"r" ((unsigned int)src) , "i" (mask))
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/* Multiply Accumulate Instrutions */
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#define _macsw_(hi, lo, src1, src2) __asm__("macsw %1,%0" \
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: =l (lo), =h (hi) \
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: "r" ((short)src1) , "r" (src2))
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#define _macuw_(hi, lo, src1, src2) __asm__("macuw %1,%0" \
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: =l (lo), =h (hi) \
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: "r" ((unsigned short)src1) , "r" (src2))
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#define _macqw_(src1, src2) __asm__("macqw %1,%0" \
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: =l (lo), =h (hi) \
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:"r" ((short)src1) , "r" (src2))
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/* Move Instructions */
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#define _movb_(src, dest) __asm__("movb %1,%0" : "=r" (dest) : \
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"ri" ((unsigned char)src) , "0" (dest))
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#define _movw_(src, dest) __asm__("movw %1,%0" : "=r" (dest) : \
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"ri" ((unsigned short)src) , "0" (dest))
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#define _movd_(src, dest) __asm__("movd %1,%0" : "=r" (dest) : \
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"ri" ((unsigned int)src) , "0" (dest))
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#define _movxb_(src, dest) __asm__("movxb %1,%0" : "=r" (dest) : \
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"r" (src), "0" (dest) )
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#define _movzb_(src, dest) __asm__("movzb %1,%0" : "=r" (dest) : \
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"r" (src), "0" (dest) )
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#define _movxw_(src, dest) __asm__("movxw %1,%0" : "=r" (dest) : \
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"r" (src), "0" (dest) )
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#define _movzw_(src, dest) __asm__("movzw %1,%0" : "=r" (dest) : \
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"r" (src), "0" (dest) )
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/* Multiplication Instructions */
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#define _mulb_(src, dest) __asm__("mulb %1,%0" : "=r" (dest) : \
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"ri" ((char)src) , "0" (dest))
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#define _mulw_(src, dest) __asm__("mulw %1,%0" : "=r" (dest) : \
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"ri" ((short)src) , "0" (dest))
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#define _mulsb_(src, dest) __asm__("mulsb %1,%0" : "=r" (dest) : \
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"r" ((char)src) , "0" (dest))
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#define _mulsw_(src, dest) __asm__("mulsw %1,%0" : "=r" (dest) : \
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"r" ((short)src) , "0" (dest))
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#define _muluw_(src, dest) __asm__("muluw %1,%0" : "=r" (dest) : \
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"r" ((unsigned short)src) , "0" (dest))
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/* nop Instruction */
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#define _nop_() __asm__("nop")
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/* or Instructions */
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#define _orb_(src, dest) __asm__("orb %1,%0" : "=r" (dest) : \
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"ri" ((unsigned char)src) , "0" (dest))
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#define _orw_(src, dest) __asm__("orw %1,%0" : "=r" (dest) : \
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"ri" ((unsigned short)src) , "0" (dest))
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#define _ord_(src, dest) __asm__("ord %1,%0" : "=r" (dest) : \
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"ri" ((unsigned int)src) , "0" (dest))
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/* retx Instruction */
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#define _retx_() __asm__("retx")
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/* Set Bit Instructions */
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#define _sbitb_(pos, dest) __asm__("sbitb %1,%0" : "=mr" (dest) : \
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"i" ((unsigned char)pos) , "0" (dest) : "cc")
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#define _sbitw_(pos, dest) __asm__("sbitw %1,%0" : "=mr" (dest) : \
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"i" ((unsigned char)pos) , "0" (dest) : "cc")
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/* spr and sprd Instructions */
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#define _spr_(procreg, dest) __asm__("spr\t" procreg ",%0" : \
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"=r" (dest) : /* no input */ "0" (dest) : "cc")
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#define _sprd_(procregd, dest) __asm__("sprd\t" procregd ",%0" : \
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"=r" (dest) : /* no input */ "0" (dest) : "cc")
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/* Store Instructions */
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#define _storb_(src, address) __asm__("storb %1,%0" : "=m" (address) : \
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"ri" ((unsigned int)src))
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#define _storw_(src, address) __asm__("storw %1,%0" : "=m" (address) : \
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"ri" ((unsigned int)src))
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#define _stord_(src, address) __asm__("stord %1,%0" : "=m" (address) : \
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"ri" ((unsigned int)src))
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/* Store Multiple Instructions */
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#define _storm_(mask, src) __asm__("storm %1,%0" : /* No output here */ : \
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"i" (mask) , "r" ((unsigned int)src))
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#define _stormp_(mask, src) __asm__("stormp %1,%0" : /* No output here */ : \
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"i" (mask) , "r" ((unsigned int)src))
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/* Substruct Instructions */
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#define _subb_(src, dest) __asm__("subb %1, %0" : "=r" (dest) : \
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"ri" ((unsigned char)src), "0" (dest) : "cc")
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#define _subw_(src, dest) __asm__("subw %1, %0" : "=r" (dest) : \
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"ri" ((unsigned short)src), "0" (dest) : "cc")
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#define _subd_(src, dest) __asm__("subd %1, %0" : "=r" (dest) : \
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"ri" ((unsigned long)src), "0" (dest) : "cc")
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/* Substruct with Carry Instructions */
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#define _subcb_(src, dest) __asm__("subcb %1, %0" : "=r" (dest) : \
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"ri" ((unsigned char)src), "0" (dest) : "cc")
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#define _subcw_(src, dest) __asm__("subcw %1, %0" : "=r" (dest) : \
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"ri" ((unsigned short)src), "0" (dest) : "cc")
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/* Test Bit Instructions */
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#define _tbit_(offset, base) __asm__("tbit %0,%1" : /* no output */ : \
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"ri" ((unsigned char)offset) , "r" (base) : "cc")
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#define _tbitb_(pos, dest) __asm__("tbitb %0,%1" : /* No output */ : \
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"i" ((unsigned char)pos) , "m" (dest) : "cc")
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#define _tbitw_(pos, dest) __asm__("tbitw %0,%1" : /* No output */ : \
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"i" ((unsigned char)pos) , "m" (dest) : "cc")
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/* wait Instruction*/
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#define _wait_() __asm__ volatile ("wait" : : : "cc")
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/* xor Instructions */
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#define _xorb_(src, dest) __asm__("xorb %1,%0" : "=r" (dest) : \
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"ri" ((unsigned char)src) , "0" (dest))
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#define _xorw_(src, dest) __asm__("xorw %1,%0" : "=r" (dest) : \
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"ri" ((unsigned short)src) , "0" (dest))
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#define _xord_(src, dest) __asm__("xord %1,%0" : "=r" (dest) : \
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"ri" ((unsigned long)src) , "0" (dest))
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#if !defined (__CR16C__)
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#define _di_() __asm__ volatile ("di\n" : : : "cc")
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#else
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/* In CR16C architecture the "nop" instruction is required after the di instruction
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in order to be sure the interrupts are indeed disabled.
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For details, refer the the CR16C Programmers Reference Manual. */
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#define _di_() __asm__ volatile ("di\n\tnop" : : : "cc")
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#endif
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/* mtgpr Instruction */
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#define _mtgpr_(src, gpr) \
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__asm__ volatile ("movd\t%[_src], " gpr : /* no output */ \
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: [_src] "ri" (src) \
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: gpr )
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/* mfgpr Instruction */
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#define _mfgpr_(gpr, dest) \
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__asm__ volatile ("movd\t" gpr ", %[_dest]" : [_dest] "=r" (dest) \
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: /* no inputs */ )
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/* set_i_bit Operation Definition */
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#define set_i_bit() \
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do \
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{ \
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unsigned short tpsr; \
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_spr_("psr", tpsr); \
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tpsr |= 0x0800; \
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_lpr_("psr",tpsr); \
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} while(0)
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/* set_i_bit Macro Definition */
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#define _enable_global_interrupt_ set_i_bit
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/* clear_i_bit Operation Definition */
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#define clear_i_bit() \
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do \
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{ \
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unsigned short tpsr; \
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_spr_("psr", tpsr); \
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tpsr &= 0xf7ff; \
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_lpr_("psr",tpsr); \
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} while(0)
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/* clear_i_bit Macro Definition */
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#define _disbale_global_interrupt_ clear_i_bit
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#define _save_asm_(x) \
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__asm__ volatile (x ::: "memory","cc", \
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"r0","r1","r2","r3","r4","r5","r6","r7", \
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"r8","r9","r10","r11","r12","r13")
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#endif /* _ASM */
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