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160 lines
3.9 KiB
ArmAsm
160 lines
3.9 KiB
ArmAsm
/* This is a simple version of setjmp and longjmp for MIPS 32 and 64.
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Ian Lance Taylor, Cygnus Support, 13 May 1993. */
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#ifdef __mips16
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/* This file contains 32 bit assembly code. */
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.set nomips16
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#endif
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#define GPR_LAYOUT \
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GPR_OFFSET ($16, 0); \
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GPR_OFFSET ($17, 1); \
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GPR_OFFSET ($18, 2); \
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GPR_OFFSET ($19, 3); \
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GPR_OFFSET ($20, 4); \
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GPR_OFFSET ($21, 5); \
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GPR_OFFSET ($22, 6); \
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GPR_OFFSET ($23, 7); \
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GPR_OFFSET ($29, 8); \
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GPR_OFFSET ($30, 9); \
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GPR_OFFSET ($31, 10)
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#define NUM_GPRS_SAVED 11
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#ifdef __mips_hard_float
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#if _MIPS_SIM == _ABIN32
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#define FPR_LAYOUT \
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FPR_OFFSET ($f20, 0); \
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FPR_OFFSET ($f22, 1); \
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FPR_OFFSET ($f24, 2); \
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FPR_OFFSET ($f26, 3); \
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FPR_OFFSET ($f28, 4); \
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FPR_OFFSET ($f30, 5);
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#elif _MIPS_SIM == _ABI64
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#define FPR_LAYOUT \
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FPR_OFFSET ($f24, 0); \
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FPR_OFFSET ($f25, 1); \
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FPR_OFFSET ($f26, 2); \
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FPR_OFFSET ($f27, 3); \
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FPR_OFFSET ($f28, 4); \
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FPR_OFFSET ($f29, 5); \
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FPR_OFFSET ($f30, 6); \
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FPR_OFFSET ($f31, 7);
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#elif __mips_fpr == 0 || __mips_fpr == 64
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/* This deals with the o32 FPXX and FP64 cases. Here we must use
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SDC1 and LDC1 to access the FPRs. These instructions require
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8-byte aligned addresses.
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Unfortunately, the MIPS jmp_buf only guarantees 4-byte alignment
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and this cannot be increased without breaking compatibility with
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pre-existing objects built against newlib. There are 11 GPRS
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saved in the jmp_buf so a buffer that happens to be 8-byte aligned
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ends up leaving the FPR slots 4-byte aligned and an (only) 4-byte
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aligned buffer leads to the FPR slots being 8-byte aligned!
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To resolve this, we move the location of $31 to the last slot
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in the jmp_buf when the overall buffer is 8-byte aligned. $31
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is simply loaded/stored twice to avoid adding complexity to the
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GPR_LAYOUT macro above as well as FPR_LAYOUT.
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The location of the last slot is index 22 which is calculated
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from there being 11 GPRs saved and then 12 FPRs saved so the
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index of the last FPR is 11+11.
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The base of the jmp_buf is modified in $4 to allow the
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FPR_OFFSET macros to just use the usual constant slot numbers
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regardless of whether the realignment happened or not. */
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#define FPR_LAYOUT \
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and $8, $4, 4; \
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bne $8, $0, 1f; \
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GPR_OFFSET ($31, 22); \
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addiu $4, $4, -4; \
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1: \
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FPR_OFFSET ($f20, 0); \
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FPR_OFFSET ($f22, 2); \
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FPR_OFFSET ($f24, 4); \
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FPR_OFFSET ($f26, 6); \
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FPR_OFFSET ($f28, 8); \
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FPR_OFFSET ($f30, 10);
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#else /* Assuming _MIPS_SIM == _ABIO32 */
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#define FPR_LAYOUT \
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FPR_OFFSET ($f20, 0); \
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FPR_OFFSET ($f21, 1); \
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FPR_OFFSET ($f22, 2); \
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FPR_OFFSET ($f23, 3); \
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FPR_OFFSET ($f24, 4); \
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FPR_OFFSET ($f25, 5); \
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FPR_OFFSET ($f26, 6); \
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FPR_OFFSET ($f27, 7); \
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FPR_OFFSET ($f28, 8); \
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FPR_OFFSET ($f29, 9); \
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FPR_OFFSET ($f30, 10); \
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FPR_OFFSET ($f31, 11);
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#endif
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#else
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#define FPR_LAYOUT
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#endif
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#ifdef __mips64
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#define BYTES_PER_WORD 8
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#define LOAD_GPR ld
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#define LOAD_FPR ldc1
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#define STORE_GPR sd
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#define STORE_FPR sdc1
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#else
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#define LOAD_GPR lw
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#define STORE_GPR sw
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#define BYTES_PER_WORD 4
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#if __mips_fpr == 0 || __mips_fpr == 64
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#define LOAD_FPR ldc1
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#define STORE_FPR sdc1
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#else
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#define LOAD_FPR lwc1
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#define STORE_FPR swc1
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#endif
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#endif
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#define GPOFF(INDEX) (INDEX * BYTES_PER_WORD)
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#define FPOFF(INDEX) ((INDEX + NUM_GPRS_SAVED) * BYTES_PER_WORD)
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/* int setjmp (jmp_buf); */
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.globl setjmp
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.ent setjmp
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setjmp:
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.frame $sp,0,$31
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#define GPR_OFFSET(REG, INDEX) STORE_GPR REG,GPOFF(INDEX)($4)
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#define FPR_OFFSET(REG, INDEX) STORE_FPR REG,FPOFF(INDEX)($4)
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GPR_LAYOUT
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FPR_LAYOUT
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#undef GPR_OFFSET
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#undef FPR_OFFSET
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move $2,$0
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j $31
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.end setjmp
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/* volatile void longjmp (jmp_buf, int); */
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.globl longjmp
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.ent longjmp
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longjmp:
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.frame $sp,0,$31
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#define GPR_OFFSET(REG, INDEX) LOAD_GPR REG,GPOFF(INDEX)($4)
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#define FPR_OFFSET(REG, INDEX) LOAD_FPR REG,FPOFF(INDEX)($4)
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GPR_LAYOUT
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FPR_LAYOUT
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#undef GPR_OFFSET
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#undef FPR_OFFSET
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bne $5,$0,1f
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li $5,1
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1:
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move $2,$5
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j $31
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.end longjmp
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