mirror of
https://github.com/autc04/Retro68.git
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1133 lines
39 KiB
D
1133 lines
39 KiB
D
/**
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* Identify the characteristics of the host CPU, providing information
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* about cache sizes and assembly optimisation hints. This module is
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* provided primarily for assembly language programmers.
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*
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* References:
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* Some of this information was extremely difficult to track down. Some of the
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* documents below were found only in cached versions stored by search engines!
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* This code relies on information found in:
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*
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* $(UL
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* $(LI "Intel(R) 64 and IA-32 Architectures Software Developers Manual,
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* Volume 2A: Instruction Set Reference, A-M" (2007).
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* )
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* $(LI "AMD CPUID Specification", Advanced Micro Devices, Rev 2.28 (2008).
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* )
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* $(LI "AMD Processor Recognition Application Note For Processors Prior to AMD
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* Family 0Fh Processors", Advanced Micro Devices, Rev 3.13 (2005).
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* )
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* $(LI "AMD Geode(TM) GX Processors Data Book",
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* Advanced Micro Devices, Publication ID 31505E, (2005).
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* )
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* $(LI "AMD K6 Processor Code Optimisation", Advanced Micro Devices, Rev D (2000).
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* )
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* $(LI "Application note 106: Software Customization for the 6x86 Family",
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* Cyrix Corporation, Rev 1.5 (1998)
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* )
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* $(LI $(LINK http://www.datasheetcatalog.org/datasheet/nationalsemiconductor/GX1.pdf))
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* $(LI "Geode(TM) GX1 Processor Series Low Power Integrated X86 Solution",
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* National Semiconductor, (2002)
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* )
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* $(LI "The VIA Isaiah Architecture", G. Glenn Henry, Centaur Technology, Inc (2008).
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* )
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* $(LI $(LINK http://www.sandpile.org/ia32/cpuid.htm))
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* $(LI $(LINK http://www.akkadia.org/drepper/cpumemory.pdf))
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* $(LI "What every programmer should know about memory",
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* Ulrich Depper, Red Hat, Inc., (2007).
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* )
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* $(LI "CPU Identification by the Windows Kernel", G. Chappell (2009).
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* $(LINK http://www.geoffchappell.com/viewer.htm?doc=studies/windows/km/cpu/cx8.htm)
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* )
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* $(LI "Intel(R) Processor Identification and the CPUID Instruction, Application
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* Note 485" (2009).
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* )
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* )
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*
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* Bugs: Currently only works on x86 and Itanium CPUs.
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* Many processors have bugs in their microcode for the CPUID instruction,
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* so sometimes the cache information may be incorrect.
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*
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* Copyright: Copyright Don Clugston 2007 - 2009.
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* License: $(LINK2 http://www.boost.org/LICENSE_1_0.txt, Boost License 1.0)
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* Authors: Don Clugston, Tomas Lindquist Olsen <tomas@famolsen.dk>
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* Source: $(DRUNTIMESRC core/_cpuid.d)
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*/
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module core.cpuid;
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@trusted:
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nothrow:
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@nogc:
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// If optimizing for a particular processor, it is generally better
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// to identify based on features rather than model. NOTE: Normally
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// it's only worthwhile to optimise for the latest Intel and AMD CPU,
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// with a backup for other CPUs.
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// Pentium -- preferPentium1()
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// PMMX -- + mmx()
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// PPro -- default
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// PII -- + mmx()
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// PIII -- + mmx() + sse()
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// PentiumM -- + mmx() + sse() + sse2()
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// Pentium4 -- preferPentium4()
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// PentiumD -- + isX86_64()
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// Core2 -- default + isX86_64()
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// AMD K5 -- preferPentium1()
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// AMD K6 -- + mmx()
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// AMD K6-II -- + mmx() + 3dnow()
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// AMD K7 -- preferAthlon()
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// AMD K8 -- + sse2()
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// AMD K10 -- + isX86_64()
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// Cyrix 6x86 -- preferPentium1()
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// 6x86MX -- + mmx()
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// GDC support uses extended inline assembly:
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// https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html (general information and hints)
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// https://gcc.gnu.org/onlinedocs/gcc/Simple-Constraints.html (binding variables to registers)
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// https://gcc.gnu.org/onlinedocs/gcc/Machine-Constraints.html (x86 specific register short names)
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public:
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/// Cache size and behaviour
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struct CacheInfo
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{
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/// Size of the cache, in kilobytes, per CPU.
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/// For L1 unified (data + code) caches, this size is half the physical size.
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/// (we don't halve it for larger sizes, since normally
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/// data size is much greater than code size for critical loops).
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size_t size;
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/// Number of ways of associativity, eg:
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/// $(UL
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/// $(LI 1 = direct mapped)
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/// $(LI 2 = 2-way set associative)
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/// $(LI 3 = 3-way set associative)
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/// $(LI ubyte.max = fully associative)
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/// )
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ubyte associativity;
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/// Number of bytes read into the cache when a cache miss occurs.
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uint lineSize;
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}
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public:
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/// $(RED Scheduled for deprecation. Please use $(D dataCaches) instead.)
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// Note: When we deprecate it, we simply make it private.
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__gshared CacheInfo[5] datacache;
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@property pure
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{
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/// The data caches. If there are fewer than 5 physical caches levels,
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/// the remaining levels are set to size_t.max (== entire memory space)
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const(CacheInfo)[5] dataCaches() { return _dataCaches; }
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/// Returns vendor string, for display purposes only.
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/// Do NOT use this to determine features!
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/// Note that some CPUs have programmable vendorIDs.
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string vendor() {return _vendor;}
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/// Returns processor string, for display purposes only
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string processor() {return _processor;}
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/// Does it have an x87 FPU on-chip?
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bool x87onChip() {return _x87onChip;}
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/// Is MMX supported?
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bool mmx() {return _mmx;}
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/// Is SSE supported?
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bool sse() {return _sse;}
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/// Is SSE2 supported?
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bool sse2() {return _sse2;}
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/// Is SSE3 supported?
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bool sse3() {return _sse3;}
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/// Is SSSE3 supported?
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bool ssse3() {return _ssse3;}
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/// Is SSE4.1 supported?
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bool sse41() {return _sse41;}
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/// Is SSE4.2 supported?
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bool sse42() {return _sse42;}
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/// Is SSE4a supported?
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bool sse4a() {return _sse4a;}
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/// Is AES supported
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bool aes() {return _aes;}
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/// Is pclmulqdq supported
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bool hasPclmulqdq() {return _hasPclmulqdq;}
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/// Is rdrand supported
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bool hasRdrand() {return _hasRdrand;}
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/// Is AVX supported
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bool avx() {return _avx;}
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/// Is VEX-Encoded AES supported
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bool vaes() {return _vaes;}
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/// Is vpclmulqdq supported
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bool hasVpclmulqdq(){return _hasVpclmulqdq; }
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/// Is FMA supported
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bool fma() {return _fma;}
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/// Is FP16C supported
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bool fp16c() {return _fp16c;}
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/// Is AVX2 supported
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bool avx2() {return _avx2;}
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/// Is HLE (hardware lock elision) supported
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bool hle() {return _hle;}
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/// Is RTM (restricted transactional memory) supported
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bool rtm() {return _rtm;}
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/// Is rdseed supported
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bool hasRdseed() {return _hasRdseed;}
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/// Is SHA supported
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bool hasSha() {return _hasSha;}
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/// Is AMD 3DNOW supported?
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bool amd3dnow() {return _amd3dnow;}
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/// Is AMD 3DNOW Ext supported?
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bool amd3dnowExt() {return _amd3dnowExt;}
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/// Are AMD extensions to MMX supported?
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bool amdMmx() {return _amdMmx;}
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/// Is fxsave/fxrstor supported?
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bool hasFxsr() {return _hasFxsr;}
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/// Is cmov supported?
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bool hasCmov() {return _hasCmov;}
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/// Is rdtsc supported?
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bool hasRdtsc() {return _hasRdtsc;}
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/// Is cmpxchg8b supported?
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bool hasCmpxchg8b() {return _hasCmpxchg8b;}
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/// Is cmpxchg8b supported?
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bool hasCmpxchg16b() {return _hasCmpxchg16b;}
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/// Is SYSENTER/SYSEXIT supported?
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bool hasSysEnterSysExit() {return _hasSysEnterSysExit;}
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/// Is 3DNow prefetch supported?
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bool has3dnowPrefetch() {return _has3dnowPrefetch;}
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/// Are LAHF and SAHF supported in 64-bit mode?
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bool hasLahfSahf() {return _hasLahfSahf;}
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/// Is POPCNT supported?
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bool hasPopcnt() {return _hasPopcnt;}
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/// Is LZCNT supported?
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bool hasLzcnt() {return _hasLzcnt;}
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/// Is this an Intel64 or AMD 64?
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bool isX86_64() {return _isX86_64;}
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/// Is this an IA64 (Itanium) processor?
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bool isItanium() { return _isItanium; }
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/// Is hyperthreading supported?
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bool hyperThreading() { return _hyperThreading; }
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/// Returns number of threads per CPU
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uint threadsPerCPU() {return _threadsPerCPU;}
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/// Returns number of cores in CPU
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uint coresPerCPU() {return _coresPerCPU;}
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/// Optimisation hints for assembly code.
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///
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/// For forward compatibility, the CPU is compared against different
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/// microarchitectures. For 32-bit x86, comparisons are made against
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/// the Intel PPro/PII/PIII/PM family.
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///
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/// The major 32-bit x86 microarchitecture 'dynasties' have been:
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///
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/// $(UL
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/// $(LI Intel P6 (PentiumPro, PII, PIII, PM, Core, Core2). )
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/// $(LI AMD Athlon (K7, K8, K10). )
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/// $(LI Intel NetBurst (Pentium 4, Pentium D). )
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/// $(LI In-order Pentium (Pentium1, PMMX, Atom) )
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/// )
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///
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/// Other early CPUs (Nx586, AMD K5, K6, Centaur C3, Transmeta,
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/// Cyrix, Rise) were mostly in-order.
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///
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/// Some new processors do not fit into the existing categories:
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///
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/// $(UL
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/// $(LI Intel Atom 230/330 (family 6, model 0x1C) is an in-order core. )
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/// $(LI Centaur Isiah = VIA Nano (family 6, model F) is an out-of-order core. )
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/// )
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///
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/// Within each dynasty, the optimisation techniques are largely
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/// identical (eg, use instruction pairing for group 4). Major
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/// instruction set improvements occur within each dynasty.
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/// Does this CPU perform better on AMD K7 code than PentiumPro..Core2 code?
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bool preferAthlon() { return _preferAthlon; }
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/// Does this CPU perform better on Pentium4 code than PentiumPro..Core2 code?
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bool preferPentium4() { return _preferPentium4; }
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/// Does this CPU perform better on Pentium I code than Pentium Pro code?
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bool preferPentium1() { return _preferPentium1; }
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}
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private immutable
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{
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/* These exist as immutables so that the query property functions can
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* be backwards compatible with code that called them with ().
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* Also, immutables can only be set by the static this().
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*/
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const(CacheInfo)[5] _dataCaches;
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string _vendor;
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string _processor;
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bool _x87onChip;
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bool _mmx;
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bool _sse;
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bool _sse2;
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bool _sse3;
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bool _ssse3;
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bool _sse41;
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bool _sse42;
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bool _sse4a;
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bool _aes;
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bool _hasPclmulqdq;
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bool _hasRdrand;
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bool _avx;
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bool _vaes;
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bool _hasVpclmulqdq;
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bool _fma;
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bool _fp16c;
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bool _avx2;
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bool _hle;
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bool _rtm;
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bool _hasRdseed;
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bool _hasSha;
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bool _amd3dnow;
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bool _amd3dnowExt;
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bool _amdMmx;
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bool _hasFxsr;
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bool _hasCmov;
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bool _hasRdtsc;
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bool _hasCmpxchg8b;
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bool _hasCmpxchg16b;
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bool _hasSysEnterSysExit;
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bool _has3dnowPrefetch;
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bool _hasLahfSahf;
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bool _hasPopcnt;
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bool _hasLzcnt;
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bool _isX86_64;
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bool _isItanium;
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bool _hyperThreading;
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uint _threadsPerCPU;
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uint _coresPerCPU;
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bool _preferAthlon;
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bool _preferPentium4;
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bool _preferPentium1;
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}
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__gshared:
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// All these values are set only once, and never subsequently modified.
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public:
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/// $(RED Warning: This field will be turned into a property in a future release.)
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///
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/// Processor type (vendor-dependent).
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/// This should be visible ONLY for display purposes.
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uint stepping, model, family;
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/// $(RED This field has been deprecated. Please use $(D cacheLevels) instead.)
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uint numCacheLevels = 1;
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/// The number of cache levels in the CPU.
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@property uint cacheLevels() { return numCacheLevels; }
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private:
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struct CpuFeatures
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{
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bool probablyIntel; // true = _probably_ an Intel processor, might be faking
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bool probablyAMD; // true = _probably_ an AMD processor
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string processorName;
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char [12] vendorID;
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char [48] processorNameBuffer;
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uint features = 0; // mmx, sse, sse2, hyperthreading, etc
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uint miscfeatures = 0; // sse3, etc.
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uint extfeatures = 0; // HLE, AVX2, RTM, etc.
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uint amdfeatures = 0; // 3DNow!, mmxext, etc
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uint amdmiscfeatures = 0; // sse4a, sse5, svm, etc
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ulong xfeatures = 0; // XFEATURES_ENABLED_MASK
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uint maxCores = 1;
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uint maxThreads = 1;
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}
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CpuFeatures cpuFeatures;
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/* Hide from the optimizer where cf (a register) is coming from, so that
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* cf doesn't get "optimized away". The idea is to reference
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* the global data through cf so not so many fixups are inserted
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* into the executable image.
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*/
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CpuFeatures* getCpuFeatures() @nogc nothrow
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{
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pragma(inline, false);
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return &cpuFeatures;
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}
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// Note that this may indicate multi-core rather than hyperthreading.
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@property bool hyperThreadingBit() { return (cpuFeatures.features&HTT_BIT)!=0;}
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// feature flags CPUID1_EDX
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enum : uint
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{
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FPU_BIT = 1,
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TIMESTAMP_BIT = 1<<4, // rdtsc
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MDSR_BIT = 1<<5, // RDMSR/WRMSR
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CMPXCHG8B_BIT = 1<<8,
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SYSENTERSYSEXIT_BIT = 1<<11,
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CMOV_BIT = 1<<15,
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MMX_BIT = 1<<23,
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FXSR_BIT = 1<<24,
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SSE_BIT = 1<<25,
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SSE2_BIT = 1<<26,
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HTT_BIT = 1<<28,
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IA64_BIT = 1<<30
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}
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// feature flags misc CPUID1_ECX
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enum : uint
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{
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SSE3_BIT = 1,
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PCLMULQDQ_BIT = 1<<1, // from AVX
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MWAIT_BIT = 1<<3,
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SSSE3_BIT = 1<<9,
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FMA_BIT = 1<<12, // from AVX
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CMPXCHG16B_BIT = 1<<13,
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SSE41_BIT = 1<<19,
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SSE42_BIT = 1<<20,
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POPCNT_BIT = 1<<23,
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AES_BIT = 1<<25, // AES instructions from AVX
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OSXSAVE_BIT = 1<<27, // Used for AVX
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AVX_BIT = 1<<28,
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FP16C_BIT = 1<<29,
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RDRAND_BIT = 1<<30,
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}
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// Feature flags for cpuid.{EAX = 7, ECX = 0}.EBX.
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enum : uint
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{
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FSGSBASE_BIT = 1 << 0,
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BMI1_BIT = 1 << 3,
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HLE_BIT = 1 << 4,
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AVX2_BIT = 1 << 5,
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SMEP_BIT = 1 << 7,
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BMI2_BIT = 1 << 8,
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ERMS_BIT = 1 << 9,
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INVPCID_BIT = 1 << 10,
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RTM_BIT = 1 << 11,
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RDSEED_BIT = 1 << 18,
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SHA_BIT = 1 << 29,
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}
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// feature flags XFEATURES_ENABLED_MASK
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enum : ulong
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{
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XF_FP_BIT = 0x1,
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XF_SSE_BIT = 0x2,
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XF_YMM_BIT = 0x4,
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}
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// AMD feature flags CPUID80000001_EDX
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enum : uint
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{
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AMD_MMX_BIT = 1<<22,
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// FXR_OR_CYRIXMMX_BIT = 1<<24, // Cyrix/NS: 6x86MMX instructions.
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FFXSR_BIT = 1<<25,
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PAGE1GB_BIT = 1<<26, // support for 1GB pages
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RDTSCP_BIT = 1<<27,
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AMD64_BIT = 1<<29,
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AMD_3DNOW_EXT_BIT = 1<<30,
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AMD_3DNOW_BIT = 1<<31
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}
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// AMD misc feature flags CPUID80000001_ECX
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enum : uint
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{
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LAHFSAHF_BIT = 1,
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LZCNT_BIT = 1<<5,
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SSE4A_BIT = 1<<6,
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AMD_3DNOW_PREFETCH_BIT = 1<<8,
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}
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version (GNU) {
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version (X86)
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enum supportedX86 = true;
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else version (X86_64)
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enum supportedX86 = true;
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else
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enum supportedX86 = false;
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} else version (D_InlineAsm_X86) {
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enum supportedX86 = true;
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} else version (D_InlineAsm_X86_64) {
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enum supportedX86 = true;
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} else {
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enum supportedX86 = false;
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}
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static if (supportedX86) {
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// Note that this code will also work for Itanium in x86 mode.
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__gshared uint max_cpuid, max_extended_cpuid;
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// CPUID2: "cache and tlb information"
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void getcacheinfoCPUID2()
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{
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// We are only interested in the data caches
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|
void decipherCpuid2(ubyte x) @nogc nothrow {
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if (x==0) return;
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// Values from http://www.sandpile.org/ia32/cpuid.htm.
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|
// Includes Itanium and non-Intel CPUs.
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//
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static immutable ubyte [63] ids = [
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0x0A, 0x0C, 0x0D, 0x2C, 0x60, 0x0E, 0x66, 0x67, 0x68,
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// level 2 cache
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0x41, 0x42, 0x43, 0x44, 0x45, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7F,
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0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x49, 0x4E,
|
|
0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x48, 0x80, 0x81,
|
|
// level 3 cache
|
|
0x22, 0x23, 0x25, 0x29, 0x46, 0x47, 0x4A, 0x4B, 0x4C, 0x4D,
|
|
|
|
0xD0, 0xD1, 0xD2, 0xD6, 0xD7, 0xD8, 0xDC, 0xDD, 0xDE,
|
|
0xE2, 0xE3, 0xE4, 0xEA, 0xEB, 0xEC
|
|
];
|
|
static immutable uint [63] sizes = [
|
|
8, 16, 16, 64, 16, 24, 8, 16, 32,
|
|
128, 256, 512, 1024, 2048, 1024, 128, 256, 512, 1024, 2048, 512,
|
|
256, 512, 1024, 2048, 512, 1024, 4096, 6*1024,
|
|
128, 192, 128, 256, 384, 512, 3072, 512, 128,
|
|
512, 1024, 2048, 4096, 4096, 8192, 6*1024, 8192, 12*1024, 16*1024,
|
|
|
|
512, 1024, 2048, 1024, 2048, 4096, 1024+512, 3*1024, 6*1024,
|
|
2*1024, 4*1024, 8*1024, 12*1024, 28*1024, 24*1024
|
|
];
|
|
// CPUBUG: Pentium M reports 0x2C but tests show it is only 4-way associative
|
|
static immutable ubyte [63] ways = [
|
|
2, 4, 4, 8, 8, 6, 4, 4, 4,
|
|
4, 4, 4, 4, 4, 4, 8, 8, 8, 8, 8, 2,
|
|
8, 8, 8, 8, 4, 8, 16, 24,
|
|
4, 6, 2, 4, 6, 4, 12, 8, 8,
|
|
4, 8, 8, 8, 4, 8, 12, 16, 12, 16,
|
|
4, 4, 4, 8, 8, 8, 12, 12, 12,
|
|
16, 16, 16, 24, 24, 24
|
|
];
|
|
enum { FIRSTDATA2 = 8, FIRSTDATA3 = 28+9 }
|
|
for (size_t i=0; i< ids.length; ++i) {
|
|
if (x==ids[i]) {
|
|
int level = i< FIRSTDATA2 ? 0: i<FIRSTDATA3 ? 1 : 2;
|
|
if (x==0x49 && family==0xF && model==0x6) level=2;
|
|
datacache[level].size=sizes[i];
|
|
datacache[level].associativity=ways[i];
|
|
if (level == 3 || x==0x2C || x==0x0D || (x>=0x48 && x<=0x80)
|
|
|| x==0x86 || x==0x87
|
|
|| (x>=0x66 && x<=0x68) || (x>=0x39 && x<=0x3E)){
|
|
datacache[level].lineSize = 64;
|
|
} else datacache[level].lineSize = 32;
|
|
}
|
|
}
|
|
}
|
|
|
|
uint[4] a;
|
|
bool firstTime = true;
|
|
// On a multi-core system, this could theoretically fail, but it's only used
|
|
// for old single-core CPUs.
|
|
uint numinfos = 1;
|
|
do {
|
|
version (GNU) asm pure nothrow @nogc {
|
|
"cpuid" : "=a" a[0], "=b" a[1], "=c" a[2], "=d" a[3] : "a" 2;
|
|
} else asm pure nothrow @nogc {
|
|
mov EAX, 2;
|
|
cpuid;
|
|
mov a, EAX;
|
|
mov a+4, EBX;
|
|
mov a+8, ECX;
|
|
mov a+12, EDX;
|
|
}
|
|
if (firstTime) {
|
|
if (a[0]==0x0000_7001 && a[3]==0x80 && a[1]==0 && a[2]==0) {
|
|
// Cyrix MediaGX MMXEnhanced returns: EAX= 00007001, EDX=00000080.
|
|
// These are NOT standard Intel values
|
|
// (TLB = 32 entry, 4 way associative, 4K pages)
|
|
// (L1 cache = 16K, 4way, linesize16)
|
|
datacache[0].size=8;
|
|
datacache[0].associativity=4;
|
|
datacache[0].lineSize=16;
|
|
return;
|
|
}
|
|
// lsb of a is how many times to loop.
|
|
numinfos = a[0] & 0xFF;
|
|
// and otherwise it should be ignored
|
|
a[0] &= 0xFFFF_FF00;
|
|
firstTime = false;
|
|
}
|
|
for (int c=0; c<4;++c) {
|
|
// high bit set == no info.
|
|
if (a[c] & 0x8000_0000) continue;
|
|
decipherCpuid2(cast(ubyte)(a[c] & 0xFF));
|
|
decipherCpuid2(cast(ubyte)((a[c]>>8) & 0xFF));
|
|
decipherCpuid2(cast(ubyte)((a[c]>>16) & 0xFF));
|
|
decipherCpuid2(cast(ubyte)((a[c]>>24) & 0xFF));
|
|
}
|
|
} while (--numinfos);
|
|
}
|
|
|
|
// CPUID4: "Deterministic cache parameters" leaf
|
|
void getcacheinfoCPUID4()
|
|
{
|
|
int cachenum = 0;
|
|
for (;;) {
|
|
uint a, b, number_of_sets;
|
|
version (GNU) asm pure nothrow @nogc {
|
|
"cpuid" : "=a" a, "=b" b, "=c" number_of_sets : "a" 4, "c" cachenum : "edx";
|
|
} else asm pure nothrow @nogc {
|
|
mov EAX, 4;
|
|
mov ECX, cachenum;
|
|
cpuid;
|
|
mov a, EAX;
|
|
mov b, EBX;
|
|
mov number_of_sets, ECX;
|
|
}
|
|
++cachenum;
|
|
if ((a&0x1F)==0) break; // no more caches
|
|
immutable uint numthreads = ((a>>14) & 0xFFF) + 1;
|
|
immutable uint numcores = ((a>>26) & 0x3F) + 1;
|
|
if (numcores > cpuFeatures.maxCores) cpuFeatures.maxCores = numcores;
|
|
if ((a&0x1F)!=1 && ((a&0x1F)!=3)) continue; // we only want data & unified caches
|
|
|
|
++number_of_sets;
|
|
immutable ubyte level = cast(ubyte)(((a>>5)&7)-1);
|
|
if (level > datacache.length) continue; // ignore deep caches
|
|
datacache[level].associativity = a & 0x200 ? ubyte.max :cast(ubyte)((b>>22)+1);
|
|
datacache[level].lineSize = (b & 0xFFF)+ 1; // system coherency line size
|
|
immutable uint line_partitions = ((b >> 12)& 0x3FF) + 1;
|
|
// Size = number of sets * associativity * cachelinesize * linepartitions
|
|
// and must convert to Kb, also dividing by the number of hyperthreads using this cache.
|
|
immutable ulong sz = (datacache[level].associativity< ubyte.max)? number_of_sets *
|
|
datacache[level].associativity : number_of_sets;
|
|
datacache[level].size = cast(size_t)(
|
|
(sz * datacache[level].lineSize * line_partitions ) / (numthreads *1024));
|
|
if (level == 0 && (a&0xF)==3) {
|
|
// Halve the size for unified L1 caches
|
|
datacache[level].size/=2;
|
|
}
|
|
}
|
|
}
|
|
|
|
// CPUID8000_0005 & 6
|
|
void getAMDcacheinfo()
|
|
{
|
|
uint dummy, c5, c6, d6;
|
|
version (GNU) asm pure nothrow @nogc {
|
|
"cpuid" : "=a" dummy, "=c" c5 : "a" 0x8000_0005 : "ebx", "edx";
|
|
} else asm pure nothrow @nogc {
|
|
mov EAX, 0x8000_0005; // L1 cache
|
|
cpuid;
|
|
// EAX has L1_TLB_4M.
|
|
// EBX has L1_TLB_4K
|
|
// EDX has L1 instruction cache
|
|
mov c5, ECX;
|
|
}
|
|
|
|
datacache[0].size = ( (c5>>24) & 0xFF);
|
|
datacache[0].associativity = cast(ubyte)( (c5 >> 16) & 0xFF);
|
|
datacache[0].lineSize = c5 & 0xFF;
|
|
|
|
if (max_extended_cpuid >= 0x8000_0006) {
|
|
// AMD K6-III or K6-2+ or later.
|
|
ubyte numcores = 1;
|
|
if (max_extended_cpuid >= 0x8000_0008) {
|
|
version (GNU) asm pure nothrow @nogc {
|
|
"cpuid" : "=a" dummy, "=c" numcores : "a" 0x8000_0008 : "ebx", "edx";
|
|
} else asm pure nothrow @nogc {
|
|
mov EAX, 0x8000_0008;
|
|
cpuid;
|
|
mov numcores, CL;
|
|
}
|
|
++numcores;
|
|
if (numcores>cpuFeatures.maxCores) cpuFeatures.maxCores = numcores;
|
|
}
|
|
|
|
version (GNU) asm pure nothrow @nogc {
|
|
"cpuid" : "=a" dummy, "=c" c6, "=d" d6 : "a" 0x8000_0006 : "ebx";
|
|
} else asm pure nothrow @nogc {
|
|
mov EAX, 0x8000_0006; // L2/L3 cache
|
|
cpuid;
|
|
mov c6, ECX; // L2 cache info
|
|
mov d6, EDX; // L3 cache info
|
|
}
|
|
|
|
static immutable ubyte [] assocmap = [ 0, 1, 2, 0, 4, 0, 8, 0, 16, 0, 32, 48, 64, 96, 128, 0xFF ];
|
|
datacache[1].size = (c6>>16) & 0xFFFF;
|
|
datacache[1].associativity = assocmap[(c6>>12)&0xF];
|
|
datacache[1].lineSize = c6 & 0xFF;
|
|
|
|
// The L3 cache value is TOTAL, not per core.
|
|
datacache[2].size = ((d6>>18)*512)/numcores; // could be up to 2 * this, -1.
|
|
datacache[2].associativity = assocmap[(d6>>12)&0xF];
|
|
datacache[2].lineSize = d6 & 0xFF;
|
|
}
|
|
}
|
|
|
|
// For Intel CoreI7 and later, use function 0x0B
|
|
// to determine number of processors.
|
|
void getCpuInfo0B()
|
|
{
|
|
int level=0;
|
|
int threadsPerCore;
|
|
uint a, b, c, d;
|
|
do {
|
|
version (GNU) asm pure nothrow @nogc {
|
|
"cpuid" : "=a" a, "=b" b, "=c" c, "=d" d : "a" 0x0B, "c" level;
|
|
} else asm pure nothrow @nogc {
|
|
mov EAX, 0x0B;
|
|
mov ECX, level;
|
|
cpuid;
|
|
mov a, EAX;
|
|
mov b, EBX;
|
|
mov c, ECX;
|
|
mov d, EDX;
|
|
}
|
|
if (b!=0) {
|
|
// I'm not sure about this. The docs state that there
|
|
// are 2 hyperthreads per core if HT is factory enabled.
|
|
if (level==0)
|
|
threadsPerCore = b & 0xFFFF;
|
|
else if (level==1) {
|
|
cpuFeatures.maxThreads = b & 0xFFFF;
|
|
cpuFeatures.maxCores = cpuFeatures.maxThreads / threadsPerCore;
|
|
}
|
|
|
|
}
|
|
++level;
|
|
} while (a!=0 || b!=0);
|
|
}
|
|
|
|
void cpuidX86()
|
|
{
|
|
auto cf = getCpuFeatures();
|
|
|
|
uint a, b, c, d;
|
|
uint* venptr = cast(uint*)cf.vendorID.ptr;
|
|
version (GNU)
|
|
{
|
|
asm pure nothrow @nogc { "cpuid" : "=a" max_cpuid, "=b" venptr[0], "=d" venptr[1], "=c" venptr[2] : "a" 0; }
|
|
asm pure nothrow @nogc { "cpuid" : "=a" max_extended_cpuid : "a" 0x8000_0000 : "ebx", "ecx", "edx"; }
|
|
}
|
|
else
|
|
{
|
|
uint a2;
|
|
version (D_InlineAsm_X86)
|
|
{
|
|
asm pure nothrow @nogc {
|
|
mov EAX, 0;
|
|
cpuid;
|
|
mov a, EAX;
|
|
mov EAX, venptr;
|
|
mov [EAX], EBX;
|
|
mov [EAX + 4], EDX;
|
|
mov [EAX + 8], ECX;
|
|
}
|
|
}
|
|
else version (D_InlineAsm_X86_64)
|
|
{
|
|
asm pure nothrow @nogc {
|
|
mov EAX, 0;
|
|
cpuid;
|
|
mov a, EAX;
|
|
mov RAX, venptr;
|
|
mov [RAX], EBX;
|
|
mov [RAX + 4], EDX;
|
|
mov [RAX + 8], ECX;
|
|
}
|
|
}
|
|
asm pure nothrow @nogc {
|
|
mov EAX, 0x8000_0000;
|
|
cpuid;
|
|
mov a2, EAX;
|
|
}
|
|
max_cpuid = a;
|
|
max_extended_cpuid = a2;
|
|
}
|
|
|
|
|
|
cf.probablyIntel = cf.vendorID == "GenuineIntel";
|
|
cf.probablyAMD = cf.vendorID == "AuthenticAMD";
|
|
uint apic = 0; // brand index, apic id
|
|
version (GNU) asm pure nothrow @nogc {
|
|
"cpuid" : "=a" a, "=b" apic, "=c" cf.miscfeatures, "=d" cf.features : "a" 1;
|
|
} else {
|
|
asm pure nothrow @nogc {
|
|
mov EAX, 1; // model, stepping
|
|
cpuid;
|
|
mov a, EAX;
|
|
mov apic, EBX;
|
|
mov c, ECX;
|
|
mov d, EDX;
|
|
}
|
|
cf.features = d;
|
|
cf.miscfeatures = c;
|
|
}
|
|
stepping = a & 0xF;
|
|
immutable uint fbase = (a >> 8) & 0xF;
|
|
immutable uint mbase = (a >> 4) & 0xF;
|
|
family = ((fbase == 0xF) || (fbase == 0)) ? fbase + (a >> 20) & 0xFF : fbase;
|
|
model = ((fbase == 0xF) || (fbase == 6 && cf.probablyIntel) ) ?
|
|
mbase + ((a >> 12) & 0xF0) : mbase;
|
|
|
|
if (max_cpuid >= 7)
|
|
{
|
|
version (GNU) asm pure nothrow @nogc {
|
|
"cpuid" : "=a" a, "=b" cf.extfeatures, "=c" c : "a" 7, "c" 0 : "edx";
|
|
} else {
|
|
uint ext;
|
|
asm pure nothrow @nogc {
|
|
mov EAX, 7; // Structured extended feature leaf.
|
|
mov ECX, 0; // Main leaf.
|
|
cpuid;
|
|
mov ext, EBX; // HLE, AVX2, RTM, etc.
|
|
}
|
|
cf.extfeatures = ext;
|
|
}
|
|
}
|
|
|
|
if (cf.miscfeatures & OSXSAVE_BIT)
|
|
{
|
|
version (GNU) asm pure nothrow @nogc {
|
|
"xgetbv" : "=a" a, "=d" d : "c" 0;
|
|
} else asm pure nothrow @nogc {
|
|
mov ECX, 0;
|
|
xgetbv;
|
|
mov d, EDX;
|
|
mov a, EAX;
|
|
}
|
|
cf.xfeatures = cast(ulong)d << 32 | a;
|
|
}
|
|
|
|
cf.amdfeatures = 0;
|
|
cf.amdmiscfeatures = 0;
|
|
if (max_extended_cpuid >= 0x8000_0001) {
|
|
version (GNU) asm pure nothrow @nogc {
|
|
"cpuid" : "=a" a, "=c" cf.amdmiscfeatures, "=d" cf.amdfeatures : "a" 0x8000_0001 : "ebx";
|
|
} else {
|
|
asm pure nothrow @nogc {
|
|
mov EAX, 0x8000_0001;
|
|
cpuid;
|
|
mov c, ECX;
|
|
mov d, EDX;
|
|
}
|
|
cf.amdmiscfeatures = c;
|
|
cf.amdfeatures = d;
|
|
}
|
|
}
|
|
// Try to detect fraudulent vendorIDs
|
|
if (amd3dnow) cf.probablyIntel = false;
|
|
|
|
if (!cf.probablyIntel && max_extended_cpuid >= 0x8000_0008) {
|
|
//http://support.amd.com/TechDocs/25481.pdf pg.36
|
|
cf.maxCores = 1;
|
|
if (hyperThreadingBit) {
|
|
// determine max number of cores for AMD
|
|
version (GNU) asm pure nothrow @nogc {
|
|
"cpuid" : "=a" a, "=c" c : "a" 0x8000_0008 : "ebx", "edx";
|
|
} else asm pure nothrow @nogc {
|
|
mov EAX, 0x8000_0008;
|
|
cpuid;
|
|
mov c, ECX;
|
|
}
|
|
cf.maxCores += c & 0xFF;
|
|
}
|
|
}
|
|
|
|
if (max_extended_cpuid >= 0x8000_0004) {
|
|
uint* pnb = cast(uint*)cf.processorNameBuffer.ptr;
|
|
version (GNU)
|
|
{
|
|
asm pure nothrow @nogc { "cpuid" : "=a" pnb[0], "=b" pnb[1], "=c" pnb[ 2], "=d" pnb[ 3] : "a" 0x8000_0002; }
|
|
asm pure nothrow @nogc { "cpuid" : "=a" pnb[4], "=b" pnb[5], "=c" pnb[ 6], "=d" pnb[ 7] : "a" 0x8000_0003; }
|
|
asm pure nothrow @nogc { "cpuid" : "=a" pnb[8], "=b" pnb[9], "=c" pnb[10], "=d" pnb[11] : "a" 0x8000_0004; }
|
|
}
|
|
else version (D_InlineAsm_X86)
|
|
{
|
|
asm pure nothrow @nogc {
|
|
push ESI;
|
|
mov ESI, pnb;
|
|
mov EAX, 0x8000_0002;
|
|
cpuid;
|
|
mov [ESI], EAX;
|
|
mov [ESI+4], EBX;
|
|
mov [ESI+8], ECX;
|
|
mov [ESI+12], EDX;
|
|
mov EAX, 0x8000_0003;
|
|
cpuid;
|
|
mov [ESI+16], EAX;
|
|
mov [ESI+20], EBX;
|
|
mov [ESI+24], ECX;
|
|
mov [ESI+28], EDX;
|
|
mov EAX, 0x8000_0004;
|
|
cpuid;
|
|
mov [ESI+32], EAX;
|
|
mov [ESI+36], EBX;
|
|
mov [ESI+40], ECX;
|
|
mov [ESI+44], EDX;
|
|
pop ESI;
|
|
}
|
|
}
|
|
else version (D_InlineAsm_X86_64)
|
|
{
|
|
asm pure nothrow @nogc {
|
|
push RSI;
|
|
mov RSI, pnb;
|
|
mov EAX, 0x8000_0002;
|
|
cpuid;
|
|
mov [RSI], EAX;
|
|
mov [RSI+4], EBX;
|
|
mov [RSI+8], ECX;
|
|
mov [RSI+12], EDX;
|
|
mov EAX, 0x8000_0003;
|
|
cpuid;
|
|
mov [RSI+16], EAX;
|
|
mov [RSI+20], EBX;
|
|
mov [RSI+24], ECX;
|
|
mov [RSI+28], EDX;
|
|
mov EAX, 0x8000_0004;
|
|
cpuid;
|
|
mov [RSI+32], EAX;
|
|
mov [RSI+36], EBX;
|
|
mov [RSI+40], ECX;
|
|
mov [RSI+44], EDX;
|
|
pop RSI;
|
|
}
|
|
}
|
|
// Intel P4 and PM pad at front with spaces.
|
|
// Other CPUs pad at end with nulls.
|
|
int start = 0, end = 0;
|
|
while (cf.processorNameBuffer[start] == ' ') { ++start; }
|
|
while (cf.processorNameBuffer[cf.processorNameBuffer.length-end-1] == 0) { ++end; }
|
|
cf.processorName = cast(string)(cf.processorNameBuffer[start..$-end]);
|
|
} else {
|
|
cf.processorName = "Unknown CPU";
|
|
}
|
|
// Determine cache sizes
|
|
|
|
// Intel docs specify that they return 0 for 0x8000_0005.
|
|
// AMD docs do not specify the behaviour for 0004 and 0002.
|
|
// Centaur/VIA and most other manufacturers use the AMD method,
|
|
// except Cyrix MediaGX MMX Enhanced uses their OWN form of CPUID2!
|
|
// NS Geode GX1 provides CyrixCPUID2 _and_ does the same wrong behaviour
|
|
// for CPUID80000005. But Geode GX uses the AMD method
|
|
|
|
// Deal with Geode GX1 - make it same as MediaGX MMX.
|
|
if (max_extended_cpuid==0x8000_0005 && max_cpuid==2) {
|
|
max_extended_cpuid = 0x8000_0004;
|
|
}
|
|
// Therefore, we try the AMD method unless it's an Intel chip.
|
|
// If we still have no info, try the Intel methods.
|
|
datacache[0].size = 0;
|
|
if (max_cpuid<2 || !cf.probablyIntel) {
|
|
if (max_extended_cpuid >= 0x8000_0005) {
|
|
getAMDcacheinfo();
|
|
} else if (cf.probablyAMD) {
|
|
// According to AMDProcRecognitionAppNote, this means CPU
|
|
// K5 model 0, or Am5x86 (model 4), or Am4x86DX4 (model 4)
|
|
// Am5x86 has 16Kb 4-way unified data & code cache.
|
|
datacache[0].size = 8;
|
|
datacache[0].associativity = 4;
|
|
datacache[0].lineSize = 32;
|
|
} else {
|
|
// Some obscure CPU.
|
|
// Values for Cyrix 6x86MX (family 6, model 0)
|
|
datacache[0].size = 64;
|
|
datacache[0].associativity = 4;
|
|
datacache[0].lineSize = 32;
|
|
}
|
|
}
|
|
if ((datacache[0].size == 0) && max_cpuid>=4) {
|
|
getcacheinfoCPUID4();
|
|
}
|
|
if ((datacache[0].size == 0) && max_cpuid>=2) {
|
|
getcacheinfoCPUID2();
|
|
}
|
|
if (datacache[0].size == 0) {
|
|
// Pentium, PMMX, late model 486, or an obscure CPU
|
|
if (mmx) { // Pentium MMX. Also has 8kB code cache.
|
|
datacache[0].size = 16;
|
|
datacache[0].associativity = 4;
|
|
datacache[0].lineSize = 32;
|
|
} else { // Pentium 1 (which also has 8kB code cache)
|
|
// or 486.
|
|
// Cyrix 6x86: 16, 4way, 32 linesize
|
|
datacache[0].size = 8;
|
|
datacache[0].associativity = 2;
|
|
datacache[0].lineSize = 32;
|
|
}
|
|
}
|
|
if (max_cpuid >= 0x0B) {
|
|
// For Intel i7 and later, use function 0x0B to determine
|
|
// cores and hyperthreads.
|
|
getCpuInfo0B();
|
|
} else {
|
|
if (hyperThreadingBit) cf.maxThreads = (apic>>>16) & 0xFF;
|
|
else cf.maxThreads = cf.maxCores;
|
|
}
|
|
}
|
|
|
|
// Return true if the cpuid instruction is supported.
|
|
// BUG(WONTFIX): Returns false for Cyrix 6x86 and 6x86L. They will be treated as 486 machines.
|
|
bool hasCPUID()
|
|
{
|
|
version (X86_64)
|
|
return true;
|
|
else
|
|
{
|
|
uint flags;
|
|
version (GNU)
|
|
{
|
|
// http://wiki.osdev.org/CPUID#Checking_CPUID_availability
|
|
// ASM template supports both AT&T and Intel syntax.
|
|
asm nothrow @nogc { "
|
|
pushf{l|d} # Save EFLAGS
|
|
pushf{l|d} # Store EFLAGS
|
|
xor{l $0x00200000, (%%esp)| dword ptr [esp], 0x00200000}
|
|
# Invert the ID bit in stored EFLAGS
|
|
popf{l|d} # Load stored EFLAGS (with ID bit inverted)
|
|
pushf{l|d} # Store EFLAGS again (ID bit may or may not be inverted)
|
|
pop {%%}eax # eax = modified EFLAGS (ID bit may or may not be inverted)
|
|
xor {(%%esp), %%eax|eax, [esp]}
|
|
# eax = whichever bits were changed
|
|
popf{l|d} # Restore original EFLAGS
|
|
" : "=a" flags;
|
|
}
|
|
}
|
|
else version (D_InlineAsm_X86)
|
|
{
|
|
asm nothrow @nogc {
|
|
pushfd;
|
|
pop EAX;
|
|
mov flags, EAX;
|
|
xor EAX, 0x0020_0000;
|
|
push EAX;
|
|
popfd;
|
|
pushfd;
|
|
pop EAX;
|
|
xor flags, EAX;
|
|
}
|
|
}
|
|
return (flags & 0x0020_0000) != 0;
|
|
}
|
|
}
|
|
|
|
} else { // supported X86
|
|
|
|
bool hasCPUID() { return false; }
|
|
|
|
void cpuidX86()
|
|
{
|
|
datacache[0].size = 8;
|
|
datacache[0].associativity = 2;
|
|
datacache[0].lineSize = 32;
|
|
}
|
|
}
|
|
|
|
/*
|
|
// TODO: Implement this function with OS support
|
|
void cpuidPPC()
|
|
{
|
|
enum :int { PPC601, PPC603, PPC603E, PPC604,
|
|
PPC604E, PPC620, PPCG3, PPCG4, PPCG5 }
|
|
|
|
// TODO:
|
|
// asm { mfpvr; } returns the CPU version but unfortunately it can
|
|
// only be used in kernel mode. So OS support is required.
|
|
int cputype = PPC603;
|
|
|
|
// 601 has a 8KB combined data & code L1 cache.
|
|
uint sizes[] = [4, 8, 16, 16, 32, 32, 32, 32, 64];
|
|
ubyte ways[] = [8, 2, 4, 4, 4, 8, 8, 8, 8];
|
|
uint L2size[]= [0, 0, 0, 0, 0, 0, 0, 256, 512];
|
|
uint L3size[]= [0, 0, 0, 0, 0, 0, 0, 2048, 0];
|
|
|
|
datacache[0].size = sizes[cputype];
|
|
datacache[0].associativity = ways[cputype];
|
|
datacache[0].lineSize = (cputype==PPCG5)? 128 :
|
|
(cputype == PPC620 || cputype == PPCG3)? 64 : 32;
|
|
datacache[1].size = L2size[cputype];
|
|
datacache[2].size = L3size[cputype];
|
|
datacache[1].lineSize = datacache[0].lineSize;
|
|
datacache[2].lineSize = datacache[0].lineSize;
|
|
}
|
|
|
|
// TODO: Implement this function with OS support
|
|
void cpuidSparc()
|
|
{
|
|
// UltaSparcIIi : L1 = 16, 2way. L2 = 512, 4 way.
|
|
// UltraSparcIII : L1 = 64, 4way. L2= 4096 or 8192.
|
|
// UltraSparcIIIi: L1 = 64, 4way. L2= 1024, 4 way
|
|
// UltraSparcIV : L1 = 64, 4way. L2 = 16*1024.
|
|
// UltraSparcIV+ : L1 = 64, 4way. L2 = 2048, L3=32*1024.
|
|
// Sparc64V : L1 = 128, 2way. L2 = 4096 4way.
|
|
}
|
|
*/
|
|
|
|
shared static this()
|
|
{
|
|
auto cf = getCpuFeatures();
|
|
|
|
if (hasCPUID()) {
|
|
cpuidX86();
|
|
} else {
|
|
// it's a 386 or 486, or a Cyrix 6x86.
|
|
//Probably still has an external cache.
|
|
}
|
|
if (datacache[0].size==0) {
|
|
// Guess same as Pentium 1.
|
|
datacache[0].size = 8;
|
|
datacache[0].associativity = 2;
|
|
datacache[0].lineSize = 32;
|
|
}
|
|
numCacheLevels = 1;
|
|
// And now fill up all the unused levels with full memory space.
|
|
for (size_t i=1; i< datacache.length; ++i) {
|
|
if (datacache[i].size==0) {
|
|
// Set all remaining levels of cache equal to full address space.
|
|
datacache[i].size = size_t.max/1024;
|
|
datacache[i].associativity = 1;
|
|
datacache[i].lineSize = datacache[i-1].lineSize;
|
|
}
|
|
else
|
|
++numCacheLevels;
|
|
}
|
|
|
|
// Set the immortals
|
|
|
|
_dataCaches = datacache;
|
|
_vendor = cast(string)cf.vendorID;
|
|
_processor = cf.processorName;
|
|
_x87onChip = (cf.features&FPU_BIT)!=0;
|
|
_mmx = (cf.features&MMX_BIT)!=0;
|
|
_sse = (cf.features&SSE_BIT)!=0;
|
|
_sse2 = (cf.features&SSE2_BIT)!=0;
|
|
_sse3 = (cf.miscfeatures&SSE3_BIT)!=0;
|
|
_ssse3 = (cf.miscfeatures&SSSE3_BIT)!=0;
|
|
_sse41 = (cf.miscfeatures&SSE41_BIT)!=0;
|
|
_sse42 = (cf.miscfeatures&SSE42_BIT)!=0;
|
|
_sse4a = (cf.amdmiscfeatures&SSE4A_BIT)!=0;
|
|
_aes = (cf.miscfeatures&AES_BIT)!=0;
|
|
_hasPclmulqdq = (cf.miscfeatures&PCLMULQDQ_BIT)!=0;
|
|
_hasRdrand = (cf.miscfeatures&RDRAND_BIT)!=0;
|
|
|
|
enum avx_mask = XF_SSE_BIT|XF_YMM_BIT;
|
|
_avx = (cf.xfeatures & avx_mask) == avx_mask && (cf.miscfeatures&AVX_BIT)!=0;
|
|
|
|
_vaes = avx && aes;
|
|
_hasVpclmulqdq = avx && hasPclmulqdq;
|
|
_fma = avx && (cf.miscfeatures&FMA_BIT)!=0;
|
|
_fp16c = avx && (cf.miscfeatures&FP16C_BIT)!=0;
|
|
_avx2 = avx && (cf.extfeatures & AVX2_BIT) != 0;
|
|
_hle = (cf.extfeatures & HLE_BIT) != 0;
|
|
_rtm = (cf.extfeatures & RTM_BIT) != 0;
|
|
_hasRdseed = (cf.extfeatures&RDSEED_BIT)!=0;
|
|
_hasSha = (cf.extfeatures&SHA_BIT)!=0;
|
|
_amd3dnow = (cf.amdfeatures&AMD_3DNOW_BIT)!=0;
|
|
_amd3dnowExt = (cf.amdfeatures&AMD_3DNOW_EXT_BIT)!=0;
|
|
_amdMmx = (cf.amdfeatures&AMD_MMX_BIT)!=0;
|
|
_hasFxsr = (cf.features&FXSR_BIT)!=0;
|
|
_hasCmov = (cf.features&CMOV_BIT)!=0;
|
|
_hasRdtsc = (cf.features&TIMESTAMP_BIT)!=0;
|
|
_hasCmpxchg8b = (cf.features&CMPXCHG8B_BIT)!=0;
|
|
_hasCmpxchg16b = (cf.miscfeatures&CMPXCHG16B_BIT)!=0;
|
|
_hasSysEnterSysExit =
|
|
// The SYSENTER/SYSEXIT features were buggy on Pentium Pro and early PentiumII.
|
|
// (REF: www.geoffchappell.com).
|
|
(cf.probablyIntel && (family < 6 || (family==6 && (model< 3 || (model==3 && stepping<3)))))
|
|
? false
|
|
: (cf.features & SYSENTERSYSEXIT_BIT)!=0;
|
|
_has3dnowPrefetch = (cf.amdmiscfeatures&AMD_3DNOW_PREFETCH_BIT)!=0;
|
|
_hasLahfSahf = (cf.amdmiscfeatures&LAHFSAHF_BIT)!=0;
|
|
_hasPopcnt = (cf.miscfeatures&POPCNT_BIT)!=0;
|
|
_hasLzcnt = (cf.amdmiscfeatures&LZCNT_BIT)!=0;
|
|
_isX86_64 = (cf.amdfeatures&AMD64_BIT)!=0;
|
|
_isItanium = (cf.features&IA64_BIT)!=0;
|
|
_hyperThreading = cf.maxThreads>cf.maxCores;
|
|
_threadsPerCPU = cf.maxThreads;
|
|
_coresPerCPU = cf.maxCores;
|
|
_preferAthlon = cf.probablyAMD && family >=6;
|
|
_preferPentium4 = cf.probablyIntel && family == 0xF;
|
|
_preferPentium1 = family < 6 || (family==6 && model < 0xF && !cf.probablyIntel);
|
|
}
|