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dingusppc/cpu/ppc/ppcemu.h

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Updating files with proper licensing header
2020-02-28 09:04:28 -07:00
/*
DingusPPC - The Experimental PowerPC Macintosh emulator
ppcemu: Make flags atomic. For flags that might be accessed by other threads.
2023-11-23 11:58:00 -08:00
Copyright (C) 2018-24 divingkatae and maximum
Updating files with proper licensing header
2020-02-28 09:04:28 -07:00
(theweirdo) spatium
(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
Add files via upload The first attempt at uploading new files.
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Move opcode decoding tables to ppcexec.cpp.
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#ifndef PPCEMU_H
#define PPCEMU_H
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Move devices into dedicated subdirectories.
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#include <devices/memctrl/memctrlbase.h>
#include <endianswap.h>
Inline ppc_set_cur_instruction It's used in the main emulator loop (ppc_exec_inner), and the function call overhead adds up. By inlining it, time to boot to the Finder using a 7.1.2 install CD and a 6100 ROM goes from ~6700ms to ~6400ms (with clang 14 on a M2 Max)
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#include <memaccess.h>
Move devices into dedicated subdirectories.
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Adding missing includes
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#include <atomic>
Move CPU initialization to ppcexec.cpp.
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#include <cinttypes>
Implement SoftTLB for writes.
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#include <functional>
Refactor PPC exception handling, part 1.
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#include <setjmp.h>
clang-format everything
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#include <string>
Rewrite MPC106 emualation from scratch. From now on, ppcmemory delegates physical address translation to MPC106 on PowerMac Beige G3.
2019-08-21 08:33:01 +02:00
clang-format everything
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// Uncomment this to have a more graceful approach to illegal opcodes
More fixes, plus a temp icon
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//#define ILLEGAL_OP_SAFE 1
Rework PPC CPU profiler.
2021-04-29 02:26:17 +02:00
//#define CPU_PROFILING // enable CPU profiling
Slight clean-up for execution type
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/** type of compiler used during execution */
enum EXEC_MODE:uint32_t {
interpreter = 0,
debugger = 1,
threaded_int = 2,
jit = 3
};
Refactored floating point emulation Refactored for better 64-bit value loading and storing. I also added missing opcodes.
2020-01-25 19:30:55 -07:00
enum endian_switch { big_end = 0, little_end = 1 };
Add files via upload The first attempt at uploading new files.
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Remove ppc_cur_instruction global variable Replace it wth an explicit opcode parameter that is passed around. That is both slightly easier to reason about (to trace where it comes from) and slightly faster, since it can be read from a register. On my machine takes booting to "Welcome to Macintosh" being output in a verbose boot of Mac OS X 10.2.8 from 31.8s to 30.6s (average of 5 runs, measured using deterministic mode and looking at when execution reaches PC 0x90004a88).
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typedef void (*PPCOpcode)(uint32_t opcode);
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Fix compilation warnings from previous commits.
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union FPR_storage {
clang-format everything
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double dbl64_r; // double floating-point representation
uint64_t int64_r; // double integer representation
Started a massive FP fix-up
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};
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/**
Except for the floating-point registers, all registers require
32 bits for representation. Floating-point registers need 64 bits.
gpr = General Purpose Register
fpr = Floating Point (FP) Register
cr = Condition Register
tbr = Time Base Register
fpscr = FP Status and Condition Register
spr = Special Register
msr = Machine State Register
sr = Segment Register
**/
typedef struct struct_ppc_state {
Fixed redunant variable names for PPC emulation.
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FPR_storage fpr[32];
clang-format everything
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uint32_t pc; // Referred as the CIA in the PPC manual
Fixed redunant variable names for PPC emulation.
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uint32_t gpr[32];
uint32_t cr;
uint32_t fpscr;
uint32_t tbr[2];
uint32_t spr[1024];
uint32_t msr;
uint32_t sr[16];
clang-format everything
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bool reserve; // reserve bit used for lwarx and stcwx
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} SetPRS;
extern SetPRS ppc_state;
Move CPU initialization to ppcexec.cpp.
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/** symbolic names for frequently used SPRs */
enum SPR : int {
ppcopcodes: Fixes for SPRs. - Rename DEC to DEC_S and add DEC_U. - MQ, RTCL_U, RTCU_U, and DEC_U should cause an illegal instruction program exception for non-MPC601 CPUs. The exception handler of classic Mac OS uses this to emulate the instruction. - For mtspr, the SPRs RTCL_U, RTCU_U, and DEC_U are treated as no-op on MPC601. - For debugging, use the supervisor instead of the user SPR number as the index for storing the values for RTC, TB, and DEC. - For debugging, RTC, TB, and DEC should be updated after each access. Previously, mfspr and mtspr would only update the half of RTC and TB that was being accessed instead of both halves.
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MQ = 0, // MQ (601)
Implement MPC601 style RTC.
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XER = 1,
ppcopcodes: Fixes for SPRs. - Rename DEC to DEC_S and add DEC_U. - MQ, RTCL_U, RTCU_U, and DEC_U should cause an illegal instruction program exception for non-MPC601 CPUs. The exception handler of classic Mac OS uses this to emulate the instruction. - For mtspr, the SPRs RTCL_U, RTCU_U, and DEC_U are treated as no-op on MPC601. - For debugging, use the supervisor instead of the user SPR number as the index for storing the values for RTC, TB, and DEC. - For debugging, RTC, TB, and DEC should be updated after each access. Previously, mfspr and mtspr would only update the half of RTC and TB that was being accessed instead of both halves.
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RTCU_U = 4, // user mode RTCU (601)
RTCL_U = 5, // user mode RTCL (601)
DEC_U = 6, // user mode decrementer (601)
Implement MPC601 style RTC.
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LR = 8,
CTR = 9,
DSISR = 18,
DAR = 19,
ppcopcodes: Fixes for SPRs. - Rename DEC to DEC_S and add DEC_U. - MQ, RTCL_U, RTCU_U, and DEC_U should cause an illegal instruction program exception for non-MPC601 CPUs. The exception handler of classic Mac OS uses this to emulate the instruction. - For mtspr, the SPRs RTCL_U, RTCU_U, and DEC_U are treated as no-op on MPC601. - For debugging, use the supervisor instead of the user SPR number as the index for storing the values for RTC, TB, and DEC. - For debugging, RTC, TB, and DEC should be updated after each access. Previously, mfspr and mtspr would only update the half of RTC and TB that was being accessed instead of both halves.
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RTCU_S = 20, // supervisor RTCU (601)
RTCL_S = 21, // supervisor RTCL (601)
DEC_S = 22, // supervisor decrementer
Implement MPC601 style RTC.
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SDR1 = 25,
SRR0 = 26,
SRR1 = 27,
TBL_U = 268, // user mode TBL
TBU_U = 269, // user mode TBU
debugger: Add more register names for reg_op. So the debugger can output their values.
2023-08-07 11:38:18 -07:00
SPRG0 = 272,
SPRG1 = 273,
SPRG2 = 274,
SPRG3 = 275,
Implement MPC601 style RTC.
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TBL_S = 284, // supervisor TBL
TBU_S = 285, // supervisor TBU
ppcemu: add enums for HID0 and HID1.
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PVR = 287,
debugger: Add more register names for reg_op. So the debugger can output their values.
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MMCR0 = 952,
PMC1 = 953,
PMC2 = 954,
SIA = 955,
MMCR1 = 956,
SDA = 959,
ppcemu: add enums for HID0 and HID1.
2022-08-15 14:45:55 +02:00
HID0 = 1008,
HID1 = 1009,
Move CPU initialization to ppcexec.cpp.
2020-01-28 01:24:12 +01:00
};
/** symbolic names for common PPC processors */
enum PPC_VER : uint32_t {
ppcemu: add PVR for 603ev.
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MPC601 = 0x00010001,
MPC603 = 0x00030001,
MPC604 = 0x00040001,
MPC603E = 0x00060101,
MPC603EV = 0x00070101,
ppcemu.h: add PVR definition for MPC604e.
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MPC750 = 0x00080200,
MPC604E = 0x00090202,
ppcexec: Make illegal operations per CPU model.
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MPC970MP = 0x00440100,
Move CPU initialization to ppcexec.cpp.
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};
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/**
typedef struct struct_ppc64_state {
Fixed redunant variable names for PPC emulation.
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FPR_storage fpr [32];
Simplified prog_counter back to pc
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uint64_t pc; //Referred as the CIA in the PPC manual
Fixed redunant variable names for PPC emulation.
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uint64_t gpr [32];
uint32_t cr;
uint32_t fpscr;
uint32_t tbr [2];
uint64_t spr [1024];
uint32_t msr;
uint32_t sr [16];
bool reserve; //reserve bit used for lwarx and stcwx
Add files via upload The first attempt at uploading new files.
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} SetPRS64;
extern SetPRS64 ppc_state64;
**/
/**
Specific SPRS to be weary of:
USER MODEL
SPR 1 - XER
SPR 8 - Link Register / Branch
b0 - Summary Overflow
b1 - Overflow
b2 - Carry
b25-31 - Number of bytes to transfer
SPR 9 - Count
SUPERVISOR MODEL
19 is the Data Address Register
22 is the Decrementer
26, 27 are the Save and Restore Registers (SRR0, SRR1)
272 - 275 are the SPRGs
284 - 285 for writing to the TBR's.
528 - 535 are the Instruction BAT registers
536 - 543 are the Data BAT registers
**/
Implement virtual time based on instruction counting.
2021-12-20 00:10:02 +01:00
extern uint64_t timebase_counter;
extern uint64_t tbr_wr_timestamp;
Implement PPC decrementer.
2023-02-09 01:38:55 +01:00
extern uint64_t dec_wr_timestamp;
Make accessing RTC or TBR not affect the other Fixed an issue where the following would cause inconsistent results (tb in the left column would sometimes decrement instead of always incrementing): 2 0 do 2 0 do cr tb@ 8 u.r ." ." 8 u.r loop 2 0 do cr 12 spaces rtc@ 8 u.r ." ." 8 u.r loop 2 0 do cr tb@ 8 u.r ." ." 8 u.r space rtc@ 8 u.r ." ." 8 u.r loop loop RTC and TBR could not be used simultaneously because they are both incremented by an amount based on the last time stamp but that time stamp can be changed by accessing either RTC or TBR. The solution is to have a different time stamp for each.
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extern uint64_t rtc_timestamp;
Implement virtual time based on instruction counting.
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extern uint64_t tbr_wr_value;
Implement PPC decrementer.
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extern uint32_t dec_wr_value;
Fix TBR range Fixed an issue where TBR doesn't have full 64-bit range. The original calculation was 64 bit and ended with a ÷ 10^9. This means the max for the upper 32 bits is 2^32/10^9 = 4. The solution is to use a multiplication method that supports a 96 bit product. core/mathutils.h contains functions for that. TBR driving frequency is assumed to be less than 1 GHz. Some minor modification is required for future > 1 GHz support.
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extern uint32_t tbr_freq_ghz;
Decrementer exception changes.
2023-08-07 11:11:02 -07:00
extern uint64_t tbr_period_ns;
Implement MPC601 style RTC.
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extern uint32_t rtc_lo, rtc_hi;
Add files via upload The first attempt at uploading new files.
2019-07-01 19:15:33 -07:00
Interpreter loop is now controlled by exec_flags.
2022-03-02 16:55:20 +01:00
/* Flags for controlling interpreter execution. */
enum {
EXEF_BRANCH = 1 << 0,
EXEF_EXCEPTION = 1 << 1,
EXEF_RFI = 1 << 2,
ppcexec: pagewise MMU translation for code.
2020-01-03 21:01:02 +01:00
};
Floating-point refactor, part 3 Condensed code to shorten enum names and remove casting. Condensed mffs and partially fixed NAN checks for FADD(S).
2021-10-10 07:48:49 -07:00
enum CR_select : int32_t {
Floating point overhaul, part 1 Cleaned up formatting and reworked the INF/NAN checks
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CR0_field = (0xF << 28),
Floating point overhaul, part 2 Further formatting fixes. Removed obsoleted separation definitions. Fixed rounding to nearest.
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CR1_field = (0xF << 24),
Floating point overhaul, part 1 Cleaned up formatting and reworked the INF/NAN checks
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};
CRx_bit enum stores masks for now.
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// Define bit masks for CR0.
// To use them in other CR fields, just right shift it by 4*CR_num bits.
Implement virtual time based on instruction counting.
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enum CRx_bit : uint32_t {
CRx_bit enum stores masks for now.
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CR_SO = 1UL << 28,
CR_EQ = 1UL << 29,
CR_GT = 1UL << 30,
CR_LT = 1UL << 31
};
Floating point overhaul, part 1 Cleaned up formatting and reworked the INF/NAN checks
2021-10-09 15:08:53 -07:00
Floating-point refactor, part 3 Condensed code to shorten enum names and remove casting. Condensed mffs and partially fixed NAN checks for FADD(S).
2021-10-10 07:48:49 -07:00
enum CR1_bit : uint32_t {
Move devices into dedicated subdirectories.
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CR1_OX = 24,
Floating point overhaul, part 1 Cleaned up formatting and reworked the INF/NAN checks
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CR1_VX,
CR1_FEX,
CR1_FX,
};
Floating-point refactor, part 3 Condensed code to shorten enum names and remove casting. Condensed mffs and partially fixed NAN checks for FADD(S).
2021-10-10 07:48:49 -07:00
enum FPSCR : uint32_t {
ppcemu: fix and beatify FPSCR enum.
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RN_MASK = 0x3,
NI = 1UL << 2,
XE = 1UL << 3,
ZE = 1UL << 4,
UE = 1UL << 5,
OE = 1UL << 6,
VE = 1UL << 7,
VXCVI = 1UL << 8,
VXSQRT = 1UL << 9,
VXSOFT = 1UL << 10,
FPCC_FUNAN = 1UL << 12,
FPCC_ZERO = 1UL << 13,
FPCC_POS = 1UL << 14,
FPCC_NEG = 1UL << 15,
Cleanup previous commit.
2023-12-19 11:58:12 +01:00
FPCC_MASK = FPCC_NEG | FPCC_POS | FPCC_ZERO | FPCC_FUNAN,
FPRCD = 1UL << 16,
FPRF_MASK = FPRCD | FPCC_MASK,
ppcemu: fix and beatify FPSCR enum.
2023-11-30 11:47:07 +01:00
FI = 1UL << 17,
FR = 1UL << 18,
VXVC = 1UL << 19,
VXIMZ = 1UL << 20,
VXZDZ = 1UL << 21,
VXIDI = 1UL << 22,
VXISI = 1UL << 23,
VXSNAN = 1UL << 24,
XX = 1UL << 25,
ZX = 1UL << 26,
UX = 1UL << 27,
OX = 1UL << 28,
VX = 1UL << 29,
FEX = 1UL << 30,
FX = 1UL << 31
Floating point overhaul, part 1 Cleaned up formatting and reworked the INF/NAN checks
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};
Further CPU cleanup
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enum MSR : int {
LE = 0x1, //little endian mode
RI = 0x2,
DR = 0x10,
IR = 0x20,
IP = 0x40,
FE1 = 0x100,
BE = 0x200,
SE = 0x400,
FE0 = 0x800,
ME = 0x1000,
FP = 0x2000,
PR = 0x4000,
EE = 0x8000, //external interrupt
ILE = 0x10000,
POW = 0x40000
};
ppcemu.h: add enum for XER bits.
2023-12-19 14:47:14 +01:00
enum XER : uint32_t {
CA = 1UL << 29,
OV = 1UL << 30,
SO = 1UL << 31
};
Floating point overhaul, part 1 Cleaned up formatting and reworked the INF/NAN checks
2021-10-09 15:08:53 -07:00
//for inf and nan checks
enum FPOP : int {
CPU code clean-up in progress Happened to fix one case in the process.
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DIV = 0x12,
SUB = 0x14,
ADD = 0x15,
SQRT = 0x16,
CPU code clean-up
2024-01-05 15:11:37 -07:00
MUL = 0x19
Floating point overhaul, part 1 Cleaned up formatting and reworked the INF/NAN checks
2021-10-09 15:08:53 -07:00
};
Refactor PPC exception handling, part 1.
2020-01-11 21:48:56 +01:00
/** PowerPC exception types. */
enum class Except_Type {
EXC_SYSTEM_RESET = 1,
EXC_MACHINE_CHECK,
EXC_DSI,
EXC_ISI,
EXC_EXT_INT,
EXC_ALIGNMENT,
EXC_PROGRAM,
EXC_NO_FPU,
EXC_DECR,
EXC_SYSCALL = 12,
clang-format everything
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EXC_TRACE = 13
Refactor PPC exception handling, part 1.
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};
Inline ppc_set_cur_instruction It's used in the main emulator loop (ppc_exec_inner), and the function call overhead adds up. By inlining it, time to boot to the Finder using a 7.1.2 install CD and a 6100 ROM goes from ~6700ms to ~6400ms (with clang 14 on a M2 Max)
2023-12-02 15:12:02 -08:00
/** Program Exception subclasses. */
Clean up program exceptions.
2020-11-30 20:59:36 +01:00
enum Exc_Cause : uint32_t {
FPU_OFF = 1 << (31 - 11),
ILLEGAL_OP = 1 << (31 - 12),
NOT_ALLOWED = 1 << (31 - 13),
TRAP = 1 << (31 - 14),
};
Interpreter loop is now controlled by exec_flags.
2022-03-02 16:55:20 +01:00
extern unsigned exec_flags;
Refactor PPC exception handling, part 1.
2020-01-11 21:48:56 +01:00
extern jmp_buf exc_env;
ppcexec: pagewise MMU translation for code.
2020-01-03 21:01:02 +01:00
debugger: Fix interrupt signal. Typing Control-C in Terminal app causes an interrupt signal that should enter the DPPC debugger but this only worked once since the signal handler never returned. Even if the signal handler reenabled the signal somehow, it calls enter_debugger recursively which is strange since the earlier calls to enter_debugger would never return. Now the signal handler just sets a flag (power_on) which can be used to exit any loop (emulator loops, stepping loops, disassembly loops, dumping loops). Main always calls enter_debugger now which calls the ppc_exec loop. The power_on flag will exit the ppc_exec loop to return to the debugger. Recursion of enter_debugger is eliminated except for calls to loguru's ABORT_F. An enum power_off_reason is used to indicate why the power_on flag is set to false and to determine what happens next.
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enum Po_Cause : int {
po_none,
po_starting_up,
viacuda: Do shutdown. Shutdown will enter the debugger or quit depending on the execution mode. Quit is different from shutdown since it is triggered outside the guest by using the host Quit menu item.
2024-05-05 23:40:32 -07:00
po_quit,
po_quitting,
debugger: Fix interrupt signal. Typing Control-C in Terminal app causes an interrupt signal that should enter the DPPC debugger but this only worked once since the signal handler never returned. Even if the signal handler reenabled the signal somehow, it calls enter_debugger recursively which is strange since the earlier calls to enter_debugger would never return. Now the signal handler just sets a flag (power_on) which can be used to exit any loop (emulator loops, stepping loops, disassembly loops, dumping loops). Main always calls enter_debugger now which calls the ppc_exec loop. The power_on flag will exit the ppc_exec loop to return to the debugger. Recursion of enter_debugger is eliminated except for calls to loguru's ABORT_F. An enum power_off_reason is used to indicate why the power_on flag is set to false and to determine what happens next.
2023-11-21 16:57:28 -08:00
po_shut_down,
po_shutting_down,
Add support for the CUDA_RESTART_SYSTEM command There are cases where when it's necessary (e.g. given uninitialized NVRAM, the Beige G3 with the 10.2 install CD inserted will update the boot device and restart to boot from it). Restart support was done by wrapping the ppc_exec function in a loop and checking for a restart power off reason. We also need to disconnect all event listeners, since they will be recreated when the machine is re-initialized.
2024-03-07 23:30:55 -08:00
po_restart,
viacuda: Do shutdown. Shutdown will enter the debugger or quit depending on the execution mode. Quit is different from shutdown since it is triggered outside the guest by using the host Quit menu item.
2024-05-05 23:40:32 -07:00
po_restarting,
debugger: Fix interrupt signal. Typing Control-C in Terminal app causes an interrupt signal that should enter the DPPC debugger but this only worked once since the signal handler never returned. Even if the signal handler reenabled the signal somehow, it calls enter_debugger recursively which is strange since the earlier calls to enter_debugger would never return. Now the signal handler just sets a flag (power_on) which can be used to exit any loop (emulator loops, stepping loops, disassembly loops, dumping loops). Main always calls enter_debugger now which calls the ppc_exec loop. The power_on flag will exit the ppc_exec loop to return to the debugger. Recursion of enter_debugger is eliminated except for calls to loguru's ABORT_F. An enum power_off_reason is used to indicate why the power_on flag is set to false and to determine what happens next.
2023-11-21 16:57:28 -08:00
po_disassemble_on,
po_disassemble_off,
po_enter_debugger,
po_entered_debugger,
po_signal_interrupt,
};
Move all PPC code execution to ppcexec.cpp.
2019-12-28 02:49:58 +01:00
extern bool power_on;
debugger: Fix interrupt signal. Typing Control-C in Terminal app causes an interrupt signal that should enter the DPPC debugger but this only worked once since the signal handler never returned. Even if the signal handler reenabled the signal somehow, it calls enter_debugger recursively which is strange since the earlier calls to enter_debugger would never return. Now the signal handler just sets a flag (power_on) which can be used to exit any loop (emulator loops, stepping loops, disassembly loops, dumping loops). Main always calls enter_debugger now which calls the ppc_exec loop. The power_on flag will exit the ppc_exec loop to return to the debugger. Recursion of enter_debugger is eliminated except for calls to loguru's ABORT_F. An enum power_off_reason is used to indicate why the power_on flag is set to false and to determine what happens next.
2023-11-21 16:57:28 -08:00
extern Po_Cause power_off_reason;
cpu/ppc: improve support for external interrupts. Support generating of external interrupt exception in MTMSR and RFI when MSR[EE] is re-enabled and external interrupt still pending.
2022-08-24 12:51:43 +02:00
extern bool int_pin;
Decrementer exception changes.
2023-08-07 11:11:02 -07:00
extern bool dec_exception_pending;
Move all PPC code execution to ppcexec.cpp.
2019-12-28 02:49:58 +01:00
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extern bool is_601; // For PowerPC 601 Emulation
ppcopcodes: Don't change MQ if not MPC601. MQ should not be writable if not doing MPC601. Fix is_601 and include_601. This fixes risu tests.
2024-11-27 03:24:52 -08:00
extern bool include_601; // For non-PowerPC 601 emulation with 601 extras (matches Mac OS 9 environment which can emulate MPC 601 instructions)
clang-format everything
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extern bool is_altivec; // For Altivec Emulation
extern bool is_64bit; // For PowerPC G5 Emulation
Add files via upload The first attempt at uploading new files.
2019-07-01 19:15:33 -07:00
Add a deterministic execution mode Adds support for a --deterministic command-line option that makes repeated runs the same: - Keyboard and mouse input is ignored - The sound server does a periodic pull from the DMA channel (so that it gets drained), but only does so via a periodic timer (instead of being driven by a cubeb callback, which could arrive at different times) - Disk image writes are disabled (reads of a modified area still work via an in-memory copy) - NVRAM writes are disabled - The current time that ViaCuda initializes the guest OS is always the same. This makes execution exactly the same each time, which should make debugging of more subtle issues easier. To validate that the deterministic mode is working, I've added a periodic log of the current "time" (measured in cycle count), PC and opcode. When comparing two runs with --log-no-uptime, the generated log files are identical.
2024-11-09 22:25:48 -08:00
// Make execution deterministic (ignore external input, used a fixed date, etc.)
extern bool is_deterministic;
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// Important Addressing Integers
Add files via upload The first attempt at uploading new files.
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extern uint32_t ppc_next_instruction_address;
Remove ppc_cur_instruction global variable Replace it wth an explicit opcode parameter that is passed around. That is both slightly easier to reason about (to trace where it comes from) and slightly faster, since it can be read from a register. On my machine takes booting to "Welcome to Macintosh" being output in a verbose boot of Mac OS X 10.2.8 from 31.8s to 30.6s (average of 5 runs, measured using deterministic mode and looking at when execution reaches PC 0x90004a88).
2024-11-28 23:30:01 +01:00
inline uint32_t ppc_read_instruction(const uint8_t* ptr) {
return READ_DWORD_BE_A(ptr);
Inline ppc_set_cur_instruction It's used in the main emulator loop (ppc_exec_inner), and the function call overhead adds up. By inlining it, time to boot to the Finder using a 7.1.2 install CD and a 6100 ROM goes from ~6700ms to ~6400ms (with clang 14 on a M2 Max)
2023-12-02 15:12:02 -08:00
}
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// Profiling Stats
Rework PPC CPU profiler.
2021-04-29 02:26:17 +02:00
#ifdef CPU_PROFILING
extern uint64_t num_executed_instrs;
extern uint64_t num_supervisor_instrs;
extern uint64_t num_int_loads;
extern uint64_t num_int_stores;
extern uint64_t exceptions_processed;
#endif
FPU Fixing + Preparing for more debugging
2020-01-11 18:43:47 -07:00
ppc: Separate enums for separate fields.
2024-03-26 01:14:23 -07:00
// instruction enums
typedef enum {
ppcexec: Rename bool function enums. Use "logical" since the functions deal with multiple bits instead of a single boolean value and because the 601 manual calls them Logical Instructions. Use "ppc" for the enums because logical_and is defined elsewhere and because the original DPPC code used these names for those functions.
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ppc_and = 1,
ppc_andc = 2,
ppc_eqv = 3,
ppc_nand = 4,
ppc_nor = 5,
ppc_or = 6,
ppc_orc = 7,
ppc_xor = 8,
} logical_fun;
ppc: Separate enums for separate fields.
2024-03-26 01:14:23 -07:00
typedef enum {
LK0,
LK1,
} field_lk;
typedef enum {
AA0,
AA1,
} field_aa;
typedef enum {
SHFT0,
SHFT1,
} field_shift;
ppcexec: Make separate enum for shift instructions.
2024-03-26 18:53:11 -07:00
typedef enum {
RIGHT0,
LEFT1,
} field_direction;
ppc: Separate enums for separate fields.
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typedef enum {
RC0,
RC1,
} field_rc;
typedef enum {
OV0,
OV1,
} field_ov;
typedef enum {
CARRY0,
CARRY1,
} field_carry;
typedef enum {
NOT601,
IS601,
} field_601;
debugger: Use a named constant when we don't have a current instruction
2024-11-29 18:17:24 +01:00
// Placeholder value for cases where we don't have a currently-executing instruction.
constexpr uint32_t NO_OPCODE = 0;
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// Function prototypes
cpu: Add cpu options to ppc_cpu_init. The first option is a flag that enables MPC601 (POWER) instructions for CPUs that are not MPC601. This can be useful for the following reasons: 1) To produce results similar to classic Mac OS which emulates MPC601 instructions on CPUs that don't implement MPC601 instructions. This option is used to compare the risu traces produced in Mac OS 9 on a G3 or G4 with DPPC. 2) May increase performance in apps that use POWER instructions on emulated machines with CPUs that are not MPC601. It is not known if any such apps exist but there could be since Apple included MPC601 emulation in classic Mac OS.
2024-04-08 21:18:45 -07:00
extern void ppc_cpu_init(MemCtrlBase* mem_ctrl, uint32_t cpu_version, bool include_601, uint64_t tb_freq);
Add is_601 flag for selecting MPC601 specific behavior.
2023-09-18 20:43:53 +02:00
extern void ppc_mmu_init();
Move CPU initialization to ppcexec.cpp.
2020-01-28 01:24:12 +01:00
Remove ppc_cur_instruction global variable Replace it wth an explicit opcode parameter that is passed around. That is both slightly easier to reason about (to trace where it comes from) and slightly faster, since it can be read from a register. On my machine takes booting to "Welcome to Macintosh" being output in a verbose boot of Mac OS X 10.2.8 from 31.8s to 30.6s (average of 5 runs, measured using deterministic mode and looking at when execution reaches PC 0x90004a88).
2024-11-28 23:30:01 +01:00
void ppc_illegalop(uint32_t opcode);
cpu/ppc: improve support for external interrupts. Support generating of external interrupt exception in MTMSR and RFI when MSR[EE] is re-enabled and external interrupt still pending.
2022-08-24 12:51:43 +02:00
void ppc_assert_int();
void ppc_release_int();
Started re-refactoring opcode retrieval
2020-10-17 14:30:37 -07:00
ppc: Use a unified opcode lookup table Instead of a primary opcode lookup table with 64 entries and a few smaller tables with 4-2048 entries, use a single 64 * 2048 (128K) entry table to dispatch opcodes. Helps with performance, since we avoid the function call overhead for some frequently-used instructions (e.g. branch, integer, floating point). Saves ~2 seconds from the time to Welcome to Macintosh (same measurement methodology as #125) Secondarily also makes opcode registration/decoding a bit more uniform, and scannable, since it's now all in initialize_ppc_opcode_table.
2024-11-30 18:54:20 +01:00
void initialize_ppc_opcode_table();
Started re-refactoring opcode retrieval
2020-10-17 14:30:37 -07:00
Add files via upload The first attempt at uploading new files.
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void ppc_changecrf0(uint32_t set_result);
Add rounding control for the host FPU.
2023-11-30 12:00:50 +01:00
void set_host_rounding_mode(uint8_t mode);
void update_fpscr(uint32_t new_fpscr);
Add files via upload The first attempt at uploading new files.
2019-07-01 19:15:33 -07:00
ppcmmu: add debug memory reading function. This function saves and restores the MMU state so no invalid user input can break CPU execution.
2020-02-23 16:41:44 +01:00
/* Exception handlers. */
Fix external exception processing.
2022-01-10 17:27:27 +01:00
void ppc_exception_handler(Except_Type exception_type, uint32_t srr1_bits);
clang-format everything
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[[noreturn]] void dbg_exception_handler(Except_Type exception_type, uint32_t srr1_bits);
Remove ppc_cur_instruction global variable Replace it wth an explicit opcode parameter that is passed around. That is both slightly easier to reason about (to trace where it comes from) and slightly faster, since it can be read from a register. On my machine takes booting to "Welcome to Macintosh" being output in a verbose boot of Mac OS X 10.2.8 from 31.8s to 30.6s (average of 5 runs, measured using deterministic mode and looking at when execution reaches PC 0x90004a88).
2024-11-28 23:30:01 +01:00
void ppc_floating_point_exception(uint32_t opcode);
void ppc_alignment_exception(uint32_t opcode, uint32_t ea);
Add files via upload The first attempt at uploading new files.
2019-07-01 19:15:33 -07:00
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// MEMORY DECLARATIONS
Refactored floating point emulation Refactored for better 64-bit value loading and storing. I also added missing opcodes.
2020-01-25 19:30:55 -07:00
extern MemCtrlBase* mem_ctrl_instance;
Rewrite MPC106 emualation from scratch. From now on, ppcmemory delegates physical address translation to MPC106 on PowerMac Beige G3.
2019-08-21 08:33:01 +02:00
Implement SoftTLB for writes.
2021-08-03 16:01:32 +02:00
extern void add_ctx_sync_action(const std::function<void()> &);
Implement all required context-synchronizing events.
2021-10-13 20:58:09 +02:00
extern void do_ctx_sync(void);
Implement SoftTLB for writes.
2021-08-03 16:01:32 +02:00
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// The functions used by the PowerPC processor
Attempted templating for interpreter
2024-03-24 12:21:19 -07:00
Further refactoring to clean up the interpreter
2020-10-17 21:46:38 -07:00
namespace dppc_interpreter {
Remove ppc_cur_instruction global variable Replace it wth an explicit opcode parameter that is passed around. That is both slightly easier to reason about (to trace where it comes from) and slightly faster, since it can be read from a register. On my machine takes booting to "Welcome to Macintosh" being output in a verbose boot of Mac OS X 10.2.8 from 31.8s to 30.6s (average of 5 runs, measured using deterministic mode and looking at when execution reaches PC 0x90004a88).
2024-11-28 23:30:01 +01:00
template <field_lk l, field_601 for601> extern void ppc_bcctr(uint32_t opcode);
template <field_lk l> extern void ppc_bclr(uint32_t opcode);
extern void ppc_crand(uint32_t opcode);
extern void ppc_crandc(uint32_t opcode);
extern void ppc_creqv(uint32_t opcode);
extern void ppc_crnand(uint32_t opcode);
extern void ppc_crnor(uint32_t opcode);
extern void ppc_cror(uint32_t opcode);
extern void ppc_crorc(uint32_t opcode);
extern void ppc_crxor(uint32_t opcode);
extern void ppc_isync(uint32_t opcode);
template <logical_fun logical_op, field_rc rec> extern void ppc_logical(uint32_t opcode);
template <field_carry carry, field_rc rec, field_ov ov> extern void ppc_add(uint32_t opcode);
template <field_rc rec, field_ov ov> extern void ppc_adde(uint32_t opcode);
template <field_rc rec, field_ov ov> extern void ppc_addme(uint32_t opcode);
template <field_rc rec, field_ov ov> extern void ppc_addze(uint32_t opcode);
extern void ppc_cmp(uint32_t opcode);
extern void ppc_cmpl(uint32_t opcode);
template <field_rc rec> extern void ppc_cntlzw(uint32_t opcode);
extern void ppc_dcbf(uint32_t opcode);
extern void ppc_dcbi(uint32_t opcode);
extern void ppc_dcbst(uint32_t opcode);
extern void ppc_dcbt(uint32_t opcode);
extern void ppc_dcbtst(uint32_t opcode);
extern void ppc_dcbz(uint32_t opcode);
template <field_rc rec, field_ov ov> extern void ppc_divw(uint32_t opcode);
template <field_rc rec, field_ov ov> extern void ppc_divwu(uint32_t opcode);
extern void ppc_eciwx(uint32_t opcode);
extern void ppc_ecowx(uint32_t opcode);
extern void ppc_eieio(uint32_t opcode);
template <class T, field_rc rec>extern void ppc_exts(uint32_t opcode);
extern void ppc_icbi(uint32_t opcode);
extern void ppc_mftb(uint32_t opcode);
extern void ppc_lhaux(uint32_t opcode);
extern void ppc_lhax(uint32_t opcode);
extern void ppc_lhbrx(uint32_t opcode);
extern void ppc_lwarx(uint32_t opcode);
extern void ppc_lwbrx(uint32_t opcode);
template <class T> extern void ppc_lzx(uint32_t opcode);
template <class T> extern void ppc_lzux(uint32_t opcode);
extern void ppc_mcrxr(uint32_t opcode);
extern void ppc_mfcr(uint32_t opcode);
template <field_rc rec> extern void ppc_mulhwu(uint32_t opcode);
template <field_rc rec> extern void ppc_mulhw(uint32_t opcode);
template <field_rc rec, field_ov ov> extern void ppc_mullw(uint32_t opcode);
template <field_rc rec, field_ov ov> extern void ppc_neg(uint32_t opcode);
template <field_direction shift, field_rc rec> extern void ppc_shift(uint32_t opcode);
template <field_rc rec> extern void ppc_sraw(uint32_t opcode);
template <field_rc rec> extern void ppc_srawi(uint32_t opcode);
template <class T> extern void ppc_stx(uint32_t opcode);
template <class T> extern void ppc_stux(uint32_t opcode);
extern void ppc_stfiwx(uint32_t opcode);
extern void ppc_sthbrx(uint32_t opcode);
extern void ppc_stwcx(uint32_t opcode);
extern void ppc_stwbrx(uint32_t opcode);
template <field_carry carry, field_rc rec, field_ov ov> extern void ppc_subf(uint32_t opcode);
template <field_rc rec, field_ov ov> extern void ppc_subfe(uint32_t opcode);
template <field_rc rec, field_ov ov> extern void ppc_subfme(uint32_t opcode);
template <field_rc rec, field_ov ov> extern void ppc_subfze(uint32_t opcode);
extern void ppc_sync(uint32_t opcode);
extern void ppc_tlbia(uint32_t opcode);
extern void ppc_tlbie(uint32_t opcode);
extern void ppc_tlbli(uint32_t opcode);
extern void ppc_tlbld(uint32_t opcode);
extern void ppc_tlbsync(uint32_t opcode);
extern void ppc_tw(uint32_t opcode);
extern void ppc_lswi(uint32_t opcode);
extern void ppc_lswx(uint32_t opcode);
extern void ppc_stswi(uint32_t opcode);
extern void ppc_stswx(uint32_t opcode);
extern void ppc_mfsr(uint32_t opcode);
extern void ppc_mfsrin(uint32_t opcode);
extern void ppc_mtsr(uint32_t opcode);
extern void ppc_mtsrin(uint32_t opcode);
extern void ppc_mcrf(uint32_t opcode);
extern void ppc_mtcrf(uint32_t opcode);
extern void ppc_mfmsr(uint32_t opcode);
extern void ppc_mfspr(uint32_t opcode);
extern void ppc_mtmsr(uint32_t opcode);
extern void ppc_mtspr(uint32_t opcode);
template <field_rc rec> extern void ppc_mtfsb0(uint32_t opcode);
template <field_rc rec> extern void ppc_mtfsb1(uint32_t opcode);
extern void ppc_mcrfs(uint32_t opcode);
template <field_rc rec> extern void ppc_fmr(uint32_t opcode);
template <field_601 for601, field_rc rec> extern void ppc_mffs(uint32_t opcode);
template <field_rc rec> extern void ppc_mtfsf(uint32_t opcode);
template <field_rc rec> extern void ppc_mtfsfi(uint32_t opcode);
template <field_shift shift> extern void ppc_addi(uint32_t opcode);
template <field_rc rec> extern void ppc_addic(uint32_t opcode);
template <field_shift shift> extern void ppc_andirc(uint32_t opcode);
template <field_lk l, field_aa a> extern void ppc_b(uint32_t opcode);
template <field_lk l, field_aa a> extern void ppc_bc(uint32_t opcode);
extern void ppc_cmpi(uint32_t opcode);
extern void ppc_cmpli(uint32_t opcode);
template <class T> extern void ppc_lz(uint32_t opcode);
template <class T> extern void ppc_lzu(uint32_t opcode);
extern void ppc_lha(uint32_t opcode);
extern void ppc_lhau(uint32_t opcode);
extern void ppc_lmw(uint32_t opcode);
extern void ppc_mulli(uint32_t opcode);
template <field_shift shift> extern void ppc_ori(uint32_t opcode);
extern void ppc_rfi(uint32_t opcode);
extern void ppc_rlwimi(uint32_t opcode);
extern void ppc_rlwinm(uint32_t opcode);
extern void ppc_rlwnm(uint32_t opcode);
extern void ppc_sc(uint32_t opcode);
template <class T> extern void ppc_st(uint32_t opcode);
template <class T> extern void ppc_stu(uint32_t opcode);
extern void ppc_stmw(uint32_t opcode);
extern void ppc_subfic(uint32_t opcode);
extern void ppc_twi(uint32_t opcode);
template <field_shift shift> extern void ppc_xori(uint32_t opcode);
extern void ppc_lfs(uint32_t opcode);
extern void ppc_lfsu(uint32_t opcode);
extern void ppc_lfsx(uint32_t opcode);
extern void ppc_lfsux(uint32_t opcode);
extern void ppc_lfd(uint32_t opcode);
extern void ppc_lfdu(uint32_t opcode);
extern void ppc_lfdx(uint32_t opcode);
extern void ppc_lfdux(uint32_t opcode);
extern void ppc_stfs(uint32_t opcode);
extern void ppc_stfsu(uint32_t opcode);
extern void ppc_stfsx(uint32_t opcode);
extern void ppc_stfsux(uint32_t opcode);
extern void ppc_stfd(uint32_t opcode);
extern void ppc_stfdu(uint32_t opcode);
extern void ppc_stfdx(uint32_t opcode);
extern void ppc_stfdux(uint32_t opcode);
template <field_rc rec> extern void ppc_fadd(uint32_t opcode);
template <field_rc rec> extern void ppc_fsub(uint32_t opcode);
template <field_rc rec> extern void ppc_fmul(uint32_t opcode);
template <field_rc rec> extern void ppc_fdiv(uint32_t opcode);
template <field_rc rec> extern void ppc_fadds(uint32_t opcode);
template <field_rc rec> extern void ppc_fsubs(uint32_t opcode);
template <field_rc rec> extern void ppc_fmuls(uint32_t opcode);
template <field_rc rec> extern void ppc_fdivs(uint32_t opcode);
template <field_rc rec> extern void ppc_fmadd(uint32_t opcode);
template <field_rc rec> extern void ppc_fmsub(uint32_t opcode);
template <field_rc rec> extern void ppc_fnmadd(uint32_t opcode);
template <field_rc rec> extern void ppc_fnmsub(uint32_t opcode);
template <field_rc rec> extern void ppc_fmadds(uint32_t opcode);
template <field_rc rec> extern void ppc_fmsubs(uint32_t opcode);
template <field_rc rec> extern void ppc_fnmadds(uint32_t opcode);
template <field_rc rec> extern void ppc_fnmsubs(uint32_t opcode);
template <field_rc rec> extern void ppc_fabs(uint32_t opcode);
template <field_rc rec> extern void ppc_fnabs(uint32_t opcode);
template <field_rc rec> extern void ppc_fneg(uint32_t opcode);
template <field_rc rec> extern void ppc_fsel(uint32_t opcode);
template <field_rc rec> extern void ppc_fres(uint32_t opcode);
template <field_rc rec> extern void ppc_fsqrts(uint32_t opcode);
template <field_rc rec> extern void ppc_fsqrt(uint32_t opcode);
template <field_rc rec> extern void ppc_frsqrte(uint32_t opcode);
template <field_rc rec> extern void ppc_frsp(uint32_t opcode);
template <field_rc rec> extern void ppc_fctiw(uint32_t opcode);
template <field_rc rec> extern void ppc_fctiwz(uint32_t opcode);
extern void ppc_fcmpo(uint32_t opcode);
extern void ppc_fcmpu(uint32_t opcode);
Add files via upload The first attempt at uploading new files.
2019-07-01 19:15:33 -07:00
clang-format everything
2020-05-12 23:55:45 +05:00
// Power-specific instructions
Remove ppc_cur_instruction global variable Replace it wth an explicit opcode parameter that is passed around. That is both slightly easier to reason about (to trace where it comes from) and slightly faster, since it can be read from a register. On my machine takes booting to "Welcome to Macintosh" being output in a verbose boot of Mac OS X 10.2.8 from 31.8s to 30.6s (average of 5 runs, measured using deterministic mode and looking at when execution reaches PC 0x90004a88).
2024-11-28 23:30:01 +01:00
template <field_rc rec, field_ov ov> extern void power_abs(uint32_t opcode);
extern void power_clcs(uint32_t opcode);
template <field_rc rec, field_ov ov> extern void power_div(uint32_t opcode);
template <field_rc rec, field_ov ov> extern void power_divs(uint32_t opcode);
template <field_rc rec, field_ov ov> extern void power_doz(uint32_t opcode);
extern void power_dozi(uint32_t opcode);
template <field_rc rec> extern void power_lscbx(uint32_t opcode);
template <field_rc rec> extern void power_maskg(uint32_t opcode);
template <field_rc rec> extern void power_maskir(uint32_t opcode);
template <field_rc rec, field_ov ov> extern void power_mul(uint32_t opcode);
template <field_rc rec, field_ov ov> extern void power_nabs(uint32_t opcode);
extern void power_rlmi(uint32_t opcode);
template <field_rc rec> extern void power_rrib(uint32_t opcode);
template <field_rc rec> extern void power_sle(uint32_t opcode);
template <field_rc rec> extern void power_sleq(uint32_t opcode);
template <field_rc rec> extern void power_sliq(uint32_t opcode);
template <field_rc rec> extern void power_slliq(uint32_t opcode);
template <field_rc rec> extern void power_sllq(uint32_t opcode);
template <field_rc rec> extern void power_slq(uint32_t opcode);
template <field_rc rec> extern void power_sraiq(uint32_t opcode);
template <field_rc rec> extern void power_sraq(uint32_t opcode);
template <field_rc rec> extern void power_sre(uint32_t opcode);
template <field_rc rec> extern void power_srea(uint32_t opcode);
template <field_rc rec> extern void power_sreq(uint32_t opcode);
template <field_rc rec> extern void power_sriq(uint32_t opcode);
template <field_rc rec> extern void power_srliq(uint32_t opcode);
template <field_rc rec> extern void power_srlq(uint32_t opcode);
template <field_rc rec> extern void power_srq(uint32_t opcode);
Further refactoring to clean up the interpreter
2020-10-17 21:46:38 -07:00
} // namespace dppc_interpreter
Add files via upload The first attempt at uploading new files.
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clang-format everything
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// AltiVec instructions
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// 64-bit instructions
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// G5+ instructions
Add files via upload The first attempt at uploading new files.
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Implement virtual time based on instruction counting.
2021-12-20 00:10:02 +01:00
extern uint64_t get_virt_time_ns(void);
Remove ppc_cur_instruction global variable Replace it wth an explicit opcode parameter that is passed around. That is both slightly easier to reason about (to trace where it comes from) and slightly faster, since it can be read from a register. On my machine takes booting to "Welcome to Macintosh" being output in a verbose boot of Mac OS X 10.2.8 from 31.8s to 30.6s (average of 5 runs, measured using deterministic mode and looking at when execution reaches PC 0x90004a88).
2024-11-28 23:30:01 +01:00
extern void ppc_main_opcode(uint32_t opcode);
Move all PPC code execution to ppcexec.cpp.
2019-12-28 02:49:58 +01:00
extern void ppc_exec(void);
extern void ppc_exec_single(void);
extern void ppc_exec_until(uint32_t goal_addr);
debugger: debugging commands for 68k code.
2020-07-16 14:26:34 +02:00
extern void ppc_exec_dbg(uint32_t start_addr, uint32_t size);
Add files via upload The first attempt at uploading new files.
2019-07-01 19:15:33 -07:00
Improve the command line debugger. Add next command. Make the debugger somewhat foolproof.
2020-02-23 15:24:49 +01:00
/* debugging support API */
clang-format everything
2020-05-12 23:55:45 +05:00
void print_fprs(void); /* print content of the floating-point registers */
debugger: a couple of cosmetic improvements.
2022-02-23 17:06:20 +01:00
uint64_t get_reg(std::string reg_name); /* get content of the register reg_name */
void set_reg(std::string reg_name, uint64_t val); /* set reg_name to val */
Improve the command line debugger. Add next command. Make the debugger somewhat foolproof.
2020-02-23 15:24:49 +01:00
ppcemu.h: remove initializers from typedef.
2020-01-26 20:37:15 +01:00
#endif /* PPCEMU_H */
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