2020-02-28 16:04:28 +00:00
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/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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2023-02-01 23:21:36 +00:00
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Copyright (C) 2018-23 divingkatae and maximum
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2020-02-28 16:04:28 +00:00
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(theweirdo) spatium
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2019-07-02 02:15:33 +00:00
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2020-02-28 16:04:28 +00:00
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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2019-08-21 06:33:01 +00:00
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2023-02-01 23:21:36 +00:00
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/** MPC106 (Grackle) definitions.
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2019-08-21 06:33:01 +00:00
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2019-08-23 19:30:30 +00:00
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Grackle IC is a combined memory and PCI controller manufactured by Motorola.
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2019-08-21 06:33:01 +00:00
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It's the central device in the Gossamer architecture.
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Manual: https://www.nxp.com/docs/en/reference-manual/MPC106UM.pdf
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2019-08-28 00:39:29 +00:00
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This code emulates as much functionality as needed to run PowerMac Beige G3.
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2019-08-21 06:33:01 +00:00
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This implies that
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- we only support address map B
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- our virtual device reports revision 4.0 as expected by machine firmware
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*/
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2019-07-02 02:15:33 +00:00
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2023-02-01 23:21:36 +00:00
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#ifndef MPC106_H
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#define MPC106_H
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2019-07-02 02:15:33 +00:00
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2021-10-23 18:17:47 +00:00
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#include <devices/common/pci/pcidevice.h>
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#include <devices/common/pci/pcihost.h>
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#include <devices/memctrl/memctrlbase.h>
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2020-05-12 18:55:45 +00:00
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#include <cinttypes>
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2022-07-17 03:33:06 +00:00
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#include <memory>
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2019-08-21 06:33:01 +00:00
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2023-02-01 23:21:36 +00:00
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/** Grackle configuration space registers. */
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enum GrackleReg : uint32_t {
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CFG10 = 0x40, // bus # + subordinate bus # + disconnect counter
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PMCR1 = 0x70, // power management config 1
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MSAR1 = 0x80, // memory starting address 1
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MSAR2 = 0x84, // memory starting address 2
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EMSAR1 = 0x88, // extended memory starting address 1
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EMSAR2 = 0x8C, // extended memory starting address 2
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MEAR1 = 0x90, // memory ending address 1
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MEAR2 = 0x94, // memory ending address 2
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EMEAR1 = 0x98, // extended memory ending address 1
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EMEAR2 = 0x9C, // extended memory ending address 2
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MBER = 0xA0, // memory bank enable
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PICR1 = 0xA8, // processor interface configuration 1
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PICR2 = 0xAC, // processor interface configuration 2
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MCCR1 = 0xF0, // memory control configuration 1
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MCCR2 = 0xF4, // memory control configuration 2
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MCCR3 = 0xF8, // memory control configuration 3
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MCCR4 = 0xFC // memory control configuration 4
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};
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/* MCCR1 bit definitions. */
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enum {
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MEMGO = 1 << 19,
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};
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2020-05-12 18:55:45 +00:00
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class MPC106 : public MemCtrlBase, public PCIDevice, public PCIHost {
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2019-08-21 06:33:01 +00:00
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public:
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MPC106();
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2022-01-16 20:30:43 +00:00
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~MPC106() = default;
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2020-03-14 13:23:46 +00:00
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2022-07-17 03:33:06 +00:00
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static std::unique_ptr<HWComponent> create() {
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return std::unique_ptr<MPC106>(new MPC106());
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}
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2022-08-22 10:16:31 +00:00
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uint32_t read(uint32_t rgn_start, uint32_t offset, int size);
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void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size);
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2019-08-21 06:33:01 +00:00
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2022-08-19 18:07:22 +00:00
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int device_postinit();
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2019-08-21 06:33:01 +00:00
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protected:
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/* PCI access */
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Fix PCI config r/w of byte and word and unaligned.
dingusppc could not read bytes from offset 1,2,3 or words from offset 2.
dingusppc did not read words from offset 1,3 and longs from offset 1,2,3 in the same way as a real Power Mac 8600 or B&W G3.
This commit fixes those issues.
- Added pci_cfg_rev_read. It takes a 32 bit value from offset 0 and returns a value of the specified size using bytes starting from the specified offset. Offsets 4,5, & 6 wrap around to 0,1, & 2 respectively. The result bytes are in flipped order as required by the read method (so a value of 0x12345678 is returned as 0x78563412)
A real Power Mac 8600 might return a random byte for offset 4, 5, 6 for vci0 but usually not for pci1. A B&W G3 seems to always wrap around correctly. We won't read random bytes, and we won't read a default such as 00 or FF. We'll do the wrap around which makes the most sense because writing 0x12345678 to any offset and reading from the same offset should produce the value that was written.
- Added pci_cfg_rev_write. It takes a 32 bit value from offset 0, and modifies a specified number of bytes starting at a specified offset with the offset wrapping around to 0 if it exceeds 3. The modified bytes take their new values from the flipped bytes passed to pci_cfg_write. When size is 4, the original value is not used since all bytes will be modified.
Basically, those two functions handle all the sizes and all the offsets and replace calls to BYTESWAP_32, read_mem or read_mem_rev, and write_mem or write_mem_rev.
read_mem_rev, as it was used by pcidevice and some other places, could read beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always read the wrong byte or word if they were not at offset 0. Same for read_mem as used by mpc106.
write_mem_rev, as it was used by pcidevice and some other places, could write beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always write the wrong byte or word if they were not at offset 0. Same for write_mem as used by mpc106.
pcidevice:
- The logging macros should be used to handle all config register access logging.
- Unaligned PCI config register accesses will be output as ERROR instead of WARNING.
- The logging macros include the offset and size. They also include the value for named registers or for writes.
- Added MMIODevice read and write methods so that PCIDevice is not abstract if a PCIDevice doesn't override the read and write method since some PCIDevices don't have MMIO.
pcihost:
- Added pci_find_device stub for handling PCI bridges in future commit.
bandit and mpc106:
- PCI host controllers will handle all PCI config access alignment and sizing. A PCIDevice will always access config registers as 32 bits on a 4 byte boundary. The AccessDetails passed to a PCIDevice config read or write method is there only for logging purposes.
bandit:
- Common MMIO code is moved to new BanditHost class so both Bandit and Chaos can use it. PCI related code is moved to new BanditPCI class.
- Simplify IDSEL to/from PCI device number conversion by removing the shift or subtract.
- Remove BANDIT_ID_SEL check. The IDSEL conversion to PCI device number can find the bandit PCI device.
- For logging, make best guess of PCI device number from invalid IDSEL - the result is always reasonable for device 0x00 to 0x0A when accessing config register 0x00 (as one would do when scanning for PCI devices like lspci does).
mpc106:
- Common config space code is put in cfg_setup. It handles extracting the offset.
- Added code to log access to unimplemented config registers of grackle.
- Don't call setup_ram when writing to config registers that setup_ram doesn't use.
- pci_cfg_read calls READ_DWORD_LE_A and pci_cfg_write calls WRITE_DWORD_LE_A. When reading or writing memory that is organized as little endian dwords, such as my_pci_cfg_hdr of mpc106, the function should explicitly state that it's little endian so that the emulator may be ported one day to a CPU architecture that is not little endian.
atirage:
- The changes correctly place user_cfg at byte 0x40 instead of 0x43 and writes the correct byte depending on size and offset.
2022-09-02 10:32:28 +00:00
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uint32_t pci_read(uint32_t offset, uint32_t size);
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void pci_write(uint32_t offset, uint32_t value, uint32_t size);
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2019-08-21 06:33:01 +00:00
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2019-08-23 19:30:30 +00:00
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/* my own PCI configuration registers access */
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Fix PCI config r/w of byte and word and unaligned.
dingusppc could not read bytes from offset 1,2,3 or words from offset 2.
dingusppc did not read words from offset 1,3 and longs from offset 1,2,3 in the same way as a real Power Mac 8600 or B&W G3.
This commit fixes those issues.
- Added pci_cfg_rev_read. It takes a 32 bit value from offset 0 and returns a value of the specified size using bytes starting from the specified offset. Offsets 4,5, & 6 wrap around to 0,1, & 2 respectively. The result bytes are in flipped order as required by the read method (so a value of 0x12345678 is returned as 0x78563412)
A real Power Mac 8600 might return a random byte for offset 4, 5, 6 for vci0 but usually not for pci1. A B&W G3 seems to always wrap around correctly. We won't read random bytes, and we won't read a default such as 00 or FF. We'll do the wrap around which makes the most sense because writing 0x12345678 to any offset and reading from the same offset should produce the value that was written.
- Added pci_cfg_rev_write. It takes a 32 bit value from offset 0, and modifies a specified number of bytes starting at a specified offset with the offset wrapping around to 0 if it exceeds 3. The modified bytes take their new values from the flipped bytes passed to pci_cfg_write. When size is 4, the original value is not used since all bytes will be modified.
Basically, those two functions handle all the sizes and all the offsets and replace calls to BYTESWAP_32, read_mem or read_mem_rev, and write_mem or write_mem_rev.
read_mem_rev, as it was used by pcidevice and some other places, could read beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always read the wrong byte or word if they were not at offset 0. Same for read_mem as used by mpc106.
write_mem_rev, as it was used by pcidevice and some other places, could write beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always write the wrong byte or word if they were not at offset 0. Same for write_mem as used by mpc106.
pcidevice:
- The logging macros should be used to handle all config register access logging.
- Unaligned PCI config register accesses will be output as ERROR instead of WARNING.
- The logging macros include the offset and size. They also include the value for named registers or for writes.
- Added MMIODevice read and write methods so that PCIDevice is not abstract if a PCIDevice doesn't override the read and write method since some PCIDevices don't have MMIO.
pcihost:
- Added pci_find_device stub for handling PCI bridges in future commit.
bandit and mpc106:
- PCI host controllers will handle all PCI config access alignment and sizing. A PCIDevice will always access config registers as 32 bits on a 4 byte boundary. The AccessDetails passed to a PCIDevice config read or write method is there only for logging purposes.
bandit:
- Common MMIO code is moved to new BanditHost class so both Bandit and Chaos can use it. PCI related code is moved to new BanditPCI class.
- Simplify IDSEL to/from PCI device number conversion by removing the shift or subtract.
- Remove BANDIT_ID_SEL check. The IDSEL conversion to PCI device number can find the bandit PCI device.
- For logging, make best guess of PCI device number from invalid IDSEL - the result is always reasonable for device 0x00 to 0x0A when accessing config register 0x00 (as one would do when scanning for PCI devices like lspci does).
mpc106:
- Common config space code is put in cfg_setup. It handles extracting the offset.
- Added code to log access to unimplemented config registers of grackle.
- Don't call setup_ram when writing to config registers that setup_ram doesn't use.
- pci_cfg_read calls READ_DWORD_LE_A and pci_cfg_write calls WRITE_DWORD_LE_A. When reading or writing memory that is organized as little endian dwords, such as my_pci_cfg_hdr of mpc106, the function should explicitly state that it's little endian so that the emulator may be ported one day to a CPU architecture that is not little endian.
atirage:
- The changes correctly place user_cfg at byte 0x40 instead of 0x43 and writes the correct byte depending on size and offset.
2022-09-02 10:32:28 +00:00
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uint32_t pci_cfg_read(uint32_t reg_offs, AccessDetails &details);
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void pci_cfg_write(uint32_t reg_offs, uint32_t value, AccessDetails &details);
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2019-08-23 19:30:30 +00:00
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2019-10-07 01:21:01 +00:00
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void setup_ram(void);
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2019-08-21 06:33:01 +00:00
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private:
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2023-02-07 13:41:42 +00:00
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inline void cfg_setup(uint32_t offset, int size, int &bus_num, int &dev_num,
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int &fun_num, uint8_t ®_offs, AccessDetails &details,
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PCIDevice *&device);
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2022-10-26 06:06:12 +00:00
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2019-08-21 06:33:01 +00:00
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uint32_t config_addr;
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2023-02-01 23:21:36 +00:00
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uint16_t pmcr1 = 0; // power management config 1
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uint8_t pmcr2 = 0; // power management config 2
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uint8_t odcr = 0xCD; // output driver control
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uint32_t picr1 = 0xFF100010; // ROM on CPU bus, address map B, CPU type = MPC601
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uint32_t picr2 = 0x000C060C;
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uint32_t mccr1 = 0xFF820000; // 64bit ROM bus
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uint32_t mccr2 = 3;
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uint32_t mccr3 = 0;
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uint32_t mccr4 = 0x00100000;
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uint32_t mem_start[2] = {};
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uint32_t ext_mem_start[2] = {};
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uint32_t mem_end[2] = {};
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uint32_t ext_mem_end[2] = {};
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uint8_t mem_bank_en = 0;
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2019-08-21 06:33:01 +00:00
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};
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2019-07-02 02:15:33 +00:00
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2023-02-01 23:21:36 +00:00
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#endif // MPC106_H
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