2021-10-25 20:18:02 +00:00
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/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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2022-02-23 21:23:02 +00:00
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Copyright (C) 2018-22 divingkatae and maximum
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2021-10-25 20:18:02 +00:00
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** @file Enhanced Serial Communications Controller (ESCC) emulation. */
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2022-05-07 19:38:27 +00:00
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#include <devices/serial/chario.h>
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#include <devices/serial/escc.h>
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2021-10-25 20:18:02 +00:00
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#include <loguru.hpp>
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2022-05-07 19:38:27 +00:00
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#include <machines/machineproperties.h>
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2021-10-25 20:18:02 +00:00
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#include <cinttypes>
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#include <memory>
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2022-05-07 19:38:27 +00:00
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#include <string>
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2021-10-25 20:18:02 +00:00
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2022-05-02 22:16:09 +00:00
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/** Remap the compatible addressing scheme to MacRISC one. */
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const uint8_t compat_to_macrisc[6] = {
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EsccReg::Port_B_Cmd, EsccReg::Port_A_Cmd,
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EsccReg::Port_B_Data, EsccReg::Port_A_Data,
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EsccReg::Enh_Reg_B, EsccReg::Enh_Reg_A
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};
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2021-10-25 20:18:02 +00:00
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EsccController::EsccController()
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{
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2022-05-07 19:38:27 +00:00
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// allocate channels
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2021-10-25 20:18:02 +00:00
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this->ch_a = std::unique_ptr<EsccChannel> (new EsccChannel("A"));
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this->ch_b = std::unique_ptr<EsccChannel> (new EsccChannel("B"));
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2022-05-07 19:38:27 +00:00
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// attach backends
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std::string backend_name = GET_STR_PROP("serial_backend");
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this->ch_a->attach_backend(
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(backend_name == "stdio") ? CHARIO_BE_STDIO : CHARIO_BE_NULL);
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this->ch_b->attach_backend(CHARIO_BE_NULL);
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2021-10-25 20:18:02 +00:00
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this->reg_ptr = 0;
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}
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2022-02-23 21:23:02 +00:00
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void EsccController::reset()
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{
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this->master_int_cntrl &= 0xFC;
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this->master_int_cntrl |= 0xC0;
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this->ch_a->reset(true);
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this->ch_b->reset(true);
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}
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2021-10-25 20:18:02 +00:00
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uint8_t EsccController::read(uint8_t reg_offset)
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{
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2022-02-26 09:55:30 +00:00
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uint8_t result = 0;
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2021-10-25 20:18:02 +00:00
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switch(reg_offset) {
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case EsccReg::Port_B_Cmd:
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LOG_F(9, "ESCC: reading Port B register RR%d", this->reg_ptr);
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2022-02-26 09:55:30 +00:00
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if (this->reg_ptr == 2) {
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// TODO: implement interrupt vector modifications
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result = this->int_vec;
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} else {
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result = this->ch_b->read_reg(this->reg_ptr);
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}
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2021-10-25 20:18:02 +00:00
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this->reg_ptr = 0;
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break;
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case EsccReg::Port_A_Cmd:
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LOG_F(9, "ESCC: reading Port A register RR%d", this->reg_ptr);
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2022-02-26 09:55:30 +00:00
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if (this->reg_ptr == 2) {
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return this->int_vec;
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} else {
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return this->ch_a->read_reg(this->reg_ptr);
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}
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2021-10-25 20:18:02 +00:00
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this->reg_ptr = 0;
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break;
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2022-02-26 09:55:30 +00:00
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case EsccReg::Port_B_Data:
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return this->ch_b->receive_byte();
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case EsccReg::Port_A_Data:
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return this->ch_a->receive_byte();
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2021-10-25 20:18:02 +00:00
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default:
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2022-02-26 09:55:30 +00:00
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LOG_F(9, "ESCC: reading from unimplemented register %d", reg_offset);
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2021-10-25 20:18:02 +00:00
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}
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2022-02-26 09:55:30 +00:00
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return result;
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2021-10-25 20:18:02 +00:00
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}
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void EsccController::write(uint8_t reg_offset, uint8_t value)
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{
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switch(reg_offset) {
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case EsccReg::Port_B_Cmd:
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this->write_internal(this->ch_b.get(), value);
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break;
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case EsccReg::Port_A_Cmd:
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this->write_internal(this->ch_a.get(), value);
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break;
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2022-02-26 09:55:30 +00:00
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case EsccReg::Port_B_Data:
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this->ch_b->send_byte(value);
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break;
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case EsccReg::Port_A_Data:
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this->ch_a->send_byte(value);
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break;
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2021-10-25 20:18:02 +00:00
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default:
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2022-02-26 09:55:30 +00:00
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LOG_F(9, "ESCC: writing 0x%X to unimplemented register %d", value, reg_offset);
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2021-10-25 20:18:02 +00:00
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}
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}
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void EsccController::write_internal(EsccChannel *ch, uint8_t value)
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{
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if (this->reg_ptr) {
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2022-02-23 21:23:02 +00:00
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// chip-specific registers
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if (this->reg_ptr == 9) {
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// see if some reset is requested
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switch(value & 0xC0) {
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case RESET_CH_B:
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this->master_int_cntrl &= 0xDF;
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this->ch_b->reset(false);
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break;
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case RESET_CH_A:
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this->master_int_cntrl &= 0xDF;
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this->ch_a->reset(false);
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break;
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case RESET_ESCC:
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this->reset();
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break;
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}
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this->master_int_cntrl = value & 0x3F;
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} else if (this->reg_ptr == 2) {
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this->int_vec = value;
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} else { // channel-specific registers
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ch->write_reg(this->reg_ptr, value);
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}
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2021-10-25 20:18:02 +00:00
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this->reg_ptr = 0;
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} else {
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this->reg_ptr = value & 7;
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switch(value >> 3) {
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case WR0Cmd::Point_High:
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this->reg_ptr |= 8;
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break;
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}
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}
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}
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2022-02-23 21:23:02 +00:00
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// ======================== ESCC Channel methods ==============================
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2022-05-07 19:38:27 +00:00
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void EsccChannel::attach_backend(int id)
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{
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switch(id) {
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case CHARIO_BE_NULL:
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this->chario = std::unique_ptr<CharIoBackEnd> (new CharIoNull);
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break;
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case CHARIO_BE_STDIO:
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this->chario = std::unique_ptr<CharIoBackEnd> (new CharIoStdin);
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break;
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default:
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LOG_F(ERROR, "ESCC: unknown backend ID %d, using NULL instead", id);
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this->chario = std::unique_ptr<CharIoBackEnd> (new CharIoNull);
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}
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}
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2022-02-23 21:23:02 +00:00
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void EsccChannel::reset(bool hw_reset)
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{
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2022-05-07 19:38:27 +00:00
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this->chario->rcv_disable();
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2022-02-23 21:23:02 +00:00
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this->write_regs[1] &= 0x24;
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this->write_regs[3] &= 0xFE;
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this->write_regs[4] |= 0x04;
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this->write_regs[5] &= 0x61;
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this->write_regs[15] = 0xF8;
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this->read_regs[0] &= 0x3C;
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this->read_regs[0] |= 0x44;
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this->read_regs[1] = 0x06;
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this->read_regs[3] = 0x00;
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this->read_regs[10] = 0x00;
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2022-02-26 09:55:30 +00:00
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// initialize DPLL
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this->dpll_active = 0;
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this->dpll_mode = DpllMode::NRZI;
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this->dpll_clock_src = 0;
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// initialize Baud Rate Generator (BRG)
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this->brg_active = 0;
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this->brg_clock_src = 0;
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2022-02-23 21:23:02 +00:00
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if (hw_reset) {
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this->write_regs[10] = 0;
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this->write_regs[11] = 8;
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this->write_regs[14] &= 0xC0;
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this->write_regs[14] |= 0x20;
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} else {
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this->write_regs[10] &= 0x60;
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this->write_regs[14] &= 0xC3;
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this->write_regs[14] |= 0x20;
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}
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}
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2021-10-25 20:18:02 +00:00
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void EsccChannel::write_reg(int reg_num, uint8_t value)
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{
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2022-02-26 09:55:30 +00:00
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switch (reg_num) {
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case 3:
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2022-05-07 19:38:27 +00:00
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if ((this->write_regs[3] ^ value) & 0x10) {
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this->write_regs[3] |= 0x10;
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this->read_regs[0] |= 0x10; // set SYNC_HUNT flag
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LOG_F(9, "ESCC: Hunt mode entered.");
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}
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if ((this->write_regs[3] ^ value) & 1) {
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2022-02-26 09:55:30 +00:00
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if (value & 1) {
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this->write_regs[3] |= 0x1;
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2022-05-07 19:38:27 +00:00
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this->chario->rcv_enable();
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2022-02-26 09:55:30 +00:00
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LOG_F(9, "ESCC: receiver enabled.");
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2022-05-07 19:38:27 +00:00
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} else {
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this->write_regs[3] ^= 0x1;
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this->chario->rcv_disable();
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LOG_F(9, "ESCC: receiver disabled.");
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this->write_regs[3] |= 0x10; // enter HUNT mode
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this->read_regs[0] |= 0x10; // set SYNC_HUNT flag
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2022-02-26 09:55:30 +00:00
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}
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}
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this->write_regs[3] = (this->write_regs[3] & 0x11) | (value & 0xEE);
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return;
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case 7:
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if (this->write_regs[15] & 1) {
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this->wr7_enh = value;
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return;
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}
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break;
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case 14:
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switch (value >> 5) {
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2022-05-07 19:38:27 +00:00
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case DPLL_NULL_CMD:
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break;
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2022-02-26 09:55:30 +00:00
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case DPLL_ENTER_SRC_MODE:
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this->dpll_active = 1;
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this->read_regs[10] &= 0x3F;
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break;
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case DPLL_DISABLE:
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this->dpll_active = 0;
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// fallthrough
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case DPLL_RST_MISSING_CLK:
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this->read_regs[10] &= 0x3F;
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break;
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case DPLL_SET_SRC_BGR:
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this->dpll_clock_src = 0;
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break;
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case DPLL_SET_SRC_RTXC:
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this->dpll_clock_src = 1;
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break;
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case DPLL_SET_FM_MODE:
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this->dpll_mode = DpllMode::FM;
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break;
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case DPLL_SET_NRZI_MODE:
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this->dpll_mode = DpllMode::NRZI;
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break;
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default:
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LOG_F(WARNING, "ESCC: unimplemented DPLL command %d", value >> 5);
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}
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if (value & 0x1C) { // Local Loopback, Auto Echo DTR/REQ bits set
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LOG_F(WARNING, "ESCC: unexpected value in WR14 = 0x%X", value);
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}
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if (this->brg_active ^ (value & 1)) {
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this->brg_active = value & 1;
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LOG_F(9, "ESCC: BRG %s", this->brg_active ? "enabled" : "disabled");
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}
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return;
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}
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2021-10-25 20:18:02 +00:00
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this->write_regs[reg_num] = value;
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2022-02-26 09:55:30 +00:00
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}
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2022-02-23 21:23:02 +00:00
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2022-02-26 09:55:30 +00:00
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uint8_t EsccChannel::read_reg(int reg_num)
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{
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2022-05-07 19:38:27 +00:00
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if (!reg_num) {
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if (this->chario->rcv_char_available()) {
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this->read_regs[0] |= 1;
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}
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}
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2022-02-26 09:55:30 +00:00
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return this->read_regs[reg_num];
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}
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2022-02-23 21:23:02 +00:00
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2022-02-26 09:55:30 +00:00
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void EsccChannel::send_byte(uint8_t value)
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{
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2022-05-07 19:38:27 +00:00
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// TODO: put one byte into the Data FIFO
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this->chario->xmit_char(value);
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2022-02-23 21:23:02 +00:00
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}
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2022-02-26 09:55:30 +00:00
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uint8_t EsccChannel::receive_byte()
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2022-02-23 21:23:02 +00:00
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{
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2022-05-07 19:38:27 +00:00
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// TODO: remove one byte from the Receive FIFO
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uint8_t c;
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this->chario->rcv_char(&c);
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this->read_regs[0] &= ~1;
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return c;
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2021-10-25 20:18:02 +00:00
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}
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